Signal processing circuit and integrated circuit

Abstract

The embodiment of the invention provides a signal processing circuit and an integrated circuit. The signal processing circuit includes: a first amplification branch including a first operational amplifier and a first resistance network connected to the first operational amplifier; a detection branch coupled to an input of the first amplification branch, the detection branch comprising a variable resistor and configured to detect a common mode component input to the first amplification branch and generate a compensation signal based on the common mode component and a resistance value of the variable resistor; and an adjustment branch coupled between the detection branch and the first amplification branch and configured to adjust the compensation signal and apply the adjusted signal to the first amplification branch to reduce an input deviation of the first operational amplifier, the input deviation being associated with a resistance mismatch and a common mode component of the first resistance network.

Description

Technical Field

[0001] The present disclosure relates to electronic circuit technology, and more particularly, to signal processing circuits and integrated circuits. Background Art

[0002] Signal processing circuits, such as current sense amplifiers, can amplify and perform other appropriate processing on current sense signals or other types of signals, providing them to subsequent circuits for further processing. These signal processing circuits typically include an operational amplifier (OPA) and a resistor network that works with the OPA to achieve the corresponding signal processing functions.

[0003] The signal input to an operational amplifier includes both differential-mode and common-mode components. The differential-mode component is processed by the signal processing circuit and carries the valid signal, while the common-mode component can cause interference and errors. Therefore, it is generally desirable for the signal processing circuit to have good common-mode rejection performance to reduce the adverse effects of the common-mode component. However, factors such as resistor mismatch can cause the circuit's common-mode rejection performance to degrade. Currently, methods for improving common-mode rejection have many shortcomings and may introduce other problems in the process of improving common-mode rejection. Summary of the Invention

[0004] To at least partially address the above and other possible problems, embodiments of the present disclosure provide a signal processing circuit and an integrated circuit.

[0005] According to a first aspect of the present disclosure, a signal processing circuit is provided, comprising: a first amplifying branch, comprising a first operational amplifier and a first resistor network connected to the first operational amplifier; a detection branch, coupled to an input of the first amplifying branch, the detection branch comprising a variable resistor, and configured to detect a common-mode component input to the first amplifying branch and generate a compensation signal based on the common-mode component and a resistance value of the variable resistor; and an adjustment branch, coupled between the detection branch and the first amplifying branch, and configured to adjust the compensation signal and apply the adjusted signal to the first amplifying branch to reduce an input deviation of the first operational amplifier, the input deviation being associated with a resistance mismatch and a common-mode component of the first resistor network.

[0006] In some embodiments of the present disclosure, the adjustment branch is configured to perform at least one of attenuation adjustment and polarity adjustment on the compensation signal.

[0007] In some embodiments of the present disclosure, the regulating branch includes a second operational amplifier and a second resistor network connected to the second operational amplifier.

[0008] In some embodiments of the present disclosure, the regulating branch further includes a switch coupled between the second operational amplifier and the first amplifying branch and configured to switch the polarity of a signal to be applied to the first amplifying branch.

[0009] In some embodiments of the present disclosure, the second operational amplifier includes a fully differential operational amplifier, the switching switch is coupled between the non-inverting output terminal and the inverting output terminal of the fully differential operational amplifier and the first amplification branch, and the second resistor network includes: a first resistor and a second resistor, respectively coupled to the inverting input terminal and the non-inverting input terminal of the second operational amplifier; a third resistor and a fourth resistor, respectively coupled between the non-inverting output terminal and the inverting input terminal of the second operational amplifier and between the inverting output terminal and the non-inverting input terminal of the second operational amplifier; and a fifth resistor and a sixth resistor, the fifth resistor being coupled to the inverting output terminal or the non-inverting output terminal of the second operational amplifier, and the sixth resistor being coupled to the non-inverting output terminal or the inverting output terminal of the second operational amplifier.

[0010] In some embodiments of the present disclosure, a resistance ratio between the third resistor and the first resistor is less than 1, and a resistance ratio between the fourth resistor and the second resistor is less than 1.

[0011] In some embodiments of the present disclosure, the first operational amplifier includes a fully differential operational amplifier or a differential operational amplifier with a single-ended output, and wherein the fifth resistor and the sixth resistor are coupled to the inverting input and the non-inverting input of the first operational amplifier, respectively.

[0012] In some embodiments of the present disclosure, the first resistor network includes a first input resistor and a second input resistor respectively connected to the inverting input and the non-inverting input of the first operational amplifier, and the detection branch is coupled to the inverting input and the non-inverting input of the first operational amplifier via the first input resistor and the second input resistor respectively, and wherein the resistance ratio of the first input resistor to the fifth resistor is less than 1, and the resistance ratio of the second input resistor to the sixth resistor is less than 1.

[0013] In some embodiments of the present disclosure, the first operational amplifier includes a fully differential operational amplifier, and the signal processing circuit also includes: a second amplification branch, cascaded with the first amplification branch, and including a third operational amplifier and a third resistor network connected to the third operational amplifier, wherein the fifth resistor and the sixth resistor are respectively coupled to the inverting input and the non-inverting input of the third operational amplifier.

[0014] In some embodiments of the present disclosure, the first resistor network includes a first input resistor connected to the inverting input of the first operational amplifier, a second input resistor connected to the non-inverting input of the first operational amplifier, a first feedback resistor connected between the inverting input and the non-inverting output of the first operational amplifier, and a second feedback resistor connected between the non-inverting input and the inverting output of the first operational amplifier, the detection branch is coupled to the inverting input and the non-inverting input of the first operational amplifier via the first input resistor and the second input resistor, respectively, and the third resistor network includes a third input resistor and a fourth input resistor connected to the inverting input and the non-inverting input of the third operational amplifier, respectively, wherein the resistance ratio of the first input resistor to the first feedback resistor is less than 1, and the ratio between the second input resistor and the second feedback resistor is less than 1, and wherein the resistance ratio of the third input resistor to the fifth resistor is less than 1, and the resistance ratio of the fourth input resistor to the sixth resistor is less than 1.

[0015] In some embodiments of the present disclosure, the detection branch further includes: a first detection resistor and a second detection resistor, which are connected in series between the inputs of the first amplification branch; and a third detection resistor, which is connected in series with the variable resistor to a connection point between the first detection resistor and the second detection resistor.

[0016] In some embodiments of the present disclosure, the variable resistor includes a plurality of resistors connected in series and a plurality of switches connected in parallel to the plurality of resistors, respectively.

[0017] In some embodiments of the present disclosure, the signal processing circuit includes a current detection amplifier circuit.

[0018] According to a second aspect of the present disclosure, an integrated circuit is provided, comprising the signal processing circuit according to the first aspect.

[0019] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present disclosure.

[0021] Figure 1A A schematic circuit diagram of the amplifier circuit is shown.

[0022] Figure 1B A schematic circuit diagram of the amplifier circuit after adding a compensation resistor is shown.

[0023] Figure 2 A schematic circuit diagram of a signal processing circuit and a detection resistor circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A schematic circuit diagram of a variable resistor in a detection branch according to an embodiment of the present disclosure is shown.

[0025] Figure 4 A schematic circuit diagram of a signal processing circuit and a detection resistor circuit according to another embodiment of the present disclosure is shown.

[0026] Figure 5 A schematic circuit diagram of a signal processing circuit and a detection resistor circuit according to yet another embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic circuit diagram of a signal processing circuit and a detection resistor circuit according to yet another embodiment of the present disclosure is shown.

[0028] Figure 7A A graph showing the relationship between a binary code for controlling a variable resistor and a switch and an offset voltage compensation amount without applying a logic conversion operation according to an embodiment of the present disclosure is shown.

[0029] Figure 7B A graph showing the relationship between a binary code for controlling a variable resistor and a switch and an amount of compensation for an offset voltage when a logic conversion operation is applied according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can derive alternative technical solutions from the following description without departing from the spirit and scope of protection of the present disclosure.

[0031] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based, at least in part, on." The terms "one embodiment" and "an example" mean "at least one example embodiment." Other explicit and implicit definitions may be included below.

[0032] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0033] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.

[0034] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0035] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0036] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0037] The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of this application are synonymous.

[0038] As mentioned above, good common-mode rejection (CMRR) performance helps signal processing circuits reduce the impact of common-mode components. However, factors such as resistor mismatch can increase the CMRR, leading to degradation of the circuit's CMRR performance. Currently, some approaches can mitigate the increase in CMRR caused by factors such as resistor mismatch. For example, by introducing resistors to compensate for resistor mismatch, the CMRR can be eliminated or reduced. However, current solutions have several drawbacks and may degrade performance in other aspects of the circuit.

[0039] Figure 1A Schematic diagram of the amplifier circuit 10 is shown. Figure 1A As shown, the amplifier circuit 10 includes an operational amplifier 11. As an example, the operational amplifier 11 is a fully differential operational amplifier and includes two differential input terminals, two differential output terminals, and a common-mode voltage control port VCM. The amplifier circuit 10 may also include a resistor network, which includes input resistors R11 and R12 and feedback resistors R21 and R22. The input resistor R11 is connected between the input terminal VIP and the inverting input terminal of the operational amplifier 11, the input resistor R12 is connected between the other input terminal VIN and the non-inverting input terminal of the operational amplifier 11, the feedback resistor R21 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11, and the feedback resistor R22 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11.

[0040] Generally speaking, the resistance values ​​of the input resistors R11 and R12 should be the same, and the resistance values ​​of the feedback resistors R21 and R22 should be the same. However, due to factors such as manufacturing process, temperature coefficient, and material differences, there may be deviations between the input resistors R11 and R12 or between the feedback resistors R21 and R22, resulting in resistance mismatch, which will cause the common-mode rejection ratio of the discharge circuit 10 to increase. For example, the manufacturing process causes the input resistor R11 to have a resistance deviation ΔR relative to the input resistor R12. When the common-mode component input from the outside to the amplifier circuit 10 changes by Δvcmi, the common-mode current flowing through R11 and R21 inside the amplifier circuit 10 will change by Δvcmi / (R11+R21). The change in common-mode current and the resistance deviation of ΔR cause the voltage deviation (also called offset voltage) Vos at the input of the operational amplifier 11 to change by ΔVos, which can be expressed as:

[0041]

[0042] Furthermore, the common mode rejection ratio (CMRR) of the amplifier circuit 10 can be expressed as:

[0043]

[0044] Among them A ud Denotes differential mode gain, A uc Represents the common-mode gain, Δvcmi represents the change in the input common-mode component, Δvcmo represents the change in the output quantity, and ΔVos represents the change in the offset voltage. For example, the input resistors R11 and R12 are both 1MΩ, the feedback resistors R21 and R22 are both 4MΩ, and ΔR is 100Ω, that is, the mismatch ratio between the input resistors R11 and R12 is 0.1‰. In this case, from equation (1), it can be seen that for every 1V change in the input common-mode component vcmi, the offset voltage Vos changes by 20μV. From equation (2), it can be calculated that the common-mode rejection ratio CMRR drops to 20log due to the resistor mismatch. 10 (5*10 4 ), which is only about 94dB, which is far lower than the 120dB common mode rejection ratio required under normal working conditions.

[0045] Figure 1B FIG. 1 shows a schematic circuit diagram of the amplifier circuit 10′ after adding a compensation resistor. Figure 1B As shown in FIG1 , compared to the amplifier circuit 10 , variable resistors RT1 and RT2 are added as compensation resistors in the paths where the feedback resistors R21 and R22 are located in the discharge circuit 10 ′. By adjusting or changing the resistance values ​​of the variable resistors RT1 and RT2, the mismatch in the input resistor or the feedback resistor can be compensated, thereby improving the common mode rejection ratio. For example, if the difference between the variable resistors RT1 and RT2 is set to R TRIM , by introducing variable resistors RT1 and RT2, the change ΔVos of the offset voltage Vos can be compensated. The compensation amount ΔVcomp can be expressed as:

[0046]

[0047] The compensation ΔVcomp can reduce or offset the ΔVos caused by the common-mode component and the resistor mismatch, thereby improving the common-mode rejection ratio CMRR.

[0048] However, inserting variable resistors RT1 and RT2 introduces gain error and nonlinearity into amplifier circuit 10' and increases temperature drift. Furthermore, since variable resistors RT1 and RT2 are typically adjusted using switches, amplifier circuit 10' is not suitable for high-voltage circuits that may damage the switches.

[0049] In addition, the variable resistors RT1 and RT2 in the amplifier circuit 10' also occupy a considerable area and introduce large parasitics. Specifically, if the common mode rejection ratio CMRR is to be no less than 120dB, then according to equation (2), Δvcmi / ΔVos should be greater than 10 6, that is, for every 1V change in the input common-mode component vcmi (i.e. Δvcmi = 1V), the change in the offset voltage Vos ΔVos should not exceed 1μV. In addition, the resistance values ​​of the variable resistors RT1 and RT2 are R TRIM It changes with a certain adjustment step, so the compensation amount ΔVcomp determined by equation (3) is also a series of discrete values ​​that change with a certain adjustment step. In this case, in order to ensure that the common mode rejection ratio CMRR is not less than 120dB, the adjustment step of the compensation amount ΔVcomp for each 1V change of the input common mode component vcmi will not be greater than 2μV, because if the adjustment step of the compensation amount ΔVcomp is greater than 2μV, it may be that the compensated ΔVos is still greater than 1μV. In addition, considering the possible errors, the actual adjustment step of the compensation amount ΔVcomp should be lower, for example, about 1μV, so as to ensure that the common mode rejection ratio CMRR is higher than 120dB. Therefore, the resistance R of the variable resistors RT1 and RT2 is TRIM The adjustment step size also needs to be set low. For example, if the input resistor R11 is 1MΩ and the feedback resistor R21 is 4MΩ, then according to equation (3), the compensation amount ΔVcomp is Δvcmi*R TRIM / 20M. Therefore, if the adjustment step size of the compensation amount ΔVcomp when the input common mode component vcmi changes by 1V is set to about 1μV, the resistance value of the variable resistors RT1 and RT2 is R TRIM The adjustment step size needs to be maintained at around 20Ω. Variable resistors RT1 and RT2 typically use a parallel structure of resistors and switches to achieve resistance adjustment. Extremely low resistance adjustment steps require switches with extremely low on-resistance to operate, which results in large switches and therefore occupies a considerable area in the circuit or chip.

[0050] The embodiment of the present disclosure provides an improved signal processing circuit. In the improved scheme, by introducing an additional detection branch and an adjustment branch, an appropriate compensation signal can be generated according to the size of the common-mode component and the resistance value of the variable resistor and applied to the first amplification branch, thereby compensating or offsetting the input voltage deviation or offset voltage caused by the resistance mismatch and the common-mode component in the first amplification branch. In this way, the common-mode rejection performance of the signal processing circuit can be improved, the adverse effects of the resistance mismatch are eliminated, and the impact on the performance of the differential path in the signal processing circuit is small, for example, gain error and nonlinearity are not introduced and temperature drift is not increased. In addition, the signal processing circuit can be applied to high voltage, and since the detection branch and the adjustment branch are additional branches, the signal processing circuit is insensitive to the mismatch, temperature drift and nonlinearity of the detection branch and the adjustment branch itself, and the matching requirements for the paths where the detection branch and the adjustment branch are located are low, thereby improving the robustness of the signal processing circuit. In some embodiments, the improved scheme can set the adjustment step of the variable resistor to a larger resistance value, such as reaching the kilo-ohm level, which ensures that a switch with a larger on-resistance can be used to adjust the variable resistor, thereby effectively reducing the size of the switch and thus reducing the area required to be occupied by the variable resistor in the circuit or chip.

[0051] Figure 2 Schematic circuit diagram of a signal processing circuit 100 and a detection resistor circuit 200 according to an embodiment of the present disclosure is shown. As an example, the signal processing circuit 100 may be a current detection amplifier circuit and connected to the detection resistor circuit 200. In one example, the signal processing circuit 100 may be implemented as an integrated circuit or chip. Specifically, the signal processing circuit 100 as a current detection amplifier circuit may be connected across the detection resistor RS, thereby detecting the current I flowing through the resistor RS. RS Detection is performed and the detection signal is amplified to be provided to a subsequent circuit (such as an analog-to-digital conversion circuit) for further processing. However, it is understood that the signal processing circuit 100 can also be a processing circuit for other purposes, such as for sensing other types of signals or performing other signal processing functions, as long as the signal processing circuit has input deviation problems caused by common-mode components and resistor mismatch.

[0052] like Figure 2 As shown, the signal processing circuit 100 may include a first amplifying branch 110, the first amplifying branch 110 including a first operational amplifier 111 and a first resistor network connected to the first operational amplifier 111. As an example, the first operational amplifier 111 and the first resistor network may receive a voltage across a detection resistor RS in the detection resistor circuit 200 via inputs VIP and VIN. The voltage across the detection resistor RS is determined by the current to be detected I RSThe current I flowing through the sense resistor RS is RS The first operational amplifier 111 and the first resistor network can perform appropriate processing on the received signal, such as amplifying the signal to adapt to the signal requirements of the subsequent circuit. The first operational amplifier 111 can be a fully differential operational amplifier. Alternatively, the first operational amplifier 111 can also be a differential operational amplifier with a single output terminal. In some embodiments, the first resistor network includes a first input resistor RI11, a second input resistor RI12, a first feedback resistor RI21, and a second feedback resistor RI22. The first input resistor RI11 is connected to the inverting input terminal of the first operational amplifier 111, the second input resistor RI12 is connected to the non-inverting input terminal of the first operational amplifier 111, the first feedback resistor RI21 is connected between the inverting input terminal and the non-inverting output terminal of the first operational amplifier 111, and the second feedback resistor RI22 is connected to the second feedback resistor RI22 between the non-inverting input terminal and the inverting output terminal of the first operational amplifier 111.

[0053] Signal processing circuit 100 also includes a detection branch 120, which is coupled to inputs VIP and VIN of first amplifying branch 110. Detection branch 120 includes a variable resistor RT and detects the common-mode component input to first amplifying branch 110. Detection branch 120 also generates a compensation signal based on the common-mode component and the resistance value of variable resistor RT. Specifically, resistors in the first resistor network may be mismatched. For example, due to process issues, the first input resistor RI11 and the second input resistor RI12, which should be equal to each other, may be slightly larger than the second input resistor RI12. As described above, this resistance mismatch can cause input voltage deviation, reducing the common-mode rejection ratio. Because the input voltage deviation caused by resistance mismatch is not fixed and increases with the increase of the common-mode component, it is necessary to determine the common-mode component when compensating for the input voltage deviation. Therefore, a compensation signal can be determined based on the change in the common-mode component to effectively compensate for the input voltage deviation. According to the definition of the common-mode component, the common-mode component is half the sum of the potentials of the two input terminals, that is, the average of the potentials of the two input terminals. Therefore, the size of the common-mode component can be detected or obtained by means of a detection resistor network or other appropriate means. In addition, since the resistance mismatch in different amplifier circuits is different, the compensation amount used for compensation needs to be adjustable. By setting and changing the resistance value of the variable resistor RT, the compensation amount can be adjusted according to the specific situation of the resistance mismatch, thereby allowing the detection circuit 120 to be applicable to amplifier circuits under different mismatch conditions and to achieve the required compensation. Since the variable resistor RT needs to be coupled to the main path through resistors and other devices, even if the main path is connected to a high-voltage line, the switch in the variable resistor RT will not be broken down or damaged, so that the signal processing circuit 100 has the advantage of being applicable to high voltage.

[0054] The signal processing circuit 100 also includes an adjustment branch 130, which is coupled between the detection branch 120 and the first amplification branch 110. The adjustment branch 130 adjusts the compensation signal and applies the adjusted signal to the first amplification branch 110 to reduce the input deviation or offset voltage of the first operational amplifier 111, which is associated with the resistance mismatch and common-mode component of the first resistor network. For example, the adjustment function of the adjustment branch 130 may include changing the signal size, changing the polarity of the signal, enhancing the signal driving capability, impedance matching, etc. By setting the adjustment branch, the signal processing circuit 100 can appropriately adjust the compensation signal generated by the detection branch 120 so that the adjusted signal can be applied to the first amplification branch 110 to achieve the desired compensation.

[0055] In some embodiments of the present disclosure, the adjustment branch 130 performs attenuation adjustment on the compensation signal output by the detection branch 120. By attenuating the compensation signal, the larger compensation signal output by the detection branch 120 can be attenuated into a smaller signal suitable for offsetting or compensating the offset voltage. This facilitates the use of a variable resistor RT with a larger adjustment step size in the detection branch 120, thereby enabling the use of a smaller switch in the variable resistor RT to adjust the resistance, thereby reducing the area required for the variable resistor RT. Alternatively or additionally, the adjustment branch 130 adjusts the polarity of the compensation signal output by the detection branch 120. Specifically, when a resistor mismatch occurs, the input voltage deviation or offset voltage may have both positive and negative polarities. For example, if the manufacturing process causes a positive error in the resistor that exceeds the expected value or a negative error that falls below the expected value, this may cause the input voltage deviation to have a positive or negative polarity. However, the detection branch 120 can only generate a compensation signal of one polarity. Therefore, the adjustment branch 130 can adjust the polarity of the compensation signal to adapt to the polarity of the input voltage deviation to be compensated.

[0056] Figure 3 FIG. 1 shows a schematic circuit diagram of a variable resistor RT in the detection branch 120 according to an embodiment of the present disclosure. Figure 3As shown, the variable resistor RT may include a plurality of resistors Rt1, Rt2, and Rt3 connected in series and a plurality of switches SW1, SW2, and SW3 connected in parallel to the plurality of resistors Rt1, Rt2, and Rt3, respectively. As an example, the resistance value of the resistor Rt2 is twice that of the resistor Rt1, and the resistance value of the resistor Rt3 is twice that of the resistor Rt2. In other words, the resistor Rt2 is 2Rt1, and the resistor Rt3 is 4Rt1. By opening SW1 and closing SW2 and SW3, the variable resistor RT can be adjusted to be equal to the resistor Rt1. By opening SW2 and closing SW1 and SW3, the variable resistor RT can be adjusted to be equal to the resistor Rt2, that is, 2Rt1. Similarly, by opening and closing the switches SW1 to SW3, the variable resistor RT can be adjusted to one of a series of resistance values ​​from 0 to 7Rt1, and the adjustment step is Rt1. It is understood that the variable resistor RT can also be implemented in other forms, for example, a resistor can be connected in series with a switch and multiple series branches can be connected in parallel to form a variable resistor. Figure 3 The structure of the variable resistor RT shown is more preferred, as it has many advantages, such as uniform adjustment steps, easy selection of switches and resistors, simple structure, low cost and easy implementation. Figure 3 The number of resistors and switches shown in FIG is three, but more or fewer resistors and switches can be provided as required, thereby providing a wider range and more optional resistance values.

[0057] Figure 4 FIG2 shows a schematic circuit diagram of a signal processing circuit 100 and a detection resistor circuit 200 according to another embodiment of the present disclosure. Figure 2 , Figure 4 The internal circuits of the detection branch 120 and the regulation branch 130 are shown in more detail.

[0058] In some embodiments of the present disclosure, in addition to the variable resistor RT, the detection branch 120 further includes a first detection resistor RCM1, a second detection resistor RCM2, and a third detection resistor RCM3. The first detection resistor RCM1 and the second detection resistor RCM2 are connected in series between the inputs VIP and VIN of the first amplification branch 110. The third detection resistor RCM3 is connected in series with the variable resistor RT at the connection point between the first detection resistor RCM1 and the second detection resistor RCM2.

[0059] The first detection resistor RCM1 and the second detection resistor RCM2 have the same resistance value, so that the average value of the potentials of the inputs VIP and VIN is obtained at the connection point between the two, which corresponds to the common-mode component input to the first amplification branch 110. The series circuit formed by the third detection resistor RCM3 and the variable resistor RT can divide the common-mode component, thereby generating a compensation signal associated with the common-mode component and the resistance value of the variable resistor at both ends of the variable resistor RT. In one example, if the common-mode component input to the first amplification branch 110 is vcmi and the other end of the variable resistor RT is connected to the potential VCM, the absolute value of the compensation signal can be expressed as If the absolute value of the compensation signal is differentiated or differentiated and the change in the common-mode component is expressed as Δvcmi, the change in the compensation signal can be expressed as

[0060] In some embodiments of the present disclosure, the adjustment branch 130 includes a second operational amplifier 131 and a second resistor network connected to the second operational amplifier 131. Through the second operational amplifier 131 and the second resistor network, the adjustment branch 130 can implement a desired adjustment function, such as attenuation adjustment and / or polarity adjustment for a signal, and the resistors in the second operational amplifier 131 and the second resistor network hardly contribute to noise.

[0061] In some embodiments of the present disclosure, the adjustment branch 130 further includes a switch 132, which is coupled between the second operational amplifier 131 and the first amplifying branch 110 and switches the polarity of the signal applied to the first amplifying branch 110. Thus, the switch can be set according to the polarity of the input voltage deviation caused by the resistance mismatch, ensuring that the polarity of the compensation signals applied by the detection branch 120 and the adjustment branch 130 is opposite to the polarity of the input resistance deviation, thereby offsetting each other and effectively achieving compensation.

[0062] In some embodiments of the present disclosure, the second operational amplifier 131 is a fully differential operational amplifier, and the switch 132 is coupled between the non-inverting and inverting output terminals of the fully differential operational amplifier and the first amplification branch 110. The second resistor network includes a first resistor RC11, a second resistor RC12, a third resistor RC21, a fourth resistor RC22, a fifth resistor RC31, and a sixth resistor RC32. The first resistor RC11 and the second resistor RC12 are coupled to the inverting and non-inverting input terminals of the second operational amplifier 131, respectively. The third resistor RC21 is coupled between the non-inverting and inverting output terminals of the second operational amplifier 131, and the fourth resistor RC22 is coupled between the inverting and non-inverting output terminals of the second operational amplifier 131. Depending on the switching state of the switch 132, the fifth resistor RC31 is coupled to the inverting or non-inverting output terminal of the second operational amplifier 131, and the sixth resistor RC32 is coupled to the non-inverting or inverting output terminal of the second operational amplifier 131. The first resistor RC11 and the second resistor RC12 have the same resistance value as each other, the third resistor RC21 and the fourth resistor RC22 have the same resistance value as each other, and the fifth resistor RC31 and the sixth resistor RC32 have the same resistance value as each other.

[0063] The second operational amplifier 131 and its connected resistor can work together with the variable resistor RT in the detection branch 120 to convert the common mode into a differential mode to be applied to the first amplification branch 110 to offset the input voltage deviation Vos caused by the resistor mismatch, thereby improving the common mode rejection ratio. The second operational amplifier 131 and the input resistor and feedback resistor can further adjust the compensation signal. For example, the change in the compensation signal is expressed as In the case of the compensation signal, the variation of the compensation signal is converted into after being adjusted by the second operational amplifier 131 and the first resistor RC11 and the third resistor RC21 (and the second resistor RC12 and the fourth resistor RC22). In some embodiments, the resistance ratio between the third resistor RC21 and the first resistor RC11 is less than 1, and the resistance ratio between the fourth resistor RC22 and the second resistor RC12 is less than 1. In this way, the compensation signal can be attenuated and adjusted, so that a larger resistance adjustment step size can be selected for the variable resistor RT, which is conducive to using smaller switches in the variable resistor RT to reduce the area required by the variable resistor RT.

[0064] In some embodiments of the present disclosure, the first operational amplifier 111 in the first amplifying branch 110 is a fully differential operational amplifier, and the signal processing circuit 100 further includes a second amplifying branch 140 cascaded with the first amplifying branch 110. The second amplifying branch 140 includes a third operational amplifier 142 and a third resistor network connected to the third operational amplifier 142. The fifth resistor RC31 and the sixth resistor RC32 in the adjustment branch 130 are coupled to the inverting input and the non-inverting input of the third operational amplifier 142, respectively. For example, if the signal processing circuit 100 is a current sensing amplifier circuit or current sensing amplifier, the first amplifying branch 110 can serve as the input stage, while the second amplifying branch 140 can serve as the output stage to drive an external analog-to-digital converter in a subsequent stage. The two cascaded amplifying branches can be used for PWM suppression and gain-bandwidth control, respectively. Furthermore, the compensation signal generated by the sensing branch 120 and the signal regulated by the adjustment branch 130 can be applied to the first amplifying branch 110 via the inputs of the operational amplifier 142 of the second amplifying branch 140. This allows the signals output by detection branch 120 and regulation branch 130 to offset input voltage deviations caused by resistor mismatch, thereby improving the common-mode rejection ratio. This connection method has many advantages, including minimal impact on the performance of the main path, lower matching requirements for the paths containing the detection and regulation branches, and avoidance of PWM suppression degradation caused by resistor mismatch in the regulation circuit.

[0065] In some embodiments of the present disclosure, the first resistor network of the first amplifying branch 110 includes a first input resistor RI11 connected to the inverting input of the first operational amplifier 111, a second input resistor RI12 connected to the non-inverting input of the first operational amplifier 111, a first feedback resistor RI21 connected between the inverting input and the non-inverting output of the first operational amplifier 111, and a second feedback resistor RI22 connected between the non-inverting input and the inverting output of the first operational amplifier 111. The detection branch 120 is coupled to the inverting input and the non-inverting input of the first operational amplifier 111 via the first input resistor RI11 and the second input resistor RI12, respectively. The third resistor network of the second amplifying branch 140 includes a third input resistor RO11 and a fourth input resistor RO12, respectively connected to the inverting input and the non-inverting input of the third operational amplifier 142. In addition, the third resistor network may further include a third feedback resistor RO21 and a fourth feedback resistor RO22. The third feedback resistor RO21 is connected between the inverting input terminal and the non-inverting output terminal of the third operational amplifier 142, while the fourth feedback resistor RO22 is connected between the non-inverting input terminal and the inverting output terminal of the third operational amplifier 142. The resistance ratio of the first input resistor RI11 to the first feedback resistor RI21 is less than 1, and the ratio of the second input resistor RI12 to the second feedback resistor RI22 is less than 1. The resistance ratio of the third input resistor RO11 to the fifth resistor RC31 is less than 1, and the resistance ratio of the fourth input resistor RO12 to the sixth resistor RC32 is less than 1.

[0066] In this way, the compensation signal used to offset the input voltage deviation can be further attenuated. For example, the change in the compensation signal is expressed as In the case of , after being adjusted by the second operational amplifier 131, the first resistor RC11 and the third resistor RC21 (as well as the second resistor RC12 and the fourth resistor RC22), the fifth resistor RC31 and the third input resistor RO11 (as well as the sixth resistor RC32 and the fourth input resistor RO12), and the first feedback resistor RI21 and the first input resistor RI11 (as well as the second feedback resistor RI22 and the second input resistor RI12), the variation of the compensation signal is converted to Thus, even if the resistance adjustment step of the variable current RT is set to a large resistance value, the compensation signal can be attenuated to an order of magnitude equivalent to the input voltage deviation. As an example, if RCM1 = RCM2 = 2MΩ, RCM3 = 9MΩ, RC21 / RC11 = RC22 / RC12 = 1 / 10, RO11 / RC31 = RO12 / RC32 = 1 / 25, and RI11 / RI21 = RI12 / RI22 = 1 / 4, the variation of the compensation signal generated by the detection branch 120 will be converted into Since RT is relatively small, the change in the converted compensation signal can be further simplified as As mentioned above, if the common-mode rejection ratio is to be increased to above 120dB, the adjustment step size of the compensation signal ΔVcomp for each 1V change in the input common-mode component vcmi should be around 1μV. Therefore, as long as the resistance adjustment step size of the variable resistor RT is set to around 10kΩ, the adjustment step size requirement for the compensation amount ΔVcomp can be met. Figure 1B The 20Ω adjustment step of the variable resistors RT1 and RT2 is significantly increased, thereby allowing the use of small-sized switches for the variable resistors, which in turn reduces the area and space required for the variable resistors. In addition, since neither the detection branch 120 nor the adjustment branch 130 is located on the differential signal path, even if there is a mismatch in the resistances in the detection circuit 120 and the adjustment branch 130, only a change in the adjustment step of the compensation amount will be introduced without affecting the signal processing performance of the signal processing circuit. In addition, in some cases, in order to eliminate potential problems caused by the resistance mismatch in the detection circuit 120 and the adjustment branch 130, the adjustment step of the variable resistor RT can be reduced to ensure sufficient compensation margin.

[0067] Figure 5 FIG2 shows a schematic circuit diagram of a signal processing circuit 100 and a detection resistor circuit 200 according to another embodiment of the present disclosure. Figure 4 The difference of the signal processing circuit 100 shown is that Figure 5 In the signal processing circuit 100, the fifth resistor RC31 and the sixth resistor RC32 of the adjustment branch 130 are respectively coupled to the inverting input terminal and the non-inverting input terminal of the first operational amplifier 111 in the first amplification branch 110. Figure 5 The second amplifying branch 140 is not shown, but Figure 5 The signal processing circuit 100 may also be provided with a second amplifying branch 140, and similarly Figure 4 As shown in FIG, the second amplifying branch 140 is cascaded with the first amplifying branch 110. In some embodiments of the present disclosure, the resistance ratio of the first input resistor RI11 in the first amplifying branch 110 to the fifth resistor RC31 in the regulating branch 130 is less than 1, and the resistance ratio of the second input resistor RI12 in the first amplifying branch 110 to the sixth resistor RC32 in the regulating branch 130 is less than 1. The first input resistor RI11 and the fifth resistor RC31 (as well as the second input resistor RI12 and the sixth resistor RC32) can further attenuate the compensation signal, thereby attenuating the compensation signal to a value equivalent to the input voltage deviation caused by the resistance mismatch when the adjustment step size of the variable resistor RT is large.

[0068] For example, the change in the compensation signal is expressed as In the case of , after being adjusted by the second operational amplifier 131, the first resistor RC11 and the third resistor RC21 (and the second resistor RC12 and the fourth resistor RC22), and the fifth resistor RC31 and the first input resistor RI11 (and the sixth resistor RC32 and the second input resistor RI12), the variation of the compensation signal is converted to

[0069] As an example, if RCM3 = 1 MΩ, RC21 / RC11 = RC22 / RC12 = 1 / 20, and RI11 / RC31 = RI12 / RC32 = 1 / 25, and the common mode rejection ratio is to be increased to above 120 dB, as long as the resistance adjustment step of the variable resistor RT is set to about 500 Ω, the adjustment step requirement of the compensation amount ΔVcomp can be met.

[0070] Figure 6 FIG2 shows a schematic circuit diagram of a signal processing circuit 100 and a detection resistor circuit 200 according to another embodiment of the present disclosure. Figure 5 The difference of the signal processing circuit 100 shown is that Figure 6 In the signal processing circuit 100, the operational amplifier 111A of the first amplifying branch 110 is a differential operational amplifier with a single-ended output, rather than a Figure 5 The fully differential operational amplifier in . Figure 6 The working principle of the signal processing circuit 100 is similar to that of Figure 4 and Figure 5 The signal processing circuit 100 in FIG. 1 is not described in detail.

[0071] Figure 2 、 Figure 4 、 Figure 5 and Figure 6 The signal processing circuit 100 can be debugged and configured before leaving the factory to eliminate the input voltage deviation caused by the common mode component and the resistance mismatch and to improve the common mode rejection ratio to the desired level. Figure 3Taking the variable resistor RT as an example, the switch combination of the variable resistor RT can be represented by a binary code, and these switch combinations can include, for example, 0000, 0001, 0010 ... 1111, where the highest bit represents the switch state of the switch 132 (which indicates the positive or negative polarity of the compensation amount), and the lower three bits represent the switch states of the switches SW3 to SW1. For example, 0000 can represent that the switch 132 is in the first polarity position (e.g., negative polarity) and the switches SW3 to SW1 are all open, 1001 represents that the switch 132 is in the second polarity position (e.g., positive polarity) and the switches SW3 and SW2 are open and SW1 is closed, and other binary codes can be deduced in the same way. It can be understood that the switch states corresponding to 0 and 1 described above are merely exemplary and can be arbitrarily set as needed, for example, 1 is set to represent the negative polarity position of the switch 132 and the open state of the switches SW3-SW1, and 0 is set to represent the positive polarity position of the switch 132 and the closed state of the switches SW3-SW1. During the debugging and configuration process, these binary codes can be scanned forward or reversely according to the positive or negative polarity of the input voltage deviation to determine the binary code to be configured, thereby configuring the variable resistor RT to a resistance value corresponding to the binary code.

[0072] Specifically, the variable resistor RT can be first set to a default binary code (e.g., 1000). Under the default binary code, the two input terminals VIP and VIN of the first amplifying branch 110 are both connected to 0V and the output of the first amplifying branch 110 is measured, and the input voltage deviation or offset voltage Vos1 is estimated based on the output of the first amplifying branch 110 and the amplification gain from the input to the output. Subsequently, under the default binary code, the two input terminals VIP and VIN of the first amplifying branch 110 are both connected to another potential (e.g., 36V) and the output of the first amplifying branch 110 is measured, and another input voltage deviation or offset voltage Vos2 is estimated based on the output of the first amplifying branch 110 and the amplification gain. Subsequently, (Vos1-Vos2) / Δvcmi can be calculated. For example, when Vos1 is measured at 0V and Vos2 is measured at 36V, (Vos1-Vos2) / Δvcmi is (Vos1-Vos2) / 36.

[0073] If the difference between (Vos1-Vos2) / Δvcmi is greater than a first preset value (e.g., 0.5 μV), the resistance values ​​of the variable resistor RT are scanned in a forward direction, for example, 1000, 1001, 1010, etc. are scanned in sequence, and the measurement and calculation of (Vos1-Vos2) / Δvcmi under the default binary code are repeated under each binary code until (Vos1-Vos2) / Δvcmi falls between the first preset value and the second preset value (e.g., between -0.5 μV and 0.5 μV). If (Vos1-Vos2) / Δvcmi is less than the second preset value (for example, -0.5μV), the resistance values ​​of the variable resistor RT are reversely scanned, for example, 0111, 0110, 0101... in sequence, and the measurement and calculation of (Vos1-Vos2) / Δvcmi under the default binary code are repeated under each binary code until (Vos1-Vos2) / Δvcmi falls between the first preset value and the second preset value (for example, between -0.5μV and 0.5μV).

[0074] Furthermore, during the scanning process, the polarity of the switch 132 can be switched and logic conversion can be performed to ensure debugging consistency. For example, when scanning from 0000 to 1111, the debugging direction of the scanning process from 0000 to 0111 may be inconsistent with the debugging direction of the scanning process from 1000 to 1111, and the compensation amount may change in a step. To ensure consistency in debugging direction, a logic conversion operation can be performed to change the direction of change of the compensation amount during the scanning process from 0000 to 0111 or the scanning process from 1000 to 1111. For example, the lower three bits of the range 0000 to 0111 can be logically inverted to convert 0000 to 0111, 0001 to 0110, 0010 to 0101, and so on.

[0075] Figure 7A A graph showing the relationship between the binary code for controlling the variable resistor RT and the switch 132 and the compensation amount of the offset voltage when no logic conversion operation is applied, and Figure 7B FIG1 shows a graph showing the relationship between the binary code and the compensation amount of the offset voltage when a logic conversion operation is applied. Figure 7A and Figure 7B In FIG, the horizontal axis represents the binary code, and the vertical axis represents the ratio of the offset voltage change value ΔVos to the common mode component change value Δvcmi (which indicates the offset voltage change value per 1V change in the common mode component). In addition, it is assumed that 0 represents the negative polarity position of the switch 132 and the closed state of the switch SW3-SW1, and 1 represents the positive polarity position of the switch 132 and the open state of the switch SW3-SW1. Figure 7AAs shown, in the case where no logic conversion operation is applied, during the scanning process from 0000 to 0111, the variable resistor RT gradually increases, and the compensation amount decreases from a smaller negative value to a larger negative value. After the binary code reaches the highest bit (i.e., 0111), the switch 132 is controlled to switch the polarity from negative polarity to positive polarity, thereby continuing the scanning process from 1000 to 1111. However, during the scanning process from 1000 to 1111, the variable resistor RT gradually increases, and the compensation amount increases from a smaller positive value to a larger positive value, which is inconsistent with the debugging direction of the scanning process from 0000 to 0111, and the compensation amount undergoes a step change. As shown in FIG. Figure 7B As shown, a logical inversion operation can be performed on the lower three bits of the numbers 0000 to 0111. Consequently, when a logical inversion operation is applied, the variable resistance RT gradually decreases during the scan from 0000 to 0111, and the compensation amount changes from a larger negative value to a smaller negative value. This is consistent with the debugging direction during the scan from 1000 to 1111, and the compensation amount exhibits a continuous change. In this way, debugging consistency can be ensured even when scanning from 0000 to 1111 and undergoing polarity switching.

[0076] After determining the desired binary code, the binary code is programmed, thereby fixing the switch of the variable resistor RT in the on / off state corresponding to the binary code. The resistance value of the variable resistor RT does not change after shipment. This effectively enables debugging and configuration of the signal processing circuit, eliminates the adverse effects of resistor mismatch, and ultimately achieves a signal processing circuit with high common-mode rejection.

[0077] Through the teachings given in the above description and the associated drawings, many modifications and other embodiments of the present disclosure given here will be recognized by those skilled in the art of the present disclosure. Therefore, it is to be understood that the embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the present disclosure. In addition, although the above description and the associated drawings have described the example embodiments in the context of certain example combinations of parts and / or functions, it should be appreciated that different combinations of parts and / or functions can be provided by alternative embodiments without departing from the scope of the present disclosure. In this regard, for example, other combinations of parts and / or functions that are different from those explicitly described above are also expected to be within the scope of the present disclosure. Although specific terms are used here, they are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A signal processing circuit (100), comprising: A first amplifying branch (110) comprises a first operational amplifier (111) and a first resistor network connected to the first operational amplifier (111); a detection branch (120) coupled to the input (VIP, VIN) of the first amplifying branch (110), the detection branch (120) comprising a variable resistor (RT) and configured to detect a common-mode component input to the first amplifying branch (110) and generate a compensation signal based on the common-mode component and a resistance value of the variable resistor (RT); as well as An adjustment branch (130) is coupled between the detection branch (120) and the first amplification branch (110), and is configured to adjust the compensation signal and apply the adjusted signal to the first amplification branch (110) to reduce an input deviation of the first operational amplifier (111), the input deviation being associated with a resistance mismatch of the first resistor network and the common-mode component.

2. The signal processing circuit (100) according to claim 1, wherein the adjustment branch (130) is configured to perform at least one of attenuation adjustment and polarity adjustment on the compensation signal.

3. The signal processing circuit (100) according to claim 1, wherein the adjustment branch (130) comprises a second operational amplifier (131) and a second resistor network connected to the second operational amplifier (131).

4. The signal processing circuit (100) according to claim 3, wherein the regulating branch (130) further includes a switching switch (132), the switching switch (132) being coupled between the second operational amplifier (131) and the first amplifying branch (110), and being configured to switch the polarity of the signal to be applied to the first amplifying branch (110).

5. The signal processing circuit (100) according to claim 4, wherein the second operational amplifier (131) comprises a fully differential operational amplifier, the switch (132) is coupled between the non-inverting output terminal and the inverting output terminal of the fully differential operational amplifier and the first amplifying branch (110), and the second resistor network comprises: A first resistor (RC11) and a second resistor (RC12) are coupled to the inverting input terminal and the non-inverting input terminal of the second operational amplifier (131), respectively; a third resistor (RC21) and a fourth resistor (RC22), coupled between the non-inverting output terminal and the inverting input terminal of the second operational amplifier (131) and between the inverting output terminal and the non-inverting input terminal of the second operational amplifier (131), respectively; and a fifth resistor (RC31) and a sixth resistor (RC32), wherein the fifth resistor (RC31) is coupled to the inverting output terminal or the non-inverting output terminal of the second operational amplifier (131), and the sixth resistor (RC32) is coupled to the non-inverting output terminal or the inverting output terminal of the second operational amplifier (131).

6. The signal processing circuit (100) according to claim 5, wherein a resistance ratio between the third resistor (RC21) and the first resistor (RC11) is less than 1, and a resistance ratio between the fourth resistor (RC22) and the second resistor (RC12) is less than 1.

7. The signal processing circuit (100) according to claim 5, wherein the first operational amplifier (111) comprises a fully differential operational amplifier or a differential operational amplifier with a single-ended output, and The fifth resistor (RC31) and the sixth resistor (RC32) are respectively coupled to the inverting input terminal and the non-inverting input terminal of the first operational amplifier (111).

8. The signal processing circuit (100) according to claim 7, wherein the first resistor network comprises a first input resistor (RI11) and a second input resistor (RI12) connected to the inverting input terminal and the non-inverting input terminal of the first operational amplifier (111), respectively, and the detection branch (120) is coupled to the inverting input terminal and the non-inverting input terminal of the first operational amplifier (111) via the first input resistor (RI11) and the second input resistor (RI12), respectively, and The resistance ratio of the first input resistor (RI11) to the fifth resistor (RC31) is less than 1, and the resistance ratio of the second input resistor (RI12) to the sixth resistor (RC32) is less than 1.

9. The signal processing circuit (100) according to claim 5, wherein the first operational amplifier (111) comprises a fully differential operational amplifier, and the signal processing circuit (100) further comprises: A second amplifying branch (140) is cascade-connected to the first amplifying branch (110) and includes a third operational amplifier (142) and a third resistor network connected to the third operational amplifier (142). The fifth resistor (RC31) and the sixth resistor (RC32) are respectively coupled to the inverting input terminal and the non-inverting input terminal of the third operational amplifier (142).

10. The signal processing circuit (100) according to claim 9, wherein the first resistor network comprises a first input resistor (RI11) connected to the inverting input terminal of the first operational amplifier (111), a second input resistor (RI12) connected to the non-inverting input terminal of the first operational amplifier (111), a first feedback resistor (RI21) connected between the inverting input terminal and the non-inverting output terminal of the first operational amplifier (111), and a second feedback resistor (RI22) connected between the non-inverting input terminal and the inverting output terminal of the first operational amplifier (111), the detection branch (120) is coupled to the inverting input terminal and the non-inverting input terminal of the first operational amplifier (111) via the first input resistor (RI11) and the second input resistor (RI12), respectively, and the third resistor network comprises a third input resistor (RO11) and a fourth input resistor (RO12) connected to the inverting input terminal and the non-inverting input terminal of the third operational amplifier (142), respectively. wherein a resistance ratio of the first input resistor (RI11) to the first feedback resistor (RI21) is less than 1, and a ratio between the second input resistor (RI12) and the second feedback resistor (RI22) is less than 1, and The resistance ratio of the third input resistor (RO11) to the fifth resistor (RC31) is less than 1, and the resistance ratio of the fourth input resistor (RO12) to the sixth resistor (RC32) is less than 1.

11. The signal processing circuit (100) according to claim 1, wherein the detection branch (120) further comprises: A first detection resistor (RCM1) and a second detection resistor (RCM2) are connected in series between inputs (VIP, VIN) of the first amplifying branch (110); and A third detection resistor (RCM3) is connected in series with the variable resistor (RT) to a connection point between the first detection resistor (RCM1) and the second detection resistor (RCM2).

12. The signal processing circuit (100) according to claim 1, wherein the variable resistor (RT) includes a plurality of resistors (Rt1, Rt2, Rt3) connected in series and a plurality of switches (SW1, SW2, SW3) connected in parallel to the plurality of resistors (Rt1, Rt2, Rt3), respectively.

13. An integrated circuit comprising the signal processing circuit (100) according to any one of claims 1 to 12.

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