Power supply time sequence control circuit for PCIe board card

Abstract

The invention discloses a power supply time sequence control circuit for a PCIe board card, relates to the technical field of power supply time sequence control, and aims to solve the problems of strong temperature sensitivity, insufficient precision, poor anti-interference capability and the like of a traditional power supply time sequence control scheme based on resistors and capacitors. The power supply time sequence control circuit comprises a power supply input module, a plurality of VRM modules and a control module, the control module starts a power-on process by detecting the stability of the power supply input module, monitors the state of the turned-on power supply by using a GPIO interface, and controls the enabling of the next-stage power supply according to a preset time sequence after confirming that the upper-stage power supply is stable, so that the orderly power-on of the multi-stage power supply is realized, and meanwhile, the circuit can be integrated with an electronic switch to realize the automatic switching of 12V voltage. The method is suitable for various PCIe board cards with high requirements on the power supply time sequence precision and stability, can effectively guarantee the stable operation of the board cards, and improves the reliability and adaptability of the whole power supply management.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply timing control, and more particularly to a power supply timing control circuit for a PCIe board. Background Art

[0002] In the field of computer hardware and expansion devices, PCIe, as a high-speed serial expansion bus standard, has become a core interface connecting various boards and host systems. It is widely used in devices such as graphics cards, network cards, storage controllers, and various specialized accelerator cards. These PCIe boards typically integrate complex functional modules, each with strict requirements for the type, amplitude, and power-up sequence of the supply voltage. The accuracy and stability of power sequencing directly determine the board's ability to boot properly, operate stably, and even extend its lifespan.

[0003] Traditional PCIe card power sequencing solutions rely on RC delay circuits constructed from passive components such as resistors and capacitors. Their core logic leverages the charge-discharge characteristics of capacitors and the current-limiting properties of resistors to delay the start-up time of the voltage regulator module (VRM) enable pins, thereby controlling the power-up of multiple power stages in a pre-set sequence. However, this passive component-based control approach has inherent drawbacks that are difficult to overcome.

[0004] From an environmental perspective, the capacitance and resistance of capacitors and resistors are highly susceptible to temperature fluctuations, causing them to drift. In the complex operating environments PCIe cards may face, temperature fluctuations can directly cause RC delays to shift, disrupting the preset power-up sequence. This can lead to abnormal startup of card functional modules and even the risk of hardware damage.

[0005] From a precision perspective, resistors and capacitors inherently have tolerances. These tolerances accumulate in multi-stage power sequencing, leading to significant deviations between actual electrical spacing and design targets. For boards with stringent timing requirements, these deviations can prevent core functional modules from completing initialization due to power sequencing errors, impacting overall board performance.

[0006] Furthermore, as analog signal nodes, RC nodes have weak resistance to electromagnetic interference. During PCIe card operation, high voltage and current transients generate strong electromagnetic interference, which can easily couple to the RC nodes, causing random fluctuations in delay time and unstable power-up timing. This instability can manifest as intermittent card failures over long-term operation, increasing the difficulty of troubleshooting and maintenance.

[0007] As PCIe cards continue to evolve and integrate more functional modules, the complexity and precision requirements for power sequencing are increasing. Traditional solutions, due to limitations in temperature sensitivity, control accuracy, and interference immunity, are no longer able to meet the demands of modern PCIe cards, especially those specialized for high-performance computing, artificial intelligence, and other fields. Therefore, a new power sequencing solution is urgently needed to address these issues. Summary of the Invention

[0008] The object of the present invention is to provide a power timing control circuit for a PCIe board to solve the above-mentioned problem.

[0009] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows: A power timing control circuit for a PCIe board, comprising: A power input module, used to provide initial power supply voltage; Multiple VRM modules, used to convert the initial power supply voltage into various levels of operating voltage required by the PCIe board, each VRM module is provided with a PG pin and an EN pin; a control module, the control module being electrically connected to the power input module and the plurality of VRM modules; Wherein, the control module is configured as follows: Detecting the voltage stability of the power input module, and starting the board power-on process when the power input module is stable; The PG pin of each VRM module is electrically connected to the first GPIO interface of the control module, and the first GPIO interface is configured in input mode for detecting whether the output voltage of the corresponding VRM module is stable; The EN pin of each VRM module is electrically connected to the second GPIO interface of the control module, and the second GPIO interface is configured in output mode; After detecting the power good signal of the upper VRM module, the EN pin of the next-level VRM module is controlled to be turned on after a preset time, thereby realizing the sequential power-on of multiple power supplies.

[0010] As a further improvement of the present invention, the control module is any one of MCU, CPLD, FPGA or DSP.

[0011] As a further improvement of the present invention, the power input module includes a main input voltage of +3.3V and +12V provided by a PCIe gold finger, and an optional external 12V auxiliary input voltage.

[0012] As a further improvement of the present invention, the multiple VRM modules include at least two modules for outputting Core voltage, DRAM voltage, CLCI voltage, PLL voltage, and IO voltage, and the VRM modules of each level of voltage are powered on in sequence according to a preset timing.

[0013] As a further improvement of the present invention, the preset time is controlled by an internal timer of the control module, and the time accuracy is not less than 1ms.

[0014] As a further improvement of the present invention, the control module further includes an ADC interface, which is electrically connected to the 12V output end of the power input module and is used to detect the stability of the 12V voltage through analog-to-digital conversion.

[0015] As a further improvement of the present invention, the number of the first GPIO interfaces and the second GPIO interfaces is consistent with the number of the VRM modules, and each of the VRM modules independently corresponds to a group of first GPIO interfaces and second GPIO interfaces.

[0016] As a further improvement of the present invention, it also includes an electronic switch, which is connected in series in the 12V power input path and is used for automatic switching between the PCIe gold finger +12V and 12V_external voltage. When one of the voltages is abnormal, it automatically switches to another available voltage input to ensure the continuity of the 12V power supply.

[0017] As a further improvement of the present invention, a voltage divider circuit consisting of two resistors R1 and R2 is connected in series in the 12V power input path. One end of the resistor R1 is connected to the 12V output end of the electronic switch, and the other end is connected to the second resistor R2 and the ADC interface. The other end of the second resistor R2 is grounded.

[0018] As a further improvement of the present invention, it also includes a peripheral voltage module, which includes at least one of an emmc power supply module and a control module power supply module. The power input end of the control module power supply module is directly electrically connected to the +3.3V output end of the power input module, and the power input end of the emmc power supply module is electrically connected to the corresponding VRM module output end. The PG pins of the peripheral voltage modules are all electrically connected to the third GPIO interface of the control module, and the third GPIO interface is configured as input mode.

[0019] Compared with the prior art, the advantages of the present invention are: (1) The present invention effectively solves the temperature sensitivity problem of traditional power timing control schemes. Traditional schemes rely on the characteristics of passive components such as resistors and capacitors to achieve timing control, and the parameters of these components are easily affected by temperature changes, resulting in timing offset. The present invention uses an MCU as the control core and accurately controls the power-on intervals of each level of power supply through an internal timer. The timing accuracy of the timer is not affected by changes in ambient temperature, ensuring that the power timing of the PCIe board remains stable under different temperature environments, thereby improving the adaptability of the board in complex environments.

[0020] (2) The present invention significantly improves the accuracy and anti-interference capability of power supply timing control. In traditional solutions, the tolerances of resistors and capacitors will accumulate and cause timing errors, and the RC nodes are susceptible to electromagnetic interference. The present invention implements timing control through digital signal transmission: the PG signal and EN signal of the VRM module are both connected to the MCU through the GPIO interface. The high anti-interference characteristics of the digital signal effectively avoid the impact of electromagnetic interference on the timing; at the same time, the timing accuracy of the MCU timer is much higher than that of the RC delay circuit, and it can be flexibly configured through software, which greatly reduces the error of timing control and meets the stringent requirements of high-end PCIe boards for timing accuracy.

[0021] (3) The present invention enhances the reliability and scalability of the power supply system. By setting up electronic switches and resistor elements, the 12V power input is automatically switched, ensuring the continuity of power supply. At the same time, the PG signal of the peripheral voltage module is included in the monitoring range of the MCU, so that the status of the entire card power system can be fully monitored. Once an abnormality occurs, the protection mechanism can be triggered in time, reducing the risk of hardware damage. In addition, the control module can use a variety of devices such as MCU, CPLD, FPGA, etc. The number of VRM modules and the output voltage can be flexibly adjusted according to the requirements of the board, which greatly improves the scalability of the solution and is suitable for different types of PCIe board scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a circuit diagram of the present invention; Figure 2 This is a schematic diagram of the power-on timing of the present invention; Figure 3 Schematic diagram of the circuit of the prior art. DETAILED DESCRIPTION

[0023] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments, and all other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative work are within the scope of protection of the present invention.

[0024] Example: See also Figure 1 A power timing control circuit for PCIe boards includes a power input module, five VRM modules, a control module (MCU is selected), an electronic switch, a resistor element, and a peripheral voltage module.

[0025] The power input module includes +3.3V and +12V voltages provided by the PCIe gold finger, as well as an external 12V auxiliary input interface, providing initial power to the entire card. The 12V power input path includes an electronic switch in series, using a dual-control N-channel MOSFET array (for example, two IRF3205s in parallel controlling the 12V main and external circuits). A gate drive circuit is configured as needed, or an intelligent power switch (Infineon IRF6727Mpbf) is used. The voltage divider circuit consists of resistors R1 (30kΩ) and R2 (10kΩ) connected in series. One end of R1 is connected to the 12V output of the electronic switch, the other end to R2 and the MCUADC interface, and the other end of R2 is connected to ground. This voltage divider converts the 12V voltage into a proportional 0-3V signal, matching the MCUADC acquisition range.

[0026] The five VRM modules use DC-DC technology and are used to output Core voltage, DRAM voltage, CLCI voltage, PLL voltage, and IO voltage. Each VRM module has a PG pin (power good pin) and an EN pin (enable pin): the PG pin of VRM1 (output Core voltage) is connected to the first GPIO interface (GPIO1, configured as input mode) of the MCU, and the EN pin is connected to the second GPIO interface (GPIO2, configured as output mode) of the MCU; the PG pin of VRM2 (output DRAM voltage) is connected to the first GPIO interface (GPIO3, configured as input mode) of the MCU, and the EN pin is connected to the second GPIO interface (GPIO4, configured as output mode) of the MCU; the PG pin of VRM3 (output CLCI voltage) is connected to the MCU The first GPIO interface (GPIO5, configured as input mode) of the CU and its EN pin are connected to the second GPIO interface (GPIO6, configured as output mode) of the MCU; the PG pin of the VRM4 (output PLL voltage) is connected to the first GPIO interface (GPIO7, configured as input mode) of the MCU and its EN pin is connected to the second GPIO interface (GPIO8, configured as output mode) of the MCU; the PG pin of the VRM5 (output IO voltage) is connected to the first GPIO interface (GPIO9, configured as input mode) of the MCU and its EN pin is connected to the second GPIO interface (GPIO10, configured as output mode) of the MCU.

[0027] The control module uses an MCU (model STM32F407) with an integrated ADC module and multiple GPIO interfaces. Its power pin is directly connected to the 1.8V output of the control module power supply module. This ensures that when the VRM module is not started, the MCU can complete initialization through an independent power supply path from +3.3V to 1.8V, including GPIO interface configuration, ADC module startup, timer calibration and other operations, to prepare for subsequent control of the VRM module.

[0028] The peripheral voltage module includes an eMMC power supply module and a control module power supply module. The control module power supply module's power input is directly connected to the +3.3V output of the PCIe gold finger. A linear voltage regulator circuit converts the +3.3V into the 1.8V operating voltage required by the MCU, ensuring the MCU can be independently powered without relying on any VRM modules. The control module power supply module's PG pin is connected to the MCU's third GPIO interface (GPIO12, configured in input mode) to provide feedback on its own voltage output stability. The eMMC power supply module's power input remains connected to the output of VRM5 (IO voltage), and its PG pin is connected to the MCU's third GPIO interface (GPIO11, configured in input mode).

[0029] See also Figure 2 The power-on timing is controlled through the GPIO of the MCU. When the upper MCU receives the power-good signal, the enable pin of the next-level power supply is turned on. The opening intervals T1, T2, and Tn are precisely controlled by the internal timer of the MCU.

[0030] See also Figure 1-3 , where V1, V2...Vn are multiple VRM modules, which are used to convert the initial power supply voltage into the various operating voltages required by the PCIe board, including Core voltage, DRAM voltage, CLCI voltage, PLL voltage, IO voltage, etc. Therefore, V1, V2, Vn can be understood as the operating voltages at each level, corresponding to the output voltages of different VRM modules respectively.

[0031] Working principle: The working process of this circuit mainly includes four stages: power input detection, power-on timing control, voltage anomaly protection and peripheral voltage monitoring.

[0032] Power input detection phase: When the PCIe accelerator card is inserted into the motherboard, the +3.3V voltage from the PCIe gold finger first powers the control module's power supply module. This module converts the +3.3V to 1.8V and transmits it to the MCU, booting the MCU and completing initialization (including configuring the system clock, initializing the GPIO and ADC interfaces, etc.). After initialization is complete, the MCU immediately checks the PG signal from the control module's power supply module through the third GPIO interface (GPIO12). If this signal is high, indicating that its own power supply is stable, the 12V power supply detection process will then begin. If the PG signal is abnormal, the MCU triggers its internal fault handling mechanism and prohibits subsequent power-on processes.

[0033] During 12V power supply detection, the MCU uses the ADC interface to collect the voltage signal at the output of the electronic switch through a voltage divider circuit to determine the stability of the PCIe gold finger +12V or the external 12V auxiliary input. If the main 12V is stable, the MCU outputs a high level through the GPIO interface, driving the electronic switch to conduct, providing a turn-on signal for the main 12V power supply. If the main 12V is abnormal, the MCU switches the electronic switch to the external 12V auxiliary input to ensure 12V power continuity. During this process, since the MCU has already completed initialization through independent power supply, there is no need to wait for any VRM modules to start up.

[0034] Power-on sequencing: After the 12V power supply stabilizes, the MCU initiates the entire card power-up process. First, the MCU enables VRM1 by outputting a high signal to the EN pin of VRM1 (Core voltage) via its second GPIO interface (GPIO2). After VRM1 boots up, its PG pin outputs a high signal, which is detected by the MCU's first GPIO interface (GPIO1), indicating that the Core voltage is stable. The MCU then starts an internal timer. After a preset time (precisely controlled by the timer), the MCU outputs a high signal to the EN pin of VRM2 (DRAM voltage) via its second GPIO interface (GPIO4), enabling VRM2. Once the PG pin of VRM2 outputs a high signal and is detected by GPIO3, the MCU restarts the timer again and, following the same logic, sequentially enables VRM3 (CLCI voltage), VRM4 (PLL voltage), and VRM5 (IO voltage), completing the multi-stage power-up sequence.

[0035] Voltage Abnormality Protection Phase: During card operation, the MCU continuously monitors the PG signal of each VRM module via the first GPIO interface. If the PG signal of a VRM module goes low (indicating an abnormal output voltage), the MCU immediately outputs a low-level signal through the corresponding second GPIO interface, turning off the EN pin of that VRM module, halting the subsequent power enable process, and triggering a protection mechanism through internal logic. For the 12V power input, if the ADC module detects a voltage abnormality, the MCU controls the electronic switch to switch to the backup power supply. If the backup power supply is also abnormal, the EN pins of all VRM modules are turned off, cutting power to the entire card.

[0036] During the peripheral voltage monitoring phase, the MCU monitors the PG signals of the eMMC power supply and control module power supply modules in real time via the third GPIO interface (GPIO11 and GPIO12). If an abnormal voltage is detected in the eMMC power supply module, the MCU suspends eMMC-related operations through software logic. If an abnormal voltage is detected in the control module power supply module, an emergency protection process is triggered to ensure stable power supply to the MCU itself.

[0037] It should be noted that the present invention can be used on all PCIe cards, as well as cards with complex multi-rail power supplies, cards with strict chip power-on timing requirements, and AI inference / training cards.

[0038] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as exemplary and non-restrictive.

[0039] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A power timing control circuit for a PCIe board, characterized in that: include: A power input module, used to provide initial power supply voltage; Multiple VRM modules, used to convert the initial power supply voltage into various levels of operating voltage required by the PCIe board, each VRM module is provided with a PG pin and an EN pin; a control module, the control module being electrically connected to the power input module and the plurality of VRM modules; Wherein, the control module is configured as follows: Detecting the voltage stability of the power input module, and starting the board power-on process when the power input module is stable; The PG pin of each VRM module is electrically connected to the first GPIO interface of the control module, and the first GPIO interface is configured in input mode for detecting whether the output voltage of the corresponding VRM module is stable; The EN pin of each VRM module is electrically connected to the second GPIO interface of the control module, and the second GPIO interface is configured in output mode; After detecting the power good signal of the upper VRM module, the EN pin of the next-level VRM module is controlled to be turned on after a preset time, thereby realizing the sequential power-on of multiple power supplies.

2. The power timing control circuit for a PCIe board according to claim 1, wherein: The control module is any one of MCU, CPLD, FPGA or DSP.

3. The power timing control circuit for a PCIe board according to claim 1, wherein: The power input module includes the main input voltages of +3.3V and +12V provided by the PCIe gold finger, and an optional external 12V auxiliary input voltage.

4. The power timing control circuit for a PCIe board according to claim 1, wherein: The multiple VRM modules include at least two of the modules for outputting Core voltage, DRAM voltage, CLCI voltage, PLL voltage, and IO voltage, and the VRM modules of each level of voltage are powered on in sequence according to a preset timing.

5. The power timing control circuit for a PCIe board according to claim 1, wherein: The preset time is controlled by an internal timer of the control module, and the time accuracy is not less than 1ms.

6. The power timing control circuit for a PCIe board according to claim 1, wherein: The control module further includes an ADC interface, which is electrically connected to the 12V output end of the power input module and is used to detect the stability of the 12V voltage through analog-to-digital conversion.

7. The power timing control circuit for a PCIe board according to claim 1, wherein: The number of the first GPIO interfaces and the second GPIO interfaces is consistent with the number of the VRM modules, and each VRM module independently corresponds to a group of first GPIO interfaces and second GPIO interfaces.

8. The power timing control circuit for a PCIe board according to claim 6, wherein: It also includes an electronic switch, which is connected in series in the 12V power input path and is used for automatic switching between the PCIe gold finger +12V and 12V_external voltage. When one of the voltages is abnormal, it automatically switches to another available voltage input to ensure the continuity of the 12V power supply.

9. The power timing control circuit for a PCIe board according to claim 8, characterized in that: A voltage divider circuit consisting of two resistors R1 and R2 is connected in series in the 12V power input path. One end of the resistor R1 is connected to the 12V output end of the electronic switch, and the other end is connected to the second resistor R2 and the ADC interface. The other end of the second resistor R2 is grounded.

10. The power timing control circuit for a PCIe board according to claim 1, wherein: It also includes a peripheral voltage module, which includes at least one of an emmc power supply module and a control module power supply module. The power input end of the control module power supply module is directly electrically connected to the +3.3V output end of the power input module, and the power input end of the emmc power supply module is electrically connected to the corresponding VRM module output end. The PG pins of the peripheral voltage modules are all electrically connected to the third GPIO interface of the control module, and the third GPIO interface is configured as an input mode.

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