Apparatus and method for correcting mask for manufacturing semiconductor device

Abstract

A method for correcting a photomask is presented that includes receiving a target design layout of a semiconductor device. The method includes inferring, by a processor, a mask bias by inputting optical feature values, geometric feature values, and resist feature values of a mask layout based on a target design layout into a first machine learning model. The processor generates a predicted pattern by incorporating the mask deviation into the mask layout, compares the predicted pattern with a target design layout, and then corrects the mask layout based on a result of the comparison between the predicted pattern and the target design layout.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0041436 filed on March 26, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to an apparatus and method for correcting a mask used to manufacture a semiconductor device. Background Art

[0004] A semiconductor device (e.g., a semiconductor chip) has a pattern formed by a photolithography process and an etching process. A pattern layout is designed for the circuit pattern of the semiconductor chip to be formed on a wafer, and the designed pattern layout is transferred to the wafer using a mask through a photolithography process. Due to the optical proximity effect in the photolithography process or the loading effect in the etching process, the circuit pattern transferred to the wafer may be different from the designed circuit pattern. An optical proximity correction (OPC) operation or a process proximity correction (PPC) operation may be performed so that the circuit pattern on the mask is accurately transferred to the wafer. Summary of the Invention

[0005] Embodiments of the present disclosure provide an apparatus and a device for correcting a mask used to manufacture a semiconductor device so that a circuit pattern is accurately transferred to a wafer.

[0006] According to an embodiment of the present disclosure, a method for correcting a photomask includes: receiving a target design layout of a semiconductor device; inferring, by a processor, mask deviations by inputting optical feature values, geometric feature values, and resist feature values ​​of a mask layout based on the target design layout into a first machine learning model; generating, by the processor, a predicted pattern by incorporating the mask deviations into the mask layout; and comparing, by the processor, the predicted pattern with the target design layout.

[0007] and correcting, by the processor, the mask layout based on a comparison result between the predicted pattern and the target design layout.

[0008] According to an embodiment of the present disclosure, a method for generating a photomask correction model may include: receiving a mask layout of a semiconductor device; receiving measurement data of a wafer manufactured using a mask based on the mask layout; and training a first machine learning model by a processor using training data, wherein the training data is obtained by marking optical feature values, geometric feature values, and resist feature values ​​of the mask layout using mask deviations based on the measurement data.

[0009] According to an embodiment of the present disclosure, a method for determining a photomask correction amount may include: receiving an edge placement error corresponding to each of a plurality of evaluation points on a wafer manufactured using a mask based on a mask layout of a semiconductor device; inferring a correlation of the edge placement errors between the plurality of evaluation points using a machine learning model; and determining a photomask correction amount for the mask layout based on the correlation of the edge placement errors and the edge placement error corresponding to each of the plurality of evaluation points. The machine learning model is trained using data obtained by labeling a feature vector using a degree of change in edge placement error due to movement of one evaluation point relative to another evaluation point among the plurality of evaluation points, the feature vector including at least one of an optical feature value, a geometric feature value, and a resist feature value corresponding to each of the plurality of evaluation points, and relative coordinates between the plurality of evaluation points. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating an apparatus for correcting a mask according to some embodiments of the present disclosure.

[0012] Figure 2 It shows Figure 1 A block diagram of components of an apparatus for correcting a mask.

[0013] Figure 3 is a diagram illustrating a circuit pattern of a mask and a circuit pattern on a wafer after a photolithography process and an etching process are performed.

[0014] Figure 4 is conceptually shown for Figure 1 Schematic diagram of a method for correcting a mask using an apparatus for correcting a mask.

[0015] Figure 5 It is shown in Figure 1 A flowchart of a method for correcting a mask performed in an apparatus for correcting a mask.

[0016] Figure 6 is a diagram illustrating a first machine learning model for inferring mask bias.

[0017] Figure 7 is a diagram illustrating training data for a first machine learning model.

[0018] Figure 8 is a diagram illustrating a first machine learning model according to some embodiments.

[0019] 9A to 9Dis a diagram showing optical eigenvectors of eigenvectors.

[0020] FIG. 10A to FIG. 10B is a diagram illustrating resist feature vectors of feature vectors.

[0021] Figure 11 is a diagram illustrating the geometric eigenvectors of eigenvectors.

[0022] Figure 12A and Figure 12B Schematic diagram for describing mask correction using a Manhattan mask and a curved mask.

[0023] Figure 13 is a flow chart illustrating a method for correcting a mask based on EPE correlation.

[0024] Figure 14 is a diagram illustrating a second machine learning model for inferring mask correction amounts.

[0025] Figure 15 are diagrams illustrating a method for determining a mask correction amount.

[0026] Figure 16A is a diagram showing an initial mask layout.

[0027] Figure 16B is a diagram showing a mask layout in the process for correcting an initial mask layout.

[0028] Figure 16C is a diagram showing a mask layout when correction of the initial mask layout is completed. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that a person having ordinary skill in the art to which the present disclosure pertains can easily reproduce the present disclosure.

[0030] Figure 1 1 is a block diagram illustrating an apparatus for correcting a mask used to manufacture a semiconductor device according to some embodiments of the present disclosure. The apparatus for correcting a mask (hereinafter referred to as a "mask correction apparatus") may be implemented by a computing device 100. Correction of a mask according to the present disclosure will be described with the same meaning as correction of a mask layout used to form a mask.

[0031] The computing device 100 may include at least one processor 110, a memory device 120, a storage device 130, and an input / output device 140. The processor 110, the memory device 120, the storage device 130, and the input / output device 140 may communicate with each other using a system bus.

[0032] The computing device 100 may operate as a dedicated device to design a semiconductor device and perform an optical proximity correction (OPC) operation and / or a process proximity correction (PPC) operation.

[0033] The computing device 100 can receive a target design layout of a semiconductor device and can form a final mask layout obtained by correcting a mask layout corresponding to the target design layout through a mask tape-out (MTO) process. An electron beam (e-beam) writer can be controlled to form a pattern in a blank mask based on the final mask layout, thereby forming a mask MSK. The mask MSK formed based on the final mask layout can be used in a photolithography process of the semiconductor device. The electron beam writer can be a multi-beam mask writer (MBMW) or a variable shape beam mask writer (VSBMW). In addition, the mask MSK can be used to form a mask pattern through a layer exposure process. The mask MSK based on the final mask layout may include at least one of a straight line pattern and a curved line pattern.

[0034] Mask MSK can be used as a photolithography mask. Light emitted from a light source SRC can illuminate mask MSK via an optical system OTS, and an optical pattern formed by mask MSK can be transferred to a wafer WAF via the optical system OTS. Resist on wafer WAF can be exposed using the optical pattern transferred to wafer WAF. The exposed resist is developed to form a patterned resist on wafer WAF. Processes such as deposition, doping, and / or etching can be performed based on the patterned resist, and structures related to the circuit pattern can be formed on wafer WAF.

[0035] According to some embodiments of the present disclosure, the computing device 100 may use a mask deviation inference model 121, which is a learning model based on machine learning, to infer mask deviation. The computing device 100 may load the mask deviation inference model 121 stored in the storage device 130 onto the memory device 120 and may infer mask deviation by inputting at least one feature vector of a mask layout based on a received target design layout into the mask deviation inference model 121. According to some embodiments, the computing device 100 may generate a mask layout based on the received target design layout, or may receive a mask layout corresponding to the target design layout together with the target design layout. According to some embodiments, the target design layout of the semiconductor device may be based on at least one of an after-development inspection (ADI) design layout and a after-cleaning inspection (ACI) design layout. According to some embodiments, the mask layout may be formed by performing an OPC operation on the target design layout. According to some embodiments, the mask layout may be formed by performing an OPC operation and a PPC operation based on another process on the target design layout.

[0036] The computing device 100 can input the optical feature vector, geometric feature vector and resist feature vector of the mask layout into the mask deviation inference model 121, and can infer the mask deviation. According to some embodiments, the computing device 100 can input the optical feature vector, geometric feature vector and resist feature vector of the mask layout into a mask deviation inference model 121. In this specification, inputting the feature vector into the mask deviation inference model 121 can mean inputting the numerical value corresponding to the feature vector into the mask deviation inference model 121. The numerical value corresponding to the feature vector can be referred to as a feature vector value. Therefore, compared with the related art of directly comparing the predicted pattern image obtained by applying the optical model and / or the resist model to the mask image based on the target design layout with the target design layout, the mask deviation can be quickly inferred. In addition, according to the related art, the predicted pattern image is generated based on the image, thereby increasing the computational load and making it difficult to consider geometric information in a wider range around the individual patterns. However, according to some embodiments of the present disclosure, the computing device 100 can infer mask deviation by numerically inputting the optical feature vector, the geometric feature vector, and the resist feature vector into the mask deviation inference model 121. This allows for rapid and accurate inference of mask deviation while taking into account a wider range around individual patterns. For example, a mask deviation inference model 121 can infer mask deviation by taking into account skew caused by photolithography and etching processes in semiconductor manufacturing processes.

[0037] The computing device 100 can use the inferred mask deviations to correct the mask layout and generate the final mask layout through mask tape-out (MTO). The mask deviation inference model 121 is a learning model based on machine learning. The mask deviation inference model 121 can infer mask deviations by considering optical feature vectors, geometric feature vectors, and resist feature vectors, thereby improving the accuracy of the inferred mask deviations. As a result, the mask can be corrected so that the intended circuit pattern is accurately generated on the wafer.

[0038] Figure 2 It shows Figure 1 1 is a block diagram of components of the mask correction apparatus 100.

[0039] Computing device 100 may include a processor 110 , a memory device 120 , a storage device 130 , an input / output device 140 , a user interface 150 , and a network transceiver 160 .

[0040] The code loaded into and temporarily stored in the memory device 120 may be instructions for controlling the operation of the processor 110. According to some embodiments, the memory device 120 may be a memory device for performing a processing function (Processing-In-Memory (PIM)).

[0041] According to some embodiments of the present disclosure, the processor 110 may load the mask deviation inference model 121 from the storage device 130. The processor 110 may temporarily store the target design layout received online or offline through the network transceiver 160 in the memory device 120. The processor 110 may calculate feature vector values ​​corresponding to multiple evaluation points (EP) of the mask layout based on the target design layout. The mask deviation may be inferred by inputting the feature vector into the mask deviation inference model 121. The processor 110 may generate a predicted pattern profile based on the inferred mask deviation, and may correct the mask layout based on a comparison result between the predicted pattern profile and the target design layout. The processor 110 may repeatedly infer the mask deviation, generate the predicted pattern profile, compare the predicted pattern profile with the target design layout, and correct the mask layout until a preset standard is met.

[0042] Processor 110 may include an artificial intelligence (AI)-based learning processor to accelerate machine learning calculations. The learning processor may be a processor including a graphics processing unit (GPU), a tensor processor, a neural processing unit (NPU), and a digital signal processor (DSP). In this specification, machine learning may be interpreted as including the concept of deep learning.

[0043] The processor 110 may apply weighting parameters of the mask deviation inference model 121 to the feature vector based on machine learning.

[0044] For example, when the mask deviation inference model 121 is based on a neural network, the processor 110 may input the values ​​output from the nodes at each layer of the mask deviation inference model 121 into the nodes at the next layer. For example, when the mask deviation inference model 121 is based on a neural network, the processor 110 may input a feature vector as an input vector to each node at the input layer. The mask deviation inference model 121 may output a mask deviation based on the network structure and weight values ​​of the neural network.

[0045] Alternatively, when the mask deviation inference model 121 is based on a linear regression model, the processor 110 may perform calculations on parameters and feature vector values ​​constituting the linear regression model.

[0046] Alternatively, when the mask bias inference model 121 is based on a nonlinear model, the processor 110 may calculate the parameters and feature vector values ​​that constitute the nonlinear model, or may perform inference based on the feature vector values. For example, when the mask bias inference model 121 is based on a decision tree or random forest, which is a nonlinear model, the processor 110 may input the feature vector as an input vector to each node at the root. The mask bias inference model 121 may infer the mask bias based on a tree structure branch based on a decision reference at each node of the tree, or the mask bias inference model 121 may output a value that supplements the mask bias inferred by another learning model.

[0047] The memory device 120 may temporarily store codes for operations of the computing device 100 , data for operations of the processor 110 , parameters of the mask deviation inference model 121 , and intermediate calculation results of the mask deviation inference model 121 .

[0048] The storage device 130 can store the trained mask bias inference model 121. The storage device 130 may include a computer-readable storage medium. The storage medium includes all types of recording media for storing computer-readable data. The storage medium may include at least any one of a hard disk drive (HDD), a solid-state drive (SSD), a silicon disk drive (SDD), ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0049] According to some embodiments, the storage device 130 may store a plurality of mask deviation inference models 121 that are trained differently from one another based on optical characteristics (such as the structure of the optical system and / or the type of light source). In addition, the storage device 130 may store a plurality of mask deviation inference models 121 that are trained differently from one another based on resist characteristics (such as the recipe of the resist). Alternatively, the storage device 130 may store a plurality of mask deviation inference models 121 that are trained differently from one another based on the type of the target design layout (ACI design layout or ADI design layout). In other words, depending on the characteristics of the training data, a plurality of learning models may be stored in the storage device 130. The computing device 100 may use the mask deviation inference models 121 that are different from one another based on the metadata corresponding to the target design layout.

[0050] The mask deviation inference model 121 may be a learning model based on deep learning or machine learning, which includes multiple layers including a neural network.

[0051] The neural network of the mask bias inference model 121 may include at least any one of a convolutional neural network (CNN), a region with convolutional neural network (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a long short-term memory (LSTM) network, a stacked deep neural network (s-DNN), a state-space dynamic neural network (S-SDNN), a deep belief network (DBN) and a restricted Boltzmann machine (RBM), but other neural network structures are not excluded.

[0052] The mask bias inference model 121 is a learning model based on machine learning. The mask bias inference model 121 can be a learning model based on decision tree, random forest, k-nearest neighbor (N-NN), logistic regression, association rule, genetic algorithm, inductive learning, support vector machine (SVM), cluster analysis, Bayesian network, reinforcement learning or regression model, but learning models with other structures are not excluded.

[0053] The mask deviation inference model 121 may be implemented in hardware, software, or a combination of hardware and software. When a portion or all of the mask deviation inference model 121 is implemented in software, at least one instruction constituting the learning model may be stored in the storage device 130 .

[0054] The user interface 150 may include devices such as a display device, a mouse device, or a keyboard device to receive input from a user or provide output from the computing device 100 .

[0055] Figure 3 1 is a diagram illustrating a circuit pattern of a target design layout TLO, a circuit pattern of a mask layout MLO, a circuit pattern of a mask MSK corrected by a computing device 100 according to some embodiments of the present disclosure, a circuit pattern on a wafer LIT after a photolithography process, and a circuit pattern on a wafer ECH obtained after an etching process. The circuit pattern may be a circuit pattern on a layout or a portion of a circuit pattern on a wafer LIT. The circuit pattern on a wafer LIT after a photolithography process may be a circuit pattern at a mask layer of the wafer. Figure 3 The mask MSK may correspond to the reference Figure 1 The calculation device 100 described above processes the mask MSK through the MTO process. Figure 1 and Figure 3 Describe the changes in the circuit pattern.

[0056] Various circuit patterns can be formed on wafers using various semiconductor processes. According to some embodiments, skew caused during the photolithography, etching, deposition, and polishing processes using a mask formed based on a mask layout having a shape corresponding to the pattern may cause a difference between the shape of the pattern in the mask layout and the shape of the actual pattern formed on the wafer using the semiconductor process. Therefore, in order to form the desired circuit pattern on the wafer, the mask layout should be designed based on the skew caused by the semiconductor process.

[0057] Reference Figure 3 , a mask layout designed to have a pattern to be formed may be provided to the computing device 100, or the computing device 100 may generate a mask layout MLO based on a target design layout TLO of the semiconductor device. According to some embodiments, the mask layout MLO may be a mask layout obtained after an OPC operation. The mask layout MLO may be in the form of graphic data used in electronic design automation (EDA) software. For example, the mask layout MLO may be provided in a data format such as a Graphic Design System (GDS) or an Open Layout Exchange System Standard (OASIS). According to some embodiments, the computing device 100 may verify the mask layout MLO. For example, the computing device 100 may perform a design rule check (DRC) and / or a layout comparison schematic (LVS) on the mask layout MLO.

[0058] According to some embodiments of the present disclosure, the computing device 100 may generate a corrected mask layout MSK based on the mask layout MLO and the target design layout TLO.

[0059] When using a mask generated based on the mask layout MLO, the computing device 100 can infer the skew caused in the circuit pattern formed on the wafer through the mask deviation inference model 121 based on machine learning. The computing device 100 can generate a corrected mask layout MSK generated by correcting the mask layout MLO based on the inferred skew. Based on the skew in the process for manufacturing the semiconductor device, the shape of the corrected mask layout MSK may be changed from the shape of the mask layout MLO. For example, the corrected mask layout MSK may have a shape that is changed from the shape of the mask layout MLO based on the skew in the lithography process and / or the etching process. It can be recognized that Figure 3 The corrected mask layout MSK has a serif pattern or hammer pattern additionally provided at the corners of the pattern, and the line width of the pattern is changed compared to the line width of the mask layout MLO. In other words, the pattern of the corrected mask layout MSK may have a shape and / or size different from the shape and / or size of at least a portion of the pattern of the mask layout MLO.

[0060] A photolithography process can be performed on the wafer using a mask generated based on the corrected mask layout MSK. For example, the photolithography process can be performed by passing light radiation through the pattern of the mask generated based on the corrected mask layout MSK, or by passing light radiation through an area other than the pattern. The shape and / or size of the pattern formed on the mask layer of the wafer due to the optical proximity effect generated during the photolithography process can at least partially differ from the shape and / or size of the pattern of the corrected mask layout MSK. Thereafter, a process for manufacturing semiconductor devices can be performed using the mask layer, and a circuit pattern can be formed on the wafer. For example, in the areas exposed by the pattern included in the mask layer of the wafer LIT undergoing the photolithography process, the semiconductor device and / or upper layers on the semiconductor substrate can be etched through an etching process. The shape and / or size of the circuit pattern formed on the wafer ECH obtained after the etching process can at least partially differ from the shape and / or size of the pattern of the corrected mask layout MSK. The mask generated based on the corrected mask layout MSK can be used to accurately form a desired circuit pattern on the wafer.

[0061] Figure 4 is a diagram conceptually illustrating a method for correcting a mask layout by performing mask correction by a computing device. The computing device may correspond to Figure 1 computing device 100.

[0062] According to some embodiments of the present disclosure, the computing device 100 may at least partially correct an initial mask layout to generate a final mask layout. The computing device 100 may infer a mask deviation from the mask layout during mask correction, and may generate a predicted pattern based on the inferred mask deviation and the mask layout. By comparing the predicted pattern with the target design layout, the computing device 100 may determine whether to perform mask correction and may determine the amount of mask correction. In this specification, the mask layout and / or the target design layout may refer to the mask layout and / or the circuit pattern included in the target design layout. For example, comparing the target design layout with the predicted pattern may be comparing the circuit pattern included in the target design layout with the predicted pattern. The predicted pattern may be a predicted circuit pattern expressed in the form of a contour.

[0063] Reference Figure 4 Before generating the final mask layout, the computing device 100 may set a plurality of evaluation points (EP) at some positions of the circuit pattern included in the mask layout during mask correction. For example, Figure 4 Two evaluation points EP1 and EP2 are set in the circuit pattern included in the mask layout MLO during mask correction. In practice, although more evaluation points (EP) may be set in the circuit pattern, for ease of explanation, reference will be made under the assumption that two evaluation points EP1 and EP2 are set. Figure 4 The following description is given.

[0064] The computing device 100 may set gauges G1 and G2 corresponding to the evaluation points EP1 and EP2. When the mask layout is a Manhattan mask layout having a straight circuit pattern, the gauges G1 and G2 may be formed in a direction perpendicular to each edge of the circuit pattern having the evaluation points EP1 and EP2. When the mask layout is a curved mask layout having a curved pattern, the gauges G1 and G2 may be formed in a direction normal to each edge of the circuit pattern having the evaluation points EP1 and EP2. Points along the gauges G1 and G2 in the circuit pattern of the target design layout TLO corresponding to the evaluation points EP1 and EP2 may be set as target points TP1 and TP2.

[0065] The computing device 100 may input feature vectors corresponding to the evaluation points EP1 and EP2 into the mask deviation inference model 121 and infer mask deviations MB1 and MB2 corresponding to the evaluation points EP1 and EP2 .

[0066] The computing device 100 may generate a prediction pattern PPC based on the mask deviations MB1 and MB2 and the circuit pattern included in the mask layout MLO. For example, the prediction pattern PPC may be generated based on prediction points PP1 and PP2 of the prediction pattern PPC. Each of the prediction points PP1 and PP2 may be spaced apart from a corresponding one of the evaluation points EP1 and EP2 of the circuit pattern included in the mask layout MLO by the corresponding one of the mask deviations MB1 and MB2.

[0067] The computing device 100 may compare the predicted pattern PPC with the circuit pattern of the target design layout TLO. When the differences EPE1 and EPE2 exceed a specific benchmark, a mask correction may be determined. The difference between the predicted pattern PPC and the circuit pattern of the target design layout TLO may be a predicted edge placement error (EPE). The computing device 100 may determine a mask correction amount based on the predicted EPEs EPE1 and EPE2.

[0068] The computing device 100 may repeatedly infer mask deviations MB1 and MB2, generate a predicted pattern PPC, compare the predicted pattern PPC with a circuit pattern of a target design layout TLO, and determine whether to correct the mask until the predicted EPEEPE1 and EPE2 meet a preset benchmark.

[0069] Figure 5 is a flow chart showing a method for correcting a mask performed in an apparatus for correcting a mask. The method for correcting a mask may be performed by Figure 1 The computing device 100 executes. Figure 4 and Figure 5 A method for correcting a mask is described.

[0070] In S110, computing device 100 may receive a target design layout. According to some embodiments, computing device 100 may perform an OPC operation on the target design layout to correspond to the target design layout and may generate an initial mask layout. Alternatively, computing device 100 may receive the initial mask layout and the target design layout.

[0071] Reference Figure 4 , a plurality of evaluation points EP1 and EP2 may be set at some positions of the circuit pattern of the mask layout MLO. Reference will be made to the following under the assumption that two evaluation points EP1 and EP2 are set for the circuit pattern of the mask layout MLO. Figure 4 The following description is given.

[0072] According to some embodiments, computing device 100 may set gauges G1 and G2 to correspond to evaluation points EP1 and EP2, respectively, and may set points corresponding to evaluation points EP1 and EP2 along gauges G1 and G2 in the circuit pattern of target design layout TLO as target points TP1 and TP2.

[0073] In S120, the computing device 100 may infer a mask deviation corresponding to the mask layout by inputting the feature vector into the first machine learning model. Figure 4 A plurality of feature vectors corresponding to the plurality of evaluation points EP1 and EP2 are input into the first machine learning model, and a plurality of mask deviations MB1 and MB2 corresponding to the plurality of evaluation points EP1 and EP2 can be output from the first machine learning model.

[0074] In S130 , the computing device 100 may generate a prediction pattern PPC based on the circuit pattern of the mask layout MLO and the inferred mask deviations MB1 and MB2 .

[0075] The computing device 100 may generate a prediction pattern PPC based on prediction points PP1 and PP2, which are located apart from evaluation points EP1 and EP2 by mask deviations MB1 and MB2. For example, for a Manhattan mask, prediction pattern PPC may be generated by shifting the segments in the mask layout where evaluation points EP1 and EP2 are located by mask deviations MB1 and MB2, respectively. Each edge in a Manhattan mask may include multiple segments. For a curved mask, prediction points PP1 and PP2 may be determined by shifting evaluation points EP1 and EP2 by mask deviations MB1 and MB2, respectively. Prediction pattern PPC may be generated as a spline curve formed by linking prediction points PP1 and PP2.

[0076] In S140, the computing device 100 may compare the predicted pattern PPC with the target design layout TLO, and may determine whether to correct the mask based on the comparison result. Figure 4The predicted pattern PPC is compared with the circuit pattern of the target design layout, and when the predicted edge placement errors (EPE) EPE1 and EPE2 exceed a specific reference, mask correction can be determined. For example, when the predicted EPE EPE1 and EPE2 are less than a preset value, that is, when the predicted EPE EPE1 and EPE2 are less than a unit of a preset mask correction amount, mask correction can be stopped. Otherwise, it can be determined to continue performing mask correction.

[0077] In S150, the computing device 100 may determine a mask correction amount based on the predicted EPEs EPE1 and EPE2. According to some embodiments, the mask correction amount may be determined based on a table formed by mapping the magnitude of the predicted EPE to the mask correction amount. According to other embodiments, the mask correction amount may be determined based on a correlation between the EPE and another evaluation point. For example, a "cross-MEEF" (MEEF is short for mask error enhancement factor) between the evaluation points may be calculated, and the mask correction amount may be determined by performing a calculation between the cross-MEEF and the predicted EPEs EPE1 and EPE2.

[0078] When a mask correction amount is determined to correspond to each of the evaluation points EP1 and EP2, the computing device 100 can correct the mask layout MLO by changing the positions of the segments corresponding to the evaluation points EP1 and EP2, or the positions of the evaluation points EP1 and EP2, respectively, in the mask layout. For example, for a Manhattan mask, the mask layout MLO can be corrected by shifting each of the segments in which the evaluation points EP1 and EP2 are located in the mask layout by the corresponding mask correction amount. For a curved mask, the corrected mask layout can be generated in the form of a spline curve formed by linking points obtained by shifting the evaluation points EP1 and EP2 by the corresponding mask correction amount.

[0079] Figure 6 : is a diagram showing a first learning model (or first machine learning model) ML1 for inferring mask deviation. The first learning model ML1 can be used to infer mask deviation to obtain Figure 1 The computing device 100 performs a method for correcting a mask.

[0080] Reference Figure 6 , the first learning model ML1 may receive the feature vector FV1 at the evaluation point EP and may output the mask deviation MB_O corresponding to the evaluation point EP.

[0081] The feature vector FV1 may include optical features, geometric features, and resist features. Alternatively, the feature vector FV1 may include an optical feature vector, a geometric feature vector, and a resist feature vector that respectively include optical features, geometric features, and resist features. The computing device 100 may input the feature vector FV1 having optical feature values, geometric feature values, and resist feature values ​​and corresponding to evaluation points (EP) respectively into the first machine learning model ML1. The first machine learning model ML1 may output a plurality of mask deviations MB_O corresponding to a plurality of evaluation points based on the feature vector FV1.

[0082] The first machine learning model ML1 may be a model trained using training data, the training data being obtained by labeling a feature vector having an optical feature value, a geometric feature value, and a resist feature value using an edge placement error (EPE). Training the first machine learning model ML1 using the training data may be performed by the computing device 100 or by another computing device. The edge placement error (EPE) may be measured on a sample wafer manufactured using the mask layout. For example, the feature vector calculated based on the mask layout may be labeled using the edge placement error (EPE) measured on a sample wafer manufactured using the mask layout. The edge placement error (EPE) may be measured based on the outline of the circuit pattern included in the ADI image of the sample wafer or the difference between the outline of the circuit pattern included in the ACI image of the sample wafer and the mask layout. The EPE corresponding to the evaluation position of the mask layout may be measured based on the outline of the circuit pattern included in the ADI image or the outline of the circuit pattern included in the ACI image. The ADI image may be an image of the sample wafer after the development process of the photolithography process is completed, and the ACI image may be an image of the sample wafer after the etching process is completed.

[0083] According to some embodiments, the edge placement error (EPE) may be a measure of the critical dimension (CD) MCD. Figure 7 The measured critical dimension MCD of the ACI image or the ADI image of the sample wafer and the size MSK_SZ of the circuit pattern corresponding to the mask layout can be determined by the mask deviation MB_L from the left edge of the circuit pattern and the mask deviation MB_R from the right edge of the circuit pattern. In this case, the feature vector of the training data can be labeled with a value corresponding to half the difference between the measured critical dimension MCD and the size MSK_SZ of the circuit pattern corresponding to the mask layout ((MB_L+MB_R) / 2=|MSK_SZ-MCD| / 2).

[0084] According to some embodiments, the feature vectors of the training data can be further labeled based on the misalignment of the mask layout. For example, the value of the mask deviation MB_L from the left edge and the value of the mask deviation MB_R from the right edge can be accurately measured based on the misalignment degree MIS_ALGN of the mask layout. The feature vector corresponding to the left evaluation point EP_L can be labeled using the mask deviation MB_L from the left edge, and the feature vector corresponding to the right evaluation point EP_R can be labeled using the mask deviation MB_R from the right edge. The misalignment degree MIS_ALGN can refer to the distance between the center MSK_CEN of the circuit pattern of the mask layout and the center CD_CEN of the measured critical dimension of the sample wafer. According to an embodiment, the misalignment degree MIS_ALGN of the mask layout can be inferred by using an additional learning model. In this case, training data for inferring the degree of misalignment of the mask layout can be obtained by labeling a feature vector including optical features, geometric features, and resist features at each evaluation point with a value corresponding to half of the difference (|MB_L-MB_R|) between the mask deviation MB_L from the left edge and the mask deviation MB_R from the right edge of the mask layout.

[0085] Figure 8 is a diagram illustrating a first machine learning model according to some embodiments. Figure 8 The first machine learning model described may correspond to Figure 7 The first machine learning model ML1.

[0086] According to some embodiments, the first machine learning model ML1 may include a (1-1)th machine learning model ML1-1 for inferring a mask bias and a (1-2)th machine learning model ML1-2 for inferring a residual of the inferred mask bias.

[0087] The (1-1) machine learning model ML1-1 can be compared with the reference Figure 6 The same as the first machine learning model ML1 described above. For example, referring to Figure 4 and Figure 8 , the (1-1) machine learning model ML1-1 can be a machine learning model that is trained to infer mask deviations MB1 and MB2 as training data labels TRN_OUT using a training feature vector TRN_IN including optical feature values, geometric feature values, and resist feature values ​​corresponding to the evaluation point EP.

[0088] The (1-2)th machine learning model ML1-2 may be trained using training data obtained by labeling feature vectors using residuals of the inferred mask deviations. The residuals RES of the inferred mask deviations may be the difference between a predicted pattern based on the mask deviations inferred by the (1-1)th machine learning model ML1-1 and a target design layout. Figure 4 and Figure 8 , the (1-2)th machine learning model ML1-2 can be trained using training data labeled with measured EPEs EPE1 and EPE2, which are based on the difference between the predicted pattern (PPC) of the mask deviations MB1 and MB2 inferred by the (1-1)th machine learning model ML1-1 and the circuit pattern TLO of the target design layout. In other words, the (1-2)th machine learning model ML1-2 can receive a training feature vector TRN_IN including optical feature values, geometric feature values, and resist feature values, and can be trained to infer measured EPEs (EPE1 and EPE2) as residuals RES.

[0089] According to some embodiments, the (1-1)th machine learning model ML1-1 for inferring the mask bias may be a machine learning model based on linear regression, and the (1-2)th machine learning model ML1-2 for inferring the residual of the mask bias may be a machine learning model based on nonlinearity. For example, the (1-1)th machine learning model ML1-1 may be a linear regression model, and the (1-2)th machine learning model ML1-2 may be any one of a decision tree model and a random forest model. In this case, the computing device 100 may infer the mask bias more accurately because the (1-1)th machine learning model ML1-1 and the (1-2)th machine learning model ML1-2 have different characteristics.

[0090] 9A to 9D is a diagram showing the optical characteristic vector of the characteristic vector. 9A to 9D The eigenvectors described can correspond to Figure 6 The feature vector FV1 of the first machine learning model ML1 may correspond to Figure 8 At least any one of the training feature vectors TRN_IN of the (1-1)th machine learning model ML1-1 and the (1-2)th machine learning model ML1-2.

[0091] Figure 9A A pattern PPTN of circuit pattern prediction based on the mask layout MLO in an aerial image (AI) is shown.

[0092] An aerial image (AI) is the distribution of light intensity as a function of spatial position through a mask on a wafer. The optical properties of the lithographic apparatus (e.g., light source, mask, and other optical properties) are used to determine the aerial image. Therefore, an aerial image can be formed based on the mask layout by simulating the lithographic process. For example, the computing device 100 can generate the aerial image by applying an optical model, obtained by simulating the optical properties of the lithographic apparatus (which can be a convolution filter), to the mask layout.

[0093] Points within the predicted pattern PPTN of the aerial image may have different intensities. Figure 9A Regarding the intensity of the prediction pattern PPTN, the value of a cross cut intensity plot CCI passing through the evaluation points EPa and EPb and observed in a cross cut perpendicular to the plane of the aerial image (AI) may vary between the evaluation points EPa and EPb.

[0094] Figure 9B is shown in terms of the image pixel's perspective Figure 9A According to some embodiments, the computing device 100 may determine a portion where the value of the cross-sectional intensity map CCI varying between evaluation points EPa and EPb is equal to or greater than a preset threshold value TH as a predicted critical dimension of the prediction pattern PPTN.

[0095] Reference Figure 9C The computing device 100 may use the normalized image logarithmic slope (ILS) at a point corresponding to the edge of the predicted critical dimension in the cross-sectional intensity map CCI as one of the optical features. The image logarithmic slope ILS may be calculated to correspond to each of the evaluation points EPa and EPb. The image logarithmic slope ILS may be calculated based on the following equation 1.

[0096] Equation 1

[0097]

[0098] Reference Figure 9D , the computing device 100 may use the maximum intensity value I_MAX and the minimum intensity value I_MIN in the cross-sectional intensity map CCI as some of the optical features. Alternatively, the ratio of the minimum intensity value I_MIN to the maximum intensity value I_MAX may be used as one of the optical features. Alternatively, the image contrast based on the following equation 2 may be used as one of the optical features. Each of the optical features corresponding to the evaluation points EPa and EPb may be calculated.

[0099] Equation 2

[0100]

[0101] FIG. 10A to FIG. 10B is a diagram showing a resist feature vector of a feature vector. FIG. 10A to FIG. 10B The eigenvectors described can correspond to Figure 6 The feature vector FV1 of the first machine learning model ML1 may correspond to Figure 8 At least any one of the training feature vectors TRN_IN of the (1-1)th machine learning model ML1-1 and the (1-2)th machine learning model ML1-2.

[0102] Figure 10A and Figure 10B Results RI_ACID and RI_GAU obtained by applying the resist model to the pattern PPTN predicted based on the circuit pattern of the mask layout MLO in the resist image (RI) are shown.

[0103] A resist layer on a wafer is exposed, and an aerial image is transferred to the resist layer. The result obtained by transferring the aerial image to the resist layer can be referred to as a resist image RI. The resist image RI can be defined as the available spatial distribution of the resist at the resist layer. In order to calculate the resist image based on the aerial image, a resist model can be used. The resist model can be related only to the properties of the resist layer (e.g., the influence of chemical processes generated in the exposure, post-exposure baking (PEB) and development processes). The resist model can be a model obtained by simulating the acid-quencher reaction of the photoresist based on the properties of a preset resist layer. For example, the computing device 100 can generate a resist image RI by applying a resist core (e.g., an acid core (ACID core), an alkali core (BASE core) or a Gaussian core) to the aerial image. Alternatively, the resist model can be a model obtained by simulating the reaction of the photoresist to light in the extreme ultraviolet wavelength range (EUV) based on the properties at the preset resist layer. In addition to the kernel- or filter-based resist model, the computing device 100 may generate a resist image using a resist model that employs a rigorous modeling scheme to partially simulate variations depending on the PEB process and the development process.

[0104] Reference Figure 10A and Figure 10B , the computing device 100 may use the intensity values ​​corresponding to the evaluation points EPa and EPb in the cross-sectional intensity graph ACID_CCI or GAU_CCI observed in the cross-sectional view passing through the evaluation points EPa and EPb of the resist image RI and perpendicular to the plane of the resist image RI as some of the resist features.

[0105] Figure 11 is a diagram showing the geometric eigenvectors of the eigenvectors. Figure 11 The eigenvectors described can correspond to Figure 6 The feature vector FV1 of the first machine learning model ML1 may correspond to Figure 8 At least any one of the training feature vectors TRN_IN of the (1-1)th machine learning model ML1-1 and the (1-2)th machine learning model ML1-2.

[0106] Figure 11 The circuit patterns POL1, POL2, POL3, and POL4 of the mask layout are shown. The circuit patterns POL1, POL2, POL3, and POL4 may be referred to as "polygons."

[0107] The computing device 100 may calculate geometric properties of at least one polygon associated with a point of view (POV) as a geometric feature vector. The point of view (POV) may correspond to an evaluation point. The geometric properties may include shape, density, length, distance, or hierarchical structure.

[0108] Will refer to Figure 11 Describe the geometric characteristics of polygons by way of examples.

[0109] Reference Figure 11 , the geometric characteristics corresponding to polygons POL1, POL2, POL3, and POL4 within a preset range DST from the viewpoint POV can be calculated in the form of a geometric feature vector. For example, the length LGT of the edge of polygon POL2 located at the viewpoint POV, or the length of segment SEG1, can be included in the geometric features. Each edge of polygons POL1, POL2, POL3, and POL4 can include multiple segments. For example, the edge of polygon POL2 with the viewpoint POV can include multiple segments SEG1, SEG2, and SEG3 divided by virtual partitions DEL1 and DEL2, and the viewpoint POV can be located at segment SEG2, which is any one of the segments SEG1, SEG2, and SEG3.

[0110] In the following, other geometric features will be described.

[0111] The distance from a segment having a viewpoint POV to a polygon adjacent to the segment in a direction perpendicular to the segment may be included in the geometric feature. For example, the distance SPC from a segment SEG2 having a viewpoint POV to a polygon POL3 adjacent to the segment SEG2 in a direction perpendicular to the segment SEG2 may be included in the geometric feature.

[0112] The length of the polygon perpendicular to the edge having the viewpoint POV may be included in the geometric feature. For example, when the edge having the viewpoint POV is an edge disposed in the vertical direction, at least one of the horizontal width WDT1 of the polygon POL1, the horizontal width WDT2 of the polygon POL2, the horizontal width WDT3 of the polygon POL3, and the horizontal width WDT4 of the polygon POL4 may be included in the geometric feature.

[0113] The area of ​​the polygon POL2 having the viewpoint POV may be included in the geometric features.

[0114] The presence of the pattern under the point of view POV may be included in the geometrical features.

[0115] The density of the pattern within the preset range DST from the viewpoint POV may be included in the geometric feature. For example, the relationship between the area of ​​the polygon within the range DST and the area of ​​the range DST may be included in the geometric feature.

[0116] The spatial area and pattern area within the preset visible range VSB from the viewpoint POV can be included in the geometric features. For example, the area of ​​the polygon POL3 corresponding to the visible range VSB and the area of ​​the space not occupied by the polygon in the visible range VSB can be included in the geometric features. Although the reference is made under the assumption that the visible range VSB has a fan shape, Figure 11 The following description is made, but the visible range VSB may have other shapes.

[0117] In addition to reference 9A to 9D 、 Figure 10A and Figure 10B as well as Figure 11 In addition to the described features, computing device 100 may also include another feature into the feature vector.

[0118] For example, the position (upper, lower, right, or left) of the segment SEG2 with the viewpoint POV in the polygon can be included in the feature vector as a geometric feature. Alternatively, the lengths of the segments SEG1 and SEG3 adjacent to the segment SEG2 with the viewpoint POV and the length of the polygon in the direction perpendicular to the segment SEG2 can be included in the feature vector.

[0119] although Figure 11 The geometric features based on the pattern of the Manhattan mask are shown, but the geometric features can also be calculated based on the pattern of a curve mask similar to the Manhattan mask.

[0120] Figure 12A and Figure 12B This is a diagram for describing mask correction using Manhattan masks and curve masks. Figure 12A and Figure 12BThe Manhattan mask and curve mask described can correspond to Figure 1 mask.

[0121] Reference Figure 12A , the computing device 100 may correct the Manhattan mask by shifting each segment of the Manhattan mask by a mask correction amount corresponding to each segment. For example, Figure 12A The Manhattan mask may include multiple evaluation points EP_r1 to EP_ri, to The computing device 100 may store the segments corresponding to the plurality of evaluation points EP_r1 to EP_ri, EP_u1 to EP_uk, and gauges RG1 to RGi, LG1 to LGj, DG1 to DGm, and UG1 to UGk. to Each of the segments corresponding to EP_d1 to EP_dm and EP_u1 to EP_uk, and gauges RG1 to RGi, LG1 to LGj, DG1 to DGm, and UG1 to UGk is moved by the mask correction amount corresponding to each segment. These segments can be moved along the associated gauges. For example, Figure 12A It is shown that the segments corresponding to the two gauges RG1 and RG2 in the Manhattan mask are shifted by the mask correction amounts corresponding to these segments. It can be appreciated that the mask correction amount of the segment corresponding to gauge RG2 is different from the mask correction amount of the segment corresponding to gauge RG1.

[0122] Reference Figure 12B , the computing device 100 can correct the curved mask by moving each of the evaluation points EP1 to EP8 of the curved mask by the relevant mask correction amount. For example, Figure 12B The computing device 100 may move each of the evaluation points EP1 to EP8 of the curved mask by a related mask correction amount along a related gauge among the gauges CG1 to CG8. Figure 12B The mask correction amount associated with each of the two evaluation points EP2 and EP3 being moved is shown. The computing device 100 can generate a corrected mask by generating a spline curve linking the moved evaluation points to each other.

[0123] Figure 13 is a flow chart showing a method for correcting a mask based on EPE correlation. The method for correcting a mask based on EPE correlation can be used to correct a mask, which is determined by Figure 1 The computing device 100 is used to execute. Figure 1 、 Figure 4 and Figure 13 A method for correcting the mask based on EPE correlation is described.

[0124] In S151, the computing device 100 may determine a mask correction amount corresponding to each evaluation point (EP) based on the EPE correlation between the plurality of evaluation points (EP). For example, the computing device 100 may calculate a "cross-MEEF" between the evaluation points and perform calculations based on the "cross-MEEF" and the predicted EPE to determine the mask correction amount.

[0125] For example, the computing device 100 may receive a predicted edge placement error (EPE) corresponding to each of a plurality of evaluation points on a sample wafer manufactured using a mask based on a mask layout. The predicted EPE may be a reference Figure 4 The predicted EPE described in the preceding text can be the difference between the predicted pattern and the pattern of the target design layout. In other words, referring to Figure 4 , the predicted EPE may be distances between prediction points PP1 and PP2 corresponding to the evaluation points EP1 to EP2 of the prediction pattern PPC and target points TP1 to TP2 corresponding to the evaluation points EP1 to EP2 located in the pattern of the target design layout TLO.

[0126] The computing device 100 may infer the EPE correlations between the plurality of evaluation points using a second machine learning model. According to some embodiments, the EPE correlations may be an EPE correlation matrix having a "cross-mean" as an element, where the "cross-mean" is the EPE correlation between two evaluation points from the plurality of evaluation points. For example, the EPE correlation matrix corresponding to N evaluation points may be expressed as Equation 3.

[0127] Equation 3

[0128]

[0129] In Equation 3, “m ij " refers to the "cross-meef" between the evaluation point "i" and the evaluation point "j". The "cross-meef" between the evaluation point "i" and the evaluation point "j" can be inferred by a second machine learning model, which receives at least one of the optical feature value, geometric feature value and resist feature value of the evaluation point "j" and the relative coordinates of the evaluation point "j" relative to the evaluation point "i".

[0130] Reference Figure 14, the second machine learning model ML2 can output the EPE correlation EC_O of each evaluation point by receiving the feature vector FV2, the feature vector FV2 including at least one of the optical feature value, geometric feature value and resist feature value of each evaluation point and the relative coordinates between the multiple evaluation points. The second machine learning model ML2 can be trained by using data obtained by labeling the feature vector with the degree of EPE change of another evaluation point relative to any one of the multiple evaluation points. For example, the partial derivative expression can be used to Training data is obtained by labeling a feature vector that includes at least one of the optical feature value, geometric feature value, and resist feature value of evaluation point "j" and the relative coordinates of evaluation point "j" relative to evaluation point "i." In other words, the feature vector can be labeled with the change EPEi of evaluation point "i" predicted relative to the movement amount "Mj" of evaluation point "j."

[0131] According to some embodiments, the computing device 100 may determine a mask correction amount corresponding to each evaluation point based on the EPE correlation matrix and Equation 4 below.

[0132] Equation 4

[0133] Δmask=-η(A T A) -1 ·A T ·EPE

[0134] In Equation 4, Δmask may refer to the mask correction amount corresponding to each evaluation point, "A" may refer to the EPE correlation matrix of Equation 3, and EPE may be the predicted EPE described above. η may be a damping parameter having a value of "1" or less, which is preset to adjust the mask correction amount for convergence of the mask correction amount.

[0135] Return to reference Figure 13 In S153, the computing device 100 may correct the mask based on the determined mask correction amount. For example, the computing device 100 may move a segment corresponding to each evaluation point of the Manhattan mask, or may move each evaluation point of the curve mask.

[0136] In S155, the computing device 100 may generate a corrected mask based on the moved segments or the moved evaluation points. For example, a mask linking the moved segments may be generated as a corrected Manhattan mask, or a spline curve linking the moved evaluation points may be generated as a corrected curve mask.

[0137] Figure 15 : is a diagram showing a method for determining a mask correction amount. The method for determining a mask correction amount based on EPE correlation can be used to correct the mask, which is Figure 1 Executed by computing device 100.

[0138] In S161, the computing device 100 may receive a predicted EPE corresponding to an evaluation point (EP) of a mask layout. The predicted EPE may be a reference Figure 4 The predicted EPE described in

[0045] The predicted EPE may be the difference between the predicted pattern and the pattern of the target design layout.

[0139] In S163, the computing device 100 may infer the EPE correlation between the evaluation points EP based on the third machine learning model. The third machine learning model may be used in conjunction with the reference Figure 14 The same as described for the second machine learning model. A third machine learning model can be used to infer the EPE correlation as the EPE correlation matrix of Equation 3.

[0140] In S165 , the computing device 100 may determine a mask correction amount corresponding to each evaluation point (EP) based on the EPE correlation matrix and Equation 4.

[0141] Figure 16A The initial mask layout MLOi is shown, Figure 16B shows a mask layout MLOj during a correction process for an initial mask layout MLOi, and Figure 16C FIG shows the mask layout MLOk after the correction of the initial mask layout MLOi is completed. Figure 1 The computing device 100 executes Figure 16A 、 Figure 16B and Figure 16C The process of correcting the initial mask layout MLOi. Figure 16A 、 Figure 16B and Figure 16C The following description is made by providing two evaluation points, but more evaluation points may be provided.

[0142] Reference Figure 16A , the computing device 100 can generate an intermediate mask layout MLOj by correcting the initial mask layout MLOi.

[0143] The computing device 100 can input the feature vectors corresponding to the plurality of evaluation points EP1 and EP2 of the initial mask layout MLOi into the reference Figure 6The computing device 100 may infer a plurality of mask deviations MB1 and MB2 from the first machine learning model described herein. The computing device 100 may generate a predicted pattern PPCi based on the initial mask layout MLOi and the mask deviations MB1 and MB2. The computing device 100 may determine predicted EPEs EPE1 and EPE2 based on the predicted pattern PPCi and the target design layout TLO. According to some embodiments, the predicted EPE may be an EPE correlation matrix based on Equation 3. The computing device 100 may use a reference Figure 14 The computing device 100 may determine mask correction amounts corresponding to the plurality of evaluation points EP1 and EP2 based on the EPE correlation matrix and Equation 4. The computing device 100 may move the plurality of segments constituting the initial mask layout MLOi to correspond to the mask correction amounts.

[0144] The intermediate mask layout MLOj is a mask layout generated based on the result obtained by moving each segment of the initial mask layout MLOi. It can be appreciated that as the segments of the corners C1 to C4 of the initial mask layout MLOi are moved, hammer shapes of the mask layer are added.

[0145] Reference Figure 16B , the computing device 100 can infer mask deviations MB1 and MB2, predicted pattern PPCj, and predicted EPE1 and EPE2 for the intermediate mask layout MLOj, similar to the process for the initial mask layout MLOi. The computing device 100 can determine mask correction amounts corresponding to the plurality of evaluation points EP1 and EP2, and can correct the intermediate mask layout MLOj to determine Figure 16C The final mask layout MLOk.

[0146] Reference Figure 16C , the computing device 100 can infer mask deviations MB1 and MB2, predicted pattern PPCk, and predicted (EPE) EPE1 and EPE2 for the final mask layout MLOk, similar to the process performed for the initial mask layout MLOi. When the predicted EPEs EPE1 and EPE2 are within a preset reference, the computing device 100 can stop mask correction. The extended hammer shape of the intermediate mask layout MLOj can be identified in the final mask layout MLOk.

[0147] Furthermore, it can be appreciated that predicted EPEs EPE1 and EPE2 are reduced at each stage in the order from initial mask layout MLOi to intermediate mask layout MLOj and to final mask layout MLOk in which predicted EPEs EPE1 and EPE2 are less than preset values.

[0148] As described above, in the apparatus and method for correcting a mask of the present disclosure, a desired circuit pattern can be formed on a wafer more accurately.

[0149] According to the apparatus and method for correcting a mask of the present disclosure, a mask used in a process for manufacturing a semiconductor device can be quickly corrected.

[0150] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope that can be claimed, but rather as descriptions of features that can be specific to a specific embodiment of a specific invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be removed from the combination in some cases, and a combination may be directed to a sub-combination or a variation of a sub-combination.

[0151] The above description relates to detailed embodiments for carrying out the present disclosure. Embodiments in which the design is simply changed or easily changed may be included in the present disclosure as well as the above-mentioned embodiments. In addition, technologies that are easily changed and implemented by using the above-mentioned embodiments may be included in the present disclosure. Therefore, the scope of the present disclosure is not limited to the above-mentioned embodiments, but is defined by the appended claims and their equivalents.

[0152] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A method for calibrating a photomask, the method comprising: receiving a target design layout of a semiconductor device; inferring, by at least one processor, mask deviations by inputting optical feature values, geometric feature values, and resist feature values ​​of a mask layout based on the target design layout into a first machine learning model; generating, by the at least one processor, a predicted pattern by incorporating the mask deviation into the mask layout; comparing, by the at least one processor, the predicted pattern to the target design layout; as well as The mask layout is corrected by the at least one processor based on a comparison result between the predicted pattern and the target design layout.

2. The method according to claim 1, wherein The target design layout is based on at least one of a post-cleaning inspection design layout and a post-development inspection design layout.

3. The method according to claim 1, wherein The mask layout includes at least one of a straight line pattern and a curved line pattern.

4. The method according to claim 3, further comprising: inferring, by the at least one processor, the mask deviation corresponding to an evaluation point of the mask layout; as well as The predicted pattern is generated by the at least one processor by changing a position of a segment corresponding to the evaluation point of the straight line pattern or a position of the evaluation point of the curved line pattern based on the mask deviation.

5. The method according to claim 4, further comprising: determining, by the at least one processor, a mask correction amount corresponding to a plurality of evaluation points based on correlations of edge placement errors between the plurality of evaluation points; changing, by the at least one processor, a position of the segment corresponding to the evaluation point of the straight pattern or a position of the evaluation point of the curved pattern to correspond to the mask deviation; as well as A corrected mask layout is generated by the at least one processor based on the segments or the evaluation points having the changed positions.

6. The method according to claim 5, wherein: The dependencies of the edge placement error include: the change in edge placement error of the second evaluation point caused by the change in position of the first evaluation point, and The multiple evaluation points include the first evaluation point and the second evaluation point.

7. The method according to claim 5, further comprising: calculating, by the at least one processor, the edge placement error corresponding to the evaluation point based on the target design layout, the mask layout, and the mask deviation; as well as A second machine learning model is used by the at least one processor to infer correlations of the edge placement errors between the plurality of evaluation points.

8. The method according to claim 7, wherein: The second machine learning model is trained using data obtained by labeling a feature vector with a degree of change in edge placement error due to movement of the second evaluation point relative to the first evaluation point, the feature vector including at least one of the optical feature value, the geometric feature value, and the resist feature value corresponding to the first evaluation point, and relative coordinates between the first evaluation point and the second evaluation point.

9. The method according to claim 1, wherein Inferring the mask deviation includes: A feature vector including the optical feature value, the geometric feature value, and the resist feature value is input into the first machine learning model in the form of numerical values.

10. The method according to claim 9, wherein: The optical characteristic value corresponds to an evaluation point of the mask layout, is calculated from an aerial image based on the mask layout, and includes at least one of a maximum intensity value and a minimum intensity value of an image logarithmic slope at the evaluation point.

11. The method according to claim 9, wherein: The resist characteristic value corresponds to an evaluation point of the mask layout, is calculated from a resist image based on the mask layout, and is based on an acid-quencher reaction of the photoresist at the evaluation point.

12. The method according to claim 9, wherein The resist characteristic value corresponds to an evaluation point of the mask layout, is calculated from a resist image based on the mask layout, and is based on a response of the photoresist at the evaluation point to light of an extreme ultraviolet wavelength.

13. The method according to claim 1, wherein The first machine learning model includes: a second machine learning model for receiving a feature vector comprising at least one of the optical feature value, the geometric feature value, and the resist feature value and for inferring a first mask deviation based on linear regression; and A third nonlinear-based machine learning model is used to infer the residuals of the first mask bias.

14. The method according to claim 13, wherein The residual is a difference between the predicted pattern based on the first mask deviation and the target design layout.

15. A method for generating a photomask correction model, the method comprising: receiving a mask layout for a semiconductor device; receiving measurement data of a wafer manufactured using a mask based on the mask layout; as well as A first machine learning model is trained by at least one processor using training data obtained by labeling optical feature values, geometric feature values, and resist feature values ​​of the mask layout with mask deviations based on the measurement data.

16. The method according to claim 15, wherein The measurement data is based on wafer measurement data obtained after a photolithography process is completed or based on wafer measurement data obtained after an etching process is completed.

17. The method according to claim 15, wherein: The mask deviation is based on at least one of the mask layout, a measured edge placement error, and a measured critical dimension measured on the wafer.

18. The method according to claim 17, wherein The mask deviation is based on a distance between at least one of a pattern profile of a post-development inspection image and a pattern profile of a post-cleaning inspection image of the wafer and an evaluation point of the mask layout, or based on a difference between the measured critical dimension and a dimension of the mask layout.

19. A method for determining a photomask correction amount, the method comprising: receiving an edge placement error corresponding to each of a plurality of evaluation points on a wafer manufactured using a mask based on a mask layout of a semiconductor device; using, by at least one processor, a machine learning model to infer edge placement error correlations between the plurality of evaluation points; as well as determining, by the at least one processor, the photomask correction amount of the mask layout based on the edge placement error correlation and the edge placement error corresponding to each of the plurality of evaluation points, The following data is used to train the machine learning model: The data is data obtained by labeling a feature vector using a degree of change in edge placement error caused by movement of one of the plurality of evaluation points relative to another evaluation point, the feature vector including at least one of an optical feature value, a geometric feature value, and a resist feature value corresponding to each of the plurality of evaluation points, and relative coordinates between the plurality of evaluation points.

20. The method according to claim 19, further comprising: adjusting, by the at least one processor, the photomask correction amount of the mask layout based on a preset damping parameter, The preset damping parameter reduces a magnitude of at least one of the photomask correction amounts corresponding to each of the plurality of evaluation points.

Images