Method and system for generating and optimizing CUDA (Compute Unified Device Architecture) code based on multi-dimensional feature search and enhancement

Abstract

The invention provides a CUDA code generation and optimization method and system for multi-dimensional feature search and enhancement, and the method comprises the steps: generating an initial CUDA code through a large language model based on task description and GPU hardware parameters; executing triple verification and a feedback mechanism on the initial CUDA code; according to feedback information of triple verification, optimizing CUDA codes through multi-dimensional feature search; based on error information, adjusting large language model input to regenerate codes; dynamically selecting an optimization strategy based on a performance index, wherein the optimization strategy comprises a thread block size and a memory access mode; and iteratively executing the steps until the CUDA code which passes triple verification and meets the target performance is generated. According to the method, the code features of the CUDA code are analyzed, and a triple verification and feedback mechanism including compilation feasibility, logic correctness and performance during execution is formed, so that an automatic evaluation process of the CUDA code is realized, and the problems that the CUDA code optimization process is difficult to be automated and an optimization target is lacked in the CUDA code optimization process are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance computing and automatic program generation, and in particular to a CUDA code generation and optimization method and system for multi-dimensional feature search and enhancement. Background Art

[0002] To enable large language models to generate efficient and usable CUDA code, various translation methods based on large language models have been proposed. These methods attempt to improve the accuracy of generated code from various perspectives, such as model fine-tuning and evolutionary computation.

[0003] Existing technology uses a large language model to automatically convert PyTorch high-level expressions into CUDA kernel code to evaluate the model's application potential in the field of high-performance computing; it built the first AICUDA engineer, introduced mechanisms such as "crossover operations" in evolutionary computing, and explored potential efficient kernel structures in the search space, thereby improving the quality of generated code; by fine-tuning the large language model, it improved its success rate in converting PyTorch to CUDA code.

[0004] Patent document CN119025090A discloses a code generation method, apparatus, computer device, computer-readable storage medium, and computer program product. The method comprises: obtaining variable parameters and generating corresponding initialization variables based on the variable parameters; obtaining a target expression based on a variable configuration operation for the initialization variables; obtaining code configuration information and generating corresponding code snippets based on the code configuration information and the target expression; and obtaining target code based on the combination of the code snippets. Although the above method has made progress in translating PyTorch code into CUDA code, its generation process relies on the provided PyTorch code and does not optimize the generated CUDA code for target hardware parameters. This leads to problems such as difficulty in automating the CUDA code optimization process and a lack of optimization targets during the CUDA code optimization process. Furthermore, the error rate and performance of directly generating CUDA code from a large language model are too high.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0006] In view of the defects in the prior art, the purpose of the present invention is to provide a CUDA code generation and optimization method and system with multi-dimensional feature search and enhancement.

[0007] According to the present invention, a CUDA code generation and optimization method for multi-dimensional feature search and enhancement is provided, the method comprising the following steps:

[0008] Step S1: Generate initial CUDA code through the large language model based on the task description and GPU hardware parameters;

[0009] Step S2: Performing a triple verification and feedback mechanism on the initial CUDA code: Compilation feasibility verification: Checking whether the code can be compiled. If it fails, a compilation error message is returned; Logical correctness verification: Verifying the correctness of the code output result. If it fails, a logical error message is returned; Execution performance verification: Measuring runtime performance indicators. If it does not meet expectations, performance optimization suggestions are returned.

[0010] Step S3: Based on the feedback from the triple verification, the CUDA code is optimized through multi-dimensional feature search: the large language model input is adjusted based on the error information and the code is regenerated; the optimization strategy is dynamically selected based on performance indicators, including thread block size and memory access mode;

[0011] Step S4: iteratively execute steps S2 to S3 until a CUDA code that passes triple verification and meets target performance is generated.

[0012] Preferably, the triple verification and feedback mechanism in step S2 is performed in the following order: first, compilation feasibility verification is performed, and then logic correctness verification is performed after passing both verifications, and then execution performance verification is performed after both verifications pass;

[0013] The logic correctness verification adopts differential testing: comparing the CUDA code output with the results of the benchmark implementation, and locating the error code position when the output is inconsistent;

[0014] The indicators of the performance verification during execution include: at least two of: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

[0015] Preferably, the multi-dimensional feature search optimization in step S3 specifically includes: constructing a multi-dimensional search space based on hardware parameters, where the dimensions include thread block dimensions, shared memory configuration, and instruction pipeline strategy.

[0016] The selection optimization strategy includes: matching optimization operations according to performance bottleneck types; adjusting global memory merging access modes when there is a memory bottleneck; and enabling loop unrolling or instruction-level parallel optimization when there is a computational bottleneck.

[0017] The feedback information is processed using an incremental prompting process: compilation error information, logic error locations, and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

[0018] Preferably, the method further comprises: constructing a historical decision knowledge base during the iterative optimization process, recording the code feature-optimization strategy mapping relationship for subsequent search.

[0019] Preferably, the GPU hardware parameters in step S1 include: number of SMs, register capacity of each SM, shared memory size, memory bus width, and computing capability version.

[0020] The present invention also provides a CUDA code generation and optimization system for multi-dimensional feature search and enhancement, the system comprising the following modules:

[0021] Module M1: Generates initial CUDA code based on the task description and GPU hardware parameters through a large language model;

[0022] Module M2: performs a triple verification and feedback mechanism on the initial CUDA code: compilation feasibility verification: checks whether the code can be compiled, and returns a compilation error message if it fails; logical correctness verification: verifies the correctness of the code output results, and returns a logical error message if it fails; execution performance verification: measures runtime performance indicators, and returns performance optimization suggestions if it does not meet expectations;

[0023] Module M3: Based on the feedback from triple verification, optimizes CUDA code through multi-dimensional feature search: adjusts the large language model input based on error information and regenerates code; dynamically selects optimization strategies based on performance indicators, including thread block size and memory access mode;

[0024] Module M4: Iteratively calls module M2-module M3 until CUDA code that passes triple verification and meets the target performance is generated.

[0025] Preferably, the triple verification and feedback mechanism in the module M2 is performed in the following order: first, compilation feasibility verification is performed, and then logic correctness verification is performed after both are passed, and then execution performance verification is performed after both are passed;

[0026] The logic correctness verification adopts differential testing: comparing the CUDA code output with the results of the benchmark implementation, and locating the error code position when the output is inconsistent;

[0027] The indicators of the performance verification during execution include: at least two of: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

[0028] Preferably, the multi-dimensional feature search optimization in the module M3 specifically includes: constructing a multi-dimensional search space based on hardware parameters, where the dimensions include thread block dimensions, shared memory configuration, and instruction pipeline strategy.

[0029] The selection optimization strategy includes: matching optimization operations according to performance bottleneck types; adjusting global memory merging access modes when there is a memory bottleneck; and enabling loop unrolling or instruction-level parallel optimization when there is a computational bottleneck.

[0030] The feedback information is processed using an incremental prompting process: compilation error information, logic error locations, and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

[0031] Preferably, the system further comprises: constructing a historical decision knowledge base during the iterative optimization process to record the mapping relationship between code features and optimization strategies for subsequent searches.

[0032] Preferably, the GPU hardware parameters in the module M1 include: number of SMs, register capacity of each SM, shared memory size, memory bus width, and computing capability version.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. This invention analyzes the code features of CUDA code to form a triple verification and feedback mechanism including compilation feasibility, logical correctness, and execution performance, thereby realizing an automated evaluation process for CUDA code and solving the problems of difficulty in automating the CUDA code optimization process and lack of optimization targets in the CUDA code optimization process.

[0035] 2. This invention further optimizes CUDA code based on the feedback information from the triple verification and feedback mechanism, forming a targeted automated CUDA code optimization process. Experimental results show that this framework significantly improves the compilation feasibility and logical correctness of CUDA code generated by large language models, significantly improving execution performance, and resolving the high error rate and poor performance of CUDA code generated directly from large language models.

[0036] 3. The present invention enables the CUDA code generated by the large language model to have a high functional accuracy and extremely high execution performance, which is far better than the effect of directly using the large language model to generate CUDA code. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0038] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0040] Example 1:

[0041] Reference Figure 1 According to the present invention, a CUDA code generation and optimization method for multi-dimensional feature search and enhancement is provided, the method comprising the following steps:

[0042] Step S1: Generate initial CUDA code through a large language model based on the task description and GPU hardware parameters; GPU hardware parameters include: number of SMs, register capacity per SM, shared memory size, memory bus width, and computing capability version.

[0043] Step S2: Execute triple verification and feedback mechanism on the initial CUDA code: compilation feasibility verification: detect the compilability of the code, and return compilation error information if it fails; logic correctness verification: verify the correctness of the code output result, and return logic error information if it fails; execution performance verification: measure the runtime performance indicators, and return performance optimization suggestions if it does not meet expectations; the order of the triple verification and feedback mechanism is: first perform compilation feasibility verification, then perform logic correctness verification after passing, and then perform execution performance verification after both pass; logic correctness verification uses differential testing: compare the CUDA code output with the results of the benchmark implementation, and locate the error code position when the output is inconsistent; the indicators of execution performance verification include: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

[0044] Code compilability verification: After obtaining the CUDA code generated by the large language model, compile the code using the corresponding compiler on the hardware platform. If the compilation passes, the CUDA code is compilable. If errors occur during the compilation process, the code is not compilable.

[0045] Verify the correctness of code output: In this phase, several sets of input and output test cases generated by the relevant Python code are used. The output of the CUDA code based on the input of each test case is compared with the output provided by the test case. When the output of the CUDA code is consistent with the output of the test case, the code output is correct.

[0046] Runtime performance measurement: Use performance measurement tools (such as Nsight System) to monitor the execution of CUDA code. When the CUDA code finishes running, the corresponding performance measurement tool will output a variety of performance verification metrics, including kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

[0047] Step S3: Based on the feedback information from the triple verification, the CUDA code is optimized through multi-dimensional feature search: the large language model input is adjusted based on the error information to regenerate the code; the optimization strategy is dynamically selected based on performance indicators, including thread block size and memory access mode; the multi-dimensional feature search optimization specifically includes: constructing a multi-dimensional search space based on hardware parameters, with dimensions including thread block dimension, shared memory configuration, and instruction pipeline strategy; selecting the optimization strategy includes: matching optimization operations according to the performance bottleneck type; adjusting the global memory merge access mode when there is a memory bottleneck; enabling loop unrolling or instruction-level parallel optimization when there is a computing bottleneck; the feedback information is processed using incremental prompt engineering: the compilation error information, logical error location and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

[0048] First, a multidimensional search space constructed based on hardware parameters is used to develop optimization strategies for corresponding performance bottlenecks. For example, thread block dimensions, shared memory configuration and access methods, and instruction-level parallel optimization strategies are adjusted based on the actual hardware conditions. After obtaining feedback, performance bottlenecks in the CUDA code can be analyzed and corresponding optimization strategies selected. Second, the feedback is converted into structured prompts and appended to the large language model input. This provides the large language model with a selected optimization strategy, and the large language model undergoes a new CUDA code generation process.

[0049] Step S4: Iterate steps S2 and S3 until CUDA code is generated that passes triple verification and meets the target performance. Iteration termination conditions include reaching the target performance threshold, the performance improvement rate for three consecutive iterations being less than 5%, or the total number of iterations exceeding a preset upper limit.

[0050] The multi-dimensional feature search and enhanced CUDA code generation and optimization method also includes: building a historical decision knowledge base during the iterative optimization process to record the code feature-optimization strategy mapping relationship for subsequent search.

[0051] During the iterative optimization process, the characteristics of the CUDA code generated by the large language model and the corresponding optimization strategies are recorded and used to build a historical decision knowledge base. In subsequent iterative optimization processes, the code characteristic-optimization strategy mappings recorded in the knowledge base will be used as part of the large language model's input to guide its specific optimization behavior for CUDA code.

[0052] The present invention also provides a multi-dimensional feature search and enhanced CUDA code generation and optimization system. The multi-dimensional feature search and enhanced CUDA code generation and optimization system can be implemented by executing the process steps of the multi-dimensional feature search and enhanced CUDA code generation and optimization method. That is, those skilled in the art can understand the multi-dimensional feature search and enhanced CUDA code generation and optimization method as an optimal implementation method of the multi-dimensional feature search and enhanced CUDA code generation and optimization system.

[0053] Example 2:

[0054] The present invention also provides a CUDA code generation and optimization system for multi-dimensional feature search and enhancement, the system comprising the following modules:

[0055] Module M1: Generates initial CUDA code through a large language model based on the task description and GPU hardware parameters; GPU hardware parameters include: number of SMs, register capacity per SM, shared memory size, memory bus width, and computing capability version.

[0056] Module M2: Execute triple verification and feedback mechanism on the initial CUDA code: Compilation feasibility verification: detect the compilability of the code, and return a compilation error message if it fails; Logical correctness verification: verify the correctness of the code output result, and return a logical error message if it fails; Execution performance verification: measure the runtime performance indicators, and return performance optimization suggestions if it does not meet expectations; the order of the triple verification and feedback mechanism is: first perform compilation feasibility verification, then perform logical correctness verification after passing, and then perform execution performance verification after both pass; Logical correctness verification uses differential testing: compare the CUDA code output with the results of the benchmark implementation, and locate the error code position when the output is inconsistent; the indicators of execution performance verification include: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency. At least two of them.

[0057] Module M3: Based on the feedback information from triple verification, CUDA code is optimized through multi-dimensional feature search: the large language model input is adjusted based on the error information to regenerate the code; the optimization strategy is dynamically selected based on performance indicators, including thread block size and memory access mode; multi-dimensional feature search optimization specifically includes: building a multi-dimensional search space based on hardware parameters, with dimensions including thread block dimension, shared memory configuration, and instruction pipeline strategy; selecting optimization strategies includes: matching optimization operations according to performance bottleneck types; adjusting global memory merge access mode when there is a memory bottleneck; enabling loop unrolling or instruction-level parallel optimization when there is a computing bottleneck; feedback information is processed using incremental prompt engineering: compilation error information, logical error locations, and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

[0058] Module M4: Iteratively calls module M2-module M3 until CUDA code is generated that passes triple verification and meets the target performance. The conditions for iteration termination include: reaching the target performance threshold, the performance improvement rate for three consecutive iterations is less than 5%, or the total number of iterations exceeds the preset upper limit.

[0059] The multi-dimensional feature search and enhanced CUDA code generation and optimization system also includes: building a historical decision knowledge base during the iterative optimization process to record the code feature-optimization strategy mapping relationship for subsequent searches.

[0060] Example 3:

[0061] Based on the analysis of CUDA code characteristics (including post-compilation execution and dependence on hardware parameters), this paper constructs a triple verification and feedback mechanism that includes compilation feasibility, logical correctness, and execution performance. Based on the output of the triple verification and feedback mechanism and the CUDA code enhancement goals, a CUDA code generation and optimization framework based on multi-dimensional feature search and enhancement is constructed. Through this framework, the CUDA code generated by the large language model can have a high functional accuracy and extremely high execution performance, which is far superior to the effect of directly using the large language model to generate CUDA code.

[0062] This technology includes a triple verification and feedback mechanism for evaluating CUDA code and a CUDA code generation and optimization framework based on multi-dimensional feature search and enhancement. The flowchart is shown in the figure below. Figure 1 shown.

[0063] Triple verification and feedback mechanism. To test the CUDA code generated by the large language model, we first implemented a triple verification and feedback mechanism. This part includes three evaluation indicators: compilation feasibility, logical correctness, and execution performance. The CUDA code generated by the large language model will first undergo compilation feasibility verification. If the verification fails, the triple verification and feedback mechanism will output feedback information including compilation error information. If the compilation feasibility verification passes, the logical correctness verification part will be entered to verify whether the output of the CUDA code generated by the large language model is correct. If the logical correctness verification fails, the triple verification and feedback mechanism will output logical error feedback. If the logical correctness verification passes, the execution performance, such as execution time, will be measured. The execution performance will be used to guide the subsequent optimization process. If the performance does not meet expectations, the triple verification and feedback mechanism will output feedback information related to the optimization performance.

[0064] CUDA code generation and optimization framework. Based on the triple verification and feedback mechanism, we implemented a CUDA code generation and optimization framework based on multi-dimensional feature search and enhancement. The input of the framework is the task description of the target CUDA code and the GPU hardware information, and the output is N candidate CUDA codes. The candidate code will be passed to the triple verification and feedback mechanism. If the candidate code fails to pass the compilation feasibility verification or the logical correctness verification, the error message will be attached to the input of the large language model so that the large language model can regenerate the CUDA code and conduct a new round of verification. If the candidate code passes the compilation feasibility verification or the logical correctness verification, the performance data during execution will be measured and used to select appropriate CUDA code optimization strategies (such as adjusting the thread block size, memory access mode, etc.). When the optimized CUDA code reaches the target performance, the iterative process stops and the CUDA code at this time is output as the framework.

[0065] By analyzing the code features of CUDA code, the present invention forms a triple verification and feedback mechanism including compilation feasibility, logical correctness, and execution performance, thereby realizing an automated evaluation process for CUDA code and solving the problems of difficulty in automating the CUDA code optimization process and lack of optimization targets in the CUDA code optimization process.

[0066] This invention further optimizes CUDA code based on feedback from the triple validation and feedback mechanism, forming a targeted automated CUDA code optimization process. Experimental results demonstrate that this framework significantly improves the compilation feasibility and logical correctness of CUDA code generated by large language models, significantly improving execution performance. This addresses the high error rate and poor performance associated with directly generating CUDA code from large language models.

[0067] This paper investigates how to generate efficient CUDA code from a large language model without reference code. It also investigates how to further optimize the performance of the CUDA code generated by the large language model based on given hardware parameters. It implements a triple verification and feedback mechanism, encompassing compilation feasibility, logical correctness, and runtime performance, as well as a CUDA code generation and optimization framework based on multi-dimensional feature search and enhancement. This framework enables the CUDA code generated by the large language model to have high functional accuracy and exceptional runtime performance, far superior to directly generating CUDA code from the large language model.

[0068] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1 and Embodiment 2.

[0069] Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, and units provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same functions of the system and its various devices, modules, and units provided by the present invention in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; the devices, modules, and units for implementing various functions can also be considered as both software modules implementing the method and structures within the hardware component.

[0070] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A CUDA code generation and optimization method for multi-dimensional feature search and enhancement, characterized in that: The method comprises the following steps: Step S1: Generate initial CUDA code through the large language model based on the task description and GPU hardware parameters; Step S2: Performing a triple verification and feedback mechanism on the initial CUDA code: Compilation feasibility verification: Checking whether the code can be compiled. If it fails, a compilation error message is returned; Logical correctness verification: Verifying the correctness of the code output result. If it fails, a logical error message is returned; Execution performance verification: Measuring runtime performance indicators. If it does not meet expectations, performance optimization suggestions are returned. Step S3: Based on the feedback information from the triple verification, the CUDA code is optimized through multi-dimensional feature search: the large language model input is adjusted based on the error information and the code is regenerated; Dynamically select optimization strategies based on performance metrics, including thread block size and memory access patterns; Step S4: iteratively execute steps S2 to S3 until a CUDA code that passes triple verification and meets target performance is generated.

2. The CUDA code generation and optimization method for multi-dimensional feature search and enhancement according to claim 1, characterized in that: The triple verification and feedback mechanism in step S2 is performed in the following order: first, compilation feasibility verification is performed, then logical correctness verification is performed after passing, and then execution performance verification is performed after both pass. The logic correctness verification adopts differential testing: comparing the CUDA code output with the results of the benchmark implementation, and locating the error code position when the output is inconsistent; The indicators of the performance verification during execution include: at least two of: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

3. The CUDA code generation and optimization method for multi-dimensional feature search and enhancement according to claim 1, characterized in that: The multi-dimensional feature search optimization in step S3 specifically includes: constructing a multi-dimensional search space based on hardware parameters, where the dimensions include thread block dimensions, shared memory configuration, and instruction pipeline strategy; The selection optimization strategy includes: matching optimization operations according to performance bottleneck types; adjusting global memory merging access mode when there is a memory bottleneck; enabling loop unrolling or instruction-level parallel optimization when there is a computational bottleneck; The feedback information is processed using an incremental prompting process: compilation error information, logic error locations, and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

4. The CUDA code generation and optimization method for multi-dimensional feature search and enhancement according to claim 1, characterized in that: The method further comprises: constructing a historical decision knowledge base during the iterative optimization process, recording a code feature-optimization strategy mapping relationship for use in subsequent searches.

5. The CUDA code generation and optimization method for multi-dimensional feature search and enhancement according to claim 1, characterized in that: The GPU hardware parameters in step S1 include: number of SMs, register capacity of each SM, shared memory size, memory bus width, and computing capability version.

6. A CUDA code generation and optimization system with multi-dimensional feature search and enhancement, characterized in that: The system includes the following modules: Module M1: Generates initial CUDA code based on the task description and GPU hardware parameters through a large language model; Module M2: performs a triple verification and feedback mechanism on the initial CUDA code: compilation feasibility verification: checks whether the code can be compiled, and returns a compilation error message if it fails; logical correctness verification: verifies the correctness of the code output results, and returns a logical error message if it fails; execution performance verification: measures runtime performance indicators, and returns performance optimization suggestions if it does not meet expectations; Module M3: Based on the feedback from triple verification, optimizes CUDA code through multi-dimensional feature search: adjusts the large language model input based on error information and regenerates code; dynamically selects optimization strategies based on performance indicators, including thread block size and memory access mode; Module M4: Iteratively calls module M2-module M3 until CUDA code that passes triple verification and meets the target performance is generated.

7. The CUDA code generation and optimization system for multi-dimensional feature search and enhancement according to claim 6, characterized in that: The triple verification and feedback mechanism in the module M2 is performed in the following order: first, compilation feasibility verification is performed, then logical correctness verification is performed after passing both verifications, and then execution performance verification is performed after both verifications pass. The logic correctness verification adopts differential testing: comparing the CUDA code output with the results of the benchmark implementation, and locating the error code position when the output is inconsistent; The indicators of the performance verification during execution include: at least two of: kernel function execution time, memory bandwidth utilization, register occupancy, and branch prediction efficiency.

8. The CUDA code generation and optimization system for multi-dimensional feature search and enhancement according to claim 6, characterized in that: The multi-dimensional feature search optimization in the module M3 specifically includes: constructing a multi-dimensional search space based on hardware parameters, the dimensions of which include thread block dimensions, shared memory configuration, and instruction pipeline strategy; The selection optimization strategy includes: matching optimization operations according to performance bottleneck types; adjusting global memory merging access mode when there is a memory bottleneck; enabling loop unrolling or instruction-level parallel optimization when there is a computational bottleneck; The feedback information is processed using an incremental prompting process: compilation error information, logic error locations, and performance bottleneck data are converted into structured prompt words and appended to the large language model input.

9. The CUDA code generation and optimization system for multi-dimensional feature search and enhancement according to claim 6, characterized in that: The system also includes: building a historical decision knowledge base during the iterative optimization process to record the code feature-optimization strategy mapping relationship for subsequent search.

10. The CUDA code generation and optimization system for multi-dimensional feature search and enhancement according to claim 6, characterized in that: The GPU hardware parameters in the module M1 include: number of SMs, register capacity of each SM, shared memory size, memory bus width, and computing capability version.

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