FPGA self-excitation signal detection method and device based on signal feedback loop

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) self-excitation signal detection method and device based on a signal feedback loop, and the method comprises the steps: firstly, reading a received FPGA hardware description language code file, and integrating all modules in an FPGA code to form an overall code file from top to bottom; secondly, mapping the overall code file of the FPGA into a signal transmission network according to a transmission relationship among signals in the overall code file of the FPGA; and thirdly, searching all signal feedback loops in the signal transmission network, calculating signal feedback probabilities, selecting and recording the signal feedback loops of which the signal feedback probabilities are greater than a set threshold, and extracting signals in the signal feedback loops as self-excitation signals to be output. According to the method, the self-excitation signal in the FPGA design and the occurrence probability of the self-excitation signal can be effectively detected, the method is easy to use and low in investment cost, and the requirement for self-excitation signal detection when the triple modular redundancy design is carried out can be well met.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA testing technology, and in particular to a method and device for detecting an FPGA self-excitation signal based on a signal feedback loop. Background Art

[0002] In recent years, SRAM-based FPGAs have been widely used in various fields due to their unique reconfigurability, low latency, real-time processing, and high parallel computing capabilities. However, FPGAs are highly sensitive to space particle radiation and are prone to single-event upsets (SEEs), which can cause logic failures and signal output errors. Therefore, it is crucial to implement fault-tolerant designs in FPGAs to prevent such failures. Triple-module redundancy (TMR) design, for example, implements three identical modules within the FPGA. If one module fails, the other two modules can continue to function, maintaining normal FPGA operation. Therefore, due to its simplicity and reliability, TMR design is widely used in FPGA SEE fault-tolerant designs.

[0003] While triple-module redundancy (TMR) design can effectively improve the reliability of FPGA designs, it incurs significant additional resources and power consumption. TMR is typically implemented only for logic modules that process critical signals within an FPGA. Self-excitation signals are a special type of signal within an FPGA. Their output can potentially affect the signal itself through a feedback loop. This means that once an error occurs in such a signal, the impact can persist for a long time, or even be permanent. Therefore, fault-tolerance design for such signals is particularly important, and TMR is typically implemented for logic modules that process these signals. However, currently, there are no mature methods in the industry to accurately detect self-excitation signals. As FPGAs grow larger and incorporate more signals, detecting self-excitation signals becomes increasingly difficult. In particular, due to limited FPGA resources, fault-tolerance design is typically limited to signals with a higher probability of self-excitation. Therefore, estimating the probability of self-excitation after identifying the self-excitation signal is even more challenging. Patent CN114692551A discloses a method for detecting safety-critical signals in Verilog design files. This method can detect safety-critical signals in FPGAs based on Verilog designs. However, this method defines safety-critical signals based on the number of signals affected by the signal and is not suitable for detecting self-excited signals.

[0004] In order to meet the need for accurate detection of self-excited signals in FPGA triple-module redundancy (TMR) design, it is urgent to propose an effective technical means that can not only effectively detect potential self-excited signals in FPGA design, but also estimate the probability of self-excited occurrence of each self-excited signal, and provide effective guidance for FPGA developers to select self-excited signal-related logic modules for triple-module redundancy (TMR) design, thereby improving the quality and reliability of FPGA design. Summary of the Invention

[0005] The purpose of the present invention is to address the problem that under current technical conditions, there is currently no effective method in the industry that can accurately detect potential self-excitation signals in FPGA designs and provide the probability of self-excitation. Therefore, a method and device for detecting FPGA self-excitation signals based on a signal feedback loop are proposed. The method and device can effectively detect self-excitation signals in FPGA designs and their probability of occurrence, and are simple to use and have a low investment cost. They can well meet the needs of self-excitation signal detection when carrying out triple-module redundancy (TMR) design.

[0006] The technical solution for achieving the purpose of the present invention is as follows: In a first aspect, the present invention provides an FPGA self-excitation signal detection method based on a signal feedback loop, comprising the following steps:

[0007] Step 1: Read the received FPGA hardware description language code file, integrate the modules in the FPGA hardware description language code, and form a top-down overall code file;

[0008] Step 2: Map the FPGA overall code file into a signal transmission network based on the transmission relationship between the various signals in the FPGA overall code file;

[0009] Step 3: Find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold;

[0010] Step 4: extract the signal in the signal feedback loop and output it as a self-excited signal.

[0011] In a second aspect, the present invention provides an FPGA self-excitation signal detection device based on a signal feedback loop, for implementing the method described in the first aspect, the device comprising:

[0012] The signal transmission network generation module is used to read the received FPGA hardware description language code file, form a top-down overall code file and map it into a signal transmission network;

[0013] A signal feedback loop detection module is used to find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold;

[0014] The self-excitation signal output module is used to extract and output the self-excitation signal of the FPGA according to the signal feedback loop.

[0015] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to the first aspect when executing the program.

[0016] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0017] In a fifth aspect, the present invention provides a computer program product, comprising a computer program, which implements the steps of the method described in the first aspect when executed by a processor.

[0018] Compared with the prior art, the present invention has the following advantages: 1) the method of the present invention can accurately detect the self-excitation signal in the FPGA design and estimate the probability of its self-excitation; 2) the method of the present invention has low implementation difficulty, high detection efficiency, low investment cost, and strong practicality; 3) the method of the present invention can be easily implemented by computer, which can further improve the detection efficiency of the self-excitation signal of the FPGA design.

[0019] The present invention is further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a flow chart of the FPGA self-excitation signal detection method based on the signal feedback loop proposed by the present invention.

[0021] Figure 2 This is an FPGA hardware description language code example.

[0022] Figure 3 An example of instantiating a module code.

[0023] Figure 4 This is an example of the integrated FPGA hardware description language code.

[0024] Figure 5 An instance of the extracted signal list.

[0025] Figure 6 This is an example of calculating the probability of a directed edge.

[0026] Figure 7 This is an example of a signal transmission network.

[0027] Figure 8 An example of signal feedback probability for the transmission loop.

[0028] Figure 9 This is a schematic diagram of the FPGA self-excitation signal detection device based on the signal feedback loop proposed by the present invention. DETAILED DESCRIPTION

[0029] Combine Figure 1 The present invention proposes a method for detecting FPGA self-excitation signals based on a signal feedback loop, which specifically includes the following steps:

[0030] Step 1: Read the received FPGA hardware description language code file and integrate the various modules in the FPGA code to form a top-down overall code file;

[0031] Step 2: Map the FPGA overall code file into a signal transmission network based on the transmission relationship between the various signals in the FPGA overall code file;

[0032] Step 21: Find and record all signals defined in the FPGA overall code file, and build a corresponding signal transmission network. Each signal in the FPGA corresponds to a node in the signal transmission network.

[0033] Step 22: Find all right-link assignment statements for FPGA signals, that is, assignment statements that satisfy the right-side expression containing the signal, and record all right-link assignment statements whose right-side expressions are non-constants; classify all recorded right-link assignment statements according to the control branch to which they belong, where right-link assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M;

[0034] Step 23: Extract the signals in the left-side expressions of the right-link assignment statements of all FPGA signal records in sequence, construct a directed edge from the FPGA signal node to the extracted left-side signal node, and simultaneously analyze the right-link assignment statements of the FPGA signal, count the total number N of right-link assignment statement classes whose left sides include the above-mentioned left-side signal, calculate N / M to obtain the transmission probability of the constructed directed edge, and thus obtain the signal transmission network corresponding to the entire FPGA code file.

[0035] Step 3: Find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold;

[0036] Step 31: Determine a threshold for the signal feedback probability based on the remaining available logic resources of the FPGA. That is, if the ratio of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A.

[0037] Step 32: Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop. A signal feedback loop is a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, where transmission along any signal node as a starting point on the path can eventually return to the starting signal node.

[0038] Step 33: Record all signal feedback loops whose signal feedback probability is greater than a set threshold.

[0039] Step 4: extract the signal in the signal feedback loop and output it as a self-excited signal.

[0040] Based on the same inventive concept, the present invention also provides an FPGA self-excitation signal detection device based on a signal feedback loop, such as Figure 9 As shown, the device includes a signal transmission network generation module, a signal feedback loop detection module, and a self-excitation signal output. The signal transmission network generation module reads the received FPGA hardware description language code file, forms a top-down overall code file, and maps it into a signal transmission network; the signal feedback loop detection module searches for all signal feedback loops in the signal transmission network and calculates the signal feedback probability, selects and records the signal feedback loops whose signal feedback probability is greater than a set threshold; and the self-excitation signal output module extracts and outputs the FPGA's self-excitation signal based on the signal feedback loop.

[0041] The specific implementation methods of the above modules are the same as the above methods and will not be repeated here.

[0042] The present invention will be further described in detail below with reference to the embodiments.

[0043] Example

[0044] The FPGA hardware description language code provided in this embodiment includes two files TOP.vhd and MA.vhd. Module MA is an instantiated submodule of module TOP.

[0045] The following is an FPGA self-excitation signal detection method based on a signal feedback loop proposed by the present invention to process the RTL code file. The specific processing steps are as follows:

[0046] Step 1: Read the received FPGA hardware description language code file TOP.vhd, such as Figure 2 As shown, the module code file MA.vhd is instantiated in the FPGA code, such as Figure 3As shown, the instantiation module MA code and the top-level module TOP are integrated to form a top-down overall code file, as shown in Figure 4 As shown;

[0047] Step 2: Map the FPGA overall code file into a signal transmission network based on the transmission relationship between the various signals in the FPGA overall code file;

[0048] Step 21. Find and record all signals defined in the FPGA overall code file, such as Figure 5 As shown, each of the above signals corresponds to a node in the signal transmission network;

[0049] Step 22: Find the right-link assignment statements of all FPGA signals, that is, the assignment statements that satisfy the right-side expression containing the signal, and record all the right-link assignment statements whose right-side expressions are not constants, such as Figure 6 As shown, all recorded right-link assignment statements are classified according to the control branch they belong to. The right-link assignment statements belonging to the same control branch belong to the same category, and the total number of categories is recorded, such as Figure 6 As shown;

[0050] Step 23: Extract the signals in the left-hand side expressions of the right-link assignment statements of all FPGA signal records in sequence, and construct a directed edge from the FPGA signal node to the extracted left-hand side signal node, such as Figure 6 As shown, the right-link assignment statement of the FPGA signal is analyzed at the same time, and the total number of right-link assignment statement classes whose left side is the above left-side signal is counted, such as Figure 6 As shown, the transmission probability of each directed edge is calculated, as shown in Figure 6 As shown, the signal transmission network corresponding to the FPGA overall code file is obtained, as shown Figure 7 shown.

[0051] Step 3: Find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold;

[0052] Step 31: In this example, the remaining available logic resources of the FPGA to which the FPGA hardware description language code belongs account for 70% of the total resources, so the threshold of the signal feedback probability is set to 30%;

[0053] Step 32: Find all the signal feedback loops in the signal transmission network and obtain a total of one signal feedback loop, such as Figure 8 As shown, the transmission probabilities of all directed edges in the signal feedback loop are multiplied together, and the signal feedback probability of the signal feedback loop is 37.5%, as shown in Figure 8 As shown;

[0054] Step 33: Record all signal feedback loops whose signal feedback probability is greater than the set threshold of 30%. There is one signal feedback loop in total, such as Figure 8 shown.

[0055] Step 4: Extract the self-excited signals in the signal feedback loop: Y, A, B, C.

[0056] The foregoing is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should be considered within the scope of protection of the present invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A FPGA self-excitation signal detection method based on a signal feedback loop, characterized in that: The following steps are involved: Step 1: Read the received FPGA hardware description language code file, integrate the modules in the FPGA hardware description language code, and form a top-down overall code file; Step 2: Map the FPGA overall code file into a signal transmission network based on the transmission relationship between the various signals in the FPGA overall code file; Step 3: Find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold; Step 4: extract the signal in the signal feedback loop and output it as a self-excited signal.

2. The FPGA self-excitation signal detection method based on a signal feedback loop according to claim 1, wherein: In step 2, based on the transmission relationship between the various signals in the FPGA overall code file, the FPGA overall code file is mapped into a signal transmission network, including the following steps: Step 21: Find and record all signals defined in the FPGA overall code file, and build a corresponding signal transmission network. Each signal in the FPGA corresponds to a node in the signal transmission network. Step 22: Find all right-link assignment statements for FPGA signals, that is, assignment statements that satisfy the right-side expression containing the signal, and record all right-link assignment statements whose right-side expressions are non-constants; classify all recorded right-link assignment statements according to the control branch to which they belong, where right-link assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M; Step 23: Extract the signals in the left-side expressions of the right-link assignment statements of all FPGA signal records in sequence, construct a directed edge from the FPGA signal node to the extracted left-side signal node, and simultaneously analyze the right-link assignment statements of the FPGA signal, count the total number N of right-link assignment statement classes whose left sides are the above-mentioned left-side signals, calculate N / M to obtain the transmission probability of the constructed directed edge, and thus obtain the signal transmission network corresponding to the FPGA overall code file.

3. The FPGA self-excitation signal detection method based on a signal feedback loop according to claim 1, wherein: In step 3, all signal feedback loops in the signal transmission network are searched and the signal feedback probability is calculated, and the signal feedback loops whose signal feedback probability is greater than a set threshold are selected and recorded, which includes the following steps: Step 31: Determine a threshold for the signal feedback probability based on the remaining available logic resources of the FPGA. That is, if the ratio of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A. Step 32: Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop. A signal feedback loop is a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, where transmission along any signal node as a starting point on the path can eventually return to the starting signal node. Step 33: Record all signal feedback loops whose signal feedback probability is greater than a set threshold.

4. An FPGA self-excitation signal detection device based on a signal feedback loop, characterized in that: For implementing the method according to claim 1, the apparatus comprises: The signal transmission network generation module is used to read the received FPGA hardware description language code file, form a top-down overall code file and map it into a signal transmission network; A signal feedback loop detection module is used to find all signal feedback loops in the signal transmission network and calculate the signal feedback probability, and select and record the signal feedback loops whose signal feedback probability is greater than a set threshold; The self-excitation signal output module is used to extract and output the self-excitation signal of the FPGA according to the signal feedback loop.

5. The FPGA self-excitation signal detection device based on the signal feedback loop according to claim 4, characterized in that: According to the transmission relationship between each signal in the FPGA's overall code file, the FPGA's overall code file is mapped into a signal transmission network, specifically: Find and record all signals defined in the FPGA overall code file, and build a corresponding signal transmission network. Each signal in the FPGA corresponds to a node in the signal transmission network. Find all right-link assignment statements for FPGA signals, that is, assignment statements that satisfy the right-hand expression containing the signal, and record all right-link assignment statements whose right-hand expressions are non-constants; classify all recorded right-link assignment statements according to the control branch to which they belong, where right-link assignment statements belonging to the same control branch belong to the same category, and record the total number of categories M; The signals in the left-side expressions of the right-link assignment statements of all FPGA signal records are extracted in sequence, and a directed edge is constructed from the FPGA signal node to the extracted left-side signal node. At the same time, the right-link assignment statements of the FPGA signal are analyzed, and the total number N of right-link assignment statement types whose left sides include the above-mentioned left-side signals is counted. The transmission probability of the constructed directed edge is calculated as N / M, thereby obtaining the signal transmission network corresponding to the entire FPGA code file.

6. The FPGA self-excitation signal detection device based on the signal feedback loop according to claim 4, characterized in that: Find all signal feedback loops in the signal transmission network and calculate the signal feedback probability. Select and record the signal feedback loops whose signal feedback probability is greater than the set threshold. Specifically: The threshold of the signal feedback probability is determined based on the remaining available logic resources of the FPGA. That is, if the ratio of the remaining logic resources of the FPGA to the total resources is A, then the feedback probability threshold is 1-A. Find all signal feedback loops in the signal transmission network, and multiply the transmission probabilities corresponding to all directed edges in the found signal feedback loops to obtain the signal feedback probability of the signal feedback loop. A signal feedback loop is a circular path in the signal transmission network consisting of multiple signal nodes and their directed edges, where transmission along any signal node as the starting point on the path can eventually return to the starting signal node. Record all signal feedback loops whose signal feedback probability is greater than the set threshold.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method according to any one of claims 1 to 3 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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