Automatic integration system from asynchronous assembly line to asynchronous circuit

Abstract

The invention discloses an automatic integrated system from an asynchronous pipeline to an asynchronous circuit, which adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, and gradually maps to generate a gate-level netlist and a standard delay format file so as to be in butt joint with a commercial back-end design process. According to the method, asynchronous design based on an asynchronous structure can be automatically mapped into an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, asynchronous circuit time sequence detection and delay matching are automatically completed, the design efficiency is greatly improved, and the design cost is reduced. An automatic delay matching mechanism enables the circuit to have a good data ready detection and handshake mechanism, and the characteristics of low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, automation of asynchronous design key links such as structure abstraction, time delay modeling and testability insertion is achieved while design readability, hierarchical consistency and time sequence controllability are guaranteed.

Description

Technical Field

[0001] The invention belongs to the technical field of asynchronous circuit design, and in particular relates to an automatic synthesis system from asynchronous pipeline to asynchronous circuit. Background Art

[0002] The working mechanism of asynchronous circuits is realized by events generated by circuit logic and does not rely on the clock generated by the crystal oscillator. It decomposes specific tasks into event streams (sequences). The event streams drive the asynchronous chip to perform tasks. Events and data can be encoded uniformly or processed separately, ultimately forming a circuit subsystem with specific functions. The circuit subsystem and circuit system are driven by events to perform their functions.

[0003] Asynchronous circuits offer numerous theoretical advantages, but they still face numerous challenges in practical engineering applications. Currently, the asynchronous circuit ecosystem is not fully established and is still in its developmental stages. Mainstream electronic design automation (EDA) tools are primarily focused on synchronous circuit design. There are no commercial EDA platforms specifically designed for asynchronous circuits, and only open-source tools from a few research teams exist. Many asynchronous circuit development environments are hand-built, in-house tools. Furthermore, there is currently no unified standard for the design and verification of asynchronous circuits. Compared to the widespread use of hardware description languages ​​like Verilog and VHDL for synchronous circuits, the description languages ​​and design specifications for asynchronous circuits are not yet standardized. This results in poor compatibility between tools, limiting the promotion and application of asynchronous circuits.

[0004] In general, existing asynchronous circuit design tools have the following defects: 1. Low automation level of asynchronous circuit mapping The mapping process relies heavily on manual intervention and configuration. Designers need to perform tedious adjustments and configurations based on circuit requirements. Manual operations are prone to errors, resulting in low design efficiency. This not only increases design time and cost, but also fails to ensure consistency and repeatability in the design process, reducing overall design quality. 2. Inefficiency in handling complex designs When processing large-scale, complex designs, efficiency bottlenecks are often encountered, especially when faced with multi-layer asynchronous pipeline structures. Computational redundancy often prevents effective optimization of the mapping relationship at each layer, resulting in a time-consuming mapping process and excessive consumption of computing resources. 3. The mapping process is difficult to retain the advantages of asynchronous characteristics Typically, they rely on synchronous circuit design concepts and lack a deep understanding and optimization of asynchronous circuit characteristics. In the mapping process from asynchronous pipelines to asynchronous circuits, they often fail to fully consider the timing flexibility, low power consumption, and clockless design advantages of asynchronous circuits. As a result, the mapped circuits fail to fully exploit the advantages of asynchronous circuits and may introduce additional complexity and performance bottlenecks, making the mapping process not only inefficient but also potentially resulting in performance losses. 4. Poor scalability When dealing with large-scale or complex circuits, the system exhibits poor scalability and often cannot adapt to the demands of larger integrated circuit design. When mapping complex circuits, computational bottlenecks or memory limitations often arise, preventing efficient design completion. Furthermore, the system's weak modular design capabilities prevent it from flexibly adapting to circuits of varying scales and complexities, limiting the design's scalability and adaptability. Summary of the Invention

[0005] In order to solve the problems existing in the above-mentioned background technology, the present invention provides an automated synthesis system for asynchronous pipelines to asynchronous circuits. By building a tool chain based on C language, it realizes the full process automation of automatic parsing, structure mapping, logic generation and delay matching of high-level structure descriptions in JSON / XML format.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: An automated synthesis system for asynchronous pipelines to asynchronous circuits. This automated synthesis system is a front-end EDA tool chain for asynchronous circuit design. It adopts a modular architecture and takes high-level structure description files in JSON / XML format as input. It gradually maps and generates gate-level netlists and standard delay format files to connect to commercial back-end design processes.

[0007] The automated integrated system includes: FlowParse module: used to parse and extract semantics from high-level structure description files in JSON / XML format, and construct the flow structure FlowSt; the output of the FlowParse module is the FlowStTop data structure or gate-level netlist file, which serves as the input of the next-level Flow2Micro module; among them, the FlowStTop data structure is the top-level summary of FlowSt, and the FlowParse module retains the annotation information in the gate-level netlist file in the FlowStTop structure for module debugging and visualization; Flow2Micro module: used to map the asynchronous control logic (such as waiting, convergence, arbitration, etc.) described in the FlowSt into a composable asynchronous structure sub-instance and construct a microstructure MicroSt, where the asynchronous structure sub-is a data flow-based asynchronous micro-pipeline unit developed based on the "Sender-Relay-Receiver" structure; the output of the Flow2Micro module is the MicroStTop data structure or the gate-level netlist file of the asynchronous structure sub-level, and the MicroStTop data structure is the top-level summary of MicroSt; the Flow2Micro module has semantic verification capabilities, detecting problems such as incomplete semantic coverage of asynchronous structure sub-levels, port direction conflicts, and floating signals, and providing prompts through annotations or structural tags; Micro2Meso module: used to convert each asynchronous structure sub-instance of the MicroSt into an asynchronous control path consisting of a "send-relay-receive" structure in combination with the mesoscopic model library (a specific mesoscopic model built in the SystemVerilog language that can be called / used in processor code design) and generate a mesoscopic structure MesoSt; the output of the Micro2Meso module is a MesoSt containing a "send-relay-receive" structure or a mesoscopic gate-level netlist file, which can be used for mesoscopic model modeling verification and subsequent delay analysis; DFTInsert module: Based on MesoSt, which contains a "send-relay-receive" structure, it automatically identifies asynchronous control links and combinational logic links in MesoSt and inserts them into DFT structural units according to a preset insertion strategy file. It also inserts instance statements into the gate-level netlist file at the mesoscopic level. The DFTInsert module generates test control paths, such as test clocks, scan enables, and link resets, to ensure that the final gate-level netlist has good scannability and verifiability. Meso2Logic module: This module identifies and expands relay instances in MesoSt inserted into DFT structural units, replacing their corresponding behavioral models with basic logic combinations and trigger units. The module also strips and standardizes data and control lines, expanding multidimensional linear variables into one-dimensional standard logic bus signals for easy identification by subsequent synthesis tools. The output of the Meso2Logic module is the logic structure LogicSt and a gate-level netlist file. Synthesis module: By loading the process library file, the abstract logic gates (such as AND, MUX, DFF) in the LogicSt are mapped to specific standard cell instances (such as AND2_X1, MUX2_X1, DFF_X2, etc.), and their parameters, clock edge properties, gating signals, and other information are automatically completed. The output of the Synthesis module is a gate-level netlist file bound to the process unit, and the cell type field of all logic cells in LogicSt is updated to provide a structural basis for subsequent delay modeling, and the gate-level LogicSt is output; DelayInsert module: used to insert delay elements into the gate-level LogicSt to meet the timing alignment, path balance and asynchronous protocol accuracy requirements of the asynchronous control chain and combinational logic, complete path delay analysis and compensation, and generate accurate standard delay format files; Assemble module: used to integrate the gate-level netlist files and delay information output by all modules, complete instance path renaming, signal remapping and lint-level semantic verification, and generate a global netlist and standard delay format file as standard input for back-end physical design, simulation verification, and formal verification.

[0008] Furthermore, the FlowSt is used to store data flows described in JSON / XML; MicroSt is used to store processor design codes using asynchronous structures according to customized design specifications, and realize translation between high-level behaviors and asynchronous structures; MesoSt is used to store processor design codes using mesoscopic models according to customized design specifications; LogicSt is used to store gate-level netlist-level design codes, and record all logic units, connections, signal relationships and topological structures.

[0009] Furthermore, the "send-relay-receive" structure includes a sender (Sender), a relay (Relay) and a receiver (Receiver), wherein: Sender: includes a trigger, an inverter, and a delay module. When receiving the drive pulse signal i_drive, the Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and output as o_free. Relay: It consists of an XOR gate, an XNOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller. Receiver: includes a trigger, which is activated when the lower-level pulse signal i_freeNext is received.

[0010] Furthermore, the asynchronous structure includes Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter and Selector, where: Source includes: inverter and delay unit, which uses phase difference to generate pulse event signal; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter and flip-flop; cFifo includes sender, relay and receiver, which receives input event pulse signal, generates timing control signal, and outputs event pulse signal of the next level; cPmtFifo includes sender, relay with permission mechanism, receiver and delay unit, which receives input event pulse signal, generates timing control signal when permission signal is high, and outputs event pulse signal of the next level; Contap uses sender that does not generate free signal, and includes flip-flop and inverter to convert pulse signal into level signal; WaitMerge includes: Contap, AND gate, and OR gate; Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal; MutexMerge includes: Contap, AND gate, OR gate, and multiplexer. Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. The trap includes a delay unit that delays the input pulse and outputs it. The splitter includes a contap, an AND gate, an OR gate, and a NOR gate. The contap uses a sender that does not generate a free signal. The contap includes a trigger and an inverter to convert the pulse signal into a level signal. Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate.

[0011] Furthermore, the Flow2Micro module generates a corresponding structure description by automatically calling the asynchronous structure sub-library and parsing the gate-level netlist file of the asynchronous structure sub-level to generate MicroSt. The asynchronous structure sub-library is composed of the gate-level netlist template of the asynchronous structure sub-level. The Flow2Micro module translates each abstract node into an asynchronous structure sub-level call statement, and combines the internal topology and data flow of the Flow2Micro module to perform automatic port connection, module name remapping and multi-instance management.

[0012] Furthermore, in the Micro2Meso module, the Sender, Relay, and Receiver are injected into the mesoscopic model as black box behavior units. The output of the Sender is connected to the input of the Relay, the output of the Relay is connected to the input of the Receiver, and the output of the Receiver is connected to the input of the Relay. The pulse signal generated in the Relay is connected to the pulse signal output of the Sender and the drive pulse signal output of the Receiver after passing through the delay unit. At the same time, the Micro2Meso module performs timing analysis on the combinational logic encapsulated in the asynchronous structure, divides the combinational logic blocks according to the timing relationship in the logic, and generates the required number of relay units in the control path to match the timing logic.

[0013] Furthermore, in the DelayInsert module, the method for inserting a delay element in the gate-level LogicSt is as follows: First, a complete timing path diagram is constructed for the gate-level LogicSt, each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified; Secondly, the DelayInsert module determines the propagation path where the delay element needs to be inserted based on the configuration strategy and calculates the required delay unit size and insertion position; Finally, the delay element is inserted. The insertion process synchronously modifies LogicSt and updates the modifications to the standard delay format file. This file is used to record the IOPATH, INTERCONNECT of each logic unit and the three-value delay (min:typ:max) of the inserted delay element, and generate TIMINGCHECK items (SETUP, HOLD, WIDTH) to meet the verification requirements of simulation and STA tools.

[0014] Furthermore, in the timing path diagram, the nodes are logic gate output signals, and the edges are connection relationships. The delay of each logic gate and connection is accumulated on the timing path diagram, and the timing of each path is dynamically evaluated; by loading the standard delay format file, the delay of each logic unit and wire is automatically marked.

[0015] Furthermore, the method for the Assemble module to generate a global netlist and a standard delay format file is as follows: First, the Assemble module reads the gate-level netlist files generated by each module, constructs a module dependency graph, identifies the top-level module, automatically resolves instance relationships, and renames instances and signals according to the naming strategy (prefix, suffix, UUID), resolving cross-module signal conflicts and naming overlaps. Secondly, the gate-level netlist files output by all modules are spliced ​​or flattened to build a top-level gate-level netlist with a consistent final structure. The corresponding multiple standard delay format files are completed and merged according to the instance path mapping rules, supporting flat path (U1_U2_n3) or hierarchical path (top / U1 / U2 / n3) format output, and uniformly generating TIMESCALE, SDFVERSION, CELL-level delay and other content. Finally, the Assemble module outputs a global netlist and standard delay format files that can be directly used by the ASIC back-end EDA process, providing full-process closed-loop support for the asynchronous design process from abstract behavioral modeling to process-level simulation verification.

[0016] Furthermore, the lint-level semantic check in the Assemble module is implemented through a structural checker. The lint-level semantic check includes the detection of floating signals, dual-drive signals, repeated declarations, unconnected ports, and IO mismatches. The structural checker generates a structural check report and netlist statistical information to support users in quickly locating potential design errors.

[0017] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects: 1. By building a C-based toolchain, we have automated the entire process of automatically parsing, mapping, generating logic, and matching delays for XML / JSON asynchronous structure descriptions. This automated mapping process seamlessly handles multi-level design representations (such as asynchronous structure descriptions, micropipelines, and mesoscopic models), effectively reducing reliance on manual coding, significantly improving design efficiency, and reducing design defects and verification costs caused by manual operations. 2. Using asynchronous substructures as an abstract foundation, the essential characteristics of asynchronous behavior are preserved. Through data flow-driven hierarchical mapping and timing modeling based on a "send-relay-receive" structure, the mapping results are ensured to operate stably and collaboratively. The automatic delay matching mechanism enables the circuit to have a good data-ready detection and handshake mechanism, thus achieving low power consumption, high throughput, and no sensitivity to global clock drift. 3. A layer-by-layer mapping architecture of "asynchronous structure sub-module → mesoscopic model → circuit netlist" is employed. Each layer clearly defines input and output interfaces and intermediate state formats. Standardized data structures (XML / JSON) and unified gate-level netlist output serve as a bridge, enabling the system to achieve robust module reuse and system scalability for even more complex designs. Furthermore, key toolchain modules can be replaced or expanded to accommodate diverse design scenarios and target platforms (e.g., ASIC / FPGA). 4. A clear set of asynchronous design rules (including asynchronous substructure naming, semantics, and module boundary definition) and a supporting toolchain have been established, enabling structured analysis and verification of every step from input to output, ensuring a stable process and a unified format. Furthermore, the final output seamlessly integrates with mainstream commercial tools such as Synopsys Design Compiler / VCS, achieving a closed-loop design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is an expression diagram of the asynchronous structure provided by an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a mesoscopic model provided by an embodiment of the present invention; Figure 3 This is a logic conversion diagram of an automated integrated system for converting asynchronous pipelines to asynchronous circuits provided by an embodiment of the present invention; Figure 4 This is the overall architecture of the automated integrated system from asynchronous pipelines to asynchronous circuits provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] The present invention proposes an automated integrated system from an asynchronous pipeline to an asynchronous circuit based on an asynchronous structure. The asynchronous structure is a data flow-based asynchronous micro-pipeline unit developed based on a "sender-relay-receiver" structure. The "sender-relay-receiver" structure includes a sender, a relay, and a receiver. The sender includes a trigger, an inverter, and a delay module. When a drive pulse signal i_drive is received, the sender flips the output level signal, and the input pulse signal i_free is output as o_free after being delayed by the delay module. The relay consists of an exclusive-OR gate, an exclusive-OR gate, an AND gate, a D trigger, an inverter, and a delay module, and is implemented based on a click asynchronous controller. The receiver includes a trigger. When a lower-level pulse signal i_freeNext is received, the trigger is activated.

[0021] The expression diagram of asynchronous structure is as follows Figure 1As shown, it includes: Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter and Selector. According to different design requirements, one or more asynchronous structures can be selected and combined to implement specific functions. Among them: Source includes: inverter and delay unit, which uses phase difference to generate pulse event signal; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter and flip-flop; cFifo includes sender, relay and receiver, which receives input event pulse signal, generates timing control signal, and outputs event pulse signal of the next level; cPmtFifo includes sender, relay with permission mechanism, receiver and delay unit, which receives input event pulse signal, generates timing control signal when permission signal is high, and outputs event pulse signal of the next level; Contap uses sender that does not generate free signal, and includes flip-flop and inverter to convert pulse signal into level signal; WaitMerge includes: Contap, AND gate, and OR gate; Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal; MutexMerge includes: Contap, AND gate, OR gate, and multiplexer. Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. Trap includes: a delay unit that outputs the input pulse after delay; Splitter includes: Contap, AND gate, OR gate, and NOR gate; Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal; Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate.

[0022] The automated synthesis system for asynchronous pipelines to asynchronous circuits proposed in this paper is a front-end EDA tool chain for asynchronous circuit design. Based on this front-end EDA tool chain, open-source asynchronous EDA software has been developed. This system automatically maps asynchronous designs based on asynchronous constructs into asynchronous circuits and automatically performs timing detection and delay matching for these circuits. This automated synthesis system utilizes a modular architecture, taking high-level structure description files in JSON / XML format as input and gradually mapping them to generate gate-level netlists and standard delay format files (.sdf) for integration with commercial back-end design processes.

[0023] The automation integrated system is divided into eight modules: (1) FlowParse module, which parses input data into flow structures; (2) Flow2Micro module, which realizes the conversion between high-level behavior and asynchronous structure sub-modules; (3) Micro2Meso module, which expands asynchronous structure sub-modules to mesoscopic models; the circuit principle of the mesoscopic model is as follows Figure 2As shown, it consists of a sender, a relay, and a receiver. When the drive pulse signal i_drive is received, the trigger D value in the sender is output to the Q terminal. Meanwhile, the Q terminal is connected to the D terminal via a delay unit and an inverter. The sender's output terminal outR is connected to the relay's input terminal inR. The relay is built based on a click controller. After the signal level at input terminal inR is flipped, it sequentially flips the signal levels of pulse fire, output terminal outR, and output terminal inA. It then pulls pulse fire down, causing pulse fire to appear as a pulse. The relay's output terminal outR is connected to the receiver's input terminal inR. When the pulse signal i_free is received, the receiver's trigger D value is output to the Q terminal, and the Q terminal value is output from output terminal inA to the relay's input terminal outA. Furthermore, the pulse fire generated in the relay is connected to the sender's pulse signal o_free output terminal and the receiver's drive pulse signal o_drive output terminal after a delay unit. rst is the module's reset signal, returning the module to its initial state. LogicSt: Logic structure (LogicStruct), stores gate-level netlist-level design code, records all logic cells, connections, signal relationships and topology structures. (4) DFTInsert module, automatically inserts testability links; (5) Meso2Logic module, expands to the basic logic gate-level structure; (6) Synthesis module, implements standard cell synthesis; (7) DelayInsert module, completes path delay analysis and compensation, and generates accurate standard delay format files; (8) Assemble module, integrates the logic netlist and delay information output by all modules, completes instance path renaming, signal remapping and lint-level semantic verification, and finally generates a unified global netlist and standard delay format file, providing a standard interface for back-end layout and routing, timing simulation and formal verification. This automated synthesis system achieves automation of key asynchronous design links such as structural abstraction, delay modeling, and testability insertion while ensuring design readability, hierarchical consistency and timing controllability.

[0024] Each of the eight modules is an independent software package with a unified command line interface and is logically connected in series through intermediate data structures (such as FlowSt, MicroSt, MesoSt, LogicSt). The logical conversion in the synthesis process is as follows: Figure 3As shown. FlowSt: Flow Struct, stores data flows described in JSON / XML. GramTest0 is used to check whether the structure complies with the specifications. MicroSt: Microscopic Struct, stores processor design code using asynchronous structures according to customized design specifications. GramTest1 is used to check whether the structure complies with the specifications. MesoSt: Mesoscopic Struct, stores processor design code using mesoscopic models according to customized design specifications. GramTest2 is used to check whether the structure complies with the specifications. LogicS: Logic Struct, stores gate-level netlist-level design code. GramTest3 is used to check whether the structure complies with the specifications. Virtual Circuit Library (.sv): This is a virtual circuit library written in SystemVerilog and built with reference to the actual physical process library. It contains the electrical properties of circuit components.

[0025] The following combination Figure 4 The overall architecture diagram of the automated synthesis system from asynchronous pipelines to asynchronous circuits (named PinTu) shown in the figure provides a detailed description of the eight modules.

[0026] FlowParse module: This module parses and extracts semantics from high-level structure description files in JSON / XML format, and constructs FlowSt, which serves as the basis for modeling and transformation in subsequent stages. This module batch processes multiple input files, parsing module names, asynchronous structure subcalls, port connections, control paths, data flows, and more. The output of the FlowParse module is a FlowStTop data structure or a gate-level netlist SystemVerilog file, which serves as the input for the next-level Flow2Micro module. The FlowStTop data structure is the top-level summary of FlowSt. The FlowParse module retains annotation information from the gate-level netlist SystemVerilog file in the FlowStTop data structure for module debugging and visualization.

[0027] The Flow2Micro module maps asynchronous control logic (such as wait, converge, and arbitrate) described in FlowSt into composable asynchronous sub-struct instances and constructs the microstructure MicroSt, completing the translation from high-level behavior to asynchronous sub-structs. During the processing flow, the Flow2Micro module automatically calls the asynchronous sub-struct library (consisting of SystemVerilog templates for the asynchronous sub-struct gate-level netlist) to generate the corresponding structural description. It also supports parsing the asynchronous sub-struct gate-level netlist SystemVerilog file to generate the MicroSt. The module translates each abstract node into asynchronous sub-struct call statements, such as WaitMerge, ArbMerge, and NatSplit. Based on the internal topology and data flow of the Flow2Micro module, it automatically performs port wiring, module name remapping, and multi-instance management. The Flow2Micro module also provides semantic verification capabilities, detecting issues such as incomplete semantic coverage of asynchronous sub-structs, port direction conflicts, and floating signals, and provides these issues through annotations or structural markup. The Flow2Micro module outputs the MicroStTop data structure, which is the top-level summary of the MicroSt and provides the foundation for subsequent mesoscopic behavioral modeling.

[0028] The Micro2Meso module receives the MicroSt generated by the Flow2Micro module and, in conjunction with the mesoscopic model library (a concrete mesoscopic model built in SystemVerilog that can be called / used in processor code design), converts each asynchronous structure sub-instance into an asynchronous control path consisting of a send-relay-receive structure. The core of this stage is to deconstruct the abstract asynchronous structure sub-instance into a timing model based on relay behavior. Relay behavior refers to the behavior that constructs the timing model using the send-relay-receive format. Relay units (implementing encapsulation, callable in specific code, and encapsulated send, relay, and receive modules) remain as black boxes during this stage, while send and receive modules can be optionally expanded into control combinational logic based on context. The Micro2Meso module supports parameter binding, hierarchical path expansion, and control signal insertion for relay templates. It then generates a complete MesoSt and outputs a MesoSt file containing the send-relay-receive structure or a mesoscopic-level gate-level netlist SystemVerilog file, which can be used for mesoscopic model verification and subsequent delay analysis. In the Micro2Meso module, Sender, Relay, and Receiver are injected into the mesoscopic model as black-box behavioral units. At the same time, the combinational logic encapsulated in the asynchronous structure is subjected to timing analysis. The combinational logic blocks are divided according to the timing relationship in the logic, and the required number of relay units are generated in the control path to match the timing logic.

[0029] The DFTInsert module, based on the MesoSt architecture containing a "transmit-relay-receive" structure, automatically identifies asynchronous control links and combinational logic links within the MesoSt according to a pre-defined insertion strategy file. It then customizes the insertion of DFT building blocks, such as scan registers, pulse generators, and bypass muxes, based on their characteristics and test requirements. This module uses a strategy algorithm to control the granularity and coverage of test end-element insertion, and provides capabilities such as fan-out control, insertion redundancy optimization, and link back-annotation. All inserted DFT building blocks are synchronously updated to the MesoSt architecture containing the "transmit-relay-receive" structure, and instance statements are inserted into the meso-level gate-level netlist SystemVerilog file. The DFTInsert module also maintains a testability signal netlist and generates test control paths, such as test clocks, scan enables, and link resets, ensuring the final netlist is highly scannable and verifiable. Testability link insertion in asynchronous circuits is challenging, complex, highly customized, and prone to errors. The module's automated support significantly simplifies the test loop implementation process and ensures functional and test consistency of the inserted logic.

[0030] The Meso2Logic module takes as input the inserted DFT structural unit and a MesoSt containing a "transmit-relay-receive" structure, or the gate-level netlist SystemVerilog file of its corresponding hierarchical design. It then identifies and expands all relay instances (referring to the transmit, relay, and receive units instantiated in the code), replacing their corresponding behavioral models with basic logic combinations and trigger units. The Meso2Logic module also strips and standardizes data and control lines, expanding multidimensional linear variables into one-dimensional standard logic bus signals for easy recognition by subsequent synthesis tools. The Meso2Logic module outputs a unified logic structure, LogicSt, and a gate-level netlist SystemVerilog file. LogicSt is used to store gate-level netlist design code, recording all logic units, connections, signal relationships, and topology. It also supports the conversion and output of data structures into gate-level SystemVerilog code.

[0031] The Synthesis module maps logic structures to specific process cells. By loading process libraries, it maps abstract logic gates (such as AND, MUX, and DFF) in LogicSt to specific standard cell instances (such as AND2_X1, MUX2_X1, and DFF_X2), automatically completing their parameters, clock edge properties, and gating signal information. The Synthesis module selects target cells based on factors such as drive strength, fan-out capability, area, and power consumption, and performs necessary logic rewrites and optimizations, such as merging common subexpressions, collapsing redundant flip-flops, and balancing combinational paths. In this automated synthesis system, the Synthesis module can be integrated with existing commercial synthesis tools (such as Yosys and DC) or performed offline by built-in synthesis logic. The specific implementation is configurable. The Synthesis module outputs a SystemVerilog gate-level netlist file with the process cells bound to it. It also updates the cell type field of all logic cells in LogicSt, providing a structural basis for subsequent delay modeling, and outputs the updated gate-level LogicSt.

[0032] DelayInsert module: Inserts delay elements into gate-level LogicSt to meet the timing alignment, path balance, and asynchronous protocol accuracy requirements of asynchronous control chains and combinational logic. It also performs path delay analysis and compensation and generates accurate standard delay format files. The module inserts delay elements into gate-level LogicSt as follows: First, a complete timing path diagram is constructed for gate-level LogicSt. In the timing path diagram, nodes are logic gate output signals and edges are connection relationships. The delay of each logic gate and connection is accumulated on the timing path diagram, and the timing of each path is dynamically evaluated. By loading a standard delay format file (such as .lib), each logic unit and wire is automatically annotated with delay. Each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified. Secondly, the DelayInsert module determines the propagation path where the delay element needs to be inserted based on the configuration strategy and calculates the required delay unit size and insertion position; Finally, the delay element is inserted. This process involves inserting new logic cells into LogicSt, updating signal connections, and automatically generating instance names, signal names, and constraint tags. In addition to the logical structure, the insertion process also modifies LogicSt and updates these modifications to the standard delay format file. This records the IOPATH and INTERCONNECT values ​​for each logic cell, as well as the three-value delay (min:typ:max) of the inserted delay element. TIMINGCHECK items (SETUP, HOLD, WIDTH) are generated to meet the verification requirements of simulation and STA tools. This module also supports patch mode updates for existing standard delay format files, preserving the timing information for unchanged paths and incrementally updating only the modified portions.

[0033] The Assemble module integrates the gate-level netlist SystemVerilog files and delay information output by all modules, performing instance path renaming, signal remapping, and lint-level semantic checking to generate a global netlist (.sv) and standard delay format files. First, the Assemble module reads the gate-level netlist SystemVerilog files generated by each module, constructs a module dependency graph, identifies the top-level module, automatically resolves instance relationships, and renames instances and signals according to the naming strategy (prefix, suffix, and UUID), resolving cross-module signal conflicts and name overlaps. Second, the gate-level netlist SystemVerilog files output by all modules are concatenated or flattened to construct a final, structurally consistent top-level gate-level netlist. The corresponding standard delay format files are then path-completed and merged according to instance path mapping rules. Output formats include flat paths (U1_U2_n3) and hierarchical paths (top / U1 / U2 / n3). TIMESCALE, SDFVERSION, and cell-level delays are uniformly generated. Lint-level semantic checking in the Assemble module is implemented through a structural checker. This includes detection of floating signals, dual-driven signals, duplicate declarations, unconnected ports, and I / O mismatches. The structural checker generates structural check reports and netlist statistics, enabling users to quickly identify potential design errors. Finally, the Assemble module outputs a global netlist (.sv) and standard delay format file that can be directly used in the ASIC back-end EDA process. This seamlessly integrates with mainstream commercial tools such as Synopsys VCS / P&R, providing closed-loop support for the asynchronous design process, from abstract behavioral modeling to process-level simulation verification.

[0034] The overall architecture of the automated integrated system from asynchronous pipeline to asynchronous circuit proposed by the present invention is as follows: Figure 4As shown, the system employs a layer-by-layer mapping architecture from asynchronous structured substructures to mesoscopic models to circuit netlists. Each layer clearly defines input and output interfaces and intermediate state formats. Standardized data structures (XML / JSON) and a unified gate-level netlist SystemVerilog file output serve as a bridge, enabling the system to leverage module reuse and system scalability for even more complex designs. Furthermore, key modules can be replaced or expanded to accommodate diverse design scenarios and target platforms (such as ASICs / FPGAs). This modular design supports asynchronous circuit designs of varying scales and complexities, ensuring the tool's robust scalability to adapt to increasingly complex and diverse design requirements. The system automates the entire process from automatic parsing of XML / JSON asynchronous structured substructures, structure mapping, logic generation, and delay matching.

[0035] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An automated integration system for asynchronous pipelines to asynchronous circuits, characterized in that: include: FlowParse module: used to parse and extract semantics of high-level structure description files in JSON / XML format, and build the flow structure FlowSt; The FlowParse module outputs the top-level summary or gate-level netlist file of FlowSt; Flow2Micro module: used to map the asynchronous control logic described in the FlowSt into a composable asynchronous structure sub-instance and construct a microstructure MicroSt; the asynchronous structure sub-instance is an asynchronous micro-pipeline unit based on the "send-relay-receive" structure; The Flow2Micro module outputs a top-level summary of MicroSt or a gate-level netlist file of the asynchronous structure sub-level; Micro2Meso module: used to convert each asynchronous structure sub-instance of the MicroSt into an asynchronous control path composed of a "send-relay-receive" structure and generate a mesostructure MesoSt; the Micro2Meso module outputs a MesoSt containing the "send-relay-receive" structure or a gate-level netlist file at the mesolevel; DFTInsert module: automatically identifies asynchronous control links and combinational logic links in MesoSt containing a "transmit-relay-receive" structure and inserts them into DFT structural units, inserting instance statements into the gate-level netlist file at the mesoscopic level; Meso2Logic module: This module is used to identify and expand relay instances in MesoSt inserted into DFT structural units, replacing the behavioral models corresponding to the relay instances with basic logic combinations and trigger units. The Meso2Logic module also strips and standardizes data and control lines, expanding multidimensional linear variables into one-dimensional standard logic bus signals. The Meso2Logic module outputs the logic structure LogicSt and a gate-level netlist file. Synthesis module: By loading the process library file, the abstract logic gates in the LogicSt are mapped to specific standard unit instances, and the parameters, clock edge properties, and gate control signals are automatically completed. The Synthesis module outputs the gate-level LogicSt and the gate-level netlist file of the bound process unit. DelayInsert module: used to insert delay elements into the gate-level LogicSt and generate accurate standard delay format files; Assemble module: used to integrate the gate-level netlist files and delay information output by all modules to generate a global netlist and standard delay format files.

2. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 1, wherein: The FlowSt is used to store data flows described in JSON / XML, MesoSt is used to store processor design codes using mesoscopic models, and LogicSt is used to store the logical structure of gate-level netlist-level design codes.

3. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 1, wherein: The "Send-Relay-Receive" structure includes Sender, Relay and Receiver, where: Sender: includes a trigger, an inverter, and a delay module. When receiving the drive pulse signal i_drive, the Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and output as o_free. Relay: It consists of an XOR gate, an XNOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller. Receiver: includes a trigger, which is activated when the lower-level pulse signal i_freeNext is received.

4. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 3, wherein: The asynchronous structure includes Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter and Selector, among which: Source includes: inverter and delay unit, which uses phase difference to generate pulse event signal; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter and flip-flop; cFifo includes sender, relay and receiver, which receives input event pulse signal, generates timing control signal, and outputs event pulse signal of the next level; cPmtFifo includes sender, relay with permission mechanism, receiver and delay unit, which receives input event pulse signal, generates timing control signal when permission signal is high, and outputs event pulse signal of the next level; Contap uses sender that does not generate free signal, and includes flip-flop and inverter to convert pulse signal into level signal; WaitMerge includes: Contap, AND gate, and OR gate; Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal; MutexMerge includes: Contap, AND gate, OR gate, and multiplexer. Contap uses a sender that does not generate a free signal. Contap includes a trigger and an inverter to convert the pulse signal into a level signal. The trap includes a delay unit that delays the input pulse and outputs it. The splitter includes a contap, an AND gate, an OR gate, and a NOR gate. The contap uses a sender that does not generate a free signal. The contap includes a trigger and an inverter to convert the pulse signal into a level signal. Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate.

5. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 4, characterized in that: The Flow2Micro module generates a MicroSt by automatically calling the asynchronous structure sub-library to generate the corresponding structure description and parsing the gate-level netlist file of the asynchronous structure sub-level. The asynchronous structure sub-library is composed of the gate-level netlist template of the asynchronous structure sub-level. The Flow2Micro module translates each abstract node into an asynchronous structure sub-level call statement, and combines the internal topology and data flow of the Flow2Micro module to perform automatic port connection, module name remapping and multi-instance management.

6. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 3, characterized in that: In the Micro2Meso module, the sender, relay, and receiver are injected into the mesoscopic model as black box behavioral units. The output of the sender is connected to the input of the relay, the output of the relay is connected to the input of the receiver, and the output of the receiver is connected to the input of the relay. The pulse signal generated in the relay is connected to the pulse signal output of the sender and the drive pulse signal output of the receiver after passing through the delay unit. At the same time, the Micro2Meso module performs timing analysis on the combinational logic encapsulated in the asynchronous structure, divides the combinational logic blocks according to the timing relationship in the logic, and generates the required number of relay units in the control path to match the timing logic.

7. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 1, wherein: In the DelayInsert module, the method for inserting a delay element in the gate-level LogicSt is as follows: First, a complete timing path diagram is constructed for the gate-level LogicSt, each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified; Secondly, the DelayInsert module determines the propagation path where the delay element needs to be inserted based on the configuration strategy and calculates the required delay unit size and insertion position; Finally, the delay element is inserted. The insertion process modifies LogicSt synchronously and updates the modifications to the standard delay format file.

8. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 7, characterized in that: In the timing path diagram, nodes are logic gate output signals, and edges are connection relationships. The delay of each logic gate and connection is accumulated on the timing path diagram, and the timing of each path is dynamically evaluated. By loading a standard delay format file, the delay of each logic unit and wire is automatically marked.

9. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 1, wherein: The method for the Assemble module to generate a global netlist and a standard delay format file is as follows: First, the Assemble module reads the gate-level netlist files generated by each module, constructs a module dependency graph, identifies the top-level module, automatically resolves instance relationships, and renames instances and signals according to the naming strategy to resolve cross-module signal conflicts and naming overlaps. Secondly, the gate-level netlist files output by all modules are spliced ​​or flattened to construct a top-level gate-level netlist with a consistent final structure. The corresponding multiple standard delay format files are path-completed and merged according to the instance path mapping rules. Flat or hierarchical path format output is supported, and TIMESCALE, SDFVERSION, and CELL-level delay content are uniformly generated. Finally, the Assemble module outputs a global netlist and a standard delay format file.

10. The automated integration system from asynchronous pipeline to asynchronous circuit according to claim 1, wherein: The Assemble module implements lint-level semantic verification through a structural checker. Lint-level semantic verification includes detection of floating signals, dual-driven signals, repeated declarations, unconnected ports, and IO mismatches. The structural checker generates a structural inspection report and netlist statistics to support users in quickly locating potential design errors.

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