Wafer test data processing method, device, equipment and medium

Abstract

The invention provides a wafer test data processing method and device, equipment and a medium, and can be applied to the technical field of chips. The method comprises the following steps: acquiring a standard test data file generated when a wafer is tested; analyzing the standard test data file to obtain data files respectively corresponding to the plurality of data types; wherein the data file comprises test record data belonging to a corresponding data type; based on the data files corresponding to the multiple data types respectively, respectively generating analyzable data corresponding to each preset category in the multiple preset categories; and outputting the analyzable data corresponding to each preset category. According to the invention, automatic analysis and classification of the wafer test data are realized, and the efficiency is high.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a wafer test data processing method, device, equipment and medium. Background Art

[0002] STDF (Standard Test Data File) is a storage specification for chip test data in the semiconductor industry. It is mainly used to record and track various data and information during the wafer manufacturing process. These data and information are very important for semiconductor manufacturing because they can help improve production processes, improve product quality and reduce production costs.

[0003] STDF files contain a large amount of data with a wide variety of data types. Currently, technicians rely on manual classification and organization of STDF files to extract the data that meets analysis requirements. However, this method is inefficient and prone to data errors caused by human factors. Summary of the Invention

[0004] The present application provides a wafer test data processing method, device, equipment and medium, which realizes the automatic parsing and classification of wafer test data with high efficiency.

[0005] In a first aspect, the present application provides a wafer test data processing method, comprising:

[0006] Obtaining a standard test data file generated when testing a wafer;

[0007] Parsing the standard test data file to obtain data files corresponding to a plurality of data types; wherein the data files include test record data belonging to corresponding data types;

[0008] Based on the data files corresponding to the multiple data types, respectively, generating analyzable data corresponding to each of the multiple preset categories;

[0009] The analyzable data corresponding to each of the preset categories are output respectively.

[0010] Optionally, in the standard test data file, test record data corresponding to each data type is located in different positions; parsing the standard test data file to obtain data files corresponding to multiple data types includes:

[0011] For each data type, perform the following operations respectively:

[0012] Traversing the standard test data file and extracting test record data from a position corresponding to the data type;

[0013] The extracted test record data is stored in the corresponding data file.

[0014] Optionally, after parsing the standard test data file to obtain data files corresponding to multiple data types, the method further includes:

[0015] The specific fields in each of the data files are mapped in a normative manner.

[0016] Optionally, if the standard test data file is generated during CP testing, the plurality of preset categories include a hard decision category, a soft decision category, a yield category, a test decision result category, a test data category, and a test pass condition category;

[0017] The analyzable data belonging to the hard decision category includes statistical information corresponding to a plurality of hard decision types, and the statistical information includes the number of position chips belonging to the corresponding hard decision type and passing the test;

[0018] The analyzable data belonging to the soft decision category includes statistical information corresponding to a plurality of soft decision types, and the statistical information includes the number of position chips belonging to the corresponding soft decision type and passing the test;

[0019] The analyzable data belonging to the yield category includes the yield corresponding to each test item and the yield corresponding to the wafer;

[0020] The analyzable data belonging to the test determination result category includes the test determination results corresponding to each chip at each position on the wafer, and the test determination results include the test determination results of each test item tested by the chip at the corresponding position;

[0021] The analyzable data belonging to the test data category includes test data corresponding to each test item, and the test data includes test data corresponding to each position chip that has tested the corresponding test item;

[0022] The analyzable data belonging to the test pass condition category includes the test pass conditions corresponding to each test item.

[0023] Optionally, when the preset category is a test determination result category, generating analyzable data corresponding to the test determination result category based on the data files corresponding to the multiple data types respectively includes:

[0024] For each chip on the wafer, perform the following operations:

[0025] For each test item tested by the position chip, the test pass conditions corresponding to the test item and the test data corresponding to the position chip are obtained from the data files corresponding to the multiple data types respectively, and the test judgment result of the position chip for the test item is determined based on the test pass conditions corresponding to the test item and the test data corresponding to the position chip; the test judgment result indicates test pass, test failure or not tested.

[0026] Optionally, it also includes:

[0027] Obtain a user-defined test item group; the test item group includes multiple test items;

[0028] For each position chip on the wafer, obtaining the test determination results of each position chip for each test item from the analyzable data belonging to the test determination result category;

[0029] Based on the test judgment results of the chips at each position on the wafer for each of the test items, a corresponding yield rate and wafer map corresponding to continued testing when failure occurs are generated.

[0030] Optionally, generating a yield and a wafer map corresponding to continued testing in the event of failure according to the test determination results of the chips at each position on the wafer for each test item includes:

[0031] For each position chip on the wafer, numerically mapping the test determination results of the position chip for each test item to obtain a state matrix of the position chip for each test item, wherein the elements in the state matrix are the test determination results expressed in numerical form;

[0032] For each position chip on the wafer, multiply the state matrix of each test item of the position chip to obtain a final determination result; the final determination result indicates pass, fail or not tested;

[0033] Determine the yield as the ratio between the number of position chips on the wafer that are finally determined to be passed and the total number of position chips on the wafer;

[0034] The wafer map is generated based on the coordinates corresponding to the chips at each position on the wafer and the final determination result.

[0035] In a second aspect, the present application provides a wafer test data processing device, comprising:

[0036] An acquisition module, used for acquiring a standard test data file generated when testing a wafer;

[0037] A parsing module, configured to parse the standard test data file to obtain data files corresponding to a plurality of data types; wherein the data files include test record data belonging to corresponding data types;

[0038] A generating module, configured to generate analyzable data corresponding to each of a plurality of preset categories based on the data files corresponding to the plurality of data types;

[0039] The output module is used to output the analyzable data corresponding to each of the preset categories respectively.

[0040] In a third aspect, the present application provides an electronic device, comprising: a processor and a memory communicatively connected to the processor;

[0041] The memory stores computer-executable instructions;

[0042] The processor executes the computer-executable instructions stored in the memory to implement the wafer test data processing method as described in any one of the first aspects.

[0043] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the wafer test data processing method described in any one of the first aspects.

[0044] In a fifth aspect, the present application provides a computer program product, comprising computer execution instructions, which, when executed by a processor, implement the wafer test data processing method described in any one of the first aspects.

[0045] The wafer test data processing method, device, equipment and medium provided in the present application first parse the STDF file generated when the wafer is tested to obtain data files corresponding to multiple data types, and then generate corresponding analyzable data according to multiple preset categories, thereby realizing automatic parsing and classification of wafer test data. Compared with manual classification and organization, the present application is more efficient and reduces the occurrence of data errors caused by human factors. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0047] Figure 1 is a schematic diagram showing an application scenario according to an exemplary embodiment;

[0048] Figure 2is a flow chart showing a method for processing wafer test data according to an exemplary embodiment;

[0049] Figure 3 is a schematic diagram illustrating a COF wafer image generation process according to an exemplary embodiment;

[0050] Figure 4 is a schematic structural diagram of a wafer test data processing device according to an exemplary embodiment;

[0051] Figure 5 The figure is a schematic structural diagram of an electronic device according to an exemplary embodiment.

[0052] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0054] The terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the following embodiments, "plurality" means more than two, unless otherwise specifically defined.

[0055] Die: Also known as a positional chip, it refers to a chip at a certain location on a wafer that contains a complete functional unit or a group of related functional units. In chip design, the die is cut into small squares and encapsulated in the chip's housing.

[0056] In order to clearly understand the technical solution of the present application, the solution of the prior art is first introduced in detail.

[0057] STDF files are a storage specification for chip test data in the semiconductor industry. They are mainly used to record and track various data and information during the wafer manufacturing process. These data and information are very important for semiconductor manufacturing because they can help improve production processes, improve product quality, and reduce production costs.

[0058] STDF files are widely used in wafer probing (CP) and final test (FT). Among them, CP test is between wafer manufacturing and packaging in the entire chip production process. After the wafer is manufactured, multiple position chips are distributed on it, and the pins of the position chips are exposed. The CP test is used to test whether the position chips meet the requirements, and then the position chips that meet the requirements are packaged. Specifically, the probe can be connected to the test machine to test whether its functions and parameters meet the standards. Once the test fails, it will be marked (Ink) so that the marked position chips can be skipped in the subsequent packaging process, thereby improving the packaging efficiency. By analyzing the test data related to the CP test, it can also be determined whether the power consumption of the product and the device meet the manufacturing goals. Among them, the test object of the FT test is the packaged chip, which can be used to detect the process level of the packaging factory.

[0059] STDF files consist of binary information streams and cannot be read directly. Furthermore, STDF files contain a large amount of data and a wide variety of data types. Currently, technicians rely primarily on manual classification and organization of STDF files to extract the data that meets analysis requirements. However, this method is inefficient and prone to data errors caused by human error.

[0060] The present application provides a wafer test data processing method, which can realize efficient parsing and classification of STDF files, is applicable to a variety of chip products, and adapts to the needs of product analysts for rapid analysis, accurate diagnosis and problem location. Specifically, the present application first parses the STDF file generated when the wafer is tested, obtains data files corresponding to multiple data types, and then generates analyzable data corresponding thereto according to multiple preset categories, thereby realizing automatic parsing and classification of wafer test data. Compared with the method of manual classification and sorting, the efficiency of the present application is higher, and the phenomenon of data errors caused by human factors is reduced.

[0061] The following introduces the application scenarios of the wafer test data processing method provided in the embodiment of the present application.

[0062] Figure 1 FIG. 1 is a schematic diagram showing an application scenario according to an exemplary embodiment. Figure 1 As shown, this application scenario includes electronic equipment. The electronic equipment is a terminal device used by product analysts. In this embodiment, the electronic equipment first obtains the STDF file generated during wafer testing, then parses the STDF file to obtain data files corresponding to multiple data types. It then generates and outputs analyzable data corresponding to each preset category for review by product analysts.

[0063] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0064] Figure 2 This is a flow chart of a wafer test data processing method according to an exemplary embodiment. The execution subject of the wafer test data processing method provided in this application is a wafer test data processing device, which is integrated into an electronic device. Figure 2 As shown, the wafer test data processing method provided in this embodiment includes the following steps:

[0065] Step S101 , obtaining a standard test data file generated when testing a wafer.

[0066] In practical applications, performing a CP test or an FT test on a wafer will obtain a corresponding STDF file. In this embodiment, by executing the wafer test data processing method provided in this application, it is possible to process an STDF file individually or to process multiple STDF files in batches, and the manner in which each STDF file is processed is similar to the manner in which an STDF file is processed individually. This embodiment is not limited to this, and this embodiment is illustrated by taking the processing of an STDF file individually as an example.

[0067] The format of the test data in the STDF file is binary format. The user cannot read the binary format directly and needs to parse the STDF file. Accordingly, after obtaining the STDF file, the following step S102 is executed.

[0068] Step S102 , parsing the standard test data file to obtain data files corresponding to a plurality of data types; wherein the data files include test record data belonging to corresponding data types.

[0069] This embodiment parses the STDF file to obtain data files corresponding to multiple data types, thereby achieving segmentation of the STDF file.

[0070] If the STDF file is generated during CP testing, the multiple data types include at least two of test configuration, test results, and test attribution.

[0071] Exemplarily, the data file corresponding to the test configuration includes multiple types of test record data, such as product identification (Product Id), lot identification (Lot Id), wafer identification (Wafer Id), test station (Site) identification, test start and end time, or test record data corresponding to at least two of other test configurations. Exemplarily, the test record data is stored in the data file in a key-value format. For example, the key is the product identification and the value is A, indicating that the product identification to which the wafer being tested belongs is A. For another example, the key is the batch identification and the value is 2, indicating that the product batch to which the wafer being tested belongs is the second batch.

[0072] Exemplarily, the data file corresponding to the test results includes the test results corresponding to each position chip on the wafer. Exemplarily, the test results corresponding to the position chip include the test results of each test item tested by the position chip, where the test items include parameter tests and functional tests.

[0073] Exemplarily, test assignments include two categories: HardBin (hard decision) and SoftBin (soft decision), and the data files corresponding to the test assignments include two categories: hard decision data files and soft decision data files. In practical applications, HardBin is usually used to indicate physical defects or faults, while SoftBin is usually used to indicate functional or logical problems. Exemplarily, a hard decision data file contains test record data corresponding to multiple hard decision types, such as OS (OpenShort, open short circuit test), DFT (Design for Testability, testability design), IP (Intellectual Property, intellectual property), etc. Among them, OS testing is used to confirm whether the signal pin is electrically connected to the corresponding channel of the test system during the test, and whether there is a short circuit between the signal pin and other signal pins, power supply or ground. IP in the chip industry is generally called IP core, which is a general term for integrated circuit cores with intellectual property cores, including designed, verified, and reusable integrated circuit modules. Accordingly, for any hard decision type, the test record data corresponding to the hard decision type includes the location chip belonging to that hard decision type, and the location chip is represented by coordinates, which are used to indicate the location of the location chip on the wafer. Similarly, the soft decision data file contains test record data corresponding to multiple soft decision types, and the test record data corresponding to the soft decision type includes the location chip belonging to that soft decision type, and the location chip is represented by coordinates. Among them, the location chip belonging to a certain type indicates that the location chip failed the test for that type.

[0074] For example, the data file obtained by parsing may be a file in a format such as Excel or CSV (Comma-Separated Values).

[0075] It should be noted that in addition to the multiple data types listed above, data files corresponding to other data types can also be parsed as needed. For example, multiple data types also include hardware information. Accordingly, the data file corresponding to the hardware information includes test record data such as the model and number of the probe station and probe card, and the arrangement information of the test stations.

[0076] Step S103 : generating analyzable data corresponding to each of a plurality of preset categories based on the data files corresponding to the plurality of data types.

[0077] The multiple preset categories can be set based on actual needs. For example, a user can set multiple preset categories based on analysis requirements. For example, if the STDF file is generated during CP testing, the multiple preset categories include a hard decision category, a soft decision category, a yield category, a test decision result category, a test data category, and a test pass condition category.

[0078] Step S104: outputting the analyzable data corresponding to each preset category.

[0079] Exemplarily, the analyzable data corresponding to each preset category is output in the form of a file.

[0080] In this embodiment, for the STDF file generated when the wafer is tested, the STDF file is first parsed to obtain data files corresponding to multiple data types, and then corresponding analyzable data are generated according to multiple preset categories, thereby realizing automatic parsing and classification of wafer test data. Compared with manual classification and organization, the present application is more efficient and reduces the occurrence of data errors caused by human factors.

[0081] In an exemplary embodiment, in the standard test data file, the test record data corresponding to each data type is located in a different position; the implementation of step S102 includes:

[0082] For each data type, perform the following operations:

[0083] Traverse the standard test data file and extract the test record data from the position corresponding to the data type;

[0084] The extracted test record data is stored in the corresponding data file.

[0085] Among them, the STDF file uses a unified specification to record the data generated during the test. Different types of data are recorded in different locations in the STDF file. Therefore, the location information corresponding to each data type can be determined in advance according to the STDF file specification, and the location information corresponding to each data type can be stored. The location information corresponding to the data type is used to indicate the location of the data belonging to the data type in the STDF file. When parsing the STDF file, according to the stored location information corresponding to each data type, the STDF file is traversed and the test record data is extracted, and then stored in the data file.

[0086] For example, in the STDF file, data of the test configuration data type is located in the Part Information Record (PIR) data block; data of the test result data type is located in the Part Results Record (PRR) data block, and the test results corresponding to each position chip are separated respectively; test attribution, that is, Binning, is the work done by the test machine, and data of this data type is located in the Test Record (TR) data block.

[0087] Since the data in the STDF file is in binary format, after the test record data is extracted, it can be converted into a readable format and then stored in a data file.

[0088] In this embodiment, by traversing the STDF file and extracting test record data from the location corresponding to each data type, the accuracy of data extraction can be ensured. Storing the data in the corresponding data file also helps to keep the data neat and orderly, and can also ensure the security and traceability of the data, which is convenient for subsequent use. Through automated parsing, work efficiency is improved and the occurrence of human errors is reduced.

[0089] In an exemplary embodiment, after step S102 , the wafer test data processing method provided by the present application further includes: performing normative mapping on specific fields in each data file.

[0090] Among them, the STDF file is a file generated by the test machine. Some fields in the test record data extracted from the STDF file may not conform to the user's reading habits, so specific fields can be normatively mapped to make them conform to the user's reading habits. Accordingly, the user can set at least one set of field mapping relationships in advance as needed and store them in the electronic device. After parsing the data file, traverse the data file and perform normative mapping on the specific fields in the data file according to the stored field mapping relationships to obtain the processed fields. For example, the product identification field can be replaced with the product name, and the batch identification field can be replaced with the batch number.

[0091] In this embodiment, by performing normative mapping on specific fields, the standardization of data is improved and the reading habits of users can be conformed to as much as possible.

[0092] In an exemplary embodiment, if the standard test data file is generated during CP testing, the plurality of preset categories include a hard decision category, a soft decision category, a yield category, a test decision result category, a test data category, and a test pass condition category.

[0093] The analyzable data belonging to the hard decision category includes statistical information corresponding to multiple hard decision types, and the statistical information includes the number of location chips belonging to the corresponding hard decision type. As can be seen from the description of step S102, in the hard decision data file, the test record data corresponding to each hard decision type includes location chips belonging to that hard decision type. Therefore, when the preset category is the hard decision category, the method for generating analyzable data corresponding to the hard decision category based on the data files corresponding to the multiple data types includes determining the number of location chips in the test record data corresponding to each hard decision type in the hard decision data file to obtain statistical information corresponding to each hard decision type.

[0094] The analyzable data belonging to the soft decision category includes statistical information corresponding to multiple soft decision types, and the statistical information includes the number of position chips belonging to the corresponding soft decision type. Specifically, each soft decision type includes at least one test item, and the statistical information corresponding to the soft decision type includes not only the number of position chips belonging to the soft decision type, but also includes statistical information corresponding to each test item belonging to the soft decision type, and the statistical information includes the number of position chips belonging to the test item. From the relevant description of step S102, it can be seen that: in the soft decision data file, the test record data corresponding to each soft decision type includes the position chips belonging to this soft decision type. Then, based on the data files corresponding to multiple data types, the implementation method of generating analyzable data corresponding to the soft decision category includes: determining the number of position chips in the test record data corresponding to each soft decision type in the soft decision data file to obtain the statistical information corresponding to each soft decision type.

[0095] Among them, the analyzable data belonging to the yield category includes the yield corresponding to each test item and the yield corresponding to the wafer. The yield corresponding to the wafer is the ratio between the number of position chips that passed the test and the total number of position chips on the wafer, and the position chips that passed the test refer to the position chips whose test results for all the tested test items passed the test. The yield corresponding to the test item is the ratio between the number of position chips whose test results for the test item passed the test and the total number of position chips on the wafer.

[0096] The analyzable data belonging to the test determination result category includes the test determination results corresponding to each chip at each position on the wafer, and the test determination results include the test determination results of each test item tested by the chip at the corresponding position. Optionally, when the preset category is the test determination result category, based on data files corresponding to multiple data types, the implementation method of generating the analyzable data corresponding to the test determination result category includes: performing the following operations for each chip at each position on the wafer:

[0097] For each test item tested by the positioning chip, the test pass conditions corresponding to the test item and the test data corresponding to the positioning chip are obtained from the data files corresponding to multiple data types respectively, and the test judgment results of the positioning chip for the test items are determined based on the test pass conditions corresponding to the test item and the test data corresponding to the positioning chip; the test judgment results indicate whether the test passed, failed or was not tested.

[0098] Among them, according to the test pass conditions corresponding to the test items and the test data corresponding to the location chip, the implementation method of determining the test judgment results of the location chip for the test items includes: for parameter-type tests, the corresponding test pass conditions are threshold ranges, and accordingly, if the test value of the location chip exceeds the threshold range, the test fails, and if the test value of the location chip does not exceed the threshold range, the test passes. For functional tests, the corresponding test pass conditions are pass identifiers, and accordingly, if the test value of the location chip is the same as the pass identifier, the test passes, and if the test value of the location chip is different from the pass identifier, the test fails. It should be noted that if the location chip does not have a test value for a certain test item, it is considered that the location chip has not tested the test item.

[0099] This embodiment provides a specific data generation solution for the test judgment result category, and obtains the test judgment results of the chips at each position on the wafer for each tested test item, eliminating the need for manual calculation by the user and simplifying the user operation.

[0100] Analyzable data belonging to the test data category includes test data corresponding to each test item. The test data includes test data corresponding to each location chip that has tested the corresponding test item. For any test item, the test data corresponding to the location chip refers to the test value of the location chip for that test item. For example, if the test item is voltage, the test data corresponding to the location chip is the specific voltage value measured.

[0101] The analyzable data belonging to the test pass condition category includes the test pass conditions corresponding to each test item. Test items include parametric tests and functional tests. For parametric tests, the corresponding test pass conditions can be set to a threshold range. For functional tests, the corresponding test pass conditions can be set to a pass flag, such as a pass flag of 1. Exemplarily, the analyzable data belonging to the test pass condition category is expressed in the SPEC (specification, detailed product requirements and standards) format.

[0102] This embodiment provides a plurality of preset categories, each of which contains different analyzable data. By dividing the data into multiple categories, it is convenient for users to read and analyze the data.

[0103] Based on the STDF file, users can also perform Continue on Fail (COF) analysis, thereby quickly understanding and grasping the distribution of wafer failures for failure tracing analysis. Accordingly, based on the above embodiment, this application also provides a wafer map generation process corresponding to COF.

[0104] Figure 3 FIG. 1 is a schematic diagram showing a COF wafer image generation process according to an exemplary embodiment. Figure 3 As shown, the COF wafer image generation process provided in this embodiment includes the following steps:

[0105] Step S201: Obtain a user-defined test item group; the test item group includes multiple test items.

[0106] In this embodiment, users can customize a test item group (SoftBin Group) based on actual needs. The test item group contains multiple test items, and these multiple test items belong to the same SoftBin. For example, the user selects multiple test items from any SoftBin through an electronic device to obtain a test item group. The test items are identified by a test item number (Test Number) and a test item name (Test Name).

[0107] In step S202 , for each position chip on the wafer, the test determination results of each position chip for each test item are obtained from the analyzable data belonging to the test determination result category.

[0108] In this step, when obtaining the test determination result of the position chip, the coordinates of the position chip are also obtained to facilitate the subsequent drawing of the wafer map corresponding to the COF.

[0109] Step S203 , generating a yield rate and a wafer map corresponding to the COF according to the test results of each test item for each chip at each position on the wafer.

[0110] This embodiment provides a solution for generating COF corresponding yield and wafer map based on the classification results of the STDF file, realizes the integration of STDF parsing classification and COF analysis functions, and simplifies the workflow of data analysts.

[0111] The COF yield is referred to as the COF yield, which refers to the ratio between the number of position chips on the wafer that have a passing result and the total number of position chips on the wafer.

[0112] For each position chip on the wafer, the test determination results of the position chip for each test item are numerically mapped to obtain a state matrix of the position chip for each test item, where the elements in the state matrix are the test determination results expressed in numerical form;

[0113] For each chip at each position on the wafer, the state matrix of each test item of the chip at each position is multiplied to obtain the final judgment result; the final judgment result indicates pass, fail or not tested;

[0114] The ratio between the number of position chips on the wafer that are finally determined to be passed and the total number of position chips on the wafer is determined as the COF yield;

[0115] According to the coordinates corresponding to the chips at each position on the wafer and the final judgment results, a wafer map corresponding to the COF is generated.

[0116] Among them, since the representation of the test determination result may not be a numerical value, for the convenience of calculation, the test determination result can be numerically mapped to obtain the corresponding state matrix. The test determination result includes three cases: pass, fail and untested. Different numerical values ​​can be set for each case to facilitate distinction. For example, the numerical value corresponding to pass (Pass) is -1.001, the numerical value corresponding to fail (Fail) is 0, and the numerical value corresponding to untested (NULL) is 1. Then the state matrix corresponding to the position chip contains one element, which is -1.001, 0 or 1. Accordingly, for each position chip on the wafer, if its test determination result is multiplied by 0, it means that there is a failure in the test determination result, and its final determination result is failure; if its test determination result is multiplied by 1, it means that the position chip has not been tested for each test item in the test item group, and its final determination result is untested; if its test determination result is multiplied by neither 0 nor 1, it means that there is no failure in the test result and the test determination result for the tested test item is passed, and its final determination result is passed.

[0117] When generating a wafer map corresponding to the COF, different colors or symbols are used for different final determination results to facilitate differentiation. The symbols corresponding to different final determination results can be set according to actual needs and are not limited by this application. For example, chips with a final determination result of "pass" are represented in green, chips with a final determination result of "fail" are represented in red, and chips with a final determination result of "untested" are represented in yellow.

[0118] In this embodiment, the final determination result of the position chip is generated according to the test determination result of each test item of the position chip, so that a wafer map corresponding to COF can be drawn and the COF yield can be calculated according to the final determination result with high accuracy.

[0119] The wafer test data processing method provided in this application has been tested by the inventors and found to be able to achieve minute-level response, greatly improving the efficiency of test data analysis, and further COF analysis also supports second-level response, which helps to quickly understand the distribution pattern of wafer failures for failure tracing.

[0120] Figure 4 FIG. 1 is a schematic structural diagram of a wafer test data processing device according to an exemplary embodiment. Figure 4 As shown, in this embodiment, the wafer test data processing device 300 can be set in an electronic device, and the wafer test data processing device 300 includes:

[0121] An acquisition module 301 is used to acquire a standard test data file generated when testing a wafer;

[0122] The parsing module 302 is used to parse the standard test data file to obtain data files corresponding to multiple data types; wherein the data files include test record data belonging to corresponding data types;

[0123] A generating module 303 is configured to generate analyzable data corresponding to each of a plurality of preset categories based on data files corresponding to the plurality of data types;

[0124] The output module 304 is used to output the analyzable data corresponding to each preset category.

[0125] Optionally, in the standard test data file, the test record data corresponding to each data type is located in a different position; the parsing module 302 is specifically used to:

[0126] For each data type, perform the following operations:

[0127] Traverse the standard test data file and extract the test record data from the position corresponding to the data type;

[0128] The extracted test record data is stored in the corresponding data file.

[0129] Optionally, a mapping module is further included, and the mapping module is used to perform normative mapping on specific fields in each data file.

[0130] Optionally, if the standard test data file is generated during CP testing, the plurality of preset categories include a hard decision category, a soft decision category, a yield category, a test decision result category, a test data category, and a test pass condition category;

[0131] The analyzable data belonging to the hard decision category includes statistical information corresponding to a plurality of hard decision types, and the statistical information includes the number of position chips belonging to the corresponding hard decision type and passing the test;

[0132] The analyzable data belonging to the soft decision category includes statistical information corresponding to a plurality of soft decision types, and the statistical information includes the number of position chips belonging to the corresponding soft decision type and passing the test;

[0133] The analyzable data belonging to the yield category includes the yield corresponding to each test item and the yield corresponding to the wafer;

[0134] The analyzable data belonging to the test determination result category includes the test determination results corresponding to each chip at each position on the wafer, and the test determination results include the test determination results of each test item tested by the chip at the corresponding position;

[0135] The analyzable data belonging to the test data category includes test data corresponding to each test item, and the test data includes test data corresponding to each position chip that has tested the corresponding test item;

[0136] The analyzable data belonging to the test pass condition category includes the test pass conditions corresponding to each test item.

[0137] Optionally, when the preset category is a test determination result category, the generating module 303 is configured to:

[0138] For each chip on the wafer, perform the following operations:

[0139] For each test item tested by the positioning chip, the test pass conditions corresponding to the test item and the test data corresponding to the positioning chip are obtained from the data files corresponding to multiple data types respectively, and the test judgment results of the positioning chip for the test items are determined based on the test pass conditions corresponding to the test item and the test data corresponding to the positioning chip; the test judgment results indicate whether the test passed, failed or was not tested.

[0140] Optionally, a COF analysis module is further included, and the COF analysis module includes:

[0141] A first acquiring unit is configured to acquire a user-defined test item group; the test item group includes a plurality of test items;

[0142] The second acquisition unit is configured to acquire, for each position chip on the wafer, the test determination result of each position chip for each test item from the analyzable data belonging to the test determination result category;

[0143] The generation unit is used to generate the corresponding yield and wafer map for continued testing when failure occurs based on the test judgment results of each test item for each chip at each position on the wafer.

[0144] Optionally, a generating unit is configured to:

[0145] For each position chip on the wafer, the test judgment result of each test item of the position chip is numerically mapped to obtain a state matrix of the position chip for each test item, where the elements in the state matrix are the test judgment results expressed in numerical form;

[0146] For each chip at each position on the wafer, the state matrix of each test item of the chip at each position is multiplied to obtain the final judgment result; the final judgment result indicates pass, fail or not tested;

[0147] The yield is determined as the ratio between the number of position chips on the wafer that are finally determined to be passed and the total number of position chips on the wafer;

[0148] A wafer map is generated based on the coordinates corresponding to the chips at each position on the wafer and the final judgment results.

[0149] The wafer test data processing device provided in this embodiment can execute the technical solution of the corresponding method embodiment. Its implementation principle and technical effects are similar to those of the corresponding method embodiment, and will not be described in detail here.

[0150] The present application also provides an electronic device. For example, the electronic device is a terminal device used by technicians in a wafer fab. For example, the electronic device is a computer, a workbench, a personal digital assistant, or other suitable terminal device. Figure 5 FIG. 1 is a schematic diagram showing the structure of an electronic device according to an exemplary embodiment. Figure 5 As shown, the electronic device 400 includes: a processor 401 and a memory 402 communicatively connected to the processor 401 .

[0151] The memory 402 stores computer-executable instructions; the processor 401 executes the computer-executable instructions stored in the memory 402 to implement the wafer test data processing method provided in this application.

[0152] In the embodiment of the present application, the memory 402 and the processor 401 are connected via a bus. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, and the like.

[0153] The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein. The various components are interconnected using different buses and can be mounted on a common motherboard or in other ways as needed.

[0154] In an exemplary embodiment, a computer-readable storage medium is further provided, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the wafer test data processing method provided in the present application.

[0155] In an exemplary embodiment, a computer program product is further provided, comprising computer-executable instructions. When the computer-executable instructions in the computer program product are executed by a processor, the computer-executable instructions are used to implement the wafer test data processing method provided in the present application.

[0156] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required by this application.

[0157] It should be further noted that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0158] It should be understood that the above-described device embodiments are merely illustrative, and the device of the present application may also be implemented in other ways. For example, the division of units / modules in the above-described embodiments is merely a logical functional division, and actual implementations may employ other division methods. For example, multiple units, modules, or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0159] In addition, unless otherwise specified, the functional units / modules in the various embodiments of the present application may be integrated into a single unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The aforementioned integrated units / modules may be implemented in the form of hardware or software program modules.

[0160] If the integrated unit / module is implemented in hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor may be any appropriate hardware processor, such as a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a digital signal processor (DSP), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. Unless otherwise specified, the memory may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a USB flash drive, random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), enhanced dynamic random-access memory (EDRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), high-bandwidth memory (HBM), hybrid memory cube (HMC), and other media that can store program code.

[0161] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory and includes a number of instructions for enabling an electronic device to execute all or part of the steps of the various embodiments of the method of the present application.

[0162] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0164] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A wafer test data processing method, characterized in that: include: Obtaining a standard test data file generated when testing a wafer; Parsing the standard test data file to obtain data files corresponding to a plurality of data types; wherein the data files include test record data belonging to corresponding data types; Based on the data files corresponding to the multiple data types, respectively, generating analyzable data corresponding to each of the multiple preset categories; The analyzable data corresponding to each of the preset categories are output respectively.

2. The method according to claim 1, characterized in that In the standard test data file, test record data corresponding to each data type is located in different positions; parsing the standard test data file to obtain data files corresponding to multiple data types includes: For each data type, perform the following operations respectively: Traversing the standard test data file and extracting test record data from a position corresponding to the data type; The extracted test record data is stored in the corresponding data file.

3. The method according to claim 1 or 2, characterized in that After parsing the standard test data file to obtain data files corresponding to multiple data types, the method further includes: The specific fields in each of the data files are mapped in a normative manner.

4. The method according to claim 1, wherein If the standard test data file is generated during CP testing, the plurality of preset categories include a hard decision category, a soft decision category, a yield category, a test decision result category, a test data category, and a test pass condition category; The analyzable data belonging to the hard decision category includes statistical information corresponding to a plurality of hard decision types, and the statistical information includes the number of position chips belonging to the corresponding hard decision type and passing the test; The analyzable data belonging to the soft decision category includes statistical information corresponding to a plurality of soft decision types, and the statistical information includes the number of position chips belonging to the corresponding soft decision type and passing the test; The analyzable data belonging to the yield category includes the yield corresponding to each test item and the yield corresponding to the wafer; The analyzable data belonging to the test determination result category includes the test determination results corresponding to each chip at each position on the wafer, and the test determination results include the test determination results of each test item tested by the chip at the corresponding position; The analyzable data belonging to the test data category includes test data corresponding to each test item, and the test data includes test data corresponding to each position chip that has tested the corresponding test item; The analyzable data belonging to the test pass condition category includes the test pass conditions corresponding to each test item.

5. The method according to claim 4, characterized in that When the preset category is a test determination result category, generating analyzable data corresponding to the test determination result category based on the data files corresponding to the multiple data types respectively includes: For each chip on the wafer, perform the following operations: For each test item tested by the position chip, the test pass conditions corresponding to the test item and the test data corresponding to the position chip are obtained from the data files corresponding to the multiple data types respectively, and the test judgment result of the position chip for the test item is determined based on the test pass conditions corresponding to the test item and the test data corresponding to the position chip; the test judgment result indicates test pass, test failure or not tested.

6. The method according to claim 4, characterized in that Also includes: Obtain a user-defined test item group; the test item group includes multiple test items; For each position chip on the wafer, obtaining the test determination results of each position chip for each test item from the analyzable data belonging to the test determination result category; Based on the test judgment results of the chips at each position on the wafer for each of the test items, a corresponding yield rate and wafer map corresponding to continued testing when failure occurs are generated.

7. The method according to claim 6, characterized in that The method of generating a yield rate and a wafer map corresponding to continued testing when a failure occurs based on the test judgment results of the chips at each position on the wafer for each test item includes: For each position chip on the wafer, numerically mapping the test determination results of the position chip for each test item to obtain a state matrix of the position chip for each test item, wherein the elements in the state matrix are the test determination results expressed in numerical form; For each position chip on the wafer, multiply the state matrix of each test item of the position chip to obtain a final determination result; the final determination result indicates pass, fail or not tested; Determine the yield as the ratio between the number of position chips on the wafer that are finally determined to be passed and the total number of position chips on the wafer; The wafer map is generated based on the coordinates corresponding to the chips at each position on the wafer and the final determination result.

8. A wafer test data processing device, characterized in that: include: An acquisition module, used for acquiring a standard test data file generated when testing a wafer; A parsing module, configured to parse the standard test data file to obtain data files corresponding to a plurality of data types; wherein the data files include test record data belonging to corresponding data types; A generating module, configured to generate analyzable data corresponding to each of a plurality of preset categories based on the data files corresponding to the plurality of data types; The output module is used to output the analyzable data corresponding to each of the preset categories respectively.

9. An electronic device, characterized in that: include: a processor and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the wafer test data processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the wafer test data processing method according to any one of claims 1 to 7.

11. A computer program product comprising computer-executable instructions, characterized in that: When the computer-executable instructions are executed by a processor, the wafer test data processing method according to any one of claims 1 to 7 is implemented.

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