Parasitic resistance calculation method and system applied to VLSI design

Abstract

The invention provides a parasitic resistance calculation method and system applied to VLSI design, and the method comprises the following steps: S1, selecting a target physical layer in a VLSI layout, and obtaining a parasitic resistance geometric shape in the target physical layer based on the position of a current inlet terminal, the position of a current outlet terminal and the position of a conductive element through frame selection; s2, performing similarity comparison on the geometrical shape of the parasitic resistor and cached data in a comparison database, if the cached data matched with the geometrical shape of the parasitic resistor exists in the comparison database, outputting a resistance matrix corresponding to the cached data, and if the cached data matched with the geometrical shape of the parasitic resistor does not exist in the comparison database, outputting a resistance matrix corresponding to the cached data; if yes, resistance matrix calculation is carried out on the parasitic resistance geometrical shape through a Laplacian equation field solver, and the parasitic resistance geometrical shape and a corresponding resistance matrix are cached into a comparison database. According to the invention, the calculation precision and speed of the resistance value of the parasitic resistor in the VLSI design can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a parasitic resistance calculation method and system applied in VLSI design. Background Art

[0002] A very large scale integration circuit (VLSI) is an integrated circuit that combines a large number of transistors into a single chip, achieving a higher level of integration than an LSI. In VLSI design, parasitic resistance refers to the non-ideal resistance caused by physical structures such as interconnects, vias, and transistors. In modern chip design, which demands high speed, low power consumption, and high-density integration, the presence of parasitic resistance has a significant impact on circuit performance. Therefore, accurately calculating and extracting parasitic resistance is a key step in VLSI design.

[0003] Under existing technology, for parasitic resistors of arbitrary shapes, conventional parasitic resistor value calculation methods include: rectangle counting, which can approximate the resistance by estimating the length and width of the interconnection line segment. However, the rectangle counting method is only applicable to regular geometric shapes. With the reduction of technology nodes and the increase in interconnection complexity, the rectangle counting method can no longer meet the requirements for calculation accuracy, especially when dealing with non-rectangular shapes or complex topological structures. The second method is based on solving the Laplace equation, but the Laplace equation calculation is relatively complex and requires a lot of computing resources and time when dealing with large-scale circuit structure design. Summary of the Invention

[0004] The present invention aims to provide a parasitic resistance calculation method and system for use in VLSI design, so as to solve the technical problem that conventional parasitic resistance calculation methods and systems cannot achieve high-precision and high-speed calculation under the existing technology.

[0005] To solve the above problems, the technical solution of the present invention is: a parasitic resistance calculation method applied in VLSI design, comprising the following steps: S1: Select the target physical layer in the VLSI layout, and select the parasitic resistance geometry based on the current inlet terminal position, the current outlet terminal position, and the conductive element position in the target physical layer; S2: Perform a similarity comparison between the parasitic resistance geometry and the cached data in the comparison database. If cached data matching the parasitic resistance geometry exists in the comparison database, output a resistance matrix corresponding to the cached data. If cached data matching the parasitic resistance geometry does not exist in the comparison database, calculate the resistance matrix of the parasitic resistance geometry using a Laplace equation field solver, and cache the parasitic resistance geometry and its corresponding resistance matrix in the comparison database.

[0006] Preferably, in S1, obtaining the parasitic resistance geometry by selecting based on the current inlet terminal position, the current outlet terminal position and the conductive element position specifically includes the following steps: S11: select any vertex in the boundary of the original shape of the parasitic resistance formed by the current inlet terminal position, the current outlet terminal position and the conductive element position, and use it as the shape origin; S12: traversing the boundary of the parasitic resistor original shape in a clockwise or counterclockwise direction, subtracting the shape origin from all remaining boundary vertex positions of the parasitic resistor original shape to obtain reference coordinates of each vertex of the parasitic resistor original shape, and subtracting the shape origin from the current inlet terminal position, the current outlet terminal position, and the conductive element position within the parasitic resistor original shape to obtain reference coordinates of the current inlet terminal position, the current outlet terminal position, and the conductive element position; S13: Recording a two-dimensional shape constructed by the vertices of the parasitic resistor original shape boundary and the reference coordinates of the current inlet terminal position, the current outlet terminal position, and the conductive element position in the parasitic resistor original shape as the parasitic resistor geometric shape in a standard form.

[0007] Preferably, the comparison database adopts a cache mechanism based on a hash function, and the cache data pre-stored in the comparison database includes a parasitic resistance comparison shape, an equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and a first hash value obtained by calculating the parasitic resistance comparison shape through a hash function; In S2, the parasitic resistance geometry is compared with the cached data in the comparison database for similarity, specifically comprising the following steps: S21: Calculate the parasitic resistance geometry through a hash function to obtain a second hash value; S22: Compare the second hash value with several first hash values ​​in the comparison database, and when there is a first hash value that is consistent with the second hash value, output an equivalent resistance matrix corresponding to the first hash value.

[0008] Preferably, the comparison database further adopts a cache mechanism of a map mapping technology, and when there is the first hash value that is consistent with the second hash value in S22, the following steps are further included: S23: Select the parasitic resistance comparison shape represented by the first hash value, and compare the reference coordinates of the vertices of the boundary of the parasitic resistance geometric shape and the reference coordinates of the current entry terminal position, the current exit terminal position, and the conductive element position of the parasitic resistance comparison shape with the parasitic resistance geometric shape in sequence. When the geometric features of the parasitic resistance comparison shape and the parasitic resistance geometric shape are completely consistent, output the equivalent resistance matrix corresponding to the first hash value.

[0009] Preferably, in S1, when simultaneously selecting and acquiring several groups of parasitic resistance geometric shapes in the target physical layer, the following steps are further included: S24: firstly perform similarity comparison on several groups of the parasitic resistance geometric shapes, assign a first identifier to the parasitic resistance geometric shapes with consistent geometric shapes, and only perform similarity comparison on the group of the parasitic resistance geometric shapes corresponding to the first identifier and the cached data in the comparison database.

[0010] Preferably, in S2, a resistance matrix calculation is performed on the parasitic resistance geometry by using a Laplace equation field solver, specifically comprising the following steps: S25: Convert the parasitic resistance geometry into a grid form and apply the Laplace equation on the grid , where V is the potential, and the potential values ​​are set at the current entry terminal and the circuit exit terminal respectively; S26: Calculate current density from potential distribution , where σ is the conductivity; S27: According to Ohm's law , where V 差 is the potential difference between the current inlet terminal and the current outlet terminal, current I is the integral of current density J, and the resistance matrix R between the current inlet terminal and the current outlet terminal is calculated.

[0011] Preferably, the solution method of the Laplace equation field solver includes finite element analysis method, boundary element method, finite difference method and Monte Carlo method.

[0012] Preferably, when there is a single current entry terminal and several current exit terminals, the resistance values ​​between the current entry terminal and different current exit terminals are calculated respectively, and a network analysis method is used to generate an equivalent single resistance matrix from the multiple resistance values ​​between the current entry terminal and multiple current exit terminals.

[0013] Preferably, establishing the comparison database specifically includes the following steps: S31: Acquire several groups of parasitic resistance original shapes that are pre-cached in the comparison database, and convert them into parasitic resistance comparison shapes in a standard form; S32: performing similarity comparison on the plurality of groups of parasitic resistance comparison shapes, assigning a second identifier to the parasitic resistance comparison shapes with the same geometric shape, and calculating a resistance matrix of each group of parasitic resistance comparison shapes corresponding to the second identifier, which is recorded as an equivalent resistance matrix; S33: caching only a group of the parasitic resistance comparison shapes corresponding to the second identifier, an equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and a hash value obtained by calculating the parasitic resistance comparison shape through a hash function in the comparison database.

[0014] Based on the same concept, the present invention further provides a parasitic resistance calculation system for VLSI design, which is used to execute any of the above-mentioned parasitic resistance calculation methods for VLSI design, comprising: A parasitic resistance shape selection module is used to obtain the parasitic resistance geometry from the target physical layer based on the current inlet terminal position, the current outlet terminal position and the conductive element position; a parasitic resistor shape comparison module, configured to compare the parasitic resistor geometry with cached data in a comparison database for similarity; The parasitic resistor value calculation module is used to perform resistance matrix calculation on the parasitic resistor geometry through a Laplace equation field solver.

[0015] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: The present invention provides a parasitic resistance calculation method and system for use in VLSI design. First, a parasitic resistance geometry is obtained by selecting a current inlet terminal position, a current outlet terminal position, and a conductive element position. The parasitic resistance geometry is compared with cached data in a comparison database for similarity. When cached data matching the parasitic resistance geometry exists, the resistance matrix of the cached data is directly called, reducing the calculation steps for parasitic resistances with repeated geometries and effectively improving the efficiency of obtaining resistance values. When cached data matching the parasitic resistance geometry does not exist, a Laplace equation field solver is used to calculate the resistance matrix of the parasitic resistance geometry, and the parasitic resistance geometry and its corresponding resistance matrix are cached in the comparison database as one of the comparison sources for subsequently obtained parasitic resistance geometries. By continuously replenishing the comparison database during the VLSI design process, the overall calculation accuracy and speed of parasitic resistance values ​​in VLSI design are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention provides a flow chart of a parasitic resistance calculation method applied in VLSI design; Figure 2 Schematic diagram of the processing process of the parasitic resistance geometry provided by the present invention. DETAILED DESCRIPTION

[0017] The following is a detailed description of a parasitic resistance calculation method and system for VLSI design proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0018] First embodiment See Figures 1 to 2 This embodiment provides a parasitic resistance calculation method applied to VLSI design, which is used to quickly calculate the parasitic resistance value in VLSI design. The method specifically includes the following steps: S1: Select a target physical layer in the VLSI layout. The physical layer includes the metal layer, via layer, diffusion layer, polysilicon layer and contact layer. In the target physical layer, select the parasitic resistance geometry based on the current inlet terminal position, current outlet terminal position and conductive element position.

[0019] Among them, parasitic resistance refers to the resistance of the conductive structure in the physical layer of the chip, which is mainly caused by the physical characteristics of the interconnecting wires, contact points, vias and active areas. Therefore, the geometric characteristics of the conductive structure in the physical layout are the parasitic resistance geometry. That is, in VLSI design, the current entry terminal, current outlet terminal and conductive elements are all specific physical entities. Their shape, size, material properties and relative position determine the size of the parasitic resistance geometry.

[0020] S2: Assume that a number of cache data are pre-stored in the comparison database, and compare the obtained parasitic resistance geometry with the cache data in the comparison database for similarity. If there is cache data matching the parasitic resistance geometry in the comparison database, the comparison database directly outputs the resistance matrix corresponding to the cache data; if there is no cache data matching the parasitic resistance geometry in the comparison database, the resistance matrix of the parasitic resistance geometry is calculated using the Laplace equation field solver, and the parasitic resistance geometry and its corresponding resistance matrix are cached in the comparison database to form a new set of cache data.

[0021] In VLSI design, steps S1-S2 are repeatedly executed until the VLSI design is complete. During the VLSI design process, since a large number of repeated parasitic resistor geometries exist within a chip, this embodiment can effectively shorten the time required to calculate all parasitic resistor values ​​in the VLSI design, thereby improving VLSI design efficiency. Furthermore, for newly acquired parasitic resistor geometries with special geometric features, the parasitic resistor geometries and their resistance matrices are cached in a comparison database, becoming a comparison source for subsequently acquired parasitic resistor geometries. The self-learning nature of the comparison database further improves the overall accuracy and speed of parasitic resistor value calculations in the VLSI design.

[0022] The following further describes in detail the specific implementation steps and functions of the parasitic resistance calculation method for VLSI design provided in this embodiment: Preferably, in this embodiment, in S1, obtaining the parasitic resistance geometry based on the current inlet terminal position, the current outlet terminal position, and the conductive element position is performed by selecting the parasitic resistance geometry, which specifically includes the following steps: S11: Select the boundary of the parasitic resistance primitive shape formed by the current inlet terminal position, the current outlet terminal position and the conductive element position, and any vertex is the shape origin. That is, if there is a polygonal parasitic resistance primitive shape, the vertex coordinates in its boundary are (x1, y2), (x2, y2), ..., (x n ,y n ), then (x1,y2) is selected as the shape origin and redefined as (0,0).

[0023] S12: Select to traverse the boundary of the original shape of the parasitic resistor in a clockwise or counterclockwise direction to obtain a complete closed boundary of the original shape of the parasitic resistor, subtract the shape origin from all remaining boundary vertex positions of the original shape of the parasitic resistor, and obtain the reference coordinates of each vertex of the original shape of the parasitic resistor, and subtract the shape origin from the current inlet terminal position, current outlet terminal position and conductive element position inside the original shape of the parasitic resistor, and obtain the reference coordinates of the current inlet terminal position, current outlet terminal position and conductive element position. That is, in one embodiment, taking the boundary vertex position of the original shape of the parasitic resistor as an example, the reference coordinates of the boundary vertex position of the original shape of the parasitic resistor will be transformed into (0,0), (x2-x1, y2-y1), (x3-x1, y3-y1), ..., (x n -x1,y n -y1).

[0024] S13: Recording a two-dimensional shape constructed by the vertices of the parasitic resistor original shape boundary and the reference coordinates of the current inlet terminal position, the current outlet terminal position, and the conductive element position in the parasitic resistor original shape as a canonical parasitic resistor geometric shape.

[0025] In VLSI design and parasitic resistance extraction, different geometric transformations (such as translation, rotation, scaling, etc.) may cause the same shape to be represented differently in the coordinate system. Therefore, in this embodiment, by converting the original shape of the parasitic resistor into a canonical parasitic resistor geometric shape, it can be ensured that the same shape can be correctly identified in any position or direction, thereby improving the speed and accuracy of similarity comparison between the parasitic resistor geometric shape and the cached data in the comparison database, avoiding repeated resistance calculations for the same shape, and thus saving computing resources and time.

[0026] Preferably, in this embodiment, the comparison database adopts a cache mechanism based on a hash function, and the cache data pre-stored in the comparison database includes the parasitic resistance comparison shape, the equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and the first hash value obtained by calculating the parasitic resistance comparison shape through the hash function; In S2, the parasitic resistance geometry is compared with the cached data in the comparison database for similarity, which specifically includes the following steps: S21: Calculate the parasitic resistance geometry through a hash function to obtain a second hash value; S22: Compare the second hash value with several first hash values ​​pre-stored in the comparison database, and when there is a first hash value consistent with the second hash value, directly output the equivalent resistance matrix corresponding to the first hash value.

[0027] That is, in this embodiment, if the reference coordinates of the vertex positions of the parasitic resistance geometric shape boundary are (0,0), (x2-x1, y2-y1), (x3-x1, y3-y1), ..., (x n -x1,y n -y1) can be represented in a canonical form, the reference coordinates of the parasitic resistance geometric shape can be converted into a string and its MD5 hash value can be calculated, wherein the reference coordinate of the parasitic resistance comparison shape is marked as the first hash value, and the reference coordinate of the parasitic resistance geometric shape is marked as the second hash value. By comparing the hash values ​​in the comparison database, the matching status of the parasitic resistance geometric shape and the cached data in the comparison database can be quickly determined, thereby realizing an efficient comparison and search function.

[0028] Furthermore, in this embodiment, the comparison database also adopts a cache mechanism of a map mapping technology. When there is a first hash value that is consistent with the second hash value in S22, the following steps are further included: S23: Select the parasitic resistance comparison shape represented by the first hash value, and compare the parasitic resistance comparison shape with the reference coordinates of the vertices of the boundary of the parasitic resistance geometric shape, and the parasitic resistance comparison shape with the reference coordinates of the current entry terminal position, current outlet terminal position, and conductive element position inside the parasitic resistance geometric shape. When the parasitic resistance comparison shape is completely consistent with the geometric features of the parasitic resistance geometric shape, the equivalent resistance matrix corresponding to the first hash value is output.

[0029] That is, in this embodiment, when a first hash value that is consistent with the second hash value is queried, the parasitic resistor geometry needs to be further verified from the perspective of the two-dimensional structure. By comparing the parasitic resistor shape and the coordinate information of the parasitic resistor geometry point by point, it is verified whether the two shapes are exactly the same, thereby ensuring the uniqueness and accuracy of the shape and avoiding misjudgment.

[0030] Furthermore, in this embodiment, a multi-threaded resistance calculation method is provided, that is, in S1, the selection range can be expanded in the target physical layer. When multiple sets of independent parasitic resistance geometries are simultaneously selected in the target physical layer, the method further includes the following steps: S24: First, a similarity comparison is performed on several groups of parasitic resistor geometric shapes. That is, by comparing the hash values ​​with the map mapping technology, it is determined whether there are identical shapes among the obtained groups of parasitic resistor geometric shapes. If so, a first identifier is assigned to the parasitic resistor geometric shapes with consistent geometric shapes. Then, only a group of parasitic resistor geometric shapes corresponding to the first identifier is compared with the cached data in the comparison database for similarity.

[0031] Therefore, in this embodiment, during the multi-threaded resistance calculation process, the step of comparing the same parasitic resistance geometry with the cached data in the comparison database can be reduced, that is, the retrieval time of the parasitic resistance geometry in the comparison database is reduced, thereby improving the overall calculation speed of the parasitic resistance in the VLSI design.

[0032] Preferably, in this embodiment, the resistance matrix calculation of the parasitic resistance geometry is performed by a Laplace equation field solver in S2, specifically comprising the following steps: S25: Convert the parasitic resistance geometry to a mesh and apply the Laplace equation on the mesh , where V is the potential, and the potential values ​​are set at the current entry terminal and the circuit exit terminal respectively.

[0033] The parasitic resistance geometry can be a complex planar structure composed of polygons, curves, etc., while the grid is an approximate expression composed of a series of discrete geometric units, most of which are simple planar structures such as rectangles and triangles. Figure 2In this embodiment, the geometric shape of the parasitic resistance is converted into a grid form, which can simplify the calculation of the subsequent Laplace equation.

[0034] The Laplace equation can be used to describe the potential distribution in the parasitic resistance geometry. Finally, corresponding potential values ​​are set at the current entry terminal and the circuit exit terminal. For example, the current entry terminal can be understood as the power supply terminal, whose potential is 1V, and the circuit exit terminal can be understood as the ground terminal, whose potential is 0V.

[0035] S26: Calculate current density from potential distribution , where σ is the conductivity and the current density J is used to represent the intensity of the current flowing through the parasitic resistive geometry.

[0036] S27: According to Ohm's law , where V 差 is the potential difference between the current inlet terminal and the current outlet terminal, and the current I is the integral of the current density J. The resistance matrix R between the current inlet terminal and the current outlet terminal is then calculated.

[0037] In this embodiment, the solving methods of the Laplace equation field solver include finite element analysis method, boundary element method, finite difference method and Monte Carlo method.

[0038] Preferably, in this embodiment, if there is a single current entry terminal and multiple current exit terminals within the obtained parasitic resistance geometry, the resistance values ​​between the current entry terminal and different current exit terminals can be calculated respectively through steps S25-S27, and a network analysis method (such as node analysis, loop analysis, or Thevenin theorem) is used to generate an equivalent single resistance matrix from the multiple resistance values ​​between the current entry terminal and the multiple current exit terminals. Figure 2 .

[0039] Preferably, in this embodiment, establishing a comparison database specifically includes the following steps: S31: Acquire several groups of parasitic resistance original shapes for pre-caching in a comparison database, and convert them into parasitic resistance comparison shapes in a standard form; S32: performing similarity comparison on a plurality of groups of parasitic resistance comparison shapes, assigning a second identifier to the parasitic resistance comparison shapes with the same geometric shape, and calculating a resistance matrix of each group of parasitic resistance comparison shapes corresponding to the second identifier, which is recorded as an equivalent resistance matrix; S33: caching only a group of parasitic resistance comparison shapes corresponding to the second identifier, an equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and a hash value obtained by calculating the parasitic resistance comparison shape through a hash function in a comparison database.

[0040] Therefore, in this embodiment, the parasitic resistance comparison shapes pre-stored in the comparison database are different, and the same parasitic resistance comparison shape is only stored once in the comparison database, avoiding the storage of a large amount of duplicate data and greatly reducing memory usage.

[0041] Second embodiment Based on the same concept, the present invention further provides a parasitic resistance calculation system for VLSI design, which is used to execute the parasitic resistance calculation method for VLSI design as described in the first embodiment, including: The parasitic resistance shape selection module is used to obtain the parasitic resistance geometry from the target physical layer based on the current input terminal position, the current output terminal position and the conductive element position.

[0042] The parasitic resistor shape comparison module is used to compare the parasitic resistor geometry with the cached data in the comparison database for similarity.

[0043] The parasitic resistor value calculation module is used to perform resistance matrix calculation for parasitic resistor geometries that are not in the comparison database using the Laplace equation field solver.

[0044] In this embodiment, the parasitic resistor shape selection module can first select and obtain the parasitic resistor geometry from the target physical layer. Then, the parasitic resistor shape comparison module determines whether the parasitic resistor geometry is already stored in the comparison database. If it is, the pre-calculated resistance matrix corresponding to the parasitic resistor geometry is directly called from the comparison database. If it is not, the parasitic resistor value calculation module calculates the resistance matrix of the parasitic resistor geometry and caches the parasitic resistor geometry and its resistance matrix in the comparison database. This embodiment can effectively reduce the calculation steps for parasitic resistors with repeated geometric shapes, thereby improving the overall calculation accuracy and speed of parasitic resistor values ​​in VLSI design.

[0045] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by the processor to implement the parasitic resistance calculation method applied to VLSI design as provided in the above method embodiment.

[0046] The memory can be used to store software programs and modules. The processor executes the parasitic resistance calculation method used in VLSI design by running the software programs and modules stored in the memory. The memory can mainly include a program storage area and a data storage area. The program storage area can store an operating system, application programs required for functions, etc.; the data storage area can store data created based on the use of the device, etc. In addition, the memory can include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory can also include a memory controller to provide the processor with access to the memory.

[0047] Among them, the processor (or CPU (Central Processing Unit)) is the computing core and control core of the electronic device. The network interface may optionally include a standard wired interface, a wireless interface (such as WI FI, a mobile communication interface, etc.). Memory is a memory device in an electronic device, used to store programs and data. It is understandable that the memory here can be a high-speed RAM storage device, or a non-volatile memory device (nonvolatile memory), such as at least one disk storage device; optionally, it can also be at least one storage device located away from the aforementioned processor. The memory provides a storage space, which stores the operating system of the electronic device, including but not limited to: Windows system (an operating system), Linux (an operating system), Android (Android, a mobile operating system) system, IOS (a mobile operating system) system, etc., which is not limited in this application; and, the storage space also stores one or more instructions suitable for being loaded and executed by the processor, and these instructions can be one or more computer programs (including program codes). In the embodiment of this specification, the processor loads and executes one or more instructions stored in the memory to implement the parasitic resistance calculation method applied to VLSI design provided by the above method embodiment.

[0048] An embodiment of the present application also provides a computer-readable storage medium, which stores at least one instruction or at least one program. The at least one instruction or at least one program is loaded and executed by a processor to implement the parasitic resistance calculation method provided in the method embodiment for application in VLSI design.

[0049] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0050] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the scope of protection of the present invention.

Claims

1. A parasitic resistance calculation method used in VLSI design, characterized in that: The steps include: S1: Select the target physical layer in the VLSI layout, and select the parasitic resistance geometry based on the current inlet terminal position, the current outlet terminal position, and the conductive element position in the target physical layer; S2: Perform a similarity comparison between the parasitic resistance geometry and the cached data in the comparison database. If cached data matching the parasitic resistance geometry exists in the comparison database, output a resistance matrix corresponding to the cached data. If cached data matching the parasitic resistance geometry does not exist in the comparison database, calculate the resistance matrix of the parasitic resistance geometry using a Laplace equation field solver, and cache the parasitic resistance geometry and its corresponding resistance matrix in the comparison database.

2. The parasitic resistance calculation method for VLSI design according to claim 1, wherein: In S1, the parasitic resistance geometry is obtained based on the current inlet terminal position, the current outlet terminal position, and the conductive element position, specifically including the following steps: S11: select any vertex in the boundary of the original shape of the parasitic resistance formed by the current inlet terminal position, the current outlet terminal position and the conductive element position, and use it as the shape origin; S12: traversing the boundary of the parasitic resistor original shape in a clockwise or counterclockwise direction, subtracting the shape origin from all remaining boundary vertex positions of the parasitic resistor original shape to obtain reference coordinates of each vertex of the parasitic resistor original shape, and subtracting the shape origin from the current inlet terminal position, the current outlet terminal position, and the conductive element position within the parasitic resistor original shape to obtain reference coordinates of the current inlet terminal position, the current outlet terminal position, and the conductive element position; S13: Recording a two-dimensional shape constructed by the vertices of the parasitic resistor original shape boundary and the reference coordinates of the current inlet terminal position, the current outlet terminal position, and the conductive element position in the parasitic resistor original shape as the parasitic resistor geometric shape in a standard form.

3. The parasitic resistance calculation method for VLSI design according to claim 1, wherein: The comparison database adopts a cache mechanism based on a hash function, and the cache data pre-stored in the comparison database includes a parasitic resistance comparison shape, an equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and a first hash value obtained by calculating the parasitic resistance comparison shape through a hash function; In S2, the parasitic resistance geometry is compared with the cached data in the comparison database for similarity, specifically comprising the following steps: S21: Calculate the parasitic resistance geometry through a hash function to obtain a second hash value; S22: Compare the second hash value with several first hash values ​​in the comparison database, and when there is a first hash value that is consistent with the second hash value, output an equivalent resistance matrix corresponding to the first hash value.

4. The parasitic resistance calculation method for VLSI design according to claim 3, wherein: The comparison database also adopts a cache mechanism of a map mapping technology. When the first hash value that is consistent with the second hash value exists in S22, the following steps are further included: S23: Select the parasitic resistance comparison shape represented by the first hash value, and compare the reference coordinates of the vertices of the boundary of the parasitic resistance geometric shape and the reference coordinates of the current entry terminal position, the current exit terminal position, and the conductive element position of the parasitic resistance comparison shape with the parasitic resistance geometric shape in sequence. When the geometric features of the parasitic resistance comparison shape and the parasitic resistance geometric shape are completely consistent, output the equivalent resistance matrix corresponding to the first hash value.

5. The parasitic resistance calculation method for VLSI design according to claim 4, wherein: When a plurality of groups of parasitic resistance geometric shapes are simultaneously selected in the target physical layer in S1, the following steps are further included: S24: firstly perform similarity comparison on several groups of the parasitic resistance geometric shapes, assign a first identifier to the parasitic resistance geometric shapes with consistent geometric shapes, and only perform similarity comparison on the group of the parasitic resistance geometric shapes corresponding to the first identifier and the cached data in the comparison database.

6. The parasitic resistance calculation method for VLSI design according to claim 2, wherein: In S2, a resistance matrix calculation is performed on the parasitic resistance geometry using a Laplace equation field solver, specifically comprising the following steps: S25: Convert the parasitic resistance geometry into a grid form and apply the Laplace equation on the grid , where V is the potential, and the potential values ​​are set at the current entry terminal and the circuit exit terminal respectively; S26: Calculate current density from potential distribution , where σ is the conductivity; S27: According to Ohm's law , where V 差 is the potential difference between the current inlet terminal and the current outlet terminal, current I is the integral of current density J, and the resistance matrix R between the current inlet terminal and the current outlet terminal is calculated.

7. The parasitic resistance calculation method for VLSI design according to claim 6, wherein: The solution methods of the Laplace equation field solver include finite element analysis method, boundary element method, finite difference method and Monte Carlo method.

8. The parasitic resistance calculation method for VLSI design according to claim 6, wherein: When there is a single current entry terminal and multiple current exit terminals, the resistance values ​​between the current entry terminal and different current exit terminals are calculated respectively, and a network analysis method is used to generate an equivalent single resistance matrix from the multiple resistance values ​​between the current entry terminal and multiple current exit terminals.

9. The parasitic resistance calculation method for VLSI design according to claim 1, wherein: Establishing the comparison database specifically includes the following steps: S31: Acquire several groups of parasitic resistance original shapes that are pre-cached in the comparison database, and convert them into parasitic resistance comparison shapes in a standard form; S32: performing similarity comparison on the plurality of groups of parasitic resistance comparison shapes, assigning a second identifier to the parasitic resistance comparison shapes with the same geometric shape, and calculating a resistance matrix of each group of parasitic resistance comparison shapes corresponding to the second identifier, which is recorded as an equivalent resistance matrix; S33: caching only a group of the parasitic resistance comparison shapes corresponding to the second identifier, an equivalent resistance matrix corresponding to the parasitic resistance comparison shape, and a hash value obtained by calculating the parasitic resistance comparison shape through a hash function in the comparison database.

10. A parasitic resistance calculation system used in VLSI design, characterized in that: The method for calculating parasitic resistance in VLSI design according to any one of claims 1 to 9 comprises: A parasitic resistance shape selection module is used to obtain the parasitic resistance geometry from the target physical layer based on the current inlet terminal position, the current outlet terminal position and the conductive element position; a parasitic resistor shape comparison module, configured to compare the parasitic resistor geometry with cached data in a comparison database for similarity; The parasitic resistor value calculation module is used to perform resistance matrix calculation on the parasitic resistor geometry through a Laplace equation field solver.

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