Curve-based wiring layer GDSII optimization method and system, medium, program and electronic terminal

Abstract

The invention provides a curve-based wiring layer GDSII optimization method and system, a medium, a program and an electronic terminal.The method comprises the steps that initial wiring is generated through a Manhattan type global wiring algorithm to serve as a base line, then the initial wiring is compared with a preset wekpoins graphic library to mark a wekpoins area in the initial wiring, only the wekpoins area is traversed, and the initial wiring is subjected to GDSII optimization; and the right-angle configuration blocks are screened out for curve replacement. Therefore, a wekpoins area is reduced under the condition that global curve wiring is not carried out, and a physical design drawing is consistent with a circuit wiring form of actual wafer photoetching; in addition, compromise among sharp corner electric stress weakening, data increment compression, calculation acceleration or template rapid replacement can be achieved by selecting different curve replacement strategies.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a curve-based wiring layer GDSII optimization method, system, medium, program and electronic terminal. Background Art

[0002] The design, production and manufacturing of integrated circuits are constantly advancing with the great development of society. Since the proposal of Moore's Law, the number of transistors in chips has also increased from a few thousand at the beginning to tens of billions today. Especially since the process node entered the nano era, the complexity of design has exploded. Since 2020, with the computing power requirements of AI, autonomous driving, and HPC, the further development of integrated circuits has been promoted. This also requires the design and manufacturing ends of integrated circuits at advanced nodes to collaborate and complete production and manufacturing. The design end needs to consider the production difficulties on the manufacturing end and avoid risks at the front end, so as to find the best balance between performance, power consumption, area and cost.

[0003] Currently, in the integrated circuit field, chip design is primarily based on right-angle wiring. Curves are only used in a few large areas to facilitate packaging. However, due to the enormous computational complexity of curved wiring, the underlying wiring layer is currently not feasible. Right-angle wiring causes current density concentration at corners (the tip discharge effect), which increases resistance and electromigration risks. Furthermore, right-angle configurations are prone to diffraction during chip lithography, resulting in rounded corner errors. This leads to a certain deviation between the physical design drawings and the actual wafer lithography circuit wiring form, causing significant errors in the subsequent RC analysis, parasitic capacitance and resistance extraction, and timing analysis. Therefore, how to avoid global curved wiring during wiring while reducing the occurrence of weakpoints caused by right angles and ensuring consistency in the physical design drawings and actual wafer lithography circuit wiring form has become an urgent problem to be solved. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide a curve-based wiring layer GDSII optimization method, system, medium, program and electronic terminal to solve the above-mentioned problems.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a curve-based wiring layer GDSII optimization method, comprising: generating an initial wiring using a Manhattan-type global wiring algorithm; performing morphological matching on the initial wiring with graphics in a preset weakpoints graphics library, and using the morphologically matched portion of the initial wiring as a weakpoints area; traversing each of the weakpoints areas one by one and extracting right-angled configuration blocks therefrom, and determining the turning direction of the right-angled configuration blocks; and performing curve replacement on the right-angled configuration blocks according to the turning direction.

[0006] In an embodiment of the first aspect of the present application, the method of traversing each of the weakpoints areas one by one and extracting the right-angle configuration block therefrom, and determining the turning direction of the right-angle configuration block includes: taking the area corresponding to the two intersecting wiring segments whose vector product is zero in the weakpoints area as the right-angle configuration block; calculating the two-dimensional cross product of the two intersecting wiring segments; wherein, if the two-dimensional cross product is greater than zero, the turning direction of the right angle in the right-angle configuration block is convex; if the two-dimensional cross product is less than zero, the turning direction of the right angle in the right-angle configuration block is concave.

[0007] In an embodiment of the first aspect of the present application, the method for performing curve replacement on the right-angled block according to the turning direction includes: locating two perpendicularly intersecting wiring segments L1 and L2 of the right-angled block and their common endpoint A; starting from A, intercepting line segments S1 and S2 to be replaced with a length of d on L1 and L2 respectively; wherein, , R min is the minimum curvature radius allowed by the process; construct a transition curve connecting S1 and S2; wherein the transition curve is an Euler spiral or a Clothoid curve, and the curvature of the transition curve increases linearly from 0 at point A to the midpoint of the curve. , and maintain the first-order continuity of the curvature; calculate the curve parameters according to the optimization model; wherein, the optimization model aims to minimize the bending strain energy, minimize the square integral value of the curvature of the transition curve within the entire arc length range, and make the area of ​​the newly added wiring segment in the right-angle configuration block after replacing the transition curve less than the preset threshold K, and the local curvature radius of any point on the transition curve is greater than or equal to R min ; Use the transition curve to replace line segments S1 and S2.

[0008] In an embodiment of the first aspect of the present application, the method for performing curve replacement on the right-angle configuration block according to the turning direction includes: positioning two perpendicular intersecting wiring segments in the right-angle configuration block, presetting positioning control points near the two wiring segments, and performing smooth curve fitting using an arc equation or an ellipse equation according to the positioning control points, and replacing the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block with the fitted smooth curve.

[0009] In an embodiment of the first aspect of the present application, the method for performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, determining the line width of the wiring segments, and using a preset arc curve corresponding to the width to replace the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block according to the line width.

[0010] In an embodiment of the first aspect of the present application, the method of performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, using a third-order Bezier or B-spline algorithm to perform smooth curve fitting, and replacing the right-angle wiring segments at corresponding positions in the corresponding right-angle configuration block with the fitted smooth curve.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a curve-based wiring layer GDSII optimization system, including: an initial wiring module, used to generate an initial wiring using a Manhattan-type global wiring algorithm; a weakpoints area screening module, used to morphologically match the initial wiring with the graphics in a preset weakpoints graphics library, and use the morphologically matched part of the initial wiring as a weakpoints area; a right-angle configuration block screening module, used to traverse each of the weakpoints areas one by one and extract the right-angle configuration block therefrom, and determine the turning direction of the right-angle configuration block; a curve replacement module, used to perform curve replacement on the right-angle configuration block according to the turning direction.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements any of the aforementioned methods when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements the method as described in any of the above items.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement any of the above-mentioned methods.

[0015] As described above, the present application has the following beneficial effects: the present application provides a curve-based routing layer GDSII optimization method, which first uses a Manhattan-style global routing algorithm to generate an initial routing in the design concept. The Manhattan-style global routing can quickly converge the routing search space, ensure the convergence of critical path delays and obtain the optimal congestion heat distribution. In addition, the deterministic pin-to-pin topology formed in the Manhattan-style global routing stage provides a repeatable and traceable benchmark for subsequent process weak point detection and curvature reconstruction. Next, the initial routing is morphologically matched with the graphics in a preset weakpoints graphic library, and the morphologically matched parts of the initial routing are used as weakpoints areas; the weakpoints graphic library is directly derived from the wafer fab's abstraction of features such as sharp corners, narrow necks, and islands with the highest measured failure rates. After matching, the geometric units most sensitive to yield are immediately located to avoid missing hidden defects. In addition, subsequent curve reconstruction is only performed on the calibrated weakpoints areas, avoiding indiscriminate scanning and replacement of the entire layout, significantly reducing data processing volume and run time. Each of the weakpoints regions is traversed one by one, and right-angled configuration blocks are extracted from them. The turning direction of the right-angled configuration block is determined, and different curves are used to replace the right-angled configurations with different turning directions, or different replacement strategies are implemented. Finally, curve replacement is performed on the right-angled configuration block according to the turning direction. In this process, a variety of curve calculation methods can be used to obtain the corresponding curve to replace the right-angled configuration to be replaced. This achieves the effect of how to reduce the appearance of weakpoints (process weak points) caused by right angles while not performing global curve routing during wiring, so that the physical design drawings and the actual wafer lithography circuit wiring are consistent in form. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a flow chart of a curve-based wiring layer GDSII optimization method according to an embodiment of the present application.

[0017] Figure 2 Shown is a flow chart of extracting right-angled blocks and determining their turning directions in one embodiment of the present application.

[0018] Figure 3 FIG. 1 is a schematic diagram showing a process of performing curve replacement on a right-angled configuration block according to a turning direction in one embodiment of the present application.

[0019] Figure 4Shown is a structural diagram of a curve-based wiring layer GDSII optimization system in one embodiment of the present application.

[0020] Figure 5 Shown is a structural schematic diagram of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0022] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same function or effect. For example, the first XX and the second XX are merely used to distinguish between different XXs and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution, and that terms such as "first" and "second" do not necessarily define differences.

[0023] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" represent examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0024] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0025] like Figure 1 As shown, the first aspect of the present application provides a curve-based wiring layer GDSII optimization method, comprising:

[0026] S1: Generate initial routing using Manhattan-style global routing algorithm.

[0027] It should be understood that in integrated circuit back-end physical design, the Manhattan-style global routing algorithm employs a strict XY orthogonal grid model, discretizing the chip plane into a grid network of routable wires and via nodes. The algorithm then uses minimum-cost flow, A* search, or Steiner tree-based heuristics on this network to rapidly generate the shortest or next-shortest pin-to-pin topology for each netlist connection. Because the grid is limited to horizontal and vertical directions, the search space is significantly compressed, and routing convergence speed is significantly faster than with arbitrary-angle grids or curved routing, providing predictable time and space complexity for large-scale designs. This regularized grid allows the global routing stage to generate deterministic wiring topologies early on. This results in highly reproducible critical path lengths, via levels, and via counts, facilitating rapid iterations in subsequent timing, power, and signal integrity analyses. Furthermore, the congestion heatmaps inherent to the orthogonal grid are clearly partitionable, allowing the optimizer to centrally schedule strategies such as layer jumps and route redistribution in local hotspots, thereby achieving near-optimal congestion balance on a global scale. More importantly, regularized layout provides a stable benchmark for layout post-processing: the spatial relationships, hierarchical occupancy, and orthogonal corner positions of all pin-to-pin connections are determined in the data structure. Subsequent weakpoints area detection and curvature reconstruction algorithms can perform differential operations on this benchmark, ensuring the traceability of modifications and avoiding redundant calculations of irrelevant areas.

[0028] S2: performing morphological matching between the initial wiring and graphics in a preset weakpoints graphics library, and using the morphologically matched portion of the initial wiring as a weakpoints area.

[0029] It should be understood that the weakpoints (process weakness) library is a knowledge base of layout process defects jointly maintained by wafer fabs, EDA vendors, and design companies. It primarily contains geometric patterns that repeatedly trigger failures in mass production lines and lithography simulations. Its construction process is typically based on large-scale wafer casting statistics: defect coordinates on wafers with declining yields are located in the layout. Through morphological clustering, high-risk structures such as sharp corners, narrow necks, islands, cantilevers, and line-end interference are identified. Digital features such as boundary contours, layer number combinations, and line width / spacing thresholds are extracted for each type of weakpoint. OPC, LFD, and electromigration simulation results are also incorporated to add metrics such as process window shrinkage and local current density amplification factor to each template.

[0030] After obtaining the initial right-angle wiring, the system first calls the weakpoints graphics library jointly maintained by the wafer fab, and then performs a morphological comparison between the problematic glass fiber and the graphics included in the weakpoints graphics library. Since the weakpoints graphics library is directly derived from mass production statistics and the latest DFM rules of the foundry, it can accurately lock the geometric units that are most sensitive to yield, avoiding missing hidden defects or falsely reporting benign structures. In addition, the matching results provide extremely precise spatial boundaries, and subsequent curvature reconstruction is only performed on local areas where potential process risks are determined, greatly compressing the calculation domain. Compared with indiscriminate scanning and replacement of the entire layout, less than 5% of the total geometry needs to be processed after morphological matching, which reduces the running time and memory usage of the curve replacement process by an order of magnitude, while ensuring that the modification range is minimized and parasitic parameter drift is controllable, bringing significant timeliness advantages to the subsequent sign-off.

[0031] Preferably, the morphological comparison algorithm adopts a morphological matching engine based on geometric hashing and topological equivalence, scans the initial wiring layer GDS data layer by layer, extracts feature vectors for each wire, polygon or path segment, and quickly matches them with the templates in the library. When a local layout is detected whose similarity with the template reaches a threshold, the system immediately marks it as a weakpoints area.

[0032] S3: Traverse each of the weakpoints regions one by one, extract right-angle configuration blocks therefrom, and determine the turning direction of the right-angle configuration blocks.

[0033] like Figure 2 As shown, preferably, the method of traversing each of the weakpoints areas one by one and extracting the right-angle configuration block therefrom, and determining the turning direction of the right-angle configuration block includes: taking the area corresponding to the two intersecting wiring segments whose vector product is zero in the weakpoints area as the right-angle configuration block; calculating the two-dimensional cross product of the two intersecting wiring segments; wherein, if the two-dimensional cross product is greater than zero, the turning direction of the right angle in the right-angle configuration block is convex; if the two-dimensional cross product is less than zero, the turning direction of the right angle in the right-angle configuration block is concave.

[0034] It should be understood that the system traverses the marked weakpoints area one by one, and for each local layout, calculates the dot product of the corresponding vectors of two adjacent wiring segments; when the dot product is zero, it is determined that the two are orthogonal to each other, that is, the candidate block forming a right angle (right-angle configuration block) is locked. The two-dimensional cross product of the vector pair is then further calculated. The sign of the two-dimensional cross product accurately reflects the turning polarity of the corner - a positive cross product indicates that the rotation direction is counterclockwise, corresponding to a convex 270-degree concave angle; a negative cross product indicates that the rotation direction is clockwise, corresponding to an inward convex 90-degree sharp angle. Through this "dot product-cross product" joint discrimination mechanism, the algorithm can quickly and unambiguously distinguish between inward concave right angles and outward convex right angles at the vector level, thereby performing differentiated right-angle-curve replacements in the subsequent process.

[0035] S4: performing curve replacement on the rectangular configuration block according to the turning direction.

[0036] like Figure 3 As shown, preferably, the method for performing curve replacement on the right-angled configuration block according to the turning direction includes: locating two perpendicularly intersecting wiring segments L1 and L2 of the right-angled configuration block and their common endpoint A; taking A as the starting point, intercepting line segments S1 and S2 to be replaced with a length of d on L1 and L2 respectively; wherein, , R min is the minimum curvature radius allowed by the process; construct a transition curve connecting S1 and S2; wherein the transition curve is an Euler spiral or a Clothoid curve, and the curvature of the transition curve increases linearly from 0 at point A to the midpoint of the curve. , and maintain the first-order continuity of the curvature; calculate the curve parameters according to the optimization model; wherein, the optimization model aims to minimize the bending strain energy, minimize the square integral value of the curvature of the transition curve within the entire arc length range, and make the area of ​​the newly added wiring segment in the right-angle configuration block after replacing the transition curve less than the preset threshold K, and the local curvature radius of any point on the transition curve is greater than or equal to R min ; Use the transition curve to replace line segments S1 and S2.

[0037] It should be understood that, first, starting from the common inflection point A, only two segments S1 and S2 to be replaced with a length d are intercepted, and d is set to be no less than the minimum curvature radius R of the process. min The necessary geometric lower limit of the transition curve is guaranteed to be arrangable at the layout level from the source. In addition, by introducing the Euler spiral or Clothoid curve as the transition curve, the curvature is linearly increased from 0 to , and maintain first-order continuity, which not only completely eliminates the curvature singularity at the sharp corners, but also is naturally consistent with the lithography step compensation curve in terms of curvature distribution, which can significantly relax the depth of focus and reduce deformation errors. In addition, when constructing this transition curve scheme, the core criterion is to reduce the bending strain energy. With the help of full-process curvature optimization, the extremely high current density peak and mechanical stress concentration at the sharp corners are suppressed simultaneously; at the same time, a hard limit of no more than the threshold K is set for the area of ​​the newly added wire to ensure that the changes in parasitic capacitance and resistance are within a controllable range, which neither destroys the timing nor introduces additional power consumption. The minimum curvature radius of the curve within the entire arc length is always greater than or equal to the R specified by the process. min , fundamentally avoiding the risk of rework during subsequent layout rule checking and lithography correction. In summary, this partial replacement strategy strikes an optimal balance between improving process yield, enhancing electromigration reliability, widening the lithography window, and suppressing layout data increments, significantly improving the engineering feasibility of advanced node layout post-processing.

[0038] Preferably, the method for performing curve replacement on the right-angle configuration block according to the turning direction includes: positioning two perpendicular intersecting wiring segments in the right-angle configuration block, presetting positioning control points near the two wiring segments, and performing smooth curve fitting using an arc equation or an ellipse equation according to the positioning control points, and replacing the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block with the fitted smooth curve.

[0039] It should be understood that by presetting positioning control points in the vicinity of two intersecting wires and performing least squares fitting on the control points using arc or ellipse equations, this embodiment can generate a smooth transition curve in the local space that is strictly consistent with the width and direction of the original trace. This approach not only eliminates the hidden dangers of tip electric field concentration and electromigration caused by right angles, but also maintains first-order tangential continuity with the original wire at the endpoints, ensuring that parasitic parameter drift is extremely small and timing integrity is not affected. Arc / elliptical curves naturally meet the lithography-friendly characteristics of constant or gradual curvature, which can significantly relax the depth of focus and reduce line edge roughness. At the same time, the number of geometric control points required for fitting is very small, and the layout data increment and processing overhead are almost negligible. This achieves a dual improvement in manufacturability and electrical reliability at a minimal data cost, providing a simple, efficient and easy-to-sign-off local curve reconstruction solution for advanced node back-end layouts.

[0040] Preferably, there may be one or more positioning control points.

[0041] It should be understood that the number of positioning control points can be flexibly set based on local routing congestion and geometric constraints, and can be single or multiple. When the neighborhood space is ample and only basic rounding is required, setting a single control point can quickly generate a fixed-radius arc with minimal computational effort. However, when the surrounding routing is dense and fine-grained curvature control is required or multi-layer conflicts need to be avoided simultaneously, multiple control points can be added to obtain an elliptical curve with higher degrees of freedom through least squares fitting. This ensures that the transition section meets the minimum curvature radius of the process while maximally fitting to the original routing boundary, further reducing data increments and improving local manufacturability.

[0042] Preferably, the method for performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, determining the line width of the wiring segments, and using a preset arc curve corresponding to the width to replace the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block according to the line width.

[0043] It should be understood that this embodiment first reads the actual line widths of the two perpendicular wires within the right-angle block, then calls a standard arc template that has been pre-calibrated according to the line width dimension, directly embedding the template curve and replacing the original right angle. On the one hand, it can ensure that the bending radius of the replacement curve strictly matches the wire width, naturally complying with the process's consistency constraint on "line width-minimum arc radius" and avoiding rule violations caused by recalculating the curvature; on the other hand, the use of templated insertion eliminates the real-time curve fitting and energy optimization steps, requiring only simple geometric Boolean operations during operation, greatly shortening post-processing time and reducing storage increments. In addition, the template curve aligns with the original wire tangent at the endpoints, making parasitic resistance and capacitance drift controllable and predictable, and subsequent timing and signal integrity verification does not require re-iteration. Overall, this width-matching arc replacement strategy achieves rapid and sign-off repairs for sharp corner weaknesses at minimal computational cost, providing an efficient and stable engineering path for mass manufacturability optimization of large-scale wiring layer GSDII.

[0044] Preferably, the method for performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, using a third-order Bezier or B-spline algorithm to perform smooth curve fitting, and replacing the right-angle wiring segments at corresponding positions in the corresponding right-angle configuration block with the fitted smooth curve.

[0045] It should be understood that by extracting the endpoints and tangent constraints of two perpendicular conductors in a right-angled block, the system invokes a third-order Bezier or B-spline algorithm to generate a smooth transition curve, achieving locally adjustable curvature distribution at the control points. Compared to fixed-radius arcs, third-order Bezier or B-spline algorithms offer greater freedom, allowing precise control of mid-segment curvature while maintaining first-order tangent continuity at the endpoints. This allows for complete elimination of current density peaks at the tips and automatic adjustment of curve outwards based on the available spacing in the neighborhood, minimizing layout area increments. The unified mathematical expression allows curve data to be described with a small number of control points, significantly reducing GDS file size. This is naturally compatible with OPC's vectorized segmentation algorithm, eliminating the need for additional discretization overhead for back-end lithography corrections. Leveraging the "local modification—full curve smoothing" feature of Bezier or B-spline, curves can be rapidly reconstructed during any design iteration by adjusting a single control point, enhancing the flexibility and maintainability of layout post-processing.

[0046] Preferably, when the inflection direction is determined to be a convex right angle (i.e., a convex angle with an internal angle of approximately 90°), the system invokes an arc, involute, or third-order B-spline algorithm. Using the start and end points and tangential constraints of the traces on either side of the inflection point, a smooth transition curve with first-order tangential continuity and second-order curvature continuity is constructed, replacing the original sharp-angled wire segment with this curve. This significantly reduces electric field concentration at the tip, lowering local current density peaks and electromigration risks, while also relaxing the lithography depth of focus and achieving forced rounding. When the inflection direction is determined to be a concave right angle (i.e., a concave angle with an internal angle of approximately 270°), a limited correction is performed by inserting a minimum radius chamfer or short arc only if the concave angle region falls below the minimum recommended process spacing. If sufficient space margin exists and does not trigger a manufacturability score penalty, the original Manhattan angle is retained. This differentiated processing avoids unnecessary data expansion for the concave region while ensuring that all potential manufacturing weaknesses are targeted and repaired, achieving an optimal balance between curve replacement effectiveness and layout increment.

[0047] like Figure 4 As shown, the second aspect of the present application provides a curve-based wiring layer GDSII optimization system, including: an initial wiring module, used to generate an initial wiring using a Manhattan-type global wiring algorithm; a weakpoints area screening module, used to morphologically match the initial wiring with a graphic in a preset weakpoints graphic library, and use the morphologically matched part of the initial wiring as a weakpoints area; a right-angle configuration block screening module, used to traverse each of the weakpoints areas one by one and extract a right-angle configuration block therefrom, and determine the turning direction of the right-angle configuration block; a curve replacement module, used to perform curve replacement on the right-angle configuration block according to the turning direction.

[0048] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0049] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0050] A third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the aforementioned methods when executed by a processor.

[0051] A fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements any of the methods described above.

[0052] like Figure 5 As shown, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement any of the aforementioned methods. The electronic terminal includes: at least one processor 501, a memory 502, at least one network interface 503, and a user interface 505. The various components in the device are coupled together via a bus system 504. It will be understood that the bus system 504 is used to implement connection and communication between these components. In addition to the data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus.

[0053] The user interface 505 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0054] It will be appreciated that the memory 502 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM) or a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0055] The memory 502 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 500. Examples of such data include: any executable program for operating on the electronic terminal 500, such as an operating system 5021 and an application 5022; the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The method provided by the embodiment of the present invention can be included in the application 5022.

[0056] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 501 or by software instructions. The above processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 501 may be a microprocessor or any conventional processor. The steps of the accessory optimization method provided in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium located in a memory. The processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0057] In an exemplary embodiment, the electronic terminal 500 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0058] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a single computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0059] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented using hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0060] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0061] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0062] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0063] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0064] In the above embodiments, the functions of each functional unit can be implemented in whole or in part via software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. A computer program product comprises one or more computer instructions (programs). When these computer program instructions (programs) are loaded and executed on a computer, they fully or partially produce the processes or functions according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0065] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the existing technology, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0066] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0067] In summary, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0068] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A curve-based wiring layer GDSII optimization method, characterized in that: include: Generate initial routing using a Manhattan-style global routing algorithm; Performing shape matching between the initial wiring and a graphic in a preset weakpoints graphic library, and using the shape-matched portion of the initial wiring as a weakpoints area; Traversing each of the weakpoints regions one by one and extracting right-angled configuration blocks therefrom, and determining the turning direction of the right-angled configuration blocks; Curve replacement is performed on the rectangular configuration block according to the turning direction.

2. The curve-based wiring layer GDSII optimization method according to claim 1, characterized in that: The method of traversing each of the weakpoints regions one by one, extracting right-angled configuration blocks therefrom, and determining the turning direction of the right-angled configuration blocks includes: The area corresponding to the two intersecting wiring segments whose vector product is zero in the weakpoints area is used as a right-angle configuration block; Calculate the two-dimensional cross product of the two intersecting wiring segments; if the two-dimensional cross product is greater than zero, the turning direction of the right angle in the right-angle configuration block is convex; if the two-dimensional cross product is less than zero, the turning direction of the right angle in the right-angle configuration block is concave.

3. A curve-based wiring layer GDSII optimization method according to claim 1 or 2, characterized in that: The method of performing curve replacement on the rectangular configuration block according to the turning direction includes: Locate two perpendicularly intersecting wiring segments L1 and L2 of the right-angle configuration block and their common endpoint A; Taking A as the starting point, cut the line segments S1 and S2 to be replaced with length d on L1 and L2 respectively; , R min The minimum curvature radius allowed by the process; Construct a transition curve connecting S1 and S2; wherein the transition curve is an Euler spiral or a Clothoid curve, and the curvature of the transition curve increases linearly from 0 at point A to the midpoint of the curve. , and keep the curvature first-order continuous; The curve parameters are calculated according to the optimization model; wherein, the optimization model aims to minimize the bending strain energy, minimize the square integral value of the curvature of the transition curve within the entire arc length, and make the area of ​​the newly added wiring segment in the right-angle configuration block after replacing the transition curve less than the preset threshold K, and the local curvature radius of any point on the transition curve is greater than or equal to R min ; The line segments S1 and S2 are replaced by the transition curve.

4. A curve-based wiring layer GDSII optimization method according to claim 1 or 2, characterized in that: The method for performing curve replacement on the right-angle configuration block according to the turning direction includes: positioning two perpendicular intersecting wiring segments in the right-angle configuration block, presetting positioning control points near the two wiring segments, performing smooth curve fitting using an arc equation or an ellipse equation according to the positioning control points, and replacing the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block with the fitted smooth curve.

5. The curve-based wiring layer GDSII optimization method according to claim 1 or 2, characterized in that: The method for performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, determining the line width of the wiring segments, and replacing the right-angle wiring segment at the corresponding position in the corresponding right-angle configuration block with a preset arc curve corresponding to the line width.

6. The curve-based wiring layer GDSII optimization method according to claim 1 or 2, characterized in that: The method for performing curve replacement on the right-angle configuration block according to the turning direction includes: locating two perpendicular intersecting wiring segments in the right-angle configuration block, using a third-order Bezier or B-spline algorithm to perform smooth curve fitting, and replacing the right-angle wiring segments at corresponding positions in the corresponding right-angle configuration block with the fitted smooth curve.

7. A curve-based wiring layer GDSII optimization system, characterized in that: include: An initial routing module, used to generate an initial routing using a Manhattan-style global routing algorithm; A weakpoints region screening module is used to perform morphological matching between the initial wiring and graphics in a preset weakpoints graphic library, and to use the morphologically matched parts of the initial wiring as weakpoints regions; A right-angled configuration block screening module is used to traverse each of the weakpoints areas one by one and extract right-angled configuration blocks therefrom, and determine the turning direction of the right-angled configuration blocks; The curve replacement module is used to perform curve replacement on the rectangular configuration block according to the turning direction.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program code, which, when executed on a computer, enables the computer to implement the method according to any one of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 6.

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