Integrated circuit and inter-processor communication method thereof

Abstract

The invention discloses an integrated circuit and a communication method between processors thereof, and relates to the technical field of integrated circuits. The method comprises the following steps: determining a first identifier respectively corresponding to a first processor and a second identifier respectively corresponding to a second processor; determining an access relationship between the first processor and the second processor; based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; and determining a communication state between the first processor and the second processor based on the matching relationship. According to the technical scheme, the communication security between the processors of the integrated circuit can be improved, the problem of communication information leakage is avoided, and thus the reliability of the integrated circuit can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an integrated circuit and an inter-processor communication method thereof. Background Art

[0002] Currently, some integrated circuits include multiple processors. Each processor can run a different operating system, allowing multiple operating systems to run on a single integrated circuit. During the operation of the integrated circuit, the processors running different operating systems can communicate with each other through a communication unit.

[0003] However, when two processors communicate through a mailbox in a communication unit, if other processors also access the current mailbox, the current communication data may be leaked or the normal communication process may be disrupted, affecting the security and reliability of communication between processors. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides an integrated circuit and an inter-processor communication method thereof, which can improve the communication security between the processors of the integrated circuit, avoid the problem of communication information leakage, and thus improve the reliability of the integrated circuit.

[0005] In a first aspect of the present disclosure, a method for inter-processor communication of an integrated circuit is provided, comprising: determining first identifiers corresponding to first processors and second identifiers corresponding to second processors; determining an access relationship between the first processor and the second processor; based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; and based on the matching relationship, determining a communication status between the first processor and the second processor.

[0006] According to a second aspect of the present disclosure, an integrated circuit is provided, comprising a plurality of processors, the plurality of processors including a first processor and a second processor, wherein a first operating system runs on the first processor and a second operating system runs on the second processor; determining first identifiers corresponding to the first processors running the first operating system and second identifiers corresponding to the second processors running the second operating system; determining an access relationship between the first operating system and the second operating system; based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; and determining a communication status between the first operating system and the second operating system based on the matching relationship.

[0007] According to a third aspect of the present disclosure, an integrated circuit is provided, comprising a plurality of processors and a communication unit, wherein the plurality of processors communicate through the communication unit, and the plurality of processors include a first processor and a second processor; the communication unit determines a first identifier corresponding to each of the first processors and a second identifier corresponding to each of the second processors; the communication unit determines an access relationship between the communication units of the first processor core and the second processor core; based on the access relationship, the communication unit determines a matching relationship between the third identifier of the first processor and the first identifier, and a matching relationship between the fourth identifier of the second processor and the second identifier; based on the matching relationship, the communication unit determines a communication status between the first processor and the second processor.

[0008] A fourth aspect of the present disclosure provides a computer-readable storage medium storing a computer program for executing the inter-processor communication method of the integrated circuit provided in the first aspect of the present disclosure.

[0009] The fifth aspect of the present disclosure provides an electronic device, which includes: a processor; a memory for storing processor-executable instructions; a processor for reading executable instructions from the memory and executing the instructions according to the inter-processor communication method of the integrated circuit provided in the first aspect of the present disclosure; or, the electronic device includes the integrated circuit provided in the second aspect or the third aspect of the present disclosure.

[0010] The sixth embodiment of the present disclosure provides a computer program product. When an instruction processor in the computer program product executes the inter-processor communication method of the integrated circuit provided by the first aspect of the present disclosure, it executes.

[0011] Based on the integrated circuit and inter-processor communication method provided by the present disclosure, by determining the first identifier and the second identifier corresponding to the first processor and the second processor respectively and determining the access relationship between the first processor and the second processor, it is possible to further determine the matching relationship between the third identifier of the first processor and the first identifier, and the fourth identifier of the second processor and the second identifier based on the access relationship; and then determine the communication state between the first processor and the second processor through the matching relationship. In this way, before the first processor and the second processor communicate, the communication state between the first processor and the second processor can be determined by the matching relationship between the corresponding identifiers. If the matching relationship between the corresponding identifiers of the first processor and the second processor meets the communication requirements, the communication state between the first processor and the second processor can be determined as communication is possible, so as to improve the security of inter-processor communication. If the matching relationship between the respective identifiers of the first processor and the second processor does not meet the communication requirements, the communication state between the first processor and the second processor can be determined as communication is not possible, so as to avoid the problem of information leakage during the communication process. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of an inter-processor communication system of an integrated circuit;

[0013] Figure 2 It is a schematic diagram of the inter-processor communication process of an integrated circuit;

[0014] Figure 3 is a structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0015] Figure 4 is a schematic diagram of configuration information provided by an exemplary embodiment of the present disclosure;

[0016] Figure 5 is a flow chart of an inter-processor communication method of an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0017] Figure 6 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0018] Figure 7 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0019] Figure 8 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0020] Figure 9 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0021] Figure 10 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0022] Figure 11 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0023] Figure 12 is a flowchart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure;

[0024] Figure 13 is another structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure;

[0025] Figure 14 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0027] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0028] Application Overview

[0029] With increasing demands for integrated circuit computing power, security, and energy efficiency, some integrated circuits now include multiple processors. Each processor in an integrated circuit can run a different operating system, allowing multiple operating systems to run within a single integrated circuit. For example, a smart car equipped with an integrated circuit can include operating systems for intelligent driving systems, intelligent cockpit systems, and in-vehicle infotainment systems. Each processor in the integrated circuit can run a different operating system, ensuring safe operation of the smart car.

[0030] During the operation of an integrated circuit, processors running different operating systems have different work tasks (such as image recognition, logic control, etc.). In order to achieve task collaboration between various operating systems, the processors need to communicate with each other to achieve data sharing or state synchronization, thereby avoiding slow response or crashes caused by inconsistent information between the processors.

[0031] Figure 1 It is a schematic diagram of the inter-processor communication system of an integrated circuit. Figure 2 This is a schematic diagram of the inter-processor communication process of an integrated circuit. Figure 1 and Figure 2 As shown, the integrated circuit may include processors 1 to 6, each of which may run an operating system. The communication unit may include multiple mailboxes, such as mailbox 0 to mailbox M, where M is a positive integer. Each mailbox does not have an information security control mechanism. Each processor may communicate with any mailbox in the communication unit via a bus.

[0032] When operating system 1 and operating system 2 need to communicate, processor 1 and processor 2 can communicate through any mailbox in the communication unit (such as mailbox 0). In the case that mailbox 0 is not set with an information security control mechanism, if an abnormal situation occurs in processor 3 (such as being attacked by hackers and logical errors), processor 3 can make abnormal access to mailbox 0 that is in the communication process. Among them, abnormal access may include abnormal access to mailbox communication data, rewriting communication data, and rewriting interrupt operations. Rewriting interrupt operations include abnormal triggering interrupts, abnormal clearing interrupts, etc. In this way, the communication process of processor 1 and processor 2 that are communicating may be destroyed or the data currently being communicated may be leaked, affecting the security and reliability of communication between processors.

[0033] In order to solve the above problems, an embodiment of the present disclosure provides an inter-processor communication method of an integrated circuit, which determines the first identifier and the second identifier corresponding to the first processor and the second processor respectively, and the access relationship between the first processor and the second processor, so that based on the access relationship, the method can further determine the matching relationship between the third identifier of the first processor and the first identifier, and the matching relationship between the fourth identifier of the second processor and the second identifier; and then determine the communication status between the first processor and the second processor through the matching relationship. In this way, before the first processor and the second processor communicate, the communication status between the first processor and the second processor can be determined through the matching relationship between the corresponding identifiers. When the matching relationship between the corresponding identifiers of the first processor and the second processor meets the security requirements, the first processor and the second processor can be allowed to communicate to improve the security of inter-processor communication.

[0034] Exemplary Systems

[0035] Figure 3 is a schematic structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 3 In the embodiment, the integrated circuit 10 includes multiple processors 11. The multiple processors may include processor 11-1, processor 11-2, processor 11-3, processor 11-4, processor 11-5, through processor 11-n, where n is a positive integer. It is understood that the number of processors 11 in the integrated circuit 10 can be adjusted according to actual conditions and is not limited in this embodiment.

[0036] Illustratively, each processor 11 may run an operating system 111. For example, processor 11-1 may run operating system 111-1, processor 11-2 may run operating system 111-2, and processor 11-n may run operating system 111-n. In this way, each processor 11 may support each operating system 111.

[0037] The integrated circuit 10 further includes an Inter Process Communication Module (IPCM) 12. Each processor 11 in the integrated circuit 10 can be communicatively connected to a first interface 14 and a second interface 15 via a bus 13, and the first interface 14 and the second interface 15 are respectively communicatively connected to the communication unit 12. In this way, each processor 11 can be communicatively connected to the communication unit 12 via the bus 13 and the first interface 14, or each processor 11 can be communicatively connected to the communication unit 12 via the bus 13 and the second interface 15.

[0038] The first interface 14 and the second interface 15 may be a memory-mapped I / O (MMIO), a dedicated configuration bus interface, a hardware queue interface, a serial interface, etc. It is understood that the specific interface types of the first interface 14 and the second interface 15 can be selected according to actual needs and are not limited in this disclosed example.

[0039] Exemplarily, the communication unit 12 can realize communication between processors 11 through a mailbox, shared memory or network-on-chip (NoC). Among them, the mailbox can realize low-latency, small-data-volume communication notification or control instruction transmission, and can avoid competition conditions through write-read-clear atomic operations. Shared memory can provide large-scale, high-bandwidth communication data sharing, and can automatically synchronize the caches of multiple processors through hardware consistency protocols. NoC can provide a high-bandwidth, scalable communication backbone for large-scale multi-processor systems, and also supports multi-hop routing and priority scheduling. It can be understood that the specific communication method adopted by the communication unit 12 can be determined according to actual conditions and is not limited in this disclosure.

[0040] In some embodiments, the bus 13 may be communicatively connected to the first interface 14 via a first sub-bus 161 , and the bus 13 may be communicatively connected to the second interface 15 via a second sub-bus 162 .

[0041] Exemplarily, when the processor 11 communicates with the communication unit 12 through the bus 13, the first sub-bus 161 and the second sub-bus 162, the first sub-bus 161 and the second sub-bus 162 can carry the master ID (MID) information corresponding to the processor 11, so that it is possible to determine which processor 11 or operating system 111 accesses the first sub-bus 161 or the second sub-bus 162 based on the MID information, so as to facilitate subsequent determination of access rights.

[0042] In some embodiments, the communication unit 12 may determine access rights to the processor based on the processor MID information.

[0043] For example, if the MID information corresponding to processor 11-1 is mid 1, then when processor 11-1 accesses communication unit 12, communication unit 12 can obtain the MID information corresponding to processor 11-1 through first sub-bus 161 or second sub-bus 162. In this case, communication unit 12 can obtain mid 1 and determine whether processor 11-1 has access rights based on mid 1.

[0044] Exemplarily, the communication unit 12 includes a configuration device 121 , a control device 122 and a communication device 123 .

[0045] In some embodiments, the configuration device 121 is communicatively connected to the bus 13 via the first interface 14 and the first sub-bus 161. In this way, the communication unit 12 can receive configuration information via the independent first interface 14 to achieve independent settings of configuration functions and communication functions.

[0046] In some embodiments, the configuration information in the configuration device 121 includes MID information stored in the first address space 121 a and the second address space 121 b .

[0047] In some embodiments, the configuration device 121 may be a register 1211, which includes a first address space 121a and a second address space 121b. The first address space 121a and the second address space 121b may store different information respectively.

[0048] In some embodiments, the configuration device 121 may also be a dedicated configuration memory, a non-volatile memory, or other device capable of receiving and storing configuration information. In the examples disclosed herein, the specific form of the configuration device 121 is not limited.

[0049] For example, the first address space 121a may allow the processor 11 in the integrated circuit 10 with the highest functional safety level to access the first address space 121a through the first sub-bus 161 and the first interface 14. In this way, the processor 11 in the integrated circuit 10 can configure the sending end access rights of the communication device 123 in the first address space 121a of the configuration device 121. The sending end of the communication device 123 refers to the communication end accessed by the processor 11 that initiates communication.

[0050] For example, according to the Automotive Safety Integrity Level (ASIL) defined by the International Organization for Standardization and the risks associated with hazards, the functional safety levels of the multiple processors 11 in the integrated circuit 10 are divided into four levels: ASIL-A, ASIL-B, ASIL-C, ASIL-D, and quality management (QM). Among them, the functional safety level specified by ASIL-D is the highest, and the functional safety levels specified by ASIL-C, ASIL-B, ASIL-A, and QM decrease in sequence. The embodiments of the present disclosure do not limit the type of functional safety level corresponding to each processor, and this is only an exemplary description.

[0051] In some embodiments, the information stored in the first address space 121a may be stored in the form of a first identifier, such as src mid m, where src represents the transmitting end and mid m represents the master identifier of the processor 11. For example, src mid 1 indicates that the master identifier of the processor 11 that can access the transmitting end of the communication device 123 is mid 1. If the master identifier of the processor 11-1 is mid 1, it means that the processor 11-1 can access the transmitting end of the communication device 123.

[0052] For example, the second address space 121b can be accessed by the processor 11 in the integrated circuit 10 with the highest functional safety level, as well as other processors 11 in the integrated circuit 10 that have access rights to the transmitter end of the communication device 123. When the processor 11 accesses the second address space 121b, it can do so through the first sub-bus 161 and the first interface 14. In this way, the processor 11 in the integrated circuit 10 can configure the receiving end access rights of the communication device 123 in the second address space 121b of the configuration device 121. The receiving end of the communication device 123 refers to the communication end accessed by the processor 11 receiving the communication.

[0053] In some embodiments, the information stored in the second address space 121b may be stored in the form of a second identifier, such as dst mid m, where dst represents the receiving end and mid m represents the master identifier of the processor 11. For example, dst mid 1 indicates that the master identifier of the processor 11 that can access the receiving end of the communication device 123 is mid 1. If the master identifier of the processor 11-1 is mid 1, it means that the processor 11-1 can access the receiving end of the communication device 123.

[0054] It can be understood that in other embodiments, the information stored in the first address space 121a and the second address space 121b can be opposite to the above example, or all information can be stored in the first address space 121a, or all information can be stored in the second address space 121b, which is not limited in the present disclosed embodiments.

[0055] Exemplarily, processor 11 can configure access rights for communication device 123, and configuration device 121 in communication unit 12 can receive configuration information from processor 11. For example, processor 11-1 can configure both processor 11-1 and processor 11-2 to have access rights to communication device 123, and configuration device 121 can then receive configuration information from processor 11-1. In this way, when processors 11-1 and 11-2 communicate via communication device 123, other processors 11 cannot access communication device 123, thereby increasing access rights to communication device 123 and enhancing communication security between processors 11-1 and 11-2.

[0056] It is understandable that the processor 11 capable of configuring the access rights of the communication device 123 through the configuration device 121 can be a designated processor or a processor with the sending end permission to access the communication device 123, which is not limited in the embodiment of the present disclosure.

[0057] In some embodiments, the control device 122 is communicatively connected to the bus 13 via the second interface 15 . Meanwhile, the configuration device 121 is communicatively connected to the control device 122 , and the control device 122 is communicatively connected to the communication device 123 .

[0058] Exemplarily, the control device 122 can control the processor 11's access to the communication device 123. For example, when the processor 11-1 requests access to the communication device 123, the control device 122 can obtain the configuration information in the configuration device 121 to determine whether the processor 11-1 has access rights to the communication device 123. If the processor 11-1 has access rights to the communication device 123, the control device 122 can allow the processor 11-1 to access the communication device 123. If the processor 11-1 does not have access rights to the communication device 123, the control device 122 can intercept the processor 11-1's access to the communication device 123 and return an error message, such as "error," thereby implementing secure access control over the communication device 123.

[0059] In some embodiments, the control device 123 can be hardware such as a memory protection unit (MPU), a hardware firewall (Hardware Firewall), a privilege level controller (Privilege Level Checker), and a security state controller (TrustZone / TPM). In the embodiments of the present disclosure, the specific form of the control device 123 is not limited.

[0060] For example, the communication device 123 may include multiple mailboxes, such as mailbox 0, mailbox 1, mailbox 2, and mailbox m, where m is a positive integer. In this way, when the processor 11 communicates through the communication device 123, it can use the mailboxes in the communication device 123 to communicate.

[0061] It should be noted that the sending end of the communication device 123 may refer to the sending end of each mailbox, and the receiving end of the communication device 123 may refer to the receiving end of each mailbox.

[0062] In some embodiments, when the processor 11 configures the access rights of the communication device 123 through the configuration device 121 , the access rights of each mailbox may be specifically configured.

[0063] Exemplarily, the configuration device 121 can configure the sending end processor 11 and the receiving end processor 11 that are allowed to access each mailbox. A sending end processor 11 that is allowed to access a mailbox is a processor 11 that initiates communication and is allowed to access a mailbox. A receiving end processor 11 that is allowed to access a mailbox is a processor 11 that receives communication and is allowed to access a mailbox.

[0064] Figure 4This is a schematic diagram of configuration information provided by an exemplary embodiment of the present disclosure, combined with Figure 3 and Figure 4 As shown, in some embodiments, the configuration information stored in the configuration device 121 can be directly targeted at each mailbox.

[0065] For example, the first address space 121a includes mailbox 0 src mid 1, mailbox 1 src mid 2, and mailbox m src mid n. Mailbox 0 src mid 1 indicates that the master identifier of processor 11, which can access the sender end of mailbox 0, is mid 1. If the master identifier of processor 11-1 is mid 1, then processor 11-1 can access the sender end of mailbox 0.

[0066] Exemplarily, the processor 11 can configure a sending-end processor 11 for each mailbox in the configuration device 121. Alternatively, the processor 11 can modify the sending-end processor 11 corresponding to each mailbox in the configuration device 121 so that each mailbox can be accessed by a different processor 11 during different communication processes. When the communication device 123 includes multiple mailboxes, the processor 11 that the sending end of each mailbox is allowed to access can be the same or different, which is not limited in the embodiments of the present disclosure.

[0067] In some embodiments, during communication between processors 11, a mailbox can only be configured to match a processor 11 that is allowed to access the sending end, so as to avoid other processors 11 accessing the sending end during the communication process, thereby affecting the normal communication.

[0068] Illustratively, the second address space 121b includes mailbox 0dst mid 1, mailbox 0dst mid 2, mailbox 0dst mid n, mailbox 1dst mid 1, mailbox 1dst mid 2, mailbox 1dst mid n, mailbox m dst mid 1, mailbox m dst mid 2, and mailbox m dst mid n. Mailbox 0dst mid 1 indicates that the master identifier of processor 11, which can access the receiving end of mailbox 0, is mid 1. If the master identifier of processor 11-1 is mid 1, then processor 11-1 can access the receiving end of mailbox 0.

[0069] Exemplarily, the processor 11 can configure a receiving-end processor 11 for each mailbox in the configuration device 121. Alternatively, the processor 11 can modify the receiving-end processor 11 corresponding to each mailbox in the configuration device 121 so that each mailbox can be accessed by a different processor 11 during different communication processes. When the communication device 123 includes multiple mailboxes, the processor 11 allowed to be accessed by the receiving end of each mailbox can be the same or different, which is not limited in the embodiments of the present disclosure.

[0070] In some embodiments, the configuration device 121 can configure one or more receiving-end processors 11 for each mailbox. In this way, the receiving-end processor 11 can access the receiving end of the mailbox to read the communication information of the sending end.

[0071] For example, if a mailbox can only be configured to match one processor 11 that is allowed to access the receiving end, it means that the mailbox can achieve one-to-one communication. If a mailbox can only be configured to match multiple processors 11 that are allowed to access the receiving end, it means that the mailbox can achieve one-to-many communication. The number of processors 11 that each mailbox can allow to access the receiving end can be determined based on actual needs and is not limited in the embodiments of the present disclosure.

[0072] It should be noted that the master identifier corresponding to each processor 11 may also be represented in other forms, and mid 1-mid m in the embodiment of the present disclosure is only an example.

[0073] It is understandable that, in other examples, the communication device 123 may also communicate through a shared memory or a NoC, which is not limited in the embodiments of the present disclosure.

[0074] Exemplary Methods

[0075] Figure 5 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, such as Figure 5 As shown, the following steps are included:

[0076] Step 110: Determine first identifiers corresponding to the first processors and second identifiers corresponding to the second processors.

[0077] Combine Figure 3 、 Figure 4 and Figure 5 As shown, illustratively, the first processor may be the processor 11 in the integrated circuit 10 that is allowed to access the transmitting end of the communication device 123 .

[0078] In some embodiments, if there are multiple processors 11 that are allowed to access the transmitting end of the communication device 123 , then there are multiple first processors. The first identifiers corresponding to the first processors are the MIDs corresponding to the processors 11 that are allowed to access the transmitting end of the communication device 123 .

[0079] In other embodiments, if there is only one processor 11 allowed to access the transmitting end of the communication device 123 , then there is also only one first processor. The first identifier corresponding to each first processor is the MID corresponding to the processor 11 allowed to access the transmitting end of the communication device 123 .

[0080] Exemplarily, the second processor may be the processor 11 in the integrated circuit 10 that is allowed to access the receiving end of the communication device 123 .

[0081] In some embodiments, if there are multiple processors 11 that are allowed to access the receiving end of the communication device 123 , then there are multiple second processors. The second identifiers corresponding to the second processors are the MIDs corresponding to the processors 11 that are allowed to access the receiving end of the communication device 123 .

[0082] In other embodiments, if there is only one processor 11 allowed to access the receiving end of the communication device 123 , there is also only one second processor. The second identifier corresponding to each second processor is the master identifier MID corresponding to the processor 11 allowed to access the receiving end of the communication device 123 .

[0083] Exemplarily, the first identifiers respectively corresponding to the first processors include a master identifier MID of the sending-end processor 11 that is allowed to access a mailbox in the communication device 123 .

[0084] In some embodiments, take the example of two processors 11 in the integrated circuit 10 communicating through mailbox 0 in the communication device 123. First, a first identifier (source mid, src mid) for the processor 11 that can access the sending end of mailbox 0 and a second identifier (destination mid, dst mid) for the processor 11 that can access the receiving end of mailbox 0 can be configured.

[0085] For example, if there is only one processor 11 on the sending side that is allowed to access mailbox 0, there is one first identifier; if there are multiple processors 11 on the sending side that are allowed to access mailbox 0, there are multiple first identifiers. If there is only one processor 11 on the receiving side that is allowed to access mailbox 0, there is one second identifier; if there are multiple processors 11 on the receiving side that are allowed to access mailbox 0, there are multiple second identifiers.

[0086] Step 120: Determine the access relationship between the first processor and the second processor.

[0087] Exemplarily, the access relationship between the first processor and the second processor includes the first processor initiating communication to the second processor, or the second processor initiating communication to the first processor. In the embodiment of the present disclosure, the first processor initiating communication to the second processor is used as an example for description.

[0088] Step 130: Determine a matching relationship between the third identifier of the first processor and the first identifier, and a matching relationship between the fourth identifier of the second processor and the second identifier, based on the access relationship.

[0089] Exemplarily, the third identifier of the first processor is the master identifier MID of the first processor itself, and the fourth identifier of the second processor is the master identifier MID of the second processor itself.

[0090] In some embodiments, after determining the access relationship between the first processor and the second processor, the master identifier MID of the first processor may be matched with the src mid of the transmitting end permitted to access the communication device 123 to determine a matching relationship between the third identifier and the first identifier. Simultaneously, the master identifier MID of the second processor may be matched with the dst mid of the receiving end permitted to access the communication device 123 to determine a matching relationship between the fourth identifier and the second identifier.

[0091] Exemplarily, the matching relationship between the third identifier and the first identifier includes that the third identifier matches the first identifier or that the third identifier does not match the first identifier. The matching relationship between the fourth identifier and the second identifier includes that the fourth identifier matches the second identifier or that the fourth identifier does not match the second identifier.

[0092] Step 140: Determine the communication status between the first processor and the second processor based on the matching relationship.

[0093] Exemplarily, the communication status includes a state in which communication is possible and a state in which communication is not possible.

[0094] In some embodiments, when the matching relationship between the third identifier and the first identifier is that the third identifier matches the first identifier, the communication status between the first processor and the communication device 123 is that communication is possible. When the matching relationship between the third identifier and the first identifier is that the third identifier does not match the first identifier, the communication status between the first processor and the communication device 123 is that communication is not possible.

[0095] Exemplarily, when the matching relationship between the fourth identifier and the second identifier is that the fourth identifier matches the second identifier, the communication status between the second processor and the communication device 123 is that communication is possible. When the matching relationship between the fourth identifier and the second identifier is that the fourth identifier does not match the second identifier, the communication status between the second processor and the communication device 123 is that communication is not possible.

[0096] In some embodiments, when the communication status between the first processor and the communication device 123 is communication-capable, and the communication status between the second processor and the communication device 123 is communication-capable, the communication status between the first processor and the second processor is communication-capable. In this way, the first processor and the second processor can communicate through the communication device 123.

[0097] In the inter-processor communication method of the integrated circuit provided by the embodiment of the present disclosure, by determining the first identifier and the second identifier corresponding to the first processor and the second processor respectively and determining the access relationship between the first processor and the second processor, it is possible to further determine the matching relationship between the third identifier of the first processor and the first identifier and the matching relationship between the fourth identifier of the second processor and the second identifier based on the access relationship; and then determine the communication state between the first processor and the second processor through the matching relationship. In this way, before the first processor and the second processor communicate, the communication state between the first processor and the second processor can be determined by the matching relationship between the corresponding identifiers. If the matching relationship between the corresponding identifiers of the first processor and the second processor meets the communication requirements, the communication state between the first processor and the second processor can be determined as communication is possible, so as to improve the security of the communication between the processors. If the matching relationship between the respective identifiers of the first processor and the second processor does not meet the communication requirements, the communication state between the first processor and the second processor can be determined as communication is not possible, so as to avoid the problem of information leakage during the communication process.

[0098] Figure 6 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 6 As shown in the above Figure 5 Based on the embodiment shown, step 110 may include the following steps:

[0099] Step 111: Receive first configuration information sent by a preset processor to a configuration device of a communication unit through a first interface.

[0100] Exemplarily, the preset processor may be any processor 11 in the integrated circuit 10 . Alternatively, the preset processor may be the processor 11 in the integrated circuit 10 with the highest functional safety level.

[0101] In some embodiments, the preset processor may be a processor 11 with a functional safety level of ASIL-D.

[0102] In some embodiments, when two processors 11 in the integrated circuit 10 need to communicate, the preset processor can access the configuration device 121 of the communication unit 12 through the first interface, so that the preset processor can configure the first configuration information in the configuration device 121 .

[0103] Exemplarily, the first configuration information may include a first identifier corresponding to the first processor and a second identifier corresponding to the second processor.

[0104] Step 112: store first identifiers corresponding to the first processors in the first configuration information in the first address space of the configuration device, and store second identifiers corresponding to the second processors in the first configuration information in the second address space of the configuration device.

[0105] Exemplarily, the configuration device 121 may include a first address space and a second address space, wherein the first address space and the second address space are used to store the MID.

[0106] In some embodiments, the preset processor may store a first identifier corresponding to the sending-end processor 11 capable of accessing each mailbox in the communication device 123 in a first address space, and simultaneously store a second identifier corresponding to the receiving-end processor 11 capable of accessing each mailbox in the communication device 123 in a second address space. In this way, when subsequently acquiring the first identifier and the second identifier, they can be acquired by accessing different address spaces, thereby improving information acquisition efficiency.

[0107] In the embodiment of the present disclosure, a preset processor can be used to configure the first identifier and the second identifier that can access each mailbox in the configuration device 121 of the communication unit 12 in advance. In this way, the access rights of each mailbox can be configured in advance by the preset processor, laying the foundation for subsequent communication security.

[0108] Figure 7 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 7 As shown in the above Figure 5 Based on the embodiment shown, step 110 may include the following steps:

[0109] Step 113: Receive second configuration information sent by the preset processor to the configuration device of the communication unit through the first interface.

[0110] It should be noted that, for the relevant description of the preset processor, reference may be made to the description of step 111 and will not be repeated here.

[0111] Exemplarily, the second configuration information includes a first identifier corresponding to the first processor. In this way, the preset processor can configure the identifier corresponding to the sending end processor 11 that can access the mailbox in the configuration device 121 of the communication unit 12.

[0112] Step 114: Store the first identifiers corresponding to the first processors in the second configuration information in the first address space of the configuration device.

[0113] Exemplarily, the preset processor may store the second configuration information in the first address space in the configuration device 121 , so as to facilitate subsequent acquisition by the control device 122 .

[0114] Step 115 : Based on the first processor initiating an access request to the communication unit, the third configuration information sent by the first processor to the configuration device is received through the first interface.

[0115] For example, after the first processor initiates an access request to the communication unit 12, the first processor can automatically send third configuration information to the configuration device 121 through the first interface. The third configuration information includes the second identifiers corresponding to the second processors. In this way, the access rights of each mailbox receiving end in the communication device 123 do not need to be set in advance in the configuration device 121. The access rights can be configured after the first processor initiates an access request to the communication unit 12, so that the processor rights that can access the receiving end of the communication device 123 can be set at the beginning of communication, thereby realizing real-time setting of access rights.

[0116] It should be noted that the first configuration information may include the first identifier corresponding to each first processor and the second identifier corresponding to each second processor. The second configuration information only includes the first identifier corresponding to each first processor, and the third configuration information only includes the second identifier corresponding to each second processor.

[0117] In other words, Figure 6 In the method shown, the information configuration of the first identifier and the second identifier is performed simultaneously. Figure 6 The configuration method shown is a static configuration. Figure 7 In the method shown, the first identifier information is configured first, and then the second identifier information is configured based on access by the first processor, which is a dynamic configuration based on communication startup.

[0118] In the embodiments of the present disclosure, Figure 6 The method in provides a static configuration method for access permissions. Figure 7The method in provides a dynamic configuration method for access rights. During the specific implementation process, the configuration method can be determined according to actual needs, and is not specifically limited in the embodiments of the present disclosure.

[0119] Step 116: Store the second identifiers corresponding to the second processors in the third configuration information in the second address space of the configuration device.

[0120] Exemplarily, the first processor may store the third configuration information in the second address space in the configuration device 121 , so as to facilitate subsequent acquisition by the control device 122 .

[0121] In the disclosed embodiment, a preset processor can be used to pre-configure in the configuration device 121 a sending-end processor capable of accessing each mailbox in the communication device 123, thereby enabling normal access to the sending end of the mailbox when the processor 11 needs to communicate. After the first processor initiates an access request to the communication unit, the first processor can receive the configuration of the access rights to the receiving end of the mailbox, thereby enabling the first processor to communicate normally with the second processor. At the same time, it can also prevent other processors from accessing the current mailbox during the communication between the first and second processors, thereby avoiding affecting communication security.

[0122] Figure 8 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 8 As shown in the above Figure 5 Based on the embodiment shown, step 130 may include the following steps:

[0123] Step 131: Based on the first processor initiating an access request to the communication device of the communication unit through the second interface, the control device of the communication unit obtains the third identifier of the first processor through the second interface.

[0124] In some embodiments, when the first processor needs to initiate communication, the first processor may access the communication device 123 of the communication unit 12 through the second interface.

[0125] Exemplarily, when the first processor needs to initiate communication, it initiates access to a designated mailbox in the communication device 123. For example, the first processor needs to communicate with the second processor through mailbox 0.

[0126] In some embodiments, the control device 122, which is communicatively connected to the second interface, can preferentially obtain the third identifier of the first processor received by the second interface. The third identifier is the MID of the first processor itself. In this way, the control device 122 can determine whether the first processor has permission to access the mailbox 0 sender in the communication device 123 based on the third identifier.

[0127] In step 132 , the control device determines a matching relationship between the third identifier and the first identifier.

[0128] Exemplarily, after the control device 122 obtains the third identifier, the control device 122 may obtain the first identifier stored in the first address space of the configuration device 121 to match the third identifier with the first identifier.

[0129] In some embodiments, if the first identifiers stored in the first address space include a first identifier that is identical to the third identifier, it indicates that the third identifier matches the first identifier. If the first identifiers stored in the first address space do not include a first identifier that is identical to the third identifier, it indicates that the third identifier does not match the first identifier.

[0130] In the embodiment of the present disclosure, if a first processor wants to communicate with a second processor through mailbox 0, the control device 122 can intercept the first processor's access to the sending end of mailbox 0 to determine whether the first processor has access rights to access the sending end of mailbox 0, thereby preventing the first processor from destroying the communication security of mailbox 0 when communicating with other processors.

[0131] Figure 9 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 9 As shown in the above Figure 5 Based on the embodiment shown, step 140 may include the following steps:

[0132] Step 141: Based on the matching of the third identifier and the first identifier, the control device determines that the communication state of the first processor includes allowing the first processor to access the communication device and allowing the first processor to write communication data to the communication device.

[0133] For example, when the third identifier matches the first identifier, it indicates that the first processor has access rights to access the sender end of the specified mailbox in the communication device 123. In this case, the control device 122 may allow the first processor to perform communication access.

[0134] For example, when the first processor communicates with the second processor through mailbox 0, the third identifier is mid 1. The first identifier stored in the first address space (the sender identifier corresponding to mailbox 0) includes mid 1, indicating that the third identifier matches the first identifier. In this case, the first processor has permission to access the sender of mailbox 0. The control device 122 can allow the first processor to access the sender of mailbox 0 and allow the first processor to write communication data to mailbox 0.

[0135] Figure 10 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 10 As shown in the above Figure 9 Based on the embodiment shown, step 141 may include the following steps:

[0136] Step 151: Based on the access of the first processor to the communication device, the communication device sends an interrupt notification to the second processor.

[0137] In some embodiments, when the first processor is able to access the communication device 123, it indicates that the communication between the first processor and the second processor has begun. At this time, the first processor can trigger the communication device 123 to send a communication notification to the second processor.

[0138] Exemplarily, the first processor triggering the communication device 123 to send a communication notification to the second processor may be that the first processor triggers a mailbox to send an interrupt signal to the second processor to notify the second processor to access the receiving end of the mailbox that sends the interrupt signal to complete the communication process.

[0139] For example, after the first processor accesses the sending end of mailbox 0, the first processor may trigger mailbox 0 to send an interrupt signal to the second processor to notify the second processor to communicate.

[0140] Figure 11 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 11 As shown in the above Figure 5 Based on the embodiment shown, step 130 may further include the following steps:

[0141] Step 133: Based on the interrupt notification, the second processor initiates an access request to the communication device through the second interface.

[0142] In some embodiments, after receiving the interrupt notification, the second processor may initiate an access request to the communication device 123 through the second interface to read the communication data of the first processor, thereby completing the communication process between the first processor and the second processor.

[0143] Illustratively, after the second processor receives the interrupt signal sent by mailbox 0, the second processor may access the receiving end of mailbox 0 through the second interface to receive the communication data of the first processor.

[0144] Step 134 : Based on the access request of the second processor, the control device obtains a fourth identifier of the second processor through the second interface.

[0145] In some embodiments, when the second processor needs to receive communication data, the second processor may access the communication device 123 of the communication unit 12 through the second interface.

[0146] Exemplarily, the second processor needs to access the receiving end of mailbox 0 through the second interface to obtain the communication data of the first processor.

[0147] In some embodiments, the control device 122, which is communicatively connected to the second interface, can preferentially obtain the fourth identifier of the second processor received by the second interface. The fourth identifier is the MID of the second processor itself. In this way, the control device 122 can determine whether the second processor has permission to access the mailbox 0 receiving end in the communication device 123 based on the fourth identifier.

[0148] Step 135: The control device determines a matching relationship between the fourth identifier and the second identifier.

[0149] Illustratively, after the control device 122 obtains the fourth identifier, the control device 122 may obtain the second identifier stored in the second address space of the configuration device 121 to match the fourth identifier with the second identifier.

[0150] In some embodiments, if the second identifiers stored in the second address space include a second identifier that is identical to the fourth identifier, it indicates that the fourth identifier matches the second identifier. If the second identifiers stored in the second address space do not include a second identifier that is identical to the fourth identifier, it indicates that the fourth identifier does not match the second identifier.

[0151] In the embodiment of the present disclosure, if the second processor communicates with the first processor through Mailbox 0 under the triggering of an interrupt notification, the control device 122 can intercept the second processor's access to the receiving end of Mailbox 0 to determine whether the second processor has access rights to access the receiving end of Mailbox 0, thereby preventing Mailbox 0 from being compromised by the second processor when communicating with other processors.

[0152] Figure 12 FIG. 1 is a flow chart of an inter-processor communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure. Figure 12 As shown in the above Figure 5 Based on the embodiment shown, step 140 may include the following steps:

[0153] Step 142: Based on the match between the fourth identifier and the second identifier, the control device determines that the communication status of the second processor includes allowing the second processor to access the communication device and allowing the second processor to read communication data in the communication device.

[0154] Exemplarily, when the fourth identifier matches the second identifier, it indicates that the second processor has access rights to access the receiving end of the designated mailbox in the communication device 123. In this case, the control device 122 may allow the second processor to perform communication access.

[0155] For example, when the first processor and the second processor communicate through mailbox 0, the fourth identifier is mid 2. The second identifier stored in the second address space (the receiving end identifier corresponding to mailbox 0) includes mid 2, indicating that the fourth identifier matches the second identifier. In this case, the second processor has permission to access the receiving end of mailbox 0. The control device 122 can allow the second processor to access the sending end of mailbox 0 and allow the second processor to read the communication data in mailbox 0.

[0156] In the inter-processor communication method provided in the embodiments of the present disclosure, access rights to each mailbox in the communication device of the communication unit are pre-set. When the processor 11 in the integrated circuit 10 needs to communicate via the mailbox, the control device in the communication unit can confirm whether each processor has access rights, thereby achieving control over access to the mailbox and improving communication security when the processors communicate via the mailbox.

[0157] In some embodiments, the first processor runs a first operating system and the second processor runs a second operating system as an example for description:

[0158] When the first operating system needs to communicate with the second operating system, it can first determine the first identifier corresponding to the first processor running the first operating system, the second identifier corresponding to the second processor running the second operating system, and the access relationship between the first operating system and the second operating system. Based on the access relationship, it can determine the matching relationship between the third identifier of the first processor and the first identifier, and the fourth identifier of the second processor and the second identifier; and then determine the communication status between the first processor and the second processor through the matching relationship. In this way, before the first processor and the second processor communicate, the communication status between the first processor and the second processor can be determined through the matching relationship of each identifier. When the matching relationship of each identifier of the first processor and the second processor meets the security requirements, the first operating system and the second operating system can be allowed to communicate through the first processor and the second processor to improve the security of communication between the processors.

[0159] Exemplary devices

[0160] Figure 13 FIG. 1 is another structural diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 13 As shown, the embodiment of the present disclosure further provides an integrated circuit 10, including multiple processors 11 and a communication unit 12. The multiple processors 11 can communicate through the communication unit 12, and the multiple processors include a first processor and a second processor, and the first processor and the second processor can communicate.

[0161] For example, the communication unit may determine a first identifier corresponding to each of the first processors, a second identifier corresponding to each of the second processors, and an access relationship between the communication units of the first and second processors. Based on the access relationship, the communication unit may determine a matching relationship between the third identifier of the first processor and the first identifier, and a matching relationship between the fourth identifier of the second processor and the second identifier; based on the matching relationship, the communication unit may determine a communication status between the first and second processors.

[0162] In some embodiments, the communication unit 12 includes a configuration module 12a, a control module 12b, and a communication module 12c. The processor 11 in the integrated circuit 10 can configure access rights for the communication module 12c in the configuration module 12a. The control module 12b can determine whether the processor 11 has permission to access the communication module 12c based on the configuration information in the configuration module 12a, thereby implementing access security management. The communication module 12c enables communication between processors 11 that have permission to access the communication module 12c.

[0163] In some embodiments, configuration module 12a is capable of receiving first configuration information sent by a preset processor to configuration module 12a. A first address space of configuration module 12a may store first identifiers corresponding to each first processor in the first configuration information; and a second address space of configuration module 12a may store second identifiers corresponding to each second processor in the first configuration information.

[0164] In some embodiments, configuration module 12a is capable of receiving second configuration information sent to configuration module 12a by a preset processor. The first address space of configuration module 12a may store first identifiers corresponding to each first processor in the second configuration information. Based on an access request initiated by the first processor to communication unit 12, configuration module 12a is capable of receiving third configuration information sent to configuration module 12a by the first processor. The second address space of configuration module 12a may store second identifiers corresponding to each second processor in the third configuration information.

[0165] In some embodiments, the control module 12b obtains the third identifier of the first processor based on the first processor initiating an access request to the communication module 12c of the communication unit 12. The control module 12b determines a matching relationship between the third identifier and the first identifier.

[0166] In some embodiments, based on the third identifier matching the first identifier, the control module 12b determines that the communication status of the first processor includes allowing the first processor to access the communication module 12c and allowing the first processor to write communication data to the communication module 12c.

[0167] In some embodiments, based on the first processor accessing the communication module 12c, the communication module 12c sends an interrupt notification to the second processor.

[0168] In some embodiments, based on the interrupt notification, the second processor initiates an access request to the communication module 12c. Based on the access request of the second processor, the control module 12b obtains the fourth identifier of the second processor and determines whether the fourth identifier matches the second identifier.

[0169] In some embodiments, based on the fourth identifier matching the second identifier, the control module 12b determines that the communication status of the second processor includes allowing the second processor to access the communication module 12c and allowing the second processor to read communication data in the communication module 12c.

[0170] The beneficial technical effects corresponding to the exemplary embodiment of this device can be found in the corresponding beneficial technical effects of the above exemplary method part, which will not be repeated here.

[0171] Exemplary electronic devices

[0172] Figure 14 14 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure, including at least one processor 1401 and a memory 1402.

[0173] The processor 1401 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0174] The memory 1402 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1401 may execute the one or more computer program instructions to implement the inter-processor communication method of the integrated circuit and / or other desired functions of the various embodiments of the present disclosure described above.

[0175] In one example, the electronic device 1400 may further include an input device 1403 and an output device 1404 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0176] The input device 1403 may also include, for example, a keyboard, a mouse, etc.

[0177] The output device 1404 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output devices, etc.

[0178] Of course, to simplify, Figure 14 Only some of the components related to the present disclosure in the electronic device 1400 are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, the electronic device 1400 may further include any other appropriate components according to specific application scenarios.

[0179] Exemplary computer program products and computer-readable storage media

[0180] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to perform the steps of the inter-processor communication method of the integrated circuit of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0181] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0182] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the inter-processor communication method of the integrated circuit of the various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0183] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or component comprising electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0184] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be considered as essential to each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0185] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A method for inter-processor communication in an integrated circuit, comprising: Determine first identifiers corresponding to the first processors and second identifiers corresponding to the second processors; determining an access relationship between the first processor and the second processor; Based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; Based on the matching relationship, a communication status between the first processor and the second processor is determined.

2. The method according to claim 1, wherein The determining of the first identifiers corresponding to the first processors and the second identifiers corresponding to the second processors includes: receiving, through the first interface, first configuration information sent by the preset processor to the configuration device of the communication unit; The first identifiers corresponding to the first processors in the first configuration information are stored in a first address space of the configuration device, and the second identifiers corresponding to the second processors in the first configuration information are stored in a second address space of the configuration device.

3. The method according to claim 1, wherein The determining of the first identifiers corresponding to the first processors and the second identifiers corresponding to the second processors includes: receiving, through the first interface, second configuration information sent by the preset processor to the configuration device of the communication unit; storing, in a first address space of the configuration device, the first identifiers respectively corresponding to the first processors in the second configuration information; Initiating an access request to the communication unit by the first processor, receiving third configuration information sent by the first processor to the configuration device through the first interface; The second identifiers respectively corresponding to the second processors in the third configuration information are stored in the second address space of the configuration device.

4. The method according to any one of claims 1 to 3, wherein: The determining, based on the access relationship, a matching relationship between the third identifier of the first processor and the first identifier includes: Based on the first processor initiating an access request to the communication device of the communication unit through the second interface, the control device of the communication unit obtains the third identifier of the first processor through the second interface; The control device determines a matching relationship between the third identifier and the first identifier.

5. The method according to claim 4, wherein The determining, based on the matching relationship, a communication state between the first processor and the second processor includes: Based on the third identifier matching the first identifier, the control device determines that the communication state of the first processor includes allowing the first processor to access the communication device and allowing the first processor to write communication data to the communication device.

6. The method according to claim 5, wherein: Also includes; Based on the access of the first processor to the communication device, the communication device sends an interrupt notification to the second processor.

7. The method according to claim 6, wherein: The determining, based on the access relationship, a matching relationship between the fourth identifier of the second processor and the second identifier includes: Based on the interrupt notification, the second processor initiates an access request to the communication device through the second interface; Based on the access request of the second processor, the control device obtains the fourth identifier of the second processor through the second interface; The control device determines a matching relationship between the fourth identifier and the second identifier.

8. The method according to claim 7, wherein: The determining, based on the matching relationship, a communication state between the first processor and the second processor further includes: Based on the fourth identifier matching the second identifier, the control device determines that the communication state of the second processor includes allowing the second processor to access the communication device and allowing the second processor to read the communication data in the communication device.

9. An integrated circuit comprising a plurality of processors, the plurality of processors comprising a first processor and a second processor, a first operating system running on the first processor, and a second operating system running on the second processor; Determine first identifiers corresponding to the first processors running the first operating system and second identifiers corresponding to the second processors running the second operating system; determining an access relationship between the first operating system and the second operating system; Based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; Based on the matching relationship, a communication status between the first operating system and the second operating system is determined.

10. An integrated circuit comprising a plurality of processors and a communication unit, wherein the plurality of processors communicate with each other via the communication unit, and wherein the plurality of processors include a first processor and a second processor; Determining, by the communication unit, first identifiers corresponding to the first processors and second identifiers corresponding to the second processors; The communication unit determines an access relationship between the first processor and the communication unit of the second processor; Based on the access relationship, the communication unit determines a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; Based on the matching relationship, the communication unit determines a communication state between the first processor and the second processor.

11. A computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the inter-processor communication method for an integrated circuit according to any one of claims 1 to 8.

12. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the inter-processor communication method of the integrated circuit according to any one of claims 1 to 8; Alternatively, the electronic device comprises the integrated circuit according to claim 9 or claim 10.

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