Multi-patterning method, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention relates to a multi-patterning method, electronic equipment and a computer readable storage medium. The method comprises the following steps: generating a first mask based on a design layout, wherein leads of a metal layer in the design layout are arranged according to a minimum design rule; a second mask is generated based on the design layout, the second mask comprises an expansion area generated by expanding each lead by a first preset distance, and the expansion area comprises a continuous area so that the leads in the corresponding areas in the design layout can be covered; and respectively exposing the first mask and the second mask to form light intensity distribution used for generating a photoetching groove corresponding to the lead in the photoresist. According to the scheme disclosed by the invention, a larger process window, higher overlay precision and good line end performance can be realized.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuits, and more particularly, to a multi-patterning method, an electronic device, and a computer-readable storage medium. Background Art

[0002] Computational lithography has been a key driver of the continued advancement of pattern miniaturization technology since the 1990s. While maintaining the existing hardware environment of lithography equipment, computational lithography aims to overcome hardware limitations in minimum exposure size through software technologies such as resolution enhancement, significantly advancing the development of advanced semiconductor processes.

[0003] In photolithography, when using a photolithography machine with the same wavelength (such as a 193nm light source photolithography machine for wet lithography), the metal wiring layer can resolve a size of 38nm / 38nm (Pitch 76nm) in a single direction in a single exposure using a special light source.

[0004] In the back-end metal interconnect layers (also known as metal layers) of advanced semiconductor processes, a type of pattern has a minimum pitch of 76nm in one direction. Because a specialized light source is required, resolution in the other direction is poor, manifesting as poor stability at the line ends. Furthermore, the need to accommodate the process window for edge patterns often necessitates repositioning the design layout, which in turn necessitates adjustments to the positions of vias in upper and lower layers. This approach presents drawbacks such as a complex process and potentially unreliable accuracy. Summary of the Invention

[0005] According to example embodiments of the present disclosure, a multi-patterning method is provided to at least partially overcome the above or other potential drawbacks.

[0006] According to one aspect of the present disclosure, a multi-patterning method is provided. The method includes: generating a first mask based on a design layout, wherein the leads of a metal layer in the design layout are arranged according to a minimum design rule; generating a second mask based on the design layout, wherein the second mask includes an extended region generated by extending each lead by a first predetermined distance, wherein the extended region includes a continuous region capable of covering the leads in the corresponding region in the design layout; and exposing the first mask and the second mask separately to form a light intensity distribution for generating a photolithographic groove corresponding to the lead in the photoresist.

[0007] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions comprising: generating a first mask based on a design layout, wherein leads of a metal layer in the design layout are arranged according to minimum design rules; generating a second mask based on the design layout, wherein the second mask includes an extended region generated by extending each lead by a first predetermined distance, the extended region including a continuous region to cover the leads in the corresponding region in the design layout; and exposing the first mask and the second mask, respectively, to form a light intensity distribution for generating a photolithographic groove corresponding to the lead in a photoresist.

[0008] In some embodiments, the leads of the metal layer in the design layout extend along a first direction, and the first mask is alternately provided with light-transmitting portions and light-non-transmitting portions extending along the first direction and penetrating the first mask.

[0009] In some embodiments, the second mask includes an extended region generated by extending each lead line by a first predetermined distance along a second direction perpendicular to the first direction.

[0010] In some embodiments, generating the first mask based on the design layout includes: determining positions of light-transmitting portions and non-light-transmitting portions in the first mask based on a development method, so that the photolithography grooves generated after exposure correspond to the leads.

[0011] In some embodiments, generating the second mask based on the design layout includes: performing a first logic operation on a pattern in the design layout to extend the width of the lead, thereby forming the extended area.

[0012] In some embodiments, performing a first logical operation on a graphic in a design layout to expand the width of a lead includes: performing a size expansion operation on the design layout in a second direction so that the width of each lead is expanded by a predetermined size to form an initial expansion area; and performing an inversion operation on the initial expansion area to generate an expansion area.

[0013] In some embodiments, the predetermined size ranges from a size greater than or equal to 0.5 grid points and a size less than 1.5 grid points, where the size of a grid point is equal to the size of a minimum design rule.

[0014] In some embodiments, exposing the first mask and the second mask separately to form photolithography grooves corresponding to the leads in the photoresist includes: applying a negative development technique to expose the first mask and the second mask separately, wherein no etching process occurs between exposing the first mask and exposing the second mask.

[0015] In some embodiments, the method further includes: performing a second logical operation on the extended area to adjust a position of an edge of the extended area along a second direction.

[0016] In some embodiments, performing the second logical operation on the extended area includes performing a size shift operation on the extended area along a second direction so that an edge of the extended area moves a second predetermined distance, wherein the second predetermined distance is smaller than the first predetermined distance.

[0017] In some embodiments, the second distance is half of a size of a minimum design rule; or the second distance is determined based on process parameters.

[0018] In some embodiments, after the edge of the extended region moves a second predetermined distance, a spacing between the leads in the first region and the leads in the second region in the metal layer is greater than or equal to twice a size of a minimum design rule.

[0019] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which machine-executable instructions are stored. When the machine-executable instructions are executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0020] It will be understood from the following description that the technical solution disclosed in the present invention can achieve a larger process window, higher overlay accuracy, and good line segment performance, and can comprehensively improve the manufacturability of the final design.

[0021] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram illustrating an example environment in which embodiments of the present disclosure can be implemented; Figure 2 shows a flowchart of a multiple patterning method according to some embodiments of the present disclosure; FIG3A is a schematic diagram showing a design layout of a metal layer arranged according to minimum design rules according to some embodiments of the present disclosure; Figure 3B Schematic diagram showing a design layout of a metal layer arranged according to minimum design rules according to other embodiments of the present disclosure; Figure 4A The corresponding embodiment of the present disclosure is shown. Figure 3A A schematic diagram of a main pattern mask of a metal layer layout; Figure 4B The corresponding embodiments according to other embodiments of the present disclosure are shown. Figure 3BA schematic diagram of a main pattern mask of a metal layer layout; Figure 5A According to some embodiments of the present disclosure, Figure 3A Schematic diagram of the initial cutting mask generated by the layout of the metal layer; Figure 5B Shows some other embodiments of the present disclosure based on Figure 3B Schematic diagram of the initial cutting mask generated by the layout of the metal layer; Figure 6A According to some embodiments of the present disclosure, Figure 5A Schematic diagram of a final cutting mask generated by an initial cutting mask; Figure 6B According to some embodiments of the present disclosure, Figure 5B Schematic diagram of a final cutting mask generated by an initial cutting mask; Figure 7 The use of some embodiments of the present disclosure is shown Figure 4A Schematic diagram of light intensity distribution obtained after exposure of the main pattern mask shown; Figure 8 The present invention is shown in some embodiments of the present invention. Figure 4A The main pattern mask shown is exposed with Figure 6B Schematic diagram of the light intensity distribution obtained by exposing the final cut mask shown; Figure 9A The final generated corresponding to some embodiments of the present disclosure is shown. Figure 3A A schematic diagram of a metal layer layout of a metal layer; Figure 9B The final generated corresponding to some embodiments of the present disclosure is shown. Figure 3A A schematic diagram of a metal layer layout of a metal layer; Figure 10 A block diagram is shown of a computing device capable of implementing various embodiments of the present disclosure.

[0023] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0024] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals can be used in the figures where possible, and similar or identical reference numerals can represent similar or identical functions. Those skilled in the art will readily recognize, from the description below, that alternative embodiments of the structures and methods described herein can be adopted without departing from the principles of the present invention described herein.

[0025] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0026] As mentioned earlier, there is a type of graphics with a minimum pitch of 76nm in a single direction. Due to the need for a special light source, the resolution in the other direction will be relatively poor, which is specifically manifested in poor stability at the line end. In addition, due to the need to take into account the process window of the edge graphics, it is often necessary to reposition the design layout, and then adjust the position of the through-hole design of the upper and lower layers. The above solution has the disadvantages of complex process and possible lack of accuracy. In view of the above situation, once the metal layer is re-designed, in most cases the through-hole layer of the upper and lower layers needs to be re-designed together. Another problem is that in the case of non-uniform graphics (i.e., all graphics have the same L / S pattern), the pitch is usually not able to be further miniaturized.

[0027] In view of this, the present disclosure provides an improved solution.

[0028] Embodiments of the present disclosure provide an improved multi-patterning method. The method includes: generating a first mask based on a design layout, wherein the leads of a metal layer in the design layout are arranged according to minimum design rules; generating a second mask based on the design layout, wherein the second mask includes an extended area generated by extending each lead by a first predetermined distance, wherein the extended area includes a continuous area capable of covering the leads in the corresponding area in the design layout; and exposing the first mask and the second mask separately to form a light intensity distribution for generating photolithographic grooves corresponding to the leads in the photoresist.

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 1 shows a schematic diagram of an example environment 100 in which embodiments according to the present disclosure can be implemented. Figure 1 As shown, the example environment 100 includes a computing device 110 and a client 120 .

[0031] In some embodiments, computing device 110 may interact with client 120. For example, computing device 110 may receive input messages from client 120 and output feedback messages to client 120. In some embodiments, the input messages from client 120 may be design layout data. Computing device 110 may perform corresponding mathematical operations on the design layout data and output the corresponding operation results to client 120.

[0032] In some embodiments, computing device 110 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0033] It should be understood that the structure and functionality of the example environment 100 is described for illustrative purposes only and is not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. This environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0034] In order to explain the principle of the present disclosure more clearly, the following will refer to Figure 2 Let's describe it in more detail.

[0035] Figure 2 A flow chart of a multi-patterning method 200 according to some embodiments of the present disclosure is shown.

[0036] At block 202 , a first mask is generated based on a design layout, wherein leads of a metal layer in the design layout are arranged according to minimum design rules.

[0037] In advanced processes, to ensure single exposure and obtain the minimum pitch (corresponding to line width + spacing, which is a representation of graphic density), metal lines in the same layer are designed in the same direction and optimized with the light source to implement the photolithography process.

[0038] In some embodiments, the positions of the translucent and non-translucent portions of the first mask can be determined based on the development method, so that the photolithographic grooves generated after exposure correspond to the leads. As is known in the industry, development methods generally include positive tone development (PTD) and negative tone development (NTD). In negative tone development, the exposed photoresist remains, while the unexposed photoresist is dissolved by the developer. In positive tone development, the opposite is true. Therefore, different development methods can be used to make the translucent or non-translucent portions correspond to the leads in the design layout.

[0039] In the design layout, you can set predefined rules when routing wires. In some embodiments, the wires are arranged according to the corresponding minimum design rule. That is, the spacing between wires is the minimum design rule size, which is the size of a grid point. In some embodiments, the minimum design rule allows the spacing between wires to be an odd number of grid points.

[0040] In some embodiments, the leads of the metal layer in the design layout extend along a first direction, and the first mask is alternately provided with light-transmitting portions and light-non-transmitting portions extending along the first direction and penetrating the first mask.

[0041] The following combination Figure 3A and 3B FIG3A shows a schematic diagram of a layout 310 of metal layers arranged according to minimum design rules according to some embodiments of the present disclosure. Figure 3A The metal layer is shown in FIG, wherein the metal lead (referred to as lead) 302 extends in the longitudinal direction (which may be referred to as the first direction). This layout may be referred to as the metal mask Y design layout. In this figure, the size of each grid point is This size is the minimum design rule size. Of course, different processes correspond to different minimum design rule sizes. In addition, Figure 3A As can be seen, the spacing between the two leads on the left and the two leads on the right is three grid points. As mentioned earlier, this also meets the minimum design rule. However, it should be noted that, as is known in the industry, the spacing here cannot be an even number of grid points; otherwise, it will not meet the minimum design rule.

[0042] Figure 3B Another schematic diagram of a layout 320 of metal layers arranged according to minimum design rules according to other embodiments of the present disclosure is shown. Figure 3B The metal layer is shown in FIG, wherein the metal lead 302 extends in the horizontal direction (which may be referred to as the second direction). This layout may be referred to as the metal mask X design layout. The lead layout is similar to the metal mask X design layout except that it extends in the horizontal direction. Figure 3A The metal layers can be X and Y alternating, so Figure 3A and Figure 3B For example, if necessary, the leads can be placed off-grid in the Y direction of the Y design (or the X direction of the X design). Here, the X direction of the Y design (or the Y direction of the X design) must be controlled to ensure good resolution.

[0043] See below Figure 4A and Figure 4B Provide a description. Figure 4A The corresponding embodiment of the present disclosure is shown. Figure 3A Schematic diagram of a first main pattern mask 410 for a layout of a metal layer. Figure 4B The corresponding embodiments according to other embodiments of the present disclosure are shown. Figure 3B Schematic diagram of the second main pattern mask 420 of the metal layer layout.

[0044] like Figure 4A As shown, the first main pattern mask 410 includes a plurality of stripes extending longitudinally (in the first direction) and arranged alternately. These stripes run through the entire first main pattern mask 410. In some embodiments, the white stripes 402 are opaque stripes and may be referred to as non-transparent portions, while the dark stripes 404 are translucent stripes and may be referred to as transparent portions.

[0045] In some embodiments, as Figure 4B As shown, the second main pattern mask 420 may have a pattern of the same shape and size as the first main pattern mask 410. The difference is that the stripes of the two extend in a vertical direction, that is, the stripes of the second main pattern mask 420 extend in the horizontal direction (the second direction).

[0046] In some embodiments, the light-transmitting portions and the non-light-transmitting portions of the first main pattern mask 410 and the second main pattern mask 420 are rectangular shapes with the same size, which respectively correspond to the leads and the spaces between the leads in the design layout.

[0047] In order to ensure that the Figure 4A While achieving excellent resolution in the horizontal direction (in the lateral direction) will significantly optimize the light source, the actual resolution in the Y direction will be significantly reduced, resulting in poor performance at the line ends. Therefore, by setting the stripes to run through the entire mask layout, a longer line end is left, allowing the subsequent cut mask to remove the excess. This results in the line ends appearing as right angles, achieving excellent performance. Simply put, the benefit of a through-the-main pattern mask is to push these poorly-resolution line end patterns as far as possible, making them easier to handle with the subsequent cut mask.

[0048] Figure 4A as well as Figure 4B The graphics in the process do not require optical proximity correction (OPC) because the graphics are particularly simple. Therefore, the largest process window can be obtained during lithography. In addition, since no auxiliary exposure graphics are required, the cost of the mask is also low. During subsequent revisions, the mask does not need to be changed.

[0049] It should be understood that the positions of the light-transmitting and non-light-transmitting portions in the mask can be determined based on the development method so that the photolithographic grooves generated after exposure correspond to the leads. Figure 4A and Figure 4B The positions of the light-transmitting and non-light-transmitting portions in the mask are set based on the negative development technology. If the positive development technology is changed to the positive development technology, the positions of the light-transmitting and non-light-transmitting portions need to be exchanged.

[0050] At block 204 , a second mask is generated based on the design layout, wherein the second mask includes an extended area generated by extending each lead by a first predetermined distance, and the extended area includes a continuous area to cover the leads in the corresponding area in the design layout.

[0051] In some embodiments, the second mask includes an extended region generated by extending each lead line by a first predetermined distance along a second direction perpendicular to the first direction.

[0052] In some embodiments, generating the second mask based on the design layout may include performing a first logic operation on a pattern in the design layout to extend the width of the leads, thereby forming the extended region. Specifically, the width of the leads is extended so that the leads are connected as a whole without gaps, i.e., forming a continuous region.

[0053] In some embodiments, performing a first logical operation on a graphic in a design layout to expand the width of a lead may include: performing a size expansion operation on the design layout in a second direction so that the width of each lead is expanded by a predetermined size to form an initial expansion area; and performing an inversion operation on the initial expansion area to generate an expansion area.

[0054] In some embodiments, the predetermined size ranges from a size greater than or equal to 0.5 grid points and a size less than 1.5 grid points, where the size of a grid point is equal to the size of a minimum design rule.

[0055] In some embodiments, the range of the predetermined size may be: 0.5 Grid <= predetermined size value < 1.5 Grid. Subsequent logical operations may be adjusted accordingly.

[0056] See below Figure 5A and Figure 5B Provide a description. Figure 5AAccording to some embodiments of the present disclosure, Figure 3A Schematic diagram of the initial cutting mask generated by the layout of the metal layer.

[0057] like Figure 5A As shown, the first initial cutting mask layout (or initial extended layout) 510 is generated by performing a first logic operation on the graphics in the design layout to extend the width of the lead. Specifically, the processing can be performed using the following logic operation formula: ; Here, Grid is the grid size. As mentioned above, in some embodiments, the Grid size may be 38 nm, which may vary according to different processes.

[0058] As is known in the industry, X Not A means removing all parts of the X pattern that are covered by the A pattern. Not A means inverting the A pattern, i.e., cutting out the A pattern from a complete pattern.

[0059] The above logic operation has two steps. Take the first logic operation as an example: the first step is X_Size_up(Design_Pattern,Grid), which is to enlarge the design pattern in the X direction to form A. Then the second step is Not A, which is to cut off this A pattern from the entire chip area (the entire chip area is dark at this time), leaving Figure 5A The dark portion in the image is the light-transmitting mask portion 502. Figure 5A The graphics in the image are initially dark in color, i.e., transparent in appearance. (X_Size_up(Design_Pattern,Grid) refers to Figure 5A as well as Figure 5B It should be understood that the embodiments of the present disclosure are not limited thereto, but can be changed accordingly according to actual needs.

[0060] Through the above logical processing, we can get Figure 5A The dark portion represents the transparent mask portion 502, the white portion represents the opaque mask portion 504 (which can be called the initial expansion area), and the spacer portion 506 is located between the two white portions. The size of the spacer portion 506 is usually required to be larger than the minimum design rule size to achieve the corresponding analytical processing. The initial expansion area is negated to obtain the expansion area. That is, the initial expansion area is cut off. Figure 5A The area cut out from the graphic becomes an opaque area, which can be called an extended area.

[0061] It's important to note that the actual mask conditions aren't considered in design, but rather defined by relevant tone information. Therefore, when performing a Not action, specifically in the design layout, the content on one layer (here, the dark portion) is removed based on the pattern on another layer. During mask manufacturing, however, the basic operation is to remove the opaque portion. Therefore, the notion of "removing" actually refers to cutting away the dark (transparent) portion of the mask. This is actually from the perspective of logical operations in the design layout, which is different from mask manufacturing.

[0062] Figure 5B Shows some other embodiments of the present disclosure based on Figure 3B Schematic diagram of the second initial cutting mask layout 520 generated by the layout of the metal layer. Figure 5A The various parts in the embodiment have the same function and will not be described in detail here.

[0063] In short, through the above processing, we finally get Figure 5A and Figure 5B Graphics in .

[0064] In addition, it should be noted that if Figure 3A The spacing between each lead in is the size of a grid point, so they can be processed together. That is, Figure 5A The spacer 506 in will not exist. In other words, Figure 5A The blank areas in the image will be formed into one, or the whole will become a continuous area.

[0065] In some embodiments, in order to ensure that all parts of the formed second initial cutting mask layout 520 can be well resolved, for example, especially the width of the aforementioned spacing portion 506 is wide enough to achieve good resolution, a second logical operation can be performed on the extended area to adjust the position of the edge of the extended area along the second direction.

[0066] In some embodiments, performing the second logical operation on the expansion area may include: performing a size shift operation on the expansion area along a second direction so that an edge of the expansion area moves a second predetermined distance, wherein the second predetermined distance is smaller than the first predetermined distance.

[0067] In some embodiments, the second distance may be determined based on process parameters. In the case where the process parameters are not perfect, the second distance may be half the size of the minimum design rule.

[0068] In some embodiments, after the edge of the extended region moves a second predetermined distance, a spacing between the leads in the first region and the leads in the second region in the metal layer is greater than or equal to twice a size of a minimum design rule.

[0069] See below Figure 6A and Figure 6B Provide a description. Figure 6A According to some embodiments of the present disclosure, Figure 5A A schematic diagram of a first final cutting mask 610 generated by an initial cutting mask; Figure 6B According to some embodiments of the present disclosure, Figure 5B Schematic diagram of the second final cutting mask 620 generated by the initial cutting mask. Specifically, the size offset processing can be performed using the following logical operation formula: ; Bias is a process parameter determined by reference to the corner rounding used in a specific process. Bias primarily compensates for certain effects (such as corner rounding, which can vary significantly between processes). As mentioned earlier, when process information is incomplete, half the grid value can be used: bias = Grid / 2, which is 19nm in this case. Bias can be positive or negative. A positive bias is equivalent to expansion, while a negative bias is contraction. This creates a more optimized mask layout than the initial cut mask layout described above, enabling better resolution.

[0070] By comparison Figure 6A and Figure 5A It can be seen that Figure 6A The width of the narrow rectangle 608 in is the offset distance (bias). Similarly, by comparing Figure 6B and Figure 5B It can be seen that Figure 6B The width of the narrow rectangle 608 is the offset distance. The narrow rectangle 608 and the light-transmitting mask portion indicated by the reference numeral 602 are the same light-transmitting portion. They are represented by different colors in the figure only to clearly show the offset distance.

[0071] For rounded corners, the middle line ( Figure 5A and Figure 5B The spacer portion 506 in the Figure 6A and Figure 6B The thinner the line (the portion between the blank area 604) the better. However, for the middle line, the thicker the better, as it is easier to make. Therefore, a compromise needs to be made and the bias value should be selected appropriately.

[0072] The initial cut mask layout can be understood as the design requirement for cutting metal lines, while the final cut layout is the adjustment to the layout target after combining the process. Their purpose is to remove the non-essential metal lines (full rows of strips) defined by the previous process.

[0073] In the above embodiment, the light intensity distribution effect on the wafer that can only be achieved through complex logical operations in traditional solutions can be achieved through simple logical operations.

[0074] At block 206 , the first mask and the second mask are exposed to light respectively to form a light intensity distribution for generating photolithographic grooves corresponding to the leads in the photoresist.

[0075] In some embodiments, exposing the first mask and the second mask separately to form a light intensity distribution in the photoresist for generating a photolithographic groove corresponding to the lead includes: applying a negative tone development (NTD) technology to expose the first mask and the second mask separately, wherein there is no etching process between exposing the first mask and exposing the second mask, that is, performing two consecutive exposures.

[0076] In some embodiments, a negative development technique can be used to expose the first mask (first main pattern mask 410 or second main pattern mask 420) and the second mask (first initial cut mask pattern 510 or second initial cut mask pattern 520) twice in succession, without etching in between. This is equivalent to litho-lithography (LLE). In the NTD process, the photoresist material is strengthened (polymerized or cross-linked) by light, and the developer only dissolves the areas not exposed to light. In other words, the exposed areas are retained, while the unexposed areas are dissolved.

[0077] In some embodiments, the characteristics of NTD are utilized to expose the first mask and the second mask to obtain the desired pattern. In some embodiments, special design techniques can be used to coordinate the number of exposures to establish a more specific pattern structure, but generally, two exposures are sufficient. In specific operations, negative development technology is used, and two exposures are performed consecutively (e.g., Figure 4A or Figure 4B The mask shown + Figure 5A or Figure 5B or Figure 6A or Figure 6B The cutting mask shown in the figure) is not developed and etched in the middle) and then developed uniformly, and finally the Figure 9A and Figure 9B It should be understood that, as is known in the industry, a preceding etching process is required to transfer the photolithographically defined grooves to the film.

[0078] See below Figure 7 and Figure 8 . Figure 7 The use of some embodiments of the present disclosure is shown Figure 4AFIG. 7 is a schematic diagram of a first light intensity distribution diagram 700 obtained after the main pattern mask is exposed. Figure 8 The present invention is shown in some embodiments of the present invention. Figure 4A The main pattern mask shown is exposed with Figure 6B FIG. 8 is a schematic diagram of a second light intensity distribution diagram 800 obtained by exposing the final cut mask.

[0079] like Figure 7 As shown in FIG8 , the dark portion 704 represents the portion that is illuminated by light after exposure, i.e., there is light intensity distribution. The white portion 702 represents the portion that is not illuminated by light after the first exposure, i.e., there is no light intensity distribution. As shown in FIG8 , the portion indicated by 804 represents the portion that is illuminated by light after the second exposure, i.e., there is light intensity distribution; the white portion represents the portion that is not illuminated by light after the second exposure, i.e., there is no light intensity distribution. Figure 8 The white areas defined in the figure correspond to the leads 302 in the design layout. Subsequent development and other processes produce photolithographic grooves. In a negative development process, the exposed areas (or areas with light intensity distribution) remain, while areas without light intensity distribution form photolithographic grooves. Subsequent etching and metal filling form metal lines.

[0080] In the above example of the present invention, by setting Figure 4A or Figure 5A In the master pattern mask, all transparent and non-transparent areas are uniform. Therefore, during analysis, only one pattern can be processed, allowing adjustments to the corresponding light source, such as using the appropriate extreme lighting method to achieve excellent results. This further enables the miniaturization of the layout.

[0081] In some embodiments of the present invention, the main pattern mask ensures good resolution in a certain direction, while the cutting mask cuts off unnecessary portions of the mask to retain good resolution at predetermined locations.

[0082] See below Figure 9A and Figure 9B Provide a description. Figure 9A The final generated corresponding to some embodiments of the present disclosure is shown. Figure 3A A schematic diagram of a metal layer layout of a metal layer; Figure 9B The final generated corresponding to some embodiments of the present disclosure is shown. Figure 3A A schematic diagram of the metal layer layout of the metal layer.

[0083] Figure 9A and Figure 9B The dark part is the photolithography groove 902, and the white part is the photoresist (photoresist). Figure 3A and 3BThe lead 302 in FIG. Then, subsequent steps such as etching and metal deposition can be performed to form a metal lead layer.

[0084] In the above embodiment, the NTD process is used as an example for description, but the embodiments of the present disclosure are not limited thereto. For example, a positive development technology is used, and corresponding adjustments are made to the first mask and the second mask at the same time.

[0085] Some embodiments of the present disclosure provide a novel multi-patterning method, which is particularly suitable for application in back-end metal wiring layers.

[0086] Some embodiments of this disclosure enable a wider process window, higher overlay accuracy, and excellent line segment performance. Specifically, by only requiring a single pattern, a wider process window and excellent line-end performance (consistency, etc.) can be achieved; fewer correction resources are required; and when necessary, the resolution limit of 76nm pitch can be exceeded (with only a single pattern, resolution of 72nm pitch or even smaller can be achieved); thus comprehensively improving the manufacturability of the final design.

[0087] It should be understood that the embodiments shown in the drawings are only for schematically illustrating some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0088] The present disclosure also discloses an electronic device in an embodiment. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions including: generating a first mask based on a design layout, wherein the leads of the metal layer in the design layout are arranged according to minimum design rules; generating a second mask based on the design layout, wherein the second mask includes an extended area generated by extending each lead by a first predetermined distance, the extended area including a continuous area to cover the leads in the corresponding area in the design layout; and exposing the first mask and the second mask respectively to form a light intensity distribution for generating a photolithographic groove corresponding to the lead in the photoresist.

[0089] An embodiment of the present disclosure further discloses a computer-readable storage medium having machine-executable instructions stored thereon. When the machine-executable instructions are executed by a processor, the multiple-graphics method according to the embodiment of the present disclosure is implemented.

[0090] Figure 10Schematic block diagrams of electronic devices according to some exemplary embodiments of the present disclosure are shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0091] like Figure 10 As shown, device 1000 includes a CPU 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. Various programs and data required for the operation of device 1000 may also be stored in RAM 1003. CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0092] Multiple components in device 1000 are connected to I / O interface 1005, including: an input unit 1006, such as a keyboard, mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a magnetic disk, optical disk, etc.; and a communication unit 1009, such as a network card, modem, wireless communication transceiver, etc. The communication unit 1009 allows device 1000 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0093] The various processes and processing described above, such as method 200, can be executed by CPU 1001. For example, in some embodiments, method 200 can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM 1002 and / or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by CPU 1001, one or more steps in method 200 described above can be performed.

[0094] The solutions according to the embodiments of the present disclosure may be methods, devices, systems, and / or computer program products. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network.

[0095] Various embodiments of the present disclosure have been described above. The above descriptions are exemplary and are only optional embodiments of the present disclosure. They are not exhaustive and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features disclosed herein, whether explicitly or implicitly or in any generalization thereof, regardless of whether it relates to the same scheme in any claim currently claimed. It should be understood that new claims may be formulated to these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0096] The terminology used herein is selected to best explain the principles of the various embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the various embodiments disclosed herein. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure are intended to be included within the scope of protection of this disclosure.

Claims

1. A multi-patterning method comprising: generating a first mask based on a design layout, wherein the leads of the metal layer in the design layout are arranged according to minimum design rules; generating a second mask based on the design layout, wherein the second mask includes an extended area generated by extending each lead by a first predetermined distance, and the extended area includes a continuous area to cover the leads in the corresponding area of ​​the design layout; and The first mask and the second mask are respectively exposed to light to form a light intensity distribution for generating a photolithography groove corresponding to the lead in the photoresist.

2. The method according to claim 1, wherein the leads of the metal layer in the design layout extend along a first direction, and the first mask is alternately provided with light-transmitting portions and light-impermeable portions extending along the first direction and passing through the first mask. 3 . The method according to claim 2 , wherein the second mask includes an expansion area generated by expanding each lead line by a first predetermined distance along a second direction perpendicular to the first direction.

4. The method according to claim 2, wherein generating the first mask based on the design layout comprises: The positions of the light-transmitting portion and the non-light-transmitting portion in the first mask are determined based on a development method, so that the photolithography grooves generated after exposure correspond to the leads.

5. The method according to claim 3, wherein generating a second mask based on the design layout comprises: A first logic operation is performed on the pattern in the design layout to expand the width of the lead, thereby forming the expansion area.

6. The method according to claim 5, wherein performing a first logic operation on the pattern in the design layout to extend the width of the lead comprises: Performing a size expansion operation in the second direction on the design layout so that the width of each of the leads is expanded by a predetermined size to form an initial expansion area; as well as A negation operation is performed on the initial extended area to generate the extended area.

7. The method according to claim 6, wherein: The predetermined size ranges from a size greater than or equal to 0.5 grid points to a size less than 1.5 grid points, wherein the size of the grid points is equal to a size of the minimum design rule.

8. The method according to claim 1 , wherein respectively exposing the first mask and the second mask to form light intensity distributions in the photoresist for generating photolithographic grooves corresponding to the leads comprises: The first mask and the second mask are exposed respectively using a negative development technique, wherein there is no etching process between the exposure of the first mask and the exposure of the second mask.

9. The method according to claim 3, further comprising: A second logical operation is performed on the extended area to adjust a position of an edge of the extended area along the second direction.

10. The method according to claim 3, wherein performing a second logical operation on the extended area comprises: A size shift operation is performed on the extended area along the second direction, so that the edge of the extended area moves by a second predetermined distance, wherein the second predetermined distance is smaller than the first predetermined distance.

11. The method according to claim 10, wherein: The second distance is half the size of the minimum design rule; or The second distance is determined based on process parameters. 12 . The method according to claim 10 , wherein after the edge of the extended area moves a second predetermined distance, a spacing between the leads in the first area and the leads in the second area in the metal layer is greater than or equal to twice a size of a minimum design rule.

13. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions comprising: generating a first mask based on a design layout, wherein the leads of the metal layer in the design layout are arranged according to minimum design rules; generating a second mask based on the design layout, wherein the second mask includes an extended area generated by extending each of the leads by a first predetermined distance, and the extended area includes a continuous area so as to cover the leads in the corresponding area of ​​the design layout; and The first mask and the second mask are respectively exposed to light to form a light intensity distribution for generating a photolithography groove corresponding to the lead in the photoresist.

14. A computer-readable storage medium having machine-executable instructions stored thereon, wherein when the machine-executable instructions are executed by a processor, the processor is caused to implement the method according to any one of claims 1 to 10.

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