Phase synchronization circuit, expanded phase-locked loop circuit and delay phase-locked loop circuit

Abstract

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a phase synchronization circuit and an expanded phase-locked loop circuit and a delay phase-locked loop circuit. Background Art

[0002] Phase synchronization circuits, such as phase-locked loop (PLL) circuits and delay-locked loop (DLL) circuits, synchronize the output signal phase with a reference clock through a feedback mechanism.

[0003] Phase synchronization circuits typically require loop filters (LPFs) with large capacitance values, which consume a large chip area. Using low-voltage devices such as MOS (metal oxide semiconductor) capacitors and varactors to reduce the LPF chip area can increase leakage current and reduce control voltage, leading to larger phase errors in the output signal.

[0004] One solution is to add a leakage current compensation circuit to prevent voltage drops. However, leakage current compensation circuits are typically implemented using analog structures such as operational amplifiers or voltage comparators. These structures themselves introduce errors that, combined with the errors in the phase synchronization circuit itself, further affect the output signal. Furthermore, leakage current compensation circuits consume additional chip area, making this solution less practical. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a phase synchronization circuit and an extended phase-locked loop circuit and a delay-locked loop circuit.

[0006] A first aspect of the present invention provides a phase synchronization circuit, comprising a clock comparison unit, a bias circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter, and a clock output unit; the clock comparison unit is connected to the clock output unit, the charge pump circuit, and the time / analog conversion circuit; the bias circuit is connected to the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected to the compensation charge pump circuit; and the loop filter is connected to the charge pump circuit, the compensation charge pump circuit, and the clock output unit; The clock comparison unit is configured to compare a reference clock with a feedback clock output from the clock output unit to form a comparison result, and output an up-pulse signal and a down-pulse signal corresponding to the comparison result to the charge pump circuit and the time / analog conversion circuit; The bias circuit is used to output a first bias current to the charge pump circuit and output a second bias current to the time / analog conversion circuit; The charge pump circuit is configured to generate a first charging current and a first discharging current according to the uplink pulse signal and the downlink pulse signal, and output the first charging current or the first discharging current as a first compensation current to the loop filter; The time / analog conversion circuit is used to generate a compensation analog voltage according to the up-pulse signal and the down-pulse signal, and output the compensation analog voltage to the compensation charge pump circuit; the compensation analog voltage includes a positive-side compensation analog voltage and a negative-side compensation analog voltage; The compensation charge pump circuit is configured to generate a second charging current and a second discharging current according to the positive-side compensation analog voltage and the negative-side compensation analog voltage, and output a current difference between the second charging current and the second discharging current as a second compensation current to the loop filter; The loop filter is used to output a control voltage to the clock output unit; the control voltage includes a control voltage of the first compensation current and a control voltage of the second compensation current; The clock output unit is configured to output an output clock based on the control voltage, and output a feedback clock based on the output clock to the clock comparison unit.

[0007] Furthermore, the time / analog conversion circuit includes a bias compensation charge injection circuit and a current control capacitor; the bias compensation charge injection circuit is used to receive the second bias current, the up pulse signal and the down pulse signal; the bias compensation charge injection circuit generates compensation charge through the second bias current; when the up pulse signal or the down pulse signal is at a high level, the compensation charge is injected into the current control capacitor, and the positive side compensation analog voltage and the negative side compensation analog voltage are changed until the pulse width of the up pulse signal and the down pulse signal is reduced to the dead zone suppression level.

[0008] Furthermore, the time / analog conversion circuit includes a current mirror circuit, an internal logic circuit, and a charge sharing circuit; the current mirror circuit is composed of a plurality of NMOS transistors and PMOS transistors and is configured as a current mirror structure; the charge sharing circuit includes a plurality of switches and a plurality of capacitors; The current mirror circuit is configured to generate a first positive bias voltage and a second positive bias voltage, a first negative bias voltage and a second negative bias voltage according to the second bias current; The internal logic circuit is used to receive the uplink pulse signal and the downlink pulse signal, and generate an uplink positive phase pulse signal, an uplink negative phase pulse signal, a downlink positive phase pulse signal and a downlink negative phase pulse signal respectively; The charge sharing circuit includes a bias loop; the bias loop is used to receive the first positive side bias voltage and the second positive side bias voltage, the first negative side bias voltage and the second negative side bias voltage, and share charge with the uplink positive phase pulse signal, the uplink negative phase pulse signal, the downlink positive phase pulse signal and the downlink negative phase pulse signal to obtain a positive side compensation analog voltage and a negative side compensation analog voltage respectively.

[0009] Furthermore, the compensation charge pump circuit includes an output PMOS transistor and an output NMOS transistor; the compensation charge pump circuit is connected to a bias loop so that the output PMOS transistor outputs the second charging current based on the positive side compensation analog voltage; and the output NMOS transistor outputs the second discharging current based on the negative side compensation analog voltage.

[0010] Furthermore, the loop filter includes a plurality of capacitors; the first charging current or the first discharging current, and the second compensation current are charged and discharged by the capacitors to obtain a control voltage which is output to the clock output unit.

[0011] Another aspect of the present invention discloses a phase-locked loop circuit, comprising the above-mentioned phase synchronization circuit; wherein the clock comparison unit comprises a phase-frequency comparator; the phase-frequency comparator is configured to compare the phase difference and frequency difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference and frequency difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled oscillator and a frequency divider, wherein the voltage-controlled oscillator is used to output an oscillation clock having an oscillation frequency corresponding to the control voltage as the output clock; the frequency divider is used to output the clock obtained by dividing the output clock as the feedback clock to the phase frequency comparator.

[0012] Another aspect of the present invention discloses a delay-locked loop circuit, comprising the above-mentioned phase synchronization circuit; wherein the clock comparison unit comprises a phase comparator; the phase comparator is used to compare the phase difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled delay line; the voltage-controlled delay line is composed of a multi-stage delay buffer; the voltage-controlled delay line is used to output a clock delayed from the reference clock as the output clock based on the control voltage, and output the output clock as the feedback clock to the phase comparator.

[0013] In another aspect, the present invention discloses a delay-locked loop circuit, comprising the above-mentioned phase synchronization circuit; wherein the clock comparison unit comprises a phase comparator; the phase comparator is configured to compare the phase difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled delay line and a lock detection circuit; wherein the voltage-controlled delay line is composed of a multi-stage delay buffer; the voltage-controlled delay line is used to output a clock delayed from the reference clock as the output clock based on the control voltage, and output the output clock as the feedback clock to the phase comparator; the lock detection circuit is used to detect whether the output clock output by the voltage-controlled delay line is locked; when it is detected that the output clock is locked, a lock detection signal is sent to the time / analog conversion circuit.

[0014] Furthermore, the time / analog conversion circuit specifically includes a current mirror circuit, an internal logic circuit, and a charge sharing circuit; the current mirror circuit is composed of a plurality of NMOS transistors and PMOS transistors and is configured as a current mirror structure; the charge sharing circuit includes a plurality of switches and a plurality of capacitors; The current mirror circuit is used to generate a first positive bias voltage and a second positive bias voltage, a first negative bias voltage and a second negative bias voltage, a positive standby bias voltage and a negative standby bias voltage according to the second bias current; The internal logic circuit is used to receive the uplink pulse signal and the downlink pulse signal, and generate an uplink positive phase pulse signal, an uplink negative phase pulse signal, a downlink positive phase pulse signal and a downlink negative phase pulse signal respectively; The internal logic circuit is further configured to receive the lock detection signal, generate a positive lock logic signal or a negative lock logic signal, and send the signal to the charge sharing circuit and the compensation charge pump circuit; The charge sharing circuit includes a bias circuit and a standby bias circuit; the bias circuit is used to receive the first positive side bias voltage and the second positive side bias voltage, the first negative side bias voltage and the second negative side bias voltage, and perform charge sharing with the uplink positive phase pulse signal, the uplink negative phase pulse signal, the downlink positive phase pulse signal and the downlink negative phase pulse signal to obtain a positive side compensation analog voltage and a negative side compensation analog voltage respectively; the standby bias circuit is used to receive the positive side standby bias voltage and the negative side standby bias voltage; The charge sharing circuit controls the switch on the backup bias loop to be closed when receiving the positive lock logic signal; and controls the switch on the backup bias loop to be opened when receiving the negative lock logic signal.

[0015] Furthermore, the compensation charge pump circuit includes an output PMOS transistor and an output NMOS transistor; when receiving the positive locking logic signal, the compensation charge pump circuit is connected to the standby bias loop, and sets the gate voltages of the output PMOS transistor and the output NMOS transistor to the positive side standby bias voltage and the negative side standby bias voltage, respectively; when receiving the negative locking logic signal, the compensation charge pump circuit is connected to the bias loop, so that the output PMOS transistor outputs the second charging current based on the positive side compensation analog voltage; and the output NMOS transistor outputs the second discharging current based on the negative side compensation analog voltage.

[0016] The embodiments of the present invention have the following beneficial effects: the phase synchronization circuit and its extended structure disclosed in the present invention can directly convert time information into voltage through the design of a time / analog conversion circuit and use it for leakage current compensation. Therefore, there is no need for voltage-based comparison operations and related circuit structures, and no need for integrated operational amplifiers, voltage comparators, and other analog circuits that occupy chip area. In some designs, time information can also be converted into time / analog voltage so that the maximum and minimum values ​​of the compensation current can be limited by pre-set limiter values, thereby achieving stable compensation action. In addition, because the phase synchronization circuit of the present invention does not contain structures such as operational amplifiers or voltage comparators, there will be no error overlap caused by the analog circuit itself. Therefore, it is possible to suppress the increase in the chip area of ​​the compensation circuit and reduce the phase error of the output clock.

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 It is a diagram showing the overall configuration of the DLL circuit according to the first and third embodiments of the present invention.

[0020] Figure 2 FIG. 1 is a diagram showing a schematic configuration of a time / analog conversion circuit according to a first embodiment of the present invention.

[0021] Figure 3 This is a diagram showing an example of the operation timing of the time / analog conversion circuit according to the first embodiment of the present invention.

[0022] Figure 4 This is a diagram showing an example of the circuit configuration of the time / analog conversion circuit according to the first embodiment of the present invention.

[0023] Figure 5 This is a diagram showing the overall configuration of a PLL circuit according to a second embodiment of the present invention.

[0024] Figure 6 This is a diagram showing the circuit configuration of a time / analog conversion circuit according to a third embodiment of the present invention.

[0025] Figure 7 This is a diagram showing an example of operating waveforms of a charge sharing circuit in a time-to-analog conversion circuit according to a third embodiment of the present invention.

[0026] Figure 8 This is a diagram showing the switch connection state of the charge sharing circuit according to the third embodiment of the present invention.

[0027] Figure 9 This is a diagram showing the overall configuration of a DLL circuit according to a fourth embodiment of the present invention.

[0028] Figure 10 This is a diagram showing the circuit configuration of a time / analog conversion circuit according to a fourth embodiment of the present invention.

[0029] Figure 11 This is a diagram showing an example of operating waveforms of a charge sharing circuit in a time-to-analog conversion circuit according to a fourth embodiment of the present invention.

[0030] Figure 12 This is a diagram showing the switch connection state of the charge sharing circuit according to the fourth embodiment of the present invention.

[0031] Reference numerals: 100, 300 DLL circuit; 101, 301 phase comparator (PD); 102, 202, 302 charge pump circuit (CP); 103, 203, 303 loop filter (LPF); 104, 304 voltage delay control line (VCDL); 105, 205, 305 time / analog conversion circuit (TA); 106, 206, 306 compensated charge pump circuit (CPS); 107, 207, 307 bias circuit (BIAS); 110 Bias compensation charge injection circuit; 111, 311 TA internal logic circuit; 112, 312 charge sharing circuit; 200 PLL circuit; 201 Phase Frequency Comparator (PFD); 204 Voltage Controlled Oscillator (VCO); 208 crossover (NDIV); 310 lock detection circuit (DRT); R1 resistor; C1, C2, C3 capacitors; PHICLK[1], PHICLK[1], PHICLK[1], PHICLK[1], PHICLK[1], PHICLK[N] phase-divided clocks; Cp, Cps are capacitors for positive side current control; Cn, Cns are capacitors for negative side current control; MN1a, MN2a, MN3a, MN4b, MN5a, MN6c NMOS transistors; MP2a, MP3b, MP4a, MP5c, MP6a PMOS transistors; SW1p first positive side switch; SW2p second positive side switch; SW3p third positive side switch; SW4p fourth positive side switch; SW1n first negative side switch; SW2n second negative side switch; SW3n third negative side switch; SW4n fourth negative side switch; SW5p fifth positive side switch; SW5n fifth negative side switch; Cp_low first positive side bias voltage holding capacitor; Cp_high second positive side bias voltage holding capacitor; Cn_high first negative side bias voltage holding capacitor; Cn_low second negative side bias voltage holding capacitor; Vgp_low first positive side bias voltage; Vgp_high second positive side bias voltage; Vgn_low first negative side bias voltage; Vgn_high Second negative side bias voltage. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0033] The first embodiment of the present invention discloses a DLL circuit. Figure 1 The following describes a DLL circuit 100 according to the first embodiment. DLL circuit 100 is a phase-synchronized circuit comprising a phase comparator (hereinafter, PD) 101, a charge pump circuit (hereinafter, CP) 102, a loop filter (hereinafter, LPF) 103, a voltage-controlled delay line (hereinafter, VCDL) 104, a time-to-analog converter (hereinafter, TA) 105, a compensation charge pump circuit (hereinafter, CPS) 106, and a bias circuit (hereinafter, BIAS) 107.

[0034] PD101 compares the phase difference between the external reference clock (REFCLK) and the feedback clock (FDCLK) output from VCDL104, and outputs an up pulse signal (UP) and a down pulse signal (DN) corresponding to the phase difference.

[0035] CP102 includes a PMOS transistor and an NMOS transistor. During the effective pulse width of the up pulse signal (UP) and the down pulse signal (DN), CP102 outputs the source current (first charging current) based on the PMOS transistor to LPF103, or outputs the drain current (first discharging current) based on the NMOS transistor to LPF103.

[0036] The LPF 103 is composed of a capacitor, and outputs a control voltage (VCNT) to the VCDL 104 by charging and discharging electric charges according to the currents output by the charge pump circuit 102 and the compensation charge pump circuit 106 .

[0037] VCDL104 consists of an N-stage delay buffer (N is a positive integer). It outputs a delayed clock (DLLCLK) from the reference clock (REFCLK) based on the control voltage (VCNT). A higher control voltage (VCNT) reduces the delay, while a lower control voltage (VCNT) increases the delay. The delayed clock (DLLCLK) is fed back to PD101 as the feedback clock (FDCLK).

[0038] BIAS 107 outputs a first bias current (Ib_cp) to CP ( 102 ) and outputs a second bias current (Ib_cps) to TA 105 .

[0039] TA105 receives the up pulse signal (UP) and the down pulse signal (DN) from PD101, and outputs the bias voltage (Vgp, Vgn) as the compensation analog voltage to CPS106. The positive side compensation analog voltage (Vgp) and the negative side compensation analog voltage (Vgn) are obtained by causing the voltage difference corresponding to the effective time of the pulse or the counting information to change in potential.

[0040] Under no-bias conditions, the CPS 106 stably outputs a compensation current. More specifically, the CPS 106 outputs a source current (second charging current) to the LPF 103 via a PMOS transistor receiving the Vgp voltage, and a drain current (second discharging current) to the LPF 103 via an NMOS transistor receiving the Vgn voltage.

[0041] The TA105 generates bias voltages (Vgp, Vgn). To save chip area, it is desirable to avoid using voltage comparison units, such as operational amplifiers and voltage comparators, which occupy large chip areas. Instead, a simple analog circuit is used.

[0042] For this purpose, refer to Figure 2 The schematic structure of the TA 105 in the first embodiment of the present invention is described below. The TA 105 in the first embodiment of the present invention includes a bias compensation charge injection circuit 110, which receives a bias current (Ib_cps), an uplink pulse signal (UP), and a downlink pulse signal (DN), and outputs compensation charge to the current control capacitors (Cp, Cn).

[0043] Reference Figure 3This section describes one implementation of the TA105 operating timing. PD101 generates an uplink pulse signal (UP) and a downlink pulse signal (DN) based on the phase difference between the reference clock (REFCLK) and the feedback clock (FDCLK). These two pulse signals (UP, DN) are simultaneously input to CP102 and TA105. During the active period when the bias current (Ib_cps) and the two pulse signals (UP, DN) are high, the bias compensation charge injection circuit 110 injects compensation charge, changing the positive compensation analog voltage (Vgp) or the negative compensation analog voltage (Vgn), thereby altering the gate voltages of the PMOS and NMOS transistors in CPS106.

[0044] The offset compensation charge injection circuit 110 performs the injection operation of the compensation charge until the two pulse signals (UP, DN) become the pulse width for suppressing the dead zone (in Figure 3 By compensating the charge, the gate voltages of the PMOS transistor (which serves as the source current source) and the NMOS transistor (which serves as the drain current source) repeatedly fluctuate in accordance with the Vgp and Vgn potentials until the widths of the two effective pulse signals (UP and DN) are sufficiently reduced.

[0045] Regarding the step voltage for potential fluctuation, voltage accuracy is not required, but it is necessary to ensure that the PMOS transistor and NMOS transistor are within the operating voltage range to function as current sources. Figure 3 In the example, the up pulse signal (UP) is dominant, the potential of Vgp decreases, and the potential of Vgn decreases. Therefore, the source current (Ip) increases, the drain current (In) decreases, and the current difference between the source and drain is output to LPF103 as the compensation current (Iout). Figure 3 In the example, since the control voltage (VCNT) has a leakage current component with respect to ground, the DC error component that drops to the low potential side is balanced by the charging current of the generated compensation current (ΔI[A]) and reaches a stable point, thus completing the compensation operation and ultimately compensating for the DC error component.

[0046] Reference Figure 4 , an implementation method of the circuit structure of TA105 is described. Figure 4In the circuit configuration shown, the bias voltage is maintained by current control capacitors (Cp, Cn) connected to the compensation analog voltages (Vgp, Vgn). The bias compensation charge injection circuit 110 includes a switch and a micro-current source. The switch is turned on only during the active pulse durations of the up pulse signal (UP) and the down pulse signal (DN), causing the compensation analog voltages (Vgp, Vgn) to vary slightly. Compensation is achieved by increasing or decreasing the gate voltages of the source current PMOS transistor and the drain current NMOS transistor within the CPS 106 with a micro-voltage.

[0047] However, in Figure 4 In the case of the TA105 circuit structure, design constants are required to ensure that the bias voltage (Vgp, Vgn) of CPS106 is within the operating voltage range. When the potential exceeds the operating voltage range, the PMOS transistor or NMOS transistor of CPS106 will not output current, resulting in incomplete compensation. Examples of circuit structures that can ensure the operating range will be described in the third and fourth embodiments below. It should be noted that Figure 2 The embodiment is an example for showing the necessary element circuits and functional outlines, and is not limited to the first embodiment. Figure 4 The specific circuit structure of TA105 is shown.

[0048] According to the DLL circuit 100 of the first embodiment, time information is directly converted into voltage and used for compensation information. Therefore, no voltage-based comparison operation is required, and no analog circuits such as operational amplifiers and voltage comparators that occupy chip area are required. In addition, since there is no overlap of errors inherent in analog circuits such as operational amplifiers and voltage comparators, the increase in chip area of ​​the compensation circuit can be suppressed, and phase error can be reduced.

[0049] The second embodiment of the present invention discloses a PLL circuit. Figure 5 The following describes a PLL circuit 200 according to a second embodiment. PLL circuit 200 is a phase synchronization circuit comprising a phase frequency comparator (hereinafter referred to as PFD) 201, a CP 202, an LPF 203, a voltage controlled oscillator (hereinafter referred to as VCO) 204, a TA 205, a CPS 206, a BIAS 207, and a frequency divider 208 (hereinafter referred to as NDIV).

[0050] PFD201 compares the phase and frequency differences between the externally input reference clock (REFCLK) and the feedback clock (FDCLK) divided by NDIV208. PFD201 outputs an uplink pulse signal (UP) and a downlink pulse signal (DN) corresponding to the phase and frequency differences.

[0051] The CP 202 is the same as the CP 102 in the first embodiment. The LPF 203 is the same as the LPF 103 in the first embodiment.

[0052] The VCO 204 may have a general structure including a ring oscillator composed of N stages (N is a positive integer) of inverters driven by a tail current source, for example, and outputs a clock having an oscillation frequency corresponding to the control voltage (VCNT).

[0053] The BIAS 207 is the same as the BIAS 107 of the first embodiment. The TA 205 is the same as the TA 105 of the first embodiment. The CPS 206 is the same as the CPS 106 of the first embodiment.

[0054] In particular, the structure and operation of TA205 are also similar to Figure 2 、 Figure 3 as well as Figure 4 The same situation applies to the first embodiment shown. While the DLL circuit aligns the delayed phase, the PLL circuit aligns the frequency. Therefore, when the NDIV 208 division ratio is set to N (N is a positive integer), the frequency of the locked output clock (PLLCLK) is N times the frequency of the reference clock (REFCLK). Specifically, it should be noted that the PFD 201 phase comparison period is the same as the reference clock (REFCLK). The further the rising edge of the output clock (PLLCLK) moves from the phase comparison timing (timming), the more likely the point at which phase error occurs, due to potential fluctuations caused by leakage of the control voltage (VCNT), etc., based on the same principle as the DLL circuit.

[0055] According to the PLL circuit 200 of the second embodiment, as in the first embodiment, time information is directly converted into voltage and used for compensation information. Therefore, there is no need for voltage-based comparison operations, and no analog circuits such as operational amplifiers and voltage comparators that occupy chip area are required. In addition, since there is no error overlap of the analog circuits such as operational amplifiers and voltage comparators themselves, it is possible to suppress the increase in the chip area of ​​the compensation circuit and reduce the phase error.

[0056] The third embodiment of the present invention discloses a DLL circuit. The DLL circuit 100 of the third embodiment is described below. The overall structure of the DLL circuit 100 of the third embodiment is the same as Figure 1 The circuit structure of TA105 is the same as that of the first embodiment shown, but as described later, it is different from that of the first embodiment.

[0057] Reference Figure 6, the circuit structure of TA105 of the third embodiment is described. TA105 includes: a current mirror circuit composed of multiple PMOS transistors (MP2a, MP3b, MP4a) and multiple NMOS transistors (MN1a, MN2a, MN3a, MN4b); a charge sharing circuit 112 including multiple switches (SW1p, SW2p, SW1n, SW2n, SW3p, SW4p, SW3n, SW4n) and multiple capacitors (Cp_high, CP_low, Cn_high, Cn_low, Cps, Cns); and an internal TA logic circuit 111. Among them, CPS106 includes: a source current source composed of a PMOS transistor (MPOUT) for constantly outputting a source current (charging current); and a drain current source composed of an NMOS transistor (MNOUT) for constantly outputting a drain current (discharging current). In addition, Figure 6 In the figure, for the sake of explanation, an example of the size ratio of the PMOS transistor and the NMOS transistor is marked as A and B respectively, and each branch current is marked for the sake of explanation at the upper part of the power line connected to the PMOS source and the lower part of the ground line connected to the NMOS source.

[0058] In TA105, the bias current (Ib_cps = A × Ibase, where Ibase is the reference unit current) from BIAS107 is input to NMOS transistor (MN1a). The drain and gate of NMOS transistor (MN1a) are short-circuited (hereinafter referred to as a diode connection) and current mirrored with NMOS transistor (MN2a). Because NMOS transistors (MN1a) and (MN2a) have the same transistor size (A × (W / L)), the same branch current (I = A × Ibase) flows through NMOS transistor (MN2a). Furthermore, the diode-connected NMOS transistor (MN1a) outputs a first negative bias voltage (V = Vgn_high).

[0059] The branch current of MN2a is input to a diode-connected PMOS transistor (MP2a). Furthermore, the PMOS transistor (MP2a) and the PMOS transistor (MP3b) are connected in a current mirror. Since the size ratio of MP3b to MP2a is (B / A), a branch current (I = B × Ibase) times the base current (B / A) flows through the PMOS transistor (MP3b). Furthermore, the diode-connected PMOS transistor (MP2a) outputs a second positive bias voltage (V = Vgp_high).

[0060] The branch current of MN3b is input to a diode-connected NMOS transistor (MN3a). Furthermore, the NMOS transistor (MN1a) and the PMOS transistor (MN4b) are current mirror-connected. Since the size ratio of MN4b to MN1a is (B / A), a branch current (I = B × Ibase) times the base current (B / A) flows through the NMOS transistor (MN4b). Furthermore, the diode-connected NMOS transistor (MN3a) outputs a second negative bias voltage (V = Vgn_low).

[0061] The branch current of MN4b is input to the diode-connected PMOS transistor (MP4a), which outputs a first positive-side bias voltage (V=Vgp_low).

[0062] The charge sharing circuit 112 is described below. A first positive bias voltage node (a node where V = Vgp_low) is connected to a first positive bias voltage holding capacitor (Cp_low) via a first positive switch (SW1p). A second positive bias voltage node (a node where V = Vgp_high) is connected to a second positive bias voltage holding capacitor (Cp_high) via a second positive switch (SW2p). A first negative bias voltage node (a node where V = Vgp_high) is connected to a first negative bias voltage holding capacitor (Cn_high) via a first negative switch (SW1n). A second negative bias voltage node (a node where V = Vgn_low) is connected to a second negative bias voltage holding capacitor (Cn_low) via a second negative switch (SW2n).

[0063] The positive-side current control capacitor (Cps) is connected to the first positive-side bias voltage holding capacitor (Cp_low) via a third positive-side switch (SW3p), and is connected to the second positive-side bias voltage holding capacitor (Cp_high) via a fourth positive-side switch (SW4p). The negative-side current control capacitor (Cns) is connected to the first negative-side bias voltage holding capacitor (Cn_high) via a third negative-side switch (SW3n), and is connected to the second negative-side bias voltage holding capacitor (Cn_low) via a fourth negative-side switch (SW4n).

[0064] Reference Figure 7 as well as Figure 8 , the operation of the charge sharing circuit 112 is described. Figure 8 : This is a diagram showing the switch connection state of the charge sharing circuit 112. In the figure, (UPS, DNS) are pulse signals corresponding to the input up pulse signal (UP) and down pulse signal (DN). (UPS, DNS) can maintain a narrow pulse width for dead zone suppression like (UP, DN), or can be like (UP, DN). Figure 7 In this way, the dead zone suppression pulse is not used by the TA internal logic circuit 111. In addition, signals ending with "x" in the signal name indicate inversion logic. That is, UPSx represents the inverted pulse signal of UPS, and DNSx represents the inverted pulse signal of DNS.

[0065] Figure 8 (1a) shows a situation where the UPS pulse is dominant, outputting pulses of a valid pulse width when UPS is High and being inactive when DNS is Low. In this case, the second positive bias holding capacitor (Cp_high) is connected to the positive current control capacitor (Cps) for charge sharing, and the second negative bias holding capacitor (Cp_low) is connected to the negative current control capacitor (Cns) for charge sharing. If the bias voltages maintained before this charge sharing are Vgp[n-1] and Vgn[n-1], respectively, the updated bias voltages Vgp[n] and Vgn[n] after charge sharing are calculated as follows.

[0066] (Mathematical formula 1): .

[0067] (Mathematical formula 2): .

[0068] The purpose of capacitors Cps and Cns is to maintain the bias voltage, so they do not need to be as large as those in the loop filter. Instead, they are set to a few hundred [fF] to a few [pF]. Capacitors Cp_high and Cn_low can be set to small enough values, on the order of a few tenths of a few [fF] to a few tens of [fF]. This can suppress the increase in area. Figure 8 In case (1a), the voltage of Vgp gradually approaches Vgp_high through charge sharing, and the voltage of Vgn gradually approaches Vgn_low through charge sharing. In this connection, the source current gradually increases and the drain current gradually decreases in the stable current output from CPS106. Therefore, the DC error component is compensated by the compensation current in the direction of the rising voltage slope of control voltage VCNT.

[0069] on the other hand, Figure 8(1b) shows a situation where the DNS pulse is dominant, with a pulse of a valid pulse width output when DNS is High and inactive when UPS is Low. In this case, the first positive-side bias holding capacitor (Cp_low) is connected to the positive-side current control capacitor (Cps) for charge sharing, and the first negative-side bias holding capacitor (Cp_high) is connected to the negative-side current control capacitor (Cns) for charge sharing. If the bias voltages maintained before this charge sharing are Vgp[n-1] and Vgn[n-1], respectively, the updated bias voltages Vgp[n] and Vgn[n] after charge sharing are calculated as follows.

[0070] (Mathematical formula 3): .

[0071] (Mathematical formula 4): .

[0072] exist Figure 8 In case (1b), the positive-side compensation analog voltage Vgp gradually approaches Vgp_low through charge sharing, and the negative-side compensation analog voltage Vgn gradually approaches Vgn_high through charge sharing. In this connection, the steady current output from CPS 106 gradually increases in leakage current and decreases in source current. Therefore, the compensation current compensates for the DC error component as the voltage slope of control voltage VCNT decreases.

[0073] Among them, it should be noted that due to Figure 8 Both operations (1a) and (1b) perform charge sharing. Therefore, in the stable circuit operation state after DLL lockup, the positive compensation analog voltage Vgp does not exceed the voltage range from Vgp_low[V] to Vgp_high[V], and the negative compensation analog voltage Vgn does not exceed the voltage range from Vgn_high[V] to Vgn_low[V]. For example, in (Equation 1), if Vgp[n-1] and Vgp_high are approximately equal (Vgp[n-1] ≈ Vgp_high), the updated voltage Vgp[n] ≈ Vgp_high is maintained unchanged. The same applies to (Equations 2), (Equations 3), and (Equations 4). Specifically, since Vgp and Vgn are automatically suppressed within a certain voltage range, malfunction of the source and drain currents of the subsequent CPS 106 can be prevented, resulting in stable operation of the compensation circuit.

[0074] Furthermore, the charge sharing circuit 112 within the TA 105 varies the Vgp and Vgn voltages independently of the UP and DN pulse widths. This is equivalent to counting the number of UPs or DNs with effective pulse widths relative to the capacitor in an analog circuit. Therefore, the circuit is insensitive to jitter in the UP and DN pulse widths.

[0075] exist Figure 6 In the CPS106, the source current side is formed by a PMOS transistor (MPOUT). When DNS is dominant and the positive-side compensation analog voltage Vgp is close to the first positive-side bias voltage Vgp_low, the source current output is close to (I = B × Ibase). When UPS is dominant and the positive-side compensation analog voltage Vgp is close to the second positive-side bias voltage Vgp_high, the source current output is close to (I = A × Ibase). If A is set to a value greater than B, the source current output is within the range with a maximum value of (A × Ibase) and a minimum value of (B × Ibase), a stable point.

[0076] exist Figure 6 In the CPS 106, the drain current side is formed by an NMOS transistor (MNOUT). When the DNS is dominant and the negative compensation analog voltage Vgn is close to the first negative bias voltage Vgn_high, the drain current output is close to (I = A × Ibase). When the UPS is dominant and the negative compensation analog voltage Vgp is close to the second bias voltage Vgn_low, the drain current output is close to (I = B × Ibase). If A is set to a value greater than B, the drain current output is within the range with a maximum of (A × Ibase) and a minimum of (B × Ibase), a stable point.

[0077] When DNS is dominant, the source current acts in a decreasing direction, the drain current acts in an increasing direction, and the output current is a current corresponding to the current difference between the output transistors (MPOUT, MNOUT). When UPS is dominant, the source current acts in an increasing direction, the drain current acts in a decreasing direction, and the output current is a current corresponding to the current difference between the output transistors (MPOUT, MNOUT).

[0078] In short, the CPS 106 outputs a current with a limited amplitude within the range of (±|(AB)×Ibase|) as the compensation current, and can perform a stable compensation operation without causing an operating point failure of the current source.

[0079] In the DLL circuit 100 of the third embodiment, similarly to the first embodiment, no operational amplifier or voltage comparator is required. Therefore, it is possible to suppress an increase in the chip area of ​​the compensation circuit and reduce the phase error.

[0080] Furthermore, by using a charge-sharing operation (counting in the analog circuit) using switches and capacitors, the time information of (UP, DN) is converted into a time / analog voltage. The maximum and minimum values ​​of the compensation current are limited by pre-set limiter values, achieving stable compensation operation. Furthermore, because the analog counting operation of (UP, DN) is used, phase error is insensitive to various analog errors of the added analog circuitry, further reducing phase error.

[0081] Although the DLL circuit 100 is used for explanation in the present disclosure, the same effect can be obtained in a PLL circuit. Figure 5 In the PLL circuit 200 of the second embodiment shown, the circuit of TA205 is made the same as the circuit of TA105 of the third embodiment, and the circuit of CPS206 is made the same as the circuit of CPS106 of the third embodiment, so that the same area saving and phase error reduction effects can be achieved.

[0082] The fourth embodiment of the present invention discloses a DLL circuit. Figure 9 The DLL circuit 300 of the fourth embodiment is described below. The DLL circuit 300 of the fourth embodiment is a phase synchronization circuit and includes a PD 301 , a CP 302 , an LPF 303 , a VCDL 304 , a TA 305 , a CPS 306 , a BIAS 307 , and a lock detection circuit (hereinafter referred to as DET) 310 .

[0083] The DLL circuit 300 of the fourth embodiment and Figure 1 In the DLL 100 of the first embodiment shown, the structures of the TA 305 and the CPS 306 are different from those of the TA 105 and the CPS 106 of the first embodiment, and the DLL circuit 300 is different from the first embodiment in that it further includes a lock detection circuit.

[0084] DET310 detects whether the DLLCLK output by VCDL is locked. When it is detected that the DLLCLK is locked, it outputs a lock detection signal (LOCK_DET) indicating that the lock is detected to TA305.

[0085] Reference Figure 10TA305 is described below. TA305 includes: a current mirror circuit comprising multiple PMOS transistors (MP2a, MP3b, MP4a, MP5c, MP6a) and multiple NMOS transistors (MN1a, MN2a, MN3a, MN4b, MN5a, MN6c); a charge sharing circuit 312 comprised of multiple switches (SW1p, SW2p, SW1n, SW2n, SW3p, SW4p, SW3n, SW4n) and multiple capacitors (Cp_high, CP_low, Cn_high, Cn_low, Cps, Cns); a circuit that supplies a backup bias voltage to the gate voltages (Vgp, Vgn) prior to lock detection via multiple switches (SW5p, SW5n); and internal TA logic circuit 311.

[0086] CPS 306 includes multiple switches (SW6p, SW6n) for stopping or disconnecting the compensation current before lock detection and for supplying or connecting the compensation current after lock detection; a source current source composed of a PMOS transistor (MPOUT) for flowing the source current; and a drain current source composed of an NMOS transistor (MNOUT) for flowing the drain current. The internal TA logic circuit 311 differs from the third embodiment in that it receives the lock detection signal LOCK_DET from DET 310 and outputs lock detection signals CLDET and CLDETx.

[0087] Figure 10 An example of the size ratio of the PMOS transistor and the NMOS transistor is marked for explanation, and each branch current is marked for explanation above the power line connected to the source of the PMOS and below the ground line connected to the source of the NMOS.

[0088] In TA305, the bias current (Ib_cps = A × Ibase, where Ibase is the reference unit current) from BIAS307 is input to NMOS transistor (MN1a). The drain and gate of NMOS transistor (MN1a) are diode-connected, and the current mirror is connected to NMOS transistor (MN2a). Because NMOS transistors (MN1a) and (MN2a) have the same transistor size (A × (W / L)), the same branch current (I = A × Ibase) flows through NMOS transistor (MN2a). Furthermore, the diode-connected NMOS transistor (MN1a) outputs a first negative bias voltage (V = Vgn_high).

[0089] The branch current of MN2a is input to a diode-connected PMOS transistor (MP2a). Furthermore, the PMOS transistor (MP2a) and the PMOS transistor (MP3b) are connected in a current mirror. Since the size ratio of MP3b to MP2a is (B / A), a branch current (I = B × Ibase) times the base current (B / A) flows through the PMOS transistor (MP3b). Furthermore, the diode-connected PMOS transistor (MP2a) outputs a second positive bias voltage (V = Vgp_high).

[0090] The branch current of MN3b is input to a diode-connected NMOS transistor (MN3a). Furthermore, the NMOS transistor (MN1a) and the PMOS transistor (MN4b) are current mirror-connected. Since the size ratio of MN4b to MN1a is (B / A), a branch current (I = B × Ibase) times the base current (B / A) flows through the NMOS transistor (MN4b). Furthermore, the diode-connected NMOS transistor (MN3a) outputs a second negative bias voltage (V = Vgn_low).

[0091] The branch current of MN4b is input to the diode-connected PMOS transistor (MP4a), which outputs a first positive-side bias voltage (V=Vgp_low).

[0092] A diode-connected PMOS transistor (MP2a) and a PMOS transistor (MP5c) are connected in a current mirror. Since the size ratio of MP5c to MP2a is (C / A), a branch current (I = C × Ibase) times the reference current flows through the PMOS transistor (MP5c). This branch current is input to a diode-connected NMOS transistor (MN5a), outputting a negative backup bias voltage (Vgn_mid). This differs from the third embodiment in the presence of a branch current (I = C × Ibias).

[0093] A diode-connected NMOS transistor (MN1a) and a PMOS transistor (MN6c) are connected in a current mirror. Since the size ratio of MN6c to MN1a is (C / A), a branch current (I = C × Ibase) times the reference current flows through the NMOS transistor (MN6c). This branch current is input to a diode-connected PMOS transistor (MP6a), which outputs a positive-side backup bias voltage (Vgp_mid). This differs from the third embodiment in the presence of a branch current (I = C × Ibias).

[0094] The charge sharing circuit 312 is described below. A first positive bias voltage node (a node where V = Vgp_low) is connected to a first positive bias voltage holding capacitor (Cp_low) via a first positive switch (SW1p). A second positive bias voltage node (a node where V = Vgp_high) is connected to a second positive bias voltage holding capacitor (Cp_high) via a second positive switch (SW2p). A first negative bias voltage node (a node where V = Vgp_high) is connected to a first negative bias voltage holding capacitor (Cn_high) via a first negative switch (SW1n). A second negative bias voltage node (a node where V = Vgn_low) is connected to a second negative bias voltage holding capacitor (Cn_low) via a second negative switch (SW2n).

[0095] The positive current control capacitor (Cps) is connected to the first positive bias voltage holding capacitor (Cp_low) via the third positive switch (SW3p), to the second positive bias voltage holding capacitor (Cp_high) via the fourth positive switch (SW4p), and to the positive backup bias voltage node (node ​​V = Vgp_mid) via the fifth positive switch (SW5p). The negative current control capacitor (Cns) is connected to the first negative bias voltage holding capacitor (Cn_high) via the third negative switch (SW3n), to the second negative bias voltage holding capacitor (Cn_low) via the fourth negative switch (SW4n), and to the negative backup bias voltage node (node ​​V = Vgn_mid) via the fifth negative switch (SW5n). This differs from the third embodiment in that it also includes connections to the backup bias voltage nodes (Vgp_mid, Vgn_mid).

[0096] The CPS306 includes a PMOS transistor (MPOUT) for sourcing current and an NMOS transistor (MNOUT) for draining current. A switch (SW6p) is provided between the drain of the PMOS transistor (MPOUT) and the output (Q), which is turned off before lockout and turned on after lockout. A switch (SW6n) is provided between the drain of the NMOS transistor (MNOUT) and the output (Q), which is turned off before lockout and turned on after lockout. This differs from the third embodiment in the inclusion of switches (SW6p and SW6n) that are turned off before lockout.

[0097] use Figure 11 as well as Figure 12The operation of the charge sharing circuit 312 will be described. The operation of the charge sharing circuit 312 is the same as that of the charge sharing circuit 112 in the third embodiment, but differs in that a positive-side standby bias voltage (Vgp_mid) and a negative-side standby bias voltage (Vgn_mid) are input. Since the lock detection signal (CLDETx, where the suffix "x" indicates a logical inversion) is high before lock detection, the bias voltages (Vgp, Vgn) are charged with the standby voltages (Vgp_mid, Vgn_mid), respectively. Furthermore, based on the lock detection signal (LOCK_DET), a lock detection signal (CLDET) is output. Before lock detection, the (UPS, DNS) signals are set to low, thereby disabling the charge sharing operation. After lock detection, the (UPS, DNS) signals are passed or output based on the (UP, DN) signal inputs, thereby enabling the charge sharing operation. The switches (SW6p, SW6n) configured in the CPS (306) are in the off state before lock detection and in the on state after lock detection.

[0098] Figure 12 The state in (1) represents the switch state before lock detection (CLDET = Low). Only the positive side backup voltage (Vgp_mid) is connected to the capacitor (Cps), and only the negative side backup voltage (Vgn_mid) is connected to the capacitor (Cns). The first reason for taking this action is to prevent the compensation current from flowing out of the loop filter during the pull-in action before lock detection and causing adverse effects on the lock loop. The second reason is that by setting the gate voltage of the output MOS transistor (MPOUT, MNOUT) of CPS (306) to (Vgp_mid, Vgn_mid) before outputting the compensation current, the saturation operation of the MOS transistor can be guaranteed, and the compensation current output immediately after lock detection can be stabilized.

[0099] Figure 12 The state in (2) represents the switch state after lock detection (CLDET = High, UPS = DNS = Low). Since the CPS306 is in the current output state and (UPS, DNS) are in the inactive state, the source current and drain current corresponding to the bias voltage (Vgp_mid, Vgn_mid) flow respectively. Because both currents flow with the same current value (I = CxIbase), the current difference (ΔI = 0) causes the compensation current to reliably reach zero immediately after lock begins, preventing abrupt changes in the lock loop and enabling stable loop operation.

[0100] As in the third embodiment, Figure 12The states (3a) and (3b) vary depending on whether UPS or DNS is dominant, and the bias voltage is changed by charge supply to flow the compensation current. The operation is the same as that of the third embodiment, so the description is omitted.

[0101] Similar to the third embodiment, the DLL circuit 300 of the fourth embodiment does not require an operational amplifier or voltage comparator, thereby minimizing the increase in chip area for the compensation circuit and reducing phase error. Furthermore, by utilizing the charge sharing operation of switches and capacitors (counting operation in the analog circuit), time information (UP, DN) is converted into analog voltage. The maximum and minimum values ​​of the compensation current are limited by pre-set limiter values, achieving stable compensation operation. Furthermore, since the analog counting operation of (UP, DN) is employed, the phase error is insensitive to various analog errors of the added analog circuitry, further reducing phase error.

[0102] Furthermore, before the lock detection, the compensation current is cut off by a switch, and the gate voltage of the transistor that outputs the compensation current is initially charged to the standby voltage, thereby ensuring the saturation operation of the current source. After the lock detection, the compensation current immediately becomes a zero current output. Therefore, there is no adverse effect on the DLL loop due to the flow of the compensation current, and a more stable operation can be achieved.

[0103] Those skilled in the art will appreciate that the modules in the devices in the embodiments of the present invention can be adaptively modified and installed in one or more devices different from the embodiments. Modules, units, or components in the embodiments of the present invention can be combined into a single module, unit, or component, and furthermore, they can be divided into multiple sub-modules, sub-units, or sub-components. All features disclosed in this specification (including the corresponding claims, abstract, and drawings), and all processes or units of any method or device disclosed therein, can be combined in any combination, except where at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) may be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0104] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0105] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0106] In addition, the terms "first" and "second" used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in this embodiment. Therefore, the features defined by the terms "first" and "second" in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of such features. In the description of the present invention, the word "plurality" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0107] In the embodiments of the present invention, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of further restrictions, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or apparatus comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0108] Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention, and those of ordinary skill in the art may change, modify, replace, and modify the above embodiments within the scope of the present invention. Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art that are not disclosed in the present invention. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present invention are indicated by the claims below.

Claims

1. A phase synchronization circuit, characterized in that: The device comprises a clock comparison unit, a bias circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit; the clock comparison unit is connected to the clock output unit, the charge pump circuit and the time / analog conversion circuit; the bias circuit is connected to the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected to the compensation charge pump circuit; the loop filter is connected to the charge pump circuit, the compensation charge pump circuit and the clock output unit; The clock comparison unit is configured to compare a reference clock with a feedback clock output from the clock output unit to form a comparison result, and output an up-pulse signal and a down-pulse signal corresponding to the comparison result to the charge pump circuit and the time / analog conversion circuit; The bias circuit is used to output a first bias current to the charge pump circuit and output a second bias current to the time / analog conversion circuit; The charge pump circuit is configured to generate a first charging current and a first discharging current according to the uplink pulse signal and the downlink pulse signal, and output the first charging current or the first discharging current as a first compensation current to the loop filter; The time / analog conversion circuit is used to generate a compensation analog voltage according to the up-pulse signal and the down-pulse signal, and output the compensation analog voltage to the compensation charge pump circuit; the compensation analog voltage includes a positive-side compensation analog voltage and a negative-side compensation analog voltage; The compensation charge pump circuit is configured to generate a second charging current and a second discharging current according to the positive-side compensation analog voltage and the negative-side compensation analog voltage, and output a current difference between the second charging current and the second discharging current as a second compensation current to the loop filter; The loop filter is used to output a control voltage to the clock output unit; the control voltage includes a control voltage of the first compensation current and a control voltage of the second compensation current; The clock output unit is configured to output an output clock based on the control voltage, and output a feedback clock based on the output clock to the clock comparison unit.

2. A phase synchronization circuit according to claim 1, characterized in that: The time / analog conversion circuit includes a bias compensation charge injection circuit and a current control capacitor; the bias compensation charge injection circuit is used to receive the second bias current, the uplink pulse signal and the downlink pulse signal; The bias compensation charge injection circuit generates compensation charge through the second bias current; When the up pulse signal or the down pulse signal is at a high level, compensation charge is injected into the current control capacitor, and the positive side compensation analog voltage and the negative side compensation analog voltage are changed until the pulse width of the up pulse signal and the down pulse signal is reduced to a dead zone suppression level.

3. The phase synchronization circuit according to claim 1, wherein: The time / analog conversion circuit includes a current mirror circuit, an internal logic circuit, and a charge sharing circuit; the current mirror circuit is composed of a plurality of NMOS transistors and PMOS transistors and is configured as a current mirror structure; the charge sharing circuit includes a plurality of switches and a plurality of capacitors; The current mirror circuit is configured to generate a first positive bias voltage and a second positive bias voltage, a first negative bias voltage and a second negative bias voltage according to the second bias current; The internal logic circuit is used to receive the uplink pulse signal and the downlink pulse signal, and generate an uplink positive phase pulse signal, an uplink negative phase pulse signal, a downlink positive phase pulse signal and a downlink negative phase pulse signal respectively; The charge sharing circuit includes a bias loop; the bias loop is used to receive the first positive side bias voltage and the second positive side bias voltage, the first negative side bias voltage and the second negative side bias voltage, and share charge with the uplink positive phase pulse signal, the uplink negative phase pulse signal, the downlink positive phase pulse signal and the downlink negative phase pulse signal to obtain a positive side compensation analog voltage and a negative side compensation analog voltage respectively.

4. A phase synchronization circuit according to claim 2 or 3, characterized in that: The compensation charge pump circuit includes an output PMOS transistor and an output NMOS transistor; the compensation charge pump circuit is connected to a bias loop so that the output PMOS transistor outputs the second charging current based on the positive-side compensation analog voltage; and the output NMOS transistor outputs the second discharging current based on the negative-side compensation analog voltage.

5. A phase synchronization circuit according to claim 4, characterized in that: The loop filter includes a plurality of capacitors; the first charging current or the first discharging current and the second compensation current are charged and discharged by the capacitors to obtain a control voltage which is output to the clock output unit.

6. A phase-locked loop circuit, characterized in that: The phase synchronization circuit according to any one of claims 1 to 2 is provided; wherein the clock comparison unit includes a phase-frequency comparator; the phase-frequency comparator is used to compare the phase difference and the frequency difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference and the frequency difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled oscillator and a frequency divider, wherein the voltage-controlled oscillator is used to output an oscillation clock having an oscillation frequency corresponding to the control voltage as the output clock; the frequency divider is used to output the clock obtained by dividing the output clock as the feedback clock to the phase frequency comparator.

7. A delay-locked loop circuit, characterized in that: The phase synchronization circuit according to any one of claims 1 to 3 is provided; wherein the clock comparison unit comprises a phase comparator; the phase comparator is used to compare the phase difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled delay line; the voltage-controlled delay line is composed of a multi-stage delay buffer; the voltage-controlled delay line is used to output a clock delayed from the reference clock as the output clock based on the control voltage, and output the output clock as the feedback clock to the phase comparator.

8. A delay-locked loop circuit, characterized in that: The phase synchronization circuit according to claim 1 is comprised of: the clock comparison unit comprising a phase comparator; the phase comparator is configured to compare the phase difference between the reference clock and the feedback clock, and output an uplink pulse signal and a downlink pulse signal corresponding to the phase difference to the charge pump circuit and the time / analog conversion circuit; The clock output unit includes a voltage-controlled delay line and a lock detection circuit; wherein the voltage-controlled delay line is composed of a multi-stage delay buffer; the voltage-controlled delay line is used to output a clock delayed from the reference clock as the output clock based on the control voltage, and output the output clock as the feedback clock to the phase comparator; the lock detection circuit is used to detect whether the output clock output by the voltage-controlled delay line is locked; when it is detected that the output clock is locked, a lock detection signal is sent to the time / analog conversion circuit.

9. The delay-locked loop circuit according to claim 8, wherein: The time / analog conversion circuit specifically includes a current mirror circuit, an internal logic circuit, and a charge sharing circuit; the current mirror circuit is composed of a plurality of NMOS transistors and PMOS transistors and is configured as a current mirror structure; the charge sharing circuit includes a plurality of switches and a plurality of capacitors; The current mirror circuit is used to generate a first positive bias voltage and a second positive bias voltage, a first negative bias voltage and a second negative bias voltage, a positive standby bias voltage and a negative standby bias voltage according to the second bias current; The internal logic circuit is used to receive the uplink pulse signal and the downlink pulse signal, and generate an uplink positive phase pulse signal, an uplink negative phase pulse signal, a downlink positive phase pulse signal and a downlink negative phase pulse signal respectively; The internal logic circuit is further configured to receive the lock detection signal, generate a positive lock logic signal or a negative lock logic signal, and send the signal to the charge sharing circuit and the compensation charge pump circuit; The charge sharing circuit includes a bias circuit and a standby bias circuit; the bias circuit is used to receive the first positive side bias voltage and the second positive side bias voltage, the first negative side bias voltage and the second negative side bias voltage, and perform charge sharing with the uplink positive phase pulse signal, the uplink negative phase pulse signal, the downlink positive phase pulse signal and the downlink negative phase pulse signal to obtain a positive side compensation analog voltage and a negative side compensation analog voltage respectively; the standby bias circuit is used to receive the positive side standby bias voltage and the negative side standby bias voltage; The charge sharing circuit controls the switch on the backup bias loop to close when receiving the positive locking logic signal; When the negative lock logic signal is received, the switch on the backup bias loop is controlled to be opened.

10. The delay-locked loop circuit according to claim 9, wherein: The compensation charge pump circuit includes an output PMOS transistor and an output NMOS transistor; when receiving the positive locking logic signal, the compensation charge pump circuit is connected to the standby bias loop and sets the gate voltages of the output PMOS transistor and the output NMOS transistor to the positive side standby bias voltage and the negative side standby bias voltage, respectively; when receiving the negative locking logic signal, the compensation charge pump circuit is connected to the bias loop so that the output PMOS transistor outputs the second charging current based on the positive side compensation analog voltage; and the output NMOS transistor outputs the second discharging current based on the negative side compensation analog voltage.

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