Test method of switch and electronic equipment

Abstract

The invention provides a test method of a switch and electronic equipment, which can be applied to the technical field of switches. The method comprises the steps that under the condition that a first interface of a mainboard and a second interface of an interface board are in a connected state, a first controller arranged on the mainboard writes a preset value into a first register of a physical layer device arranged on the interface board through a management data input and output interface, so that the physical layer device is set to be in a loopback mode, reading a first flag bit signal from a second register of the physical layer device; in response to the fact that the first flag bit signal represents that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnosis signal and sends the preset diagnosis signal to the physical layer device; in response to the received returned preset diagnosis signal, a test result is obtained according to the signal integrity of the returned preset diagnosis signal, and the test result indicates the connection state between the mainboard and the interface board.

Description

Technical Field

[0001] The present application relates to the technical field of switches, and more specifically to a switch testing method and electronic equipment. Background Art

[0002] After the switch is assembled, the connection between the switch's interface board and the mainboard connector is tested by observing the physical form of the exposed portion of the connector, such as the insertion depth and the locking state of the latch. This yields a qualitative judgment, which is difficult to guarantee the reliability of the test results. Summary of the Invention

[0003] In view of the above problems, the present application provides a switch testing method and electronic equipment that improve the reliability of detection results.

[0004] According to the first aspect of the present application, a method for testing a switch is provided, comprising: when the first interface of the above-mentioned main board and the second interface of the above-mentioned interface board are in a connected state, a first controller arranged on the above-mentioned main board writes a preset value to a first register of a physical layer device arranged on the above-mentioned interface board through a management data input and output interface, so as to set the above-mentioned physical layer device to a loopback mode, and reads a first flag signal from the second register of the above-mentioned physical layer device; in response to the above-mentioned first flag signal indicating that the loopback mode of the above-mentioned physical layer device is successfully set, the above-mentioned first controller generates a preset diagnostic signal and sends the above-mentioned preset diagnostic signal to the above-mentioned physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained according to the signal integrity of the above-mentioned returned preset diagnostic signal, and the above-mentioned test result indicates the connection status between the above-mentioned main board and the interface board.

[0005] A second aspect of the present application provides an electronic device, including a main board and an interface board, wherein the main board is provided with a first controller, and the first controller is configured to execute the above method.

[0006] According to the embodiments of the present application, by performing signal integrity analysis on the preset diagnostic signal returned by the received physical layer device and indicating the connection status between the main board and the interface board with the analysis result, the reliability of the test results of the connection status between the main board and the interface board of the switch is guaranteed. Since the test of the connection status between the main board and the interface board of the switch is a test before the switch performs a communication task, it will not affect the normal communication task of the switch, and the reliability of the normal communication task execution of the switch is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0008] Figure 1 A diagram showing an application scenario of a switch testing method and an electronic device according to an embodiment of the present application is shown.

[0009] Figure 2 A flow chart of a switch testing method according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a high-speed connector PIN interface according to an embodiment of the present application is shown.

[0011] Figure 4 A structural schematic diagram is shown in which a first interface of a mainboard and a second interface of an interface board are connected via a high-speed connector according to an embodiment of the present application.

[0012] Figure 5 A structural schematic diagram of a direct docking connection between a first interface of a mainboard and a second interface of an interface board according to an embodiment of the present application is shown.

[0013] Figure 6 A structural schematic diagram of the connection between the interface board and the main board according to an embodiment of the present application is shown.

[0014] Figure 7 A flow chart of a switch testing method according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0016] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0017] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0018] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0019] Amidst the rapid development of the information industry, the data center switch industry is undergoing profound changes driven by cloud computing, artificial intelligence, and the Internet of Things (IoT). With the explosive growth in data exchange demand, the market is placing higher demands on data center switch port flexibility. To address this, leading industry vendors have launched switches with pluggable interface boards. These devices utilize a modular design to enable flexible port configuration expansion. Their core architecture involves high-speed signal interconnection between the interface board and the mainboard. In this architecture, high-speed signal transmission, such as serializer / deserializer (SerDes) between the interface board and the mainboard, primarily relies on high-speed connectors for physical connection. However, due to structural design tolerances or assembly process variations, high-speed connectors may not be properly installed, leading to signal link contact anomalies. These anomalies can directly cause signal attenuation, increased bit error rates, or even link interruptions. These issues can lead to link errors and data transmission interruptions during device operation, severely impacting system reliability. Because connectors are typically installed inside the device chassis, visual inspection is not possible to directly determine assembly status. Traditional inspection methods struggle to detect connection issues immediately after device assembly. In practice, such issues are often only initially identified during the production line stress testing phase. They may even be traced back to the device after it has been delivered to the customer and put into operation, triggering errors due to high-load data transmission. This not only prolongs the troubleshooting cycle, increases production line rework costs and the difficulty of on-site maintenance, but can also have a lasting impact on user services due to service interruptions. Given the shortcomings of existing detection methods in terms of real-time performance and accuracy, there is an urgent need for a detection method that can quickly and reliably determine the connector connection status when the interface board is inserted into the device. This can achieve early identification and precise location of assembly issues, ensuring the stable operation of data center switches.

[0020] Currently, the industry generally relies on manual visual inspection for connector assembly on pluggable interface boards in data center switches, specifically for connectors that are easily visible and exposed outside the chassis. Based on their extensive assembly experience, technicians make subjective judgments about assembly quality by directly observing the connector's physical position, insertion depth, and appearance. While this method is simple and inexpensive, its accuracy is highly dependent on the operator's skill level, subject to significant human error and individual variability, making it difficult to meet the demands of high-precision assembly inspection.

[0021] For connectors installed in concealed locations inside a computer chassis, due to the enclosed space and poor visibility, existing technologies cannot directly determine the assembly status through visual means. Even with the help of auxiliary tools such as endoscopes, it is difficult to fully and clearly observe the actual plug-in state of the connector, making it difficult to detect assembly hazards in a timely manner.

[0022] At the structural design level, existing technologies typically employ the addition of guide pins to aid assembly. These pins precisely mate with corresponding positioning holes, physically guiding and limiting the connector during insertion, mechanically ensuring that the connector is properly installed. However, this passive structural assurance method cannot proactively monitor the actual connection quality of the connector. It only reduces the probability of assembly deviation and fails to fundamentally address the problem of detecting connection anomalies.

[0023] During the post-assembly testing phase, if faults such as signal errors or abnormal data transmission occur during system operation, technicians must manually disassemble the relevant components and troubleshoot the connection between the port card and the motherboard connector one by one. This troubleshooting process consumes a significant amount of time and manpower, and is inefficient in fault location. This not only seriously impacts production efficiency, but can also delay equipment delivery due to delays, increasing operational costs and customer service pressures.

[0024] The current detection method has not established a standardized judgment system based on electrical performance or mechanical parameters. It only relies on the physical morphology observation of the exposed part of the connector (such as insertion depth, lock bite status, etc.) for qualitative judgment. In addition, manual visual inspection is heavily dependent on the operator's experience level and is significantly affected by external factors such as visual angle and lighting conditions. This judgment method may cause different inspectors to draw different conclusions on the same assembly status, and the consistency and reliability of the test results are difficult to guarantee. In addition, the detection technology of pluggable interface board connectors of data center switches has defects such as strong subjectivity of manual visual inspection and delayed assembly status judgment.

[0025] An embodiment of the present application provides a method for testing a switch, which includes a main board and an interface board. The method includes: when a first interface of the main board and a second interface of the interface board are in a connected state, a first controller arranged on the main board writes a preset value to a first register of a physical layer device arranged on the interface board through a management data input / output interface (MDIO) to set the physical layer device to a loopback mode, and reads a first flag signal from the second register of the physical layer device; in response to the first flag signal indicating that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained based on the signal integrity of the returned preset diagnostic signal, and the test result indicates the connection status between the main board and the interface board.

[0026] According to the embodiments of the present application, by performing signal integrity analysis on the preset diagnostic signal returned by the received physical layer device and indicating the connection status between the main board and the interface board with the analysis result, the reliability of the test results of the connection status between the main board and the interface board of the switch is guaranteed. Since the test of the connection status between the main board and the interface board of the switch is a test before the switch performs a communication task, it will not affect the normal communication task of the switch, and the reliability of the normal communication task execution of the switch is guaranteed.

[0027] Figure 1 A diagram showing an application scenario of a switch testing method and an electronic device according to an embodiment of the present application is shown.

[0028] like Figure 1 As shown, according to the application scenario of this embodiment, the switch includes a mainboard 110 and an interface board 120. A first interface 111 and a first controller 112 are provided on the mainboard 110. A second interface 121 and a physical layer device 122 are provided on the interface board 120. The first controller 112 is connected to the first interface 111, the physical layer device 122 is connected to the second interface 121, and the first interface 111 and the second interface 121 are connected.

[0029] The following will be based on Figure 1 The scene described by Figure 2 The switch testing method according to the embodiment of the present application is described in detail.

[0030] Figure 2 A flow chart of a switch testing method according to an embodiment of the present application is shown.

[0031] like Figure 2As shown, the switch testing method of this embodiment includes operations S210 to S230, and the transaction processing method can be executed by the first controller.

[0032] In operation S210, when the first interface of the main board and the second interface of the interface board are in a connected state, the first controller provided on the main board writes a preset value to the first register of the physical layer device provided on the interface board through the management data input and output interface so as to set the physical layer device to loopback mode, and reads the first flag signal from the second register of the physical layer device.

[0033] According to an embodiment of the present application, a switch is provided with a first interface on the mainboard and a second interface on the interface board. The types and specifications of the first and second interfaces are related to the model and application scenario of the interface board. For example, the first and second interfaces are standard 8-bit modular interfaces, interfaces connected to high-speed connectors, etc.

[0034] According to an embodiment of the present application, a switch mainboard is provided with a first controller, which can be a Media Access Control (MAC). An interface board is provided with a physical layer (PHY) device, which can be a Gigabit / 100M electrical port switch or a device capable of loopback mode. The first controller can set the PHY device to loopback mode via a management data input / output interface.

[0035] According to an embodiment of the present application, the loopback mode of the physical layer device can be that the physical layer device directly sends the transmitted data signal back to its own receiving end, for example, the first controller sends → the first controller is connected to the physical layer device through the first interface and the second interface to form a physical link → the physical layer device loops back → the physical layer device is connected to the first controller through the second interface and the first interface to form a physical link → the first controller receives.

[0036] According to an embodiment of the present application, the first flag signal represents whether the operation of setting the physical layer device to the loopback mode is successful. That is, the first flag signal has different values, corresponding to whether the loopback mode of the physical layer device is set successfully or unsuccessfully.

[0037] In operation S220 , in response to the first flag signal indicating that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device.

[0038] According to an embodiment of the present application, the first controller transmits a preset diagnostic signal to a physical layer device through the first interface and the second interface. The preset diagnostic signal can select PRBS7 and PRBS31 in PRBS (Pseudo-Random Binary Sequence). The spectrum of the preset diagnostic signal is as wide as the Nyquist frequency and is sensitive to impedance discontinuity. That is, the signal quality of the preset diagnostic signal is easily degraded due to impedance mutations on the transmission path. Impedance mutations are impedance discontinuities, which lead to problems such as signal distortion. Since it is sensitive to impedance changes, the preset diagnostic signal can accurately identify abnormal physical and electrical characteristics of the first interface and the second interface through impedance changes, thereby achieving efficient and high-precision fault diagnosis and status monitoring.

[0039] In operation S230 , in response to receiving the returned preset diagnostic signal, a test result is obtained according to the signal integrity of the returned preset diagnostic signal, where the test result indicates the connection status between the main board and the interface board.

[0040] Since the physical layer device is set to loopback mode, after the receiving end of the physical layer device receives the preset diagnostic signal, the transmitting end of the physical layer device returns the received preset diagnostic signal to the receiving end of the first controller through the second interface and the first interface to obtain the preset diagnostic signal.

[0041] Perform signal integrity analysis on the returned preset diagnostic signal. This analysis can include analyzing the signal spectrum, the frequency response of the transmission path, and transmission line effects. The connection quality between the mainboard and interface board is determined based on the test results. For example, a poor connection can cause nonlinear effects to increase signal harmonics (such as the second and third harmonics), leading to abnormal peaks in the spectrum. Increased contact resistance can also introduce thermal noise, raising the noise floor of the spectrum.

[0042] According to the embodiments of the present application, by performing signal integrity analysis on the preset diagnostic signal returned by the received physical layer device and indicating the connection status between the main board and the interface board with the analysis result, the reliability of the test results of the connection status between the main board and the interface board of the switch is guaranteed. Since the test of the connection status between the main board and the interface board of the switch is a test before the switch performs a communication task, it will not affect the normal communication task of the switch, and the reliability of the normal communication task execution of the switch is guaranteed.

[0043] According to an embodiment of the present application, the testing method of the switch also includes: the first controller receives a second flag signal sent by a baseboard management controller set on the mainboard; the second flag signal indicates the connection status between the first interface and the second interface; wherein the baseboard management controller reads the second flag signal from a third register of the second controller set on the mainboard.

[0044] In an embodiment of the present application, a second controller and a baseboard management controller are further provided on the mainboard. The baseboard management controller is provided on the mainboard of the switch. The baseboard management controller is connected to the second controller, and the second controller is connected to the first interface.

[0045] When the motherboard is in stable operation, the baseboard management controller continuously accesses the third register of the second controller to determine whether an interface board is inserted into the motherboard. If an interface board is inserted into the motherboard, the value of the third register of the corresponding slot of the second controller changes. When the baseboard management controller detects a change in the value of the third register of the second controller, the value of the second flag signal also changes.

[0046] The second controller can be a device capable of detecting level changes in an input signal. For example, the second controller can be a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA). If the second controller is a CPLD, the third register is an in-position register of the CPLD.

[0047] When the baseboard management controller detects that an interface board is inserted into the mainboard, the diagnostic mode is triggered and the baseboard management controller sends a second flag signal to the first controller, so that the first controller is in loopback mode during configuration of the physical layer through the management data input and output interface.

[0048] According to an embodiment of the present application, by continuously accessing the third register of the second controller through the baseboard management controller, connection information can be detected in real time and the connection information can be responded to in a timely manner.

[0049] Figure 3 A schematic diagram of a high-speed connector PIN interface according to an embodiment of the present application is shown.

[0050] like Figure 3 As shown, the pins in each row of the high-speed connector PIN interface are A1-A9, B1-B9, C1-C9, D1-D9, E1-E9, F1-F9, G1-G9, and H1-H9, for a total of 72 pins. The high-speed connector PIN interface can be used on data center switch motherboards and interface boards. In operation S210, the high-speed connector PIN interface can be selected for the first interface, and the high-speed connector PIN interface can also be selected for the second interface. The first and second interfaces can be connected via a high-speed connector, or they can be directly connected for use.

[0051] According to an embodiment of the present application, the first pin of the input and output interface of the second controller and the first pin of the first interface of the main board are grounded via a resistor; the second pin of the first interface is connected to the power supply; the third pin of the second interface of the interface board and the fourth pin of the second interface are short-circuited; when the first interface and the second interface are in a connected state, the first pin is connected to the third pin; and the second pin is connected to the fourth pin.

[0052] When there are multiple first interfaces, each first interface corresponds to an input / output interface of the second controller. The connection between each first interface and the corresponding input / output interface is similar and will not be repeated here.

[0053] Each interface board is provided with a second interface. When there are multiple interface boards, each first interface is connected to a corresponding second interface. According to the embodiment of the present application, since the second controller directly detects the level change of the input and output interfaces, it is possible to timely detect the connection status between the first interface and the second interface.

[0054] Figure 4 A structural schematic diagram is shown in which a first interface of a mainboard and a second interface of an interface board are connected via a high-speed connector according to an embodiment of the present application.

[0055] like Figure 4 Board 410 can serve as the main board, while boards 420, 430, and 440 are all interface boards. The second interface on board 420 is J21, the second interface on board 430 is J22, and the second interface on board 440 is J2n. A second controller 411 is provided on the main board. Second controller 411 has multiple GPIOs (general-purpose input / output) including GPIO1, GPIO2, ..., GPIOn. The first interface includes J11, J12, ..., J1n. The power supply is connected to the second pin of J11, GPIO1 is connected to the first pin of J11, and GPIO1 is also connected to one end of resistor R1, the other end of which is grounded. The third pin of J21 is short-circuited with the fourth pin of J21. The second pin of J11 is connected to the fourth pin of J21, and the first pin of J11 is connected to the third pin of J21.

[0056] Connect the power supply to the second pin of J12, GPIO2 to the first pin of J12, and GPIO2 to one end of resistor R2. The other end of resistor R2 is grounded. Short the third pin of J22 to the fourth pin of J22. Connect the second pin of J12 to the fourth pin of J22; and the first pin of J12 to the third pin of J22. Connect the power supply to the second pin of J1n, GPIOn to the first pin of J1n, and GPIOn to one end of resistor R3. The other end of resistor R3 is grounded. Short the third pin of J2n to the fourth pin of J2n. Connect the second pin of J1n to the fourth pin of J2n; and the first pin of J1n to the third pin of J2n.

[0057] Taking the connection between J11 and J21 as an example, when the second pin in J11 is connected to the fourth pin in J21 through a high-speed connector, and the first pin in J11 is connected to the third pin in J21 through a high-speed connector, J11 and J21 are in a connected state, and the register of the corresponding slot of GPIO1 of the second controller 411 will be pulled from a high level to a low level, thereby causing the value of the third register of the second controller 411 to change.

[0058] The first interface is a female high-speed connector, and the second interface is a male high-speed connector. Boards 420, 430, and 440 use pluggable port cards with the same specifications and type of high-speed connector. The connection between the first and second interfaces is similar to the connection between J11 and J21, and other connection details are not further described here.

[0059] According to an embodiment of the present application, taking the connection between J11 and J21 as an example, the second pin in J11 can also be connected to the fourth pin in J21 through a low-speed connector, and the first pin in J11 can be connected to the third pin in J21 through a low-speed connector. Similar to the connection using a high-speed connector, Figure 4 Devices in the can also be connected using low-speed connectors.

[0060] Figure 5 A structural schematic diagram of a direct docking connection between a first interface of a mainboard and a second interface of an interface board according to an embodiment of the present application is shown.

[0061] like Figure 5 As shown, the board 410 can be used as a main board, and the connection relationship between the second controller 411, resistors R1, R2, R3, J11, J12 and J1n in the main board and the short-circuit method of J21 are the same as Figure 4The circuit diagram is similar to that shown in the figure and will not be described in detail here. Board 420 serves as an interface board. The high-speed female connector J11 of the main board is directly connected to the high-speed male connector J21 of the interface board, obtaining the path VCC→J11→J21→J11→R1→GND, and the GPIO1 of the second controller 411 will detect a high level. If J11 and J21 are not connected, J11→J21 is open circuit, and J21→J11 is also open circuit, the circuit VCC→J11→J21→J11→R1→GND forms an open circuit, and the GPIO1 of the second controller 411 detects a low level. The system can determine whether board 410 and board 420 are assembled and connected by querying the relevant register values ​​of the CPLD.

[0062] According to an embodiment of the present application, the first controller is connected to the first interface of the main board through a serializer / deserializer; the physical layer device of the interface board is connected to the second interface of the interface board through a serializer / deserializer.

[0063] When the first interface and the second interface are connected, the first controller connects to the physical layer device via the serializer / deserializer, the first interface, the second interface, and the serializer / deserializer. The first controller configures the physical layer device and reads its status via the management data input / output interface. If there are multiple first interfaces, the first controller connects to each first interface via the corresponding serializer / deserializer.

[0064] According to the embodiments of the present application, using a serializer / deserializer to connect devices at both ends can reduce the number of pins used by the devices at both ends and improve the signal transmission speed between the devices at both ends.

[0065] Figure 6 A structural schematic diagram of the connection between the interface board and the main board according to an embodiment of the present application is shown.

[0066] like Figure 6As shown, there are multiple interface boards. Board 410 serves as the main board, and boards 420, 430, and 440 are all interface boards. Each interface board is provided with a physical layer device. Board 420 is provided with a first physical layer device, board 430 is provided with a second physical layer device, and board 440 is provided with an nth physical layer device. A first controller 412 is provided on the main board. The first controller is connected to the first interface via a serializer / deserializer. When there are multiple first interfaces, the first controller is connected to J11, J12, ..., J1n respectively via corresponding serializers / deserializers. J11 connected to the first controller can be directly connected to J21, and J21 is connected to the first physical layer device via a serializer / deserializer. The first controller configures the first physical layer device through J11 and J21, sets the first physical layer device to loopback mode, and reads the status of the first physical layer device. When the loopback mode of the first physical layer device is successfully set, the first controller sends a preset diagnostic signal to the first physical layer device and receives the preset diagnostic signal returned by the first physical layer device.

[0067] The preset diagnostic signal output by the first controller can be input into the first physical layer device through the first serializer, the first interface, the second interface, and the first deserializer in sequence, and the return preset diagnostic signal output by the first physical layer device can be returned to the first controller through the second serializer, the second interface, the first interface, and the second deserializer in sequence.

[0068] If the first controller has a built-in serialization module and deserialization module, the first controller and the first interface can be directly connected. If the physical layer device has a built-in serialization module and deserialization module, the physical layer device and the second interface can be directly connected. SerDes technology is used for signal transmission between the first controller and the first interface and between the physical layer device and the second interface.

[0069] The connection relationship between the first controller 412, J12, ... J1n, J22, ... J2n, the second physical layer device, ... the nth physical layer device is similar to the connection relationship between the first controller 412, J11, J21, and the first physical layer device, and will not be repeated here.

[0070] Figure 7 A flow chart of a switch testing method according to another embodiment of the present application is shown.

[0071] like Figure 7 As shown, a switch testing method according to another embodiment of the present application includes operations S701 to S708.

[0072] In operation S701 , the baseboard management controller determines whether the interface board is inserted into the main board. If the interface board is not inserted into the main board, the baseboard management controller continuously detects whether the interface board is inserted into the main board.

[0073] In operation S702 , when the interface board is inserted into the main board, the baseboard management controller triggers a diagnosis mode and sends a second flag signal to the first controller.

[0074] In operation S703 , the first controller configures a diagnostic signal at a TX (Transmit) end in response to the received second flag signal, obtains a preset diagnostic signal, and injects the preset diagnostic signal into a SerDes signal channel of the first controller.

[0075] According to an embodiment of the present application, the amplitude of the preset diagnostic signal can set the reference voltage value of the first controller, or it can be 70%-80% of the normal signal to avoid arc damage when the second interface is not fully inserted into the first interface. The duration of the preset diagnostic signal can be 2μs-10μs to meet the statistical significance requirements.

[0076] According to an embodiment of the present application, the amplitude of the preset diagnostic signal can be set in the following ways, for example, by accessing the register of the first controller through the SPI or I2C interface, setting the output swing of the transmitter, and controlling the differential output swing. For example, adjusting the pre-emphasis strength to compensate for high-frequency attenuation. It is also possible to adjust the pre-emphasis and de-emphasis parameters in combination with the channel loss to adjust the pre-emphasis and de-emphasis. For example, increasing the pre-emphasis value during long-distance transmission can increase the high-frequency signal amplitude. It is also possible to set the current level of the transmitter through the current bias register, the register of the first controller. For example, setting the current bias register to the maximum value can increase the output amplitude, but attention should be paid to power consumption and EMI (Electromagnetic Interference) risks.

[0077] In operation S704 , an RX (Receive) terminal of the first controller receives the returned preset diagnosis signal.

[0078] According to an embodiment of the present application, after a preset diagnostic signal is injected into the SerDes signal channel, the preset diagnostic signal is injected from the TX end of the first controller on the main board, flows from the main board to the interface board through a high-speed connector, enters the RX end of the physical layer device of the interface board, passes through the internal loopback of the physical layer device to the TX end of the physical layer device, passes through the high-speed connector, returns from the interface board to the main board, and finally returns to the RX end of the first controller of the main board.

[0079] In operation S705 , a signal integrity analysis is performed on the returned preset diagnostic signal to obtain a test result.

[0080] According to an embodiment of the present application, a preset diagnostic signal returned for multiple consecutive cycles is obtained to obtain a signal to be tested; the signal to be tested is processed using the clock recovery function of the first controller to obtain a signal processed by clock recovery; the signal integrity of the signal processed by clock recovery is analyzed to obtain a test result.

[0081] According to an embodiment of the present application, for the preset diagnostic signal returned by the RX end of the first controller, the clock recovery function of the transmitting end of the first controller is used to lock the receiving timing and eliminate the influence of clock offset.

[0082] According to an embodiment of the present application, all preset diagnostic signals sent by the first controller include multiple cycles of pseudo-random binary sequence 7 or pseudo-random binary sequence 31. The preset diagnostic signal returned for multiple consecutive cycles is the signal returned by all preset diagnostic signals sent by the first controller.

[0083] According to the embodiments of the present application, the signal to be tested is processed by a clock recovery function, thereby eliminating the influence of clock offset and improving the accuracy of the test result of the switch.

[0084] In operation S706 , it is determined whether the test result meets a preset condition.

[0085] According to an embodiment of the present application, the test result includes at least one of an amplitude attenuation test result, an eye diagram test result, and a bit error rate estimation test result.

[0086] The test results can be amplitude attenuation test results, eye diagram test results, or bit error rate estimation test results. They can also be a combination of any two of the amplitude attenuation test results, eye diagram test results, and bit error rate estimation test results. They can also be a combination of the amplitude attenuation test results, eye diagram test results, and bit error rate estimation test results. The test result can be selected based on the actual situation.

[0087] According to the embodiments of the present application, the comprehensiveness of the switch test is improved by performing multi-faceted detection on the signal to be tested.

[0088] According to an embodiment of the present application, when the test results include amplitude attenuation test results, the method for obtaining the test results based on the signal integrity of the returned preset diagnostic signal includes: determining the peak voltage of the signal to be tested; determining the degree of amplitude attenuation based on the ratio of the peak voltage to the reference voltage value of the preset diagnostic signal, and using the degree of amplitude attenuation as the amplitude attenuation test result.

[0089] According to an embodiment of the present application, when the amplitude of the preset diagnostic signal is set, the attenuation is calculated according to the amplitude of the preset diagnostic signal configured by the register at the TX end of the first controller and the amplitude of the signal to be tested received by the register at the RX end of the first controller, based on the values ​​of the two registers, by using formula (1), and the attenuation is used as the amplitude attenuation test result.

[0090] (1)

[0091] in, is the attenuation, The amplitude of the configured preset diagnostic signal, is the amplitude of the received signal to be tested.

[0092] According to the embodiments of the present application, by evaluating the energy loss of the signal during transmission, the integrity of the signal to be tested is analyzed, thereby improving the reliability of the test result.

[0093] According to an embodiment of the present application, when the test results include eye diagram test results, the test results are obtained based on the signal integrity of the returned preset diagnostic signal, including: using the first controller to determine the eye diagram height quantization value or the eye diagram width quantization value of the signal to be tested, and using the eye diagram height quantization value as the eye diagram height test result, and using the eye diagram width quantization value as the eye diagram width test result.

[0094] According to an embodiment of the present application, the ADC sampling eye diagram monitoring module built into the first controller can be used to directly determine the eye diagram height quantization value or the eye diagram width quantization value of the test signal. Alternatively, the test signal can be saved as a time-voltage sequence, the time-voltage sequence can be segmented by UI (Unit Interval) length, the edges of the segmented unit sequences can be aligned, and the eye diagram height quantization value and eye diagram width quantization value can be determined based on the aligned unit sequences.

[0095] According to the embodiments of the present application, by visualizing the signal quality problem of the signal to be tested, it is possible to quickly determine whether there is a defect in the transmission path of the signal to be tested.

[0096] According to an embodiment of the present application, when the test results include bit error rate estimation test results, the test results obtained based on the signal integrity of the returned preset diagnostic signal include: determining the total number of transmission bits and the number of error bits of the signal to be tested; and determining the bit error rate estimation test results based on the ratio of the number of error bits to the total number of transmission bits.

[0097] According to an embodiment of the present application, the first controller can use a built-in counter to record the number of all returned preset diagnostic signals, and directly read the number of error bits and the total number of bits of all returned preset diagnostic signals to determine the bit error rate estimation test result.

[0098] According to the embodiments of the present application, by using quantized data to predict the reliability of signal transmission, switch failures caused by sudden bit errors in actual applications are avoided.

[0099] In operation S707 , if the test result does not meet the preset condition, an alarm message is generated, and activation of the first interface and the second interface is blocked.

[0100] If the test results do not meet the preset conditions, the first interface and the second interface are prohibited from entering the working state, that is, the first interface and the second interface cannot transmit data, avoiding data loss, network congestion and even system failure caused by abnormal links accessing the network.

[0101] According to an embodiment of the present application, an alarm message is generated when the amplitude attenuation test result is greater than a preset attenuation amount; or, an alarm message is generated when the eye diagram test result does not meet the corresponding preset standard; or, an alarm message is generated when the bit error rate estimation test result is greater than a preset bit error rate.

[0102] According to an embodiment of the present application, the eye diagram test results include an eye diagram height test result and an eye diagram width test result. When the eye diagram height test result is less than a preset eye diagram height threshold, an alarm message is generated; when the eye diagram width test result is less than a preset eye diagram width threshold, an alarm message is generated.

[0103] According to the embodiments of the present application, since the same judgment criteria are used when testing each switch, the consistency of the switch test results is improved.

[0104] An indicator light is provided on the interface board. After the baseboard management controller receives the alarm information, the baseboard management controller controls the indicator light on the interface board to light up red, requiring the staff to check the connection status of the high-speed connector.

[0105] In operation S708 , if the test result meets the preset conditions, a formal link test is started.

[0106] According to an embodiment of the present application, if the signal integrity analysis result of the returned preset diagnostic signal meets the preset conditions, a test success message can be generated. After receiving the test success message, the baseboard management controller controls the indicator light on the interface board to light up green, and at this time, the formal link test is started.

[0107] According to an embodiment of the present application, the insertion status of the high-speed connector is determined by using a power signal. When the interface board is inserted into the mainboard, the level of the third register of the corresponding slot of the second controller changes. The connection status of the high-speed signal link is determined by analyzing the signal integrity of the preset diagnostic signal returned. This advances the diagnostic detection of the high-speed interconnection of the switch from post-communication to pre-communication prevention, which is equivalent to establishing a connection quality firewall between the physical layer and the protocol layer. At the same time, the existing hardware resources of the mainboard and interface board are fully reused, eliminating the need for additional expensive detection equipment or hardware architecture modification. It has the significant advantages of low cost, convenient deployment, and strong compatibility, providing chip-level native reliability assurance for high-frequency hot-swap scenarios in data centers.

[0108] The present application also provides an electronic device, which includes a main board and an interface board. The main board is provided with a first controller, and the first controller is configured to execute a test method for a switch.

[0109] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0110] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A method for testing a switch, wherein the switch includes a main board and an interface board, wherein: The method comprises: When the first interface of the mainboard and the second interface of the interface board are in a connected state, the first controller provided on the mainboard writes a preset value to a first register of a physical layer device provided on the interface board through the management data input / output interface so as to set the physical layer device to a loopback mode, and reads a first flag signal from the second register of the physical layer device; In response to the first flag signal indicating that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; In response to receiving the returned preset diagnostic signal, a test result is obtained according to the signal integrity of the returned preset diagnostic signal, wherein the test result indicates the connection status between the main board and the interface board.

2. The method according to claim 1, characterized in that Obtaining a test result based on the signal integrity of the returned preset diagnostic signal includes: Acquire the preset diagnostic signal returned for a plurality of consecutive cycles to obtain a signal to be tested; Processing the signal to be tested using a clock recovery function of the first controller to obtain a signal processed by clock recovery; The signal integrity of the clock-recovered signal is analyzed to obtain a test result.

3. The method according to claim 2, characterized in that The test result includes at least one of an amplitude attenuation test result, an eye diagram test result, and a bit error rate estimation test result.

4. The method according to claim 3, characterized in that In the case where the test result includes an amplitude attenuation test result, the method for obtaining the test result according to the signal integrity of the returned preset diagnostic signal includes: determining a peak voltage of the signal to be tested; The amplitude attenuation degree is determined according to a ratio of the peak voltage to a reference voltage value of the preset diagnostic signal, and the amplitude attenuation degree is used as the amplitude attenuation test result.

5. The method according to claim 3, characterized in that In a case where the test result includes an eye diagram test result, obtaining the test result according to the signal integrity of the returned preset diagnostic signal includes: The first controller is used to determine an eye height quantization value or an eye width quantization value of the signal to be tested, and the eye height quantization value is used as the eye height test result, and the eye width quantization value is used as the eye width test result.

6. The method according to claim 3, characterized in that In a case where the test result includes a bit error rate estimation test result, obtaining the test result according to the signal integrity of the returned preset diagnostic signal includes: Determining the total number of transmitted bits and the number of error bits of the signal to be tested; The bit error rate estimation test result is determined according to the ratio of the number of error bits to the total number of transmitted bits.

7. The method according to claim 3, characterized in that The method further comprises: If the test result does not meet the preset conditions, an alarm message is generated.

8. The method according to claim 1, characterized in that The method further comprises: The first controller receives a second flag signal sent by a baseboard management controller provided on the mainboard; the second flag signal indicates a connection state between the first interface and the second interface; The baseboard management controller reads the second flag signal from a third register of a second controller provided on the mainboard.

9. The method according to claim 7, characterized in that When the test result does not meet the preset conditions, generating an alarm message includes: If the amplitude attenuation test result is greater than a preset attenuation amount, generating an alarm message; or If the eye diagram test result does not meet the corresponding preset standard, generating an alarm message; or When the bit error rate estimation test result is greater than a preset bit error rate, an alarm message is generated.

10. An electronic device comprising a main board and an interface board, wherein the main board is provided with a first controller, characterized in that: The first controller is configured to execute the method according to any one of claims 1 to 9.

11. The electronic device according to claim 10, characterized in that The mainboard is further provided with a second controller, wherein the input and output interface of the second controller and the first pin of the first interface of the mainboard are grounded via a resistor; the second pin of the first interface is connected to the power supply; The third pin of the second interface of the interface board and the fourth pin of the second interface are short-circuited; When the first interface and the second interface are in a connected state, the first pin is connected to the third pin; and the second pin is connected to the fourth pin.

12. The electronic device according to claim 10, wherein: The first controller is connected to the first interface of the main board through a serializer / deserializer; the physical layer device of the interface board is connected to the second interface of the interface board through a serializer / deserializer.

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