Computer-implemented method and apparatus for providing binary instructions
By setting up different architectures and conversion devices between processors, automated, diversified, redundant execution of binary instructions is achieved, solving the redundancy and conversion burden problems when processors execute instructions of different formats, and improving the robustness and conversion efficiency of the system.
Patent Information
- Application Number
- CN202480017169.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-08
- Filing Date
- 2024-02-19
- Publication Date
- 2025-10-03
AI Technical Summary
In the prior art, there is redundancy and conversion burden when the processor executes binary instructions of different formats, resulting in insufficient system robustness.
It uses processors and conversion devices with different architectures, receives and converts binary instructions through an interface, and uses conversion commands and tables in the memory to achieve automatic conversion between formats, avoiding additional processor burden.
The robustness of the system is improved, processor redundancy and conversion burden are reduced, and the resistance to system errors is enhanced.
Smart Images
Figure CN120752610A_ABST
Abstract
Description
Existing technology
[0001] The present invention relates to a computer-implemented method and an apparatus for providing binary instructions.
[0002] Conventional processors are configured to execute binary instructions provided to the processor.
[0003] A user of a processor is provided with the possibility of providing binary instructions for execution on the processor. On the one hand, these binary instructions can be provided in a predetermined format suitable for execution on the processor. On the other hand, provision can be made for these binary instructions to be provided by the user in a format different from the predetermined format and to be converted into binary instructions in the predetermined format that can be executed by the processor.
[0004] To create redundancy, multiple processors are used that are configured to execute binary instructions in a predetermined format. These processors can have the same architecture or different architectures that are capable of executing binary instructions in a predetermined format. Summary of the Invention
[0005] A device arrangement for automated, diversified, redundant execution of binary instructions includes a first processor having a first architecture and a second processor having a second architecture, wherein the first processor is configured to execute binary instructions in a first format, and the second processor is configured to execute binary instructions in a second format different from the first format. The device is configured to provide at least one binary instruction in the first format to the first processor and at least one binary instruction in the second format redundant with the at least one first binary instruction to the second processor. The device is configured to either receive the at least one binary instruction in the first format and determine at least one binary instruction in the second format based on the at least one binary instruction in the first format, or receive a binary instruction in a third format different from the first format and the second format for binary instructions that is redundant with at least one binary instruction in the first format and at least one binary instruction in the second format, and determine at least one binary instruction in the first format and at least one binary instruction in the second format based on the binary instruction in the third format. The formats are predetermined, for example, by different instruction set architectures (ISAs). A conversion of the first binary instruction into the second binary instruction can be provided, wherein the first binary instruction and the second binary instruction are each provided to one of the processors. On the other hand, a first binary instruction can be converted into a third binary instruction, wherein the second binary instruction and the third binary instruction are each provided to one of the processors. These architectures can be, for example, different microprocessor core architectures, µArch. The device creates diverse redundancy by using processors of different architectures and formats. The first binary instruction is diversely redundant with the second binary instruction. This improves robustness against systematic errors.
[0006] The device is preferably designed to provide at least one binary instruction in a first format to the first processor for conversion, wherein the first processor is designed to provide at least one binary instruction in a second format based on the at least one instruction in the first format, or the device is designed to provide at least one binary instruction in a third format to the first processor for conversion, wherein the first processor is designed to provide at least one binary instruction in the first format and at least one binary instruction in the second format based on the binary instruction in the third format. This avoids the need for an additional processor.
[0007] The device is preferably configured to provide at least one binary instruction in a first format to a third processor for conversion, wherein the third processor is configured to provide at least one binary instruction in a second format based on the at least one binary instruction in the first format. The device is preferably configured to provide binary instructions in a third format to the third processor for conversion, wherein the third processor is configured to provide at least one binary instruction in the first format and at least one binary instruction in the second format based on the binary instruction in the third format. This avoids burdening other processors with conversion.
[0008] Preferably, the third processor may be configured to convert at least one binary instruction in a first format into at least one binary instruction in a second format, wherein the device is constructed to configure the third processor for the conversion of at least one binary instruction in the first format into at least one binary instruction in the second format, or the third processor may be configured to convert at least one binary instruction in a third format into at least one binary instruction in the first format, wherein the device is constructed to configure the third processor for the conversion of at least one binary instruction in the third format into at least one binary instruction in the first format, or the third processor may be configured to convert at least one binary instruction in the third format into at least one binary instruction in the second format, wherein the device is constructed to configure the third processor for the conversion of at least one binary instruction in the third format into at least one binary instruction in the second format.
[0009] As a result, the processor provided for the diverse redundant execution of binary instructions is not additionally burdened with the conversion. The third processor can be designed according to an architecture for accelerating the conversion.
[0010] In one embodiment, the device includes a memory in which a command for converting at least one binary instruction in a first format into at least one binary instruction in a second format is stored, wherein the device is configured to read the command from the memory and determine the at least one binary instruction in the second format based on the command and the at least one binary instruction in the first format. In one embodiment, the device includes a memory in which a command for converting at least one binary instruction in a third format into at least one binary instruction in the first format is stored, wherein the device is configured to read the command from the memory and determine the at least one binary instruction in the first format based on the command and the at least one binary instruction in the third format. In one embodiment, the device includes a memory in which a command for converting at least one binary instruction in the third format into at least one binary instruction in the second format is stored, wherein the device is configured to read the command from the memory and determine the at least one binary instruction in the second format based on the command and the at least one binary instruction in the third format. This enables the determination of a previously unknown conversion result.
[0011] It can be provided that the device includes a memory in which a conversion result of converting at least one binary instruction in a first format into at least one binary instruction in a second format is stored, wherein the device is configured to read the conversion result from the memory and determine the at least one binary instruction in the second format based on the conversion result; or that the device includes a memory in which a conversion result of converting at least one binary instruction in a third format into at least one binary instruction in the first format is stored, wherein the device is configured to read the conversion result from the memory and determine the at least one binary instruction in the first format based on the conversion result; or that the device includes a memory in which a conversion result of converting at least one binary instruction in the third format into at least one binary instruction in the second format is stored, wherein the device is configured to read the conversion result from the memory and determine the at least one binary instruction in the second format based on the conversion result. This accelerates the conversion.
[0012] It can be provided that the memory includes a table for conversion results, which assigns at least one binary instruction in the second format to at least one binary instruction in the first format, wherein the device is designed to provide as a conversion result the at least one binary instruction in the second format that is assigned in the table to the at least one binary instruction in the first format, or that the memory includes a table for conversion results, which assigns at least one binary instruction in the first format to at least one binary instruction in the third format, wherein the device is designed to provide as a conversion result the at least one binary instruction in the first format that is assigned in the table to the at least one binary instruction in the third format, or that the memory includes a table for conversion results, which assigns at least one binary instruction in the second format to at least one binary instruction in the third format, wherein the device is designed to provide as a conversion result the at least one binary instruction in the second format that is assigned in the table to the at least one binary instruction in the third format. This additionally accelerates the conversion.
[0013] The device can be configured to confirm that a conversion result for conversion is already stored in the memory and read the conversion result from the memory, or to confirm that a conversion result for conversion is unknown in the memory and calculate the conversion result according to the command and store the conversion result in the memory. Thus, the unknown conversion result is calculated and stored for subsequent conversion, or an existing conversion result is reused.
[0014] In one embodiment, the first processor or the second processor includes a hardware accelerator, wherein the device is configured to determine a configuration of the hardware accelerator based on at least one binary instruction in the first format or at least one binary instruction in the third format, which means converting the instruction into a configuration.
[0015] A computer-implemented or hardware-implemented method for automated diversified redundant execution of binary instructions comprises providing at least one binary instruction in a first format to a first processor having a first architecture and configured to execute binary instructions in the first format, and providing at least one binary instruction in a second format that is redundant with the at least one binary instruction in the first format to a second processor having a second architecture different from the first architecture and configured to execute binary instructions in a second format different from the first format, wherein the at least one binary instruction in the first format is received and at least one binary instruction in the second format is determined based on the at least one binary instruction in the first format, or receiving a binary instruction in a third format different from the first format and different from the second format that is redundant with the at least one binary instruction in the first format and at least one binary instruction in the second format, and determining the binary instruction in the first format and the binary instruction in the second format based on the binary instruction in the third format. This enables redundant execution of the provided binary instructions against systematic errors in either the architecture or the format.
[0016] The following developments of the method have advantages that correspond to the advantages of the developments of the device.
[0017] It is preferably provided that at least one binary instruction in a first format is provided to the first processor for conversion, wherein at least one binary instruction in a second format is provided with the aid of the first processor based on the at least one instruction in the first format, or that at least one binary instruction in a third format is provided to the first processor for conversion, wherein at least one binary instruction in the first format and at least one binary instruction in the second format are provided with the aid of the first processor based on the binary instruction in the third format.
[0018] It is preferably provided that at least one binary instruction in a first format is provided to a third processor for conversion, wherein at least one binary instruction in a second format is provided with the aid of the third processor based on the at least one binary instruction in the first format, or that binary instructions in a third format are provided to the third processor for conversion, wherein at least one binary instruction in the first format and at least one binary instruction in the second format are provided with the aid of the third processor based on the binary instruction in the third format.
[0019] Preferably, the third processor may be configured to convert at least one binary instruction in a first format into at least one binary instruction in a second format, wherein the third processor is configured for the conversion of at least one binary instruction in the first format into at least one binary instruction in the second format, or the third processor may be configured to convert at least one binary instruction in a third format into at least one binary instruction in the first format, wherein the third processor is configured for the conversion of at least one binary instruction in the third format into at least one binary instruction in the first format, or the third processor may be configured to convert at least one binary instruction in the third format into at least one binary instruction in the second format, wherein the third processor is configured for the conversion of at least one binary instruction in the third format into at least one binary instruction in the second format.
[0020] Preferably, a command for converting at least one binary instruction in a first format into at least one binary instruction in a second format is stored in the memory, wherein the command is read from the memory and at least one binary instruction in the second format is determined based on the command and the at least one binary instruction in the first format, or a command for converting at least one binary instruction in a third format into at least one binary instruction in the first format is stored in the memory, wherein the command is read from the memory and at least one binary instruction in the first format is determined based on the command and the at least one binary instruction in the third format, or a command for converting at least one binary instruction in the third format into at least one binary instruction in the second format is stored in the memory, wherein the command is read from the memory and at least one binary instruction in the second format is determined based on the command and the at least one binary instruction in the third format.
[0021] Preferably, a conversion result of converting at least one binary instruction in a first format into at least one binary instruction in a second format is stored in the memory, wherein the conversion result is read from the memory and at least one binary instruction in the second format is determined based on the conversion result, or a conversion result of converting at least one binary instruction in a third format into at least one binary instruction in the first format is stored in the memory, wherein the conversion result is read from the memory and at least one binary instruction in the first format is determined based on the conversion result, or a conversion result of converting at least one binary instruction in the third format into at least one binary instruction in the second format is stored in the memory, wherein the conversion result is read from the memory and at least one binary instruction in the second format is determined based on the conversion result.
[0022] It is preferably provided that the memory includes a table for conversion results, which table assigns at least one binary instruction in the second format to at least one binary instruction in the first format, wherein at least one binary instruction in the second format assigned to at least one binary instruction in the first format in the table is provided as a conversion result, or the memory includes a table for conversion results, which table assigns at least one binary instruction in the first format to at least one binary instruction in the third format, wherein at least one binary instruction in the first format assigned to at least one binary instruction in the third format in the table is provided as a conversion result, or the memory includes a table for conversion results, which table assigns at least one binary instruction in the second format to at least one binary instruction in the third format, wherein at least one binary instruction in the second format assigned to at least one binary instruction in the third format in the table is provided as a conversion result.
[0023] Preferably, the conversion result for conversion is already stored in the memory and the conversion result is read from the memory, or the conversion result for conversion is confirmed to be unknown in the memory and the conversion result is calculated according to the command and stored in the memory.
[0024] Preferably, the first processor or the second processor comprises a hardware accelerator, wherein a configuration of the hardware accelerator is determined according to at least one binary instruction in the first format or at least one binary instruction in the third format.
[0025] A program including computer-readable instructions for carrying out the method when the computer executes the instructions has advantages corresponding to those of the method. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Further advantageous embodiments can be learned from the following description and the accompanying drawings. In the drawings: Figure 1 : a schematic illustration of a first embodiment of a device for providing binary instructions, Figure 2 : a schematic illustration of a second embodiment of a device for providing binary instructions, Figure 3 : A schematic illustration of a third embodiment of a device for providing binary instructions, Figure 4 : a schematic illustration of a fourth embodiment of a device for providing binary instructions, Figure 5 : A first embodiment of a method for providing binary instructions, Figure 6 : A second embodiment of the method for providing binary instructions. DETAILED DESCRIPTION
[0027] exist Figure 1 A first embodiment of a device 100 for providing binary instructions is schematically shown in FIG.
[0028] The device 100 includes a first processor 102 having a first architecture and a second processor 104 having a second architecture different from the first architecture.
[0029] The device 100 comprises an interface 106. The interface 106 is configured for receiving a first binary instruction 1 in a first format for binary instructions.
[0030] The device 100 comprises a means 108 designed to provide a first binary instruction 1 and a second binary instruction 2 in a second format different from the first format.
[0031] The device 108 is configured to provide a first binary instruction 1 in a first format for binary instructions.
[0032] The first processor 102 is configured to execute instructions in a first format. In this example, the first processor 102 is not suitable for executing binary instructions in a second format.
[0033] The second processor 104 is configured to execute instructions in the second format. In this example, the second processor 104 is not suitable for executing binary instructions in the first format.
[0034] The device 108 is designed to receive the first binary instruction 1 at the interface 106 and to determine the second binary instruction 2 as a function of the first binary instruction 1 .
[0035] The device 108 is designed to provide the instruction to be converted, namely the first binary instruction 1, to the first processor 102 for conversion. The first processor 102 is designed to provide a converted binary instruction, namely the second binary instruction 2, as a function of the instruction to be converted.
[0036] In this example, the first processor 102, the second processor 104 and the device 108 are integrated on a semiconductor 110. Figure 1 As shown in , the semiconductor device 110 may further include an interface 106. The interface 106 may also be arranged outside the semiconductor device. It may be provided that the device 108 is arranged outside the semiconductor device 110. It may be provided that each processor is provided with a semiconductor device 110.
[0037] In this example, an output of the results of executing the instructions supplied to the respective processor is provided via the interface 106 .
[0038] Device 100 optionally includes memory 112 .
[0039] Stored in the memory 112 are commands for converting binary instructions in one format into converted binary instructions in another format.
[0040] In a first embodiment, commands for converting binary instructions from a first format to a second format are stored.
[0041] The first processor 102 is designed to read a command from the memory 112 and to determine a converted binary instruction based on the command.
[0042] In this example, the command includes a table that assigns binary instructions in the second format to binary instructions in the first format to be converted. The first processor 102 is configured to find the converted second binary instruction assigned to the first binary instruction in the table and provide it to the device 108.
[0043] exist Figure 2 A second embodiment of a device 100 for providing binary instructions is schematically shown in FIG.
[0044] In contrast to the first embodiment, in the second embodiment, the interface 106 is designed to receive a third binary instruction 3 .
[0045] In contrast to the first embodiment, in the second embodiment, the device 108 is designed to receive the third binary instruction 3 at the interface 106 and to determine the first binary instruction 1 and the second binary instruction 2 as a function of the third binary instruction 3 .
[0046] The device 108 according to the second embodiment is configured to provide the instruction to be converted, namely the third binary instruction 3, to the first processor 102 for conversion. The first processor 102 according to the second embodiment is configured to provide the first binary instruction 1 and the second binary instruction 2 based on the third binary instruction 3.
[0047] Optionally, the device 100 according to the second embodiment includes a memory 112. Unlike the memory 112 according to the first embodiment, the memory 112 according to the second embodiment includes commands for converting binary instructions in the third format into binary instructions in the first format and into binary instructions in the second format. The first processor 102 according to the second embodiment is configured to read the commands from the memory 112 and determine the first binary instruction 1 and the second binary instruction 2 based on the commands.
[0048] In this example, the command includes a table that assigns binary instructions in the first format and binary instructions in the second format to a binary instruction in the third format to be converted. The first processor 102 according to the second embodiment is configured to find the first binary instruction 1 assigned to the third binary instruction 3 to be converted in the table and the second binary instruction 2 assigned to the first binary instruction 1 in the table and provide them to the device 108.
[0049] exist Figure 3 A third embodiment of a device 100 for providing binary instructions is schematically shown in FIG.
[0050] In contrast to the first embodiment, the device 100 according to the third embodiment comprises a third processor 302. The third processor 302 is designed to determine a conversion of the first binary instruction 1 into the second binary instruction 2.
[0051] Optionally, the third processor 302 is configured to determine the second binary instruction 2 according to the command from the memory 112 . For example, the third processor 302 is configured to find the second binary instruction 2 assigned to the first binary instruction 1 in the table and provide it to the device 108 .
[0052] exist Figure 4 A fourth embodiment of a device 100 for providing binary instructions is schematically shown in FIG.
[0053] In contrast to the second embodiment, the device 100 according to the fourth embodiment includes a third processor 302. The third processor 302 is designed to determine the conversion of the third binary instruction 3 into the first binary instruction 1 and the second binary instruction 2.
[0054] Optionally, the third processor 302 is configured to determine the first binary instruction 1 and the second binary instruction 2 according to a command from the memory 112. For example, the third processor 302 is configured to find the first binary instruction 1 assigned to the third binary instruction 3 in the table and the second binary instruction 2 assigned to the third binary instruction 3 in the table and provide them to the device 108.
[0055] First processor 102, second processor 104 and either device 108 or third processor 302 or both are preferably integrated on semiconductor 110. Optionally, either interface 106 or memory 112 or both are integrated on semiconductor 110.
[0056] It can be provided that the third processor 302 can be configured to convert binary instructions in one format into binary instructions in another format. It can be provided that the device 108 is configured to configure the third processor 302 to convert, for example, a command or table.
[0057] exist Figure 5 4. The steps according to a first embodiment of a computer-implemented method for providing binary instructions are shown in FIG.
[0058] In step 502 , a first binary instruction 1 is received.
[0059] In step 504 , a second binary instruction 2 is determined according to the first binary instruction 1 .
[0060] In step 504 - 1 , the first binary instruction 1 is provided to the first processor 102 for conversion.
[0061] In step 504 - 2 , the first processor 102 provides a second binary instruction 2 based on the first binary instruction 1 .
[0062] For example, a command for the conversion is stored in the memory 112. For example, provision is made for the first processor 102 to read the command and to determine the converted binary instruction based on the command.
[0063] For example, the command includes a table, for example, providing converted binary instructions that are assigned to binary instructions to be converted in the table.
[0064] As an alternative to determining the switchover with the aid of first processor 102 , provision may be made for determining the switchover with the aid of third processor 102 .
[0065] It may be provided that the third processor 302 is configured for converting binary instructions in the first format into binary instructions in the second format, for example, by generating or supplementing commands or tables with corresponding assignments.
[0066] In step 506 , a first binary instruction 1 and a second binary instruction 2 are provided.
[0067] In this example, a first binary instruction 1 is provided to the first processor 102 for execution. In this example, a second binary instruction 2 is provided to the second processor 104 for execution.
[0068] First binary instructions 1 are provided in a first format for binary instructions that are executable by a first processor 102 having a first architecture.
[0069] The second binary instructions 2 are provided in a second format different from the first format, and these binary instructions are executable by a second processor 104 having a second architecture different from the first architecture.
[0070] In this example, the result of executing the corresponding instruction on the corresponding processor is sent in step 508 .
[0071] exist Figure 6 4. Steps according to a second embodiment of a computer-implemented method for providing binary instructions are shown in FIG.
[0072] In step 602 , a third binary instruction 3 is received.
[0073] In step 604 , the first binary instruction 1 and the second binary instruction 2 are determined according to the third binary instruction 3 .
[0074] In step 604 - 1 , the third binary instruction 3 is provided to the first processor 102 for conversion.
[0075] In step 604 - 2 , the second binary instruction 2 and the first binary instruction 1 are provided by the first processor 102 according to the third binary instruction 3 .
[0076] For example, a command for the conversion is stored in the memory 112. For example, it is provided that the command is read by the first processor 102 and the converted binary instruction is determined based on the command.
[0077] For example, the command includes a table, for example, providing converted binary instructions that are assigned to binary instructions to be converted in the table.
[0078] As an alternative to determining the switchover with the aid of first processor 102 , provision may be made for determining the switchover with the aid of third processor 102 .
[0079] It may be provided that the third processor 302 is configured for converting binary instructions in the third format into binary instructions in the first format and binary instructions in the second format, for example, by generating or supplementing commands or tables with corresponding assignments.
[0080] In step 606 , a first binary instruction 1 and a second binary instruction 2 are provided.
[0081] In this example, the result of executing the corresponding instruction on the corresponding processor is sent in step 608 .
[0082] In two methods, it can be provided that the conversion result confirmed for conversion is stored in the memory 112 and the conversion result is read from the memory 112 .
[0083] In both methods, it may be provided that it is confirmed that the conversion result used for conversion is not known in the memory 112 , and the conversion result is calculated according to the command and stored in the memory 112 .
[0084] In one embodiment, the first processor 102 or the second processor 104 includes a hardware accelerator. The device 100 is configured to determine a configuration of the hardware accelerator based on at least one binary instruction 1 in the first format or at least one binary instruction 3 in the third format.
[0085] In the example, the binary instructions are converted into binary instructions for execution on the first processor 102 or the second processor 104. It can be provided that the first processor 102 or the second processor 104 includes a hardware accelerator. In this case, it can be provided that the binary instructions are also converted into binary instructions for configuring the hardware accelerator.
[0086] The hardware accelerator of the processor is configured to perform at least a portion of the calculations required to execute the binary instructions on the processor.
Claims
1. A device (100) for automated diversified redundant execution of binary instructions, characterized in that The device (100) comprises a first processor (102) having a first architecture and a second processor (104) having a second architecture, wherein the first processor (102) is configured to execute binary instructions in a first format, wherein the second processor (104) is configured to execute binary instructions in a second format different from the first format, wherein the device (100) is configured to provide at least one binary instruction (1) in the first format to the first processor (102) and to provide at least one binary instruction (2) in the second format that is redundant with the at least one first binary instruction (1) to the second processor (104), wherein The device (100) is configured to either receive at least one binary instruction (1) in the first format and determine at least one binary instruction (2) in the second format based on the at least one binary instruction (1) in the first format, or receive a binary instruction (3) in a third format for binary instructions that is different from the first format and the second format and that is redundant with at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format, and determine at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format based on the binary instruction (3) in the third format.
2. The device (100) according to claim 1, characterized in that The device (100) is configured to provide at least one binary instruction (1) in the first format to the first processor (102) for conversion, wherein the first processor (102) is configured to provide at least one binary instruction (2) in the second format based on the at least one instruction (2) in the first format, or the device (100) is configured to provide at least one binary instruction (3) in the third format to the first processor (102) for conversion, wherein the first processor (102) is configured to provide at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format based on the binary instruction (3) in the third format.
3. The device (100) according to claim 1, characterized in that The device (100) is configured to provide at least one binary instruction (1) in the first format to a third processor (302) for conversion, wherein the third processor (302) is configured to provide at least one binary instruction (2) in the second format based on the at least one binary instruction (1) in the first format, or the device (100) is configured to provide binary instructions (3) in the third format to the third processor (104) for conversion, wherein the third processor (104) is configured to provide at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format based on the binary instruction (3) in the third format.
4. The device according to claim 3, characterized in that The third processor (302) is configured to convert at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format, wherein the device (100) is configured to configure the third processor (302) to convert at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format, or the third processor (302) is configured to convert at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format, wherein the device (100) is configured to configure the third processor (302) to convert at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format, or the third processor (302) is configured to convert at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format, wherein the device (100) is configured to configure the third processor (302) to convert at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format.
5. The device according to any one of the preceding claims, characterized in that The device (100) includes a memory (112) in which a command for converting at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format is stored, wherein the device (100) is configured to read the command from the memory (112) and determine at least one binary instruction (2) in the second format based on the command and the at least one binary instruction (1) in the first format, or the device (100) includes a memory (112) in which a command for converting at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format is stored, wherein the The device (100) is configured to read the command from the memory (112) and determine the at least one binary instruction (1) in the first format based on the command and the at least one binary instruction (3) in the third format, or the device (100) includes a memory (112) in which a command for converting the at least one binary instruction (3) in the third format into the at least one binary instruction (2) in the second format is stored, wherein the device (100) is configured to read the command from the memory (112) and determine the at least one binary instruction (2) in the second format based on the command and the at least one binary instruction (3) in the third format.
6. Apparatus according to any preceding claim, characterised in that The device (100) includes a memory (112) in which a conversion result of converting at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format is stored, wherein the device (100) is configured to read the conversion result from the memory (112) and determine at least one binary instruction (2) in the second format based on the conversion result, or the device (100) includes a memory (112) in which a conversion result of converting at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format is stored. The device (100) is configured to read the conversion result from the memory (112) and determine at least one binary instruction (1) in the first format based on the conversion result, or the device (100) includes a memory (112) in which a conversion result of converting at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format is stored, wherein the device (100) is configured to read the conversion result from the memory (112) and determine at least one binary instruction (2) in the second format based on the conversion result.
7. The device according to claim 6, characterized in that The memory (112) includes a table for the conversion results, the table assigning at least one binary instruction (2) in the second format to at least one binary instruction (1) in the first format, wherein the device (100) is constructed to provide at least one binary instruction (2) in the second format assigned to at least one binary instruction (1) in the first format as the conversion result, or the memory (112) includes a table for the conversion results, the table assigning at least one binary instruction (1) in the first format to at least one binary instruction (3) in the third format, wherein the The device (100) is constructed to provide at least one binary instruction (1) in the first format that is assigned to at least one binary instruction (3) in the third format in the table as the conversion result, or the memory (112) includes a table for the conversion result, which assigns at least one binary instruction (2) in the second format to at least one binary instruction (3) in the third format, wherein the device (100) is constructed to provide at least one binary instruction (2) in the second format that is assigned to at least one binary instruction (3) in the third format in the table as the conversion result.
8. The device (100) according to any one of claims 5 to 7, characterized in that The device (100) is configured to confirm that the conversion result for the conversion has been stored in the memory (112) and read the conversion result from the memory (112), or to confirm that the conversion result for the conversion is unknown in the memory (112) and calculate the conversion result according to the command and store the conversion result in the memory (112).
9. The device (100) according to any of the preceding claims, characterized in that The first processor (102) or the second processor (104) includes a hardware accelerator, wherein the device (100) is configured to determine a configuration of the hardware accelerator based on at least one binary instruction (1) in the first format or at least one binary instruction (3) in the third format.
10. A computer-implemented or hardware-implemented method for automated diversified redundant execution of binary instructions, characterized in that: At least one binary instruction (1) in a first format is provided (506, 606) to a first processor (102) having a first architecture and configured to execute binary instructions in a first format, and at least one binary instruction (2) in a second format that is redundant with the at least one binary instruction (1) in the first format is provided (506, 606) to a second processor (104) having a second architecture different from the first architecture and configured to execute binary instructions in a second format different from the first format, wherein the at least one binary instruction (1) in the first format is received (502) and the at least one binary instruction (2) in the second format is determined (504) based on the at least one binary instruction (1) in the first format, or a binary instruction (3) in a third format that is different from the first format and different from the second format for binary instructions that is redundant with the at least one binary instruction (1) in the first format and with the at least one binary instruction (2) in the second format is received (602) and the binary instruction (1) in the first format and the binary instruction (2) in the second format is determined (604) based on the binary instruction (3) in the third format are determined (604).
11. The method according to claim 10, characterized in that At least one binary instruction (1) in the first format is provided (504-1) to the first processor (102) for conversion, wherein at least one binary instruction (2) in the second format is provided (504-2) by means of the first processor (102) based on the at least one instruction (1) in the first format, or at least one binary instruction (3) in the third format is provided (604-1) to the first processor (102) for conversion, wherein at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format are provided (604-2) by means of the first processor (102) based on the binary instruction (3) in the third format.
12. The method according to claim 10, characterized in that Providing (504-1) at least one binary instruction (1) in the first format to a third processor (302) for conversion, wherein the third processor (302) provides (504-2) at least one binary instruction (2) in the second format based on the at least one binary instruction (1) in the first format, or providing (604-1) the binary instruction (3) in the third format to the third processor (104) for conversion, wherein the third processor (104) provides (604-2) at least one binary instruction (1) in the first format and at least one binary instruction (2) in the second format based on the binary instruction (3) in the third format.
13. The method according to claim 12, characterized in that The third processor (302) is configured to convert at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format, wherein the third processor (302) is configured to convert at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format, or the third processor (302) is configured to convert at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format, wherein the third processor (302) is configured to convert at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format, or the third processor (302) is configured to convert at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format, wherein the third processor (302) is configured (504, 604) to convert at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format.
14. Method according to any one of the preceding claims 10 to 13, characterized in that A command for converting at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format is stored in the memory (112), wherein the command is read from the memory (112) and at least one binary instruction (2) in the second format is determined (504-2) based on the command and the at least one binary instruction (1) in the first format, or a command for converting at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format is stored in the memory (112), wherein the command is read from the memory (112) and at least one binary instruction (1) in the first format is determined (604-2) based on the command and the at least one binary instruction (3) in the third format, or a command for converting at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format is stored in the memory (112), wherein the command is read from the memory (112) and at least one binary instruction (2) in the second format is determined (604-2) based on the command and the at least one binary instruction (3) in the third format.
15. Method according to any one of the preceding claims 10 to 14, characterized in that A conversion result of converting at least one binary instruction (1) in the first format into at least one binary instruction (2) in the second format is stored in the memory (112), wherein the conversion result is read from the memory (112) and at least one binary instruction (2) in the second format is determined based on the conversion result, or a conversion result of converting at least one binary instruction (3) in the third format into at least one binary instruction (1) in the first format is stored in the memory (112), wherein the conversion result is read from the memory (112) and at least one binary instruction (1) in the first format is determined based on the conversion result, or a conversion result of converting at least one binary instruction (3) in the third format into at least one binary instruction (2) in the second format is stored in the memory (112), wherein the conversion result is read from the memory (112) and at least one binary instruction (2) in the second format is determined based on the conversion result.
16. The method according to claim 15, characterized in that The memory (112) includes a table for the conversion results, the table assigning at least one binary instruction (2) in the second format to at least one binary instruction (1) in the first format, wherein the at least one binary instruction (2) in the second format assigned to the at least one binary instruction (1) in the first format in the table is provided as the conversion result, or the memory (112) includes a table for the conversion results, the table assigning at least one binary instruction (1) in the first format to at least one binary instruction (3) in the third format, wherein the at least one binary instruction (1) in the first format assigned to the at least one binary instruction (3) in the third format in the table is provided as the conversion result, or the memory (112) includes a table for the conversion results, the table assigning at least one binary instruction (2) in the second format to at least one binary instruction (3) in the third format, wherein the at least one binary instruction (2) in the second format assigned to the at least one binary instruction (3) in the third format in the table is provided as the conversion result.
17. The method (100) according to any one of claims 14 to 16, characterized in that Confirming that the conversion result for the conversion has been stored in the memory (112) and reading the conversion result from the memory (112), or confirming that the conversion result for the conversion is unknown in the memory (112) and calculating the conversion result according to the command and storing the conversion result in the memory (112).
18. The method according to any one of claims 10 to 17, characterized in that The first processor (102) or the second processor (104) includes a hardware accelerator, wherein a configuration of the hardware accelerator is determined according to at least one binary instruction (1) in the first format or at least one binary instruction (3) in the third format.
19. A program, characterized in that The program includes computer-readable instructions, and when the instructions are executed by a computer, the method according to any one of claims 10 to 18 is performed.