Display driving circuit, display panel and intelligent terminal

Abstract

The invention provides a display driving circuit, a display panel and an intelligent terminal, the display driving circuit comprises a grid electrode scanning circuit and a source electrode driving circuit, when an Mth frame of image is displayed, the grid electrode scanning circuit is used for controlling a (2i-1) th row of pixel units and a 2i-th row of pixel units to synchronously start scanning, the source driving circuit is used for writing the image data of the (2i-1) th row in the Mth frame into the (2i-1) th row of pixel units and the (2i) th row of pixel units which start scanning synchronously; when an (M + 1) th frame of image is displayed, the grid electrode scanning circuit is used for controlling the 2i-th row of pixel units and the (2i + 1) th row of pixel units to synchronously start scanning, and the source electrode driving circuit is used for writing image data of the 2i-th row in the (M + 1) th frame into the 2i-th row of pixel units and the (2i + 1) th row of pixel units which synchronously start scanning. According to the display driving circuit provided by the invention, the display refresh rate can be improved, inter-line image information position compensation can be provided, and related problems such as image edge and oblique line information display sawteeth can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit, a display panel and a smart terminal. Background Art

[0002] Existing display panels typically use a row-by-row refresh method to update the screen. That is, starting from the first row of pixels in the display panel, the gate scan line corresponding to each row of pixels is activated from top to bottom. During the period when each gate scan line is turned on, the pixels in that row are charged through the data line to write the image data corresponding to the row of pixels to achieve screen refresh.

[0003] However, with the increase in display panel resolution, especially for display devices with larger resolution along the scanning direction (such as smartphones, tablets, etc.), sufficient charging time is required during row scanning to ensure the uniformity of the picture display. Therefore, it is difficult to further increase the display refresh rate after meeting the charging time limit.

[0004] In order to further improve the display refresh rate while ensuring sufficient pixel charging time, the inventors attempted to simultaneously control multiple adjacent rows of pixel units to start scanning synchronously, and only input image data of one row into the multiple rows of pixel units at the same position in consecutive frames to reduce the row scanning time of a single frame image. However, this solution has a good display effect on displays with a higher pixel density (PPI, Pixels Per Inch) (such as smartphones). However, on displays with a lower PPI (such as large-screen monitors), when using this solution to display image edges and diagonal line information, the jagged effect is more obvious, and the display effect needs to be improved.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] In response to the above technical problems, the present application provides a display driving circuit, a display panel and a smart terminal, which can provide inter-line image information position compensation while improving the display refresh rate, and improve related problems such as jagged edges and oblique line information display.

[0007] In a first aspect, the present application provides a display driving circuit, comprising a gate scanning circuit and a source driving circuit. When displaying the Mth frame image, the gate scanning circuit is used to control the 2i-1th row of pixel units and the 2ith row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are started scanning synchronously; When displaying the M+1th frame image, the gate scanning circuit is used to control the 2ith row of pixel units and the 2i+1th row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2ith row in the M+1th frame into the 2ith row of pixel units and the 2i+1th row of pixel units that are started scanning synchronously.

[0008] Optionally, the gate scanning circuit includes a first cascade driving circuit and / or a second cascade driving circuit; The first cascade drive circuit and / or the second cascade drive circuit each include a first control line, a first switch element, a plurality of second switch elements, and / or a second control line, a third switch element, a plurality of fourth switch elements; The control ends of the first switch element and the second switch element are both connected to the first control line, and the control ends of the third switch element and the fourth switch element are both connected to the second control line; When the M-th frame image is displayed, the first control line controls the first switching element and the second switching element to be turned on; When the (M+1)th frame image is displayed, the second control line controls the third switching element and the fourth switching element to be turned on.

[0009] Optionally, the first cascade driving circuit and / or the second cascade driving circuit further include a plurality of mutually cascaded first GOA units and a plurality of mutually cascaded second GOA units; the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit; The first path end of the first switch element is used to receive the initial scanning signal corresponding to the Mth frame, and the second path end of the first switch element is connected to the input end of the first GOA unit corresponding to the first odd-numbered row of pixel units; The first path end of the second switch element is connected to the input end of the scan line of the pixel unit in the 2i-1th row, and the second path end of the second switch element is connected to the input end of the scan line of the pixel unit in the 2ith row; The first channel end of the third switch element is used to receive the initial scanning signal corresponding to the M+1th frame, and the second channel end of the third switch element is connected to the input end of the second GOA unit corresponding to the first even-numbered row of pixel units; The first channel end of the fourth switch element is connected to the input end of the scan line of the 2i-th row of pixel units, and the second channel end of the fourth switch element is connected to the input end of the scan line of the 2i+1-th row of pixel units.

[0010] In a second aspect, the present application also provides a display driving circuit, comprising a mode selection module, a gate scanning circuit and a source driving circuit, The mode selection module is configured to generate a first mode selection signal or a second mode selection signal to control the display driving circuit to enter a first working mode or a second working mode. In the first working mode, when displaying an M-1th frame of image, the gate scanning circuit is configured to control i-th row of pixel units to be turned on for scanning, and the source driving circuit is configured to write image data of i-th row in the M-1th frame into the i-th row of pixel units turned on for scanning. In the second working mode, when displaying an Mth frame of image, the gate scanning circuit is configured to control 2i-1-th row of pixel units and 2i-th row of pixel units to be turned on for scanning synchronously, and the source driving circuit is configured to write image data of 2i-1-th row in the Mth frame into the 2i-1-th row of pixel units and the 2i-th row of pixel units turned on for scanning synchronously; when displaying an M+1th frame of image, the gate scanning circuit is configured to control 2i-th row of pixel units and 2i+1-th row of pixel units to be turned on for scanning synchronously, and the source driving circuit is configured to write image data of 2i-th row in the M+1th frame into the 2i-th row of pixel units and the 2i+1-th row of pixel units turned on for scanning synchronously.

[0011] Optionally, the gate scanning circuit comprises a first cascade driving circuit and a second cascade driving circuit. The first cascade driving circuit comprises a first control line, a plurality of first switching elements, and / or a second control line, a plurality of second switching elements, and a plurality of third switching elements; control ends of the first switching elements are connected with the first control line, and control ends of the second switching elements and the third switching elements are connected with the second control line. The second cascade driving circuit comprises a first control line, a plurality of fourth switching elements, and / or a third control line, a plurality of fifth switching elements, and a plurality of sixth switching elements; control ends of the fourth switching elements are connected with the first control line, and control ends of the fifth switching elements and the sixth switching elements are connected with the third control line. In the first working mode, the first control line controls the first switching elements and the fourth switching elements to be turned on. In the second working mode, when displaying the Mth frame of image, the second control line controls the second switching elements and the third switching elements to be turned on; when displaying the M+1th frame of image, the third control line controls the fifth switching elements and the sixth switching elements to be turned on.

[0012] Optionally, the first cascade driving circuit and the second cascade driving circuit each comprise a plurality of first GOA units and a plurality of second GOA units cascaded with each other; a first output end of the first GOA unit is connected with a scan line of a corresponding odd row pixel unit, and a first output end of the second GOA unit is connected with a scan line of a corresponding even row pixel unit; a first pass end of the first switch element is connected with a second output end of the first GOA unit, and a second pass end of the first switch element is connected with an input end of the second GOA unit; a first pass end of the second switch element is used for receiving an initial scan signal corresponding to an Mth frame or is connected with a second output end of the first GOA unit, and a second pass end of the second switch element is connected with an input end of a first GOA unit corresponding to a next odd row pixel unit; a first pass end of the third switch element is connected with an input end of a scan line of the 2i-1th row pixel unit, and a second pass end of the third switch element is connected with an input end of a scan line of the 2i th row pixel unit; a first pass end of the fourth switch element is used for receiving an initial scan signal corresponding to an M-1th frame or is connected with a second output end of the second GOA unit, and a second pass end of the fourth switch element is connected with an input end of the first GOA unit; a first pass end of the fifth switch element is used for receiving an initial scan signal corresponding to an M+1th frame or is connected with a second output end of the second GOA unit, and a second pass end of the fifth switch element is connected with an input end of a second GOA unit corresponding to a next even row pixel unit; a first pass end of the sixth switch element is connected with an input end of a scan line of the 2i th row pixel unit, and a second pass end of the sixth switch element is connected with an input end of a scan line of the 2i+1th row pixel unit.

[0013] Optionally, the gate scanning circuit comprises a first cascade driving circuit and / or a second cascade driving circuit; The first cascade driving circuit and / or the second cascade driving circuit each comprises a first control line, a plurality of first switch elements, and / or a second control line, a plurality of second switch elements, a plurality of third switch elements, and / or a third control line, a plurality of fourth switch elements, a plurality of fifth switch elements; control ends of the second switch elements and the third switch elements are each connected with the second control line, and control ends of the fourth switch elements and the fifth switch elements are each connected with the third control line; In the first working mode, the first control line controls the first switch element to be turned on; In the second working mode, when the Mth frame image is displayed, the second control line controls the second switching element and the third switching element to be turned on; when the M+1th frame image is displayed, the third control line controls the fourth switching element and the fifth switching element to be turned on.

[0014] Optionally, the first cascade driving circuit and / or the second cascade driving circuit further include a plurality of first GOA units and a plurality of second GOA units, and the first GOA units and the second GOA units are cascaded to each other through the first switching element; the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit; The first switch element is further connected to the input end of the first GOA unit corresponding to the first row of pixel units, and is used to receive the initial scanning signal corresponding to the M-1th frame; The first path end of the second switch element is used to receive the initial scanning signal corresponding to the Mth frame, or is connected to the second output end of the first GOA unit, and the second path end of the second switch element is connected to the input end of the first GOA unit corresponding to the next odd-numbered row of pixel units; The first channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2i-1th row, and the second channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2ith row; The first channel end of the fourth switch element is used to receive the initial scanning signal corresponding to the M+1th frame, or is connected to the second output end of the second GOA unit, and the second channel end of the fourth switch element is connected to the input end of the second GOA unit corresponding to the next even-numbered row of pixel units; The first channel end of the fifth switch element is connected to the input end of the scan line of the 2i-th row of pixel units, and the second channel end of the fifth switch element is connected to the input end of the scan line of the 2i+1-th row of pixel units.

[0015] In a third aspect, the present application further provides a display driving method, comprising the following steps: S110: When displaying the M-th frame image, write the image data of the 2i-1-th row in the M-th frame into the 2i-1-th row pixel units and the 2i-th row pixel units that are synchronously scanned; S120: When displaying the M+1th frame image, write the image data of the 2ith row in the M+1th frame into the 2ith row pixel units and the 2i+1th row pixel units that are synchronously scanned. Wherein, M and i are both positive integers.

[0016] Optionally, the method further includes: Entering the first working mode when the first mode selection signal is enabled, writing the image data of the i-th row in the M-1-th frame into the i-th row of pixel units that are started to scan, so as to display the M-th frame image; When the second mode selection signal is enabled, the second operating mode is entered to proceed to step S110 .

[0017] In a third aspect, the present application further provides a display panel comprising the display driving circuit as described above.

[0018] In a fourth aspect, the present application also provides a smart terminal comprising the display panel as described above.

[0019] As described above, the display driver circuit provided by the present application includes a gate scanning circuit and a source driver circuit. When displaying the Mth frame image, the gate scanning circuit controls the synchronous scanning of the pixel units in the 2i-1th row and the pixel units in the 2ith row, and the source driver circuit writes the image data of the 2i-1th row in the Mth frame into the pixel units in the 2i-1th row and the pixel units in the 2ith row that are synchronously scanned. When displaying the M+1th frame image, the gate scanning circuit controls the synchronous scanning of the pixel units in the 2ith row and the pixel units in the 2i+1th row, and the source driver circuit writes the image data of the 2ith row in the M+1th frame into the pixel units in the 2ith row and the pixel units in the 2i+1th row that are synchronously scanned. In this way, the gate scanning circuit and the source driver circuit control the time-sharing alternating display of the odd and even rows of the image, and the second frame in which the odd and even rows are alternately displayed is displayed offset by one row, thereby achieving complementary image information between two adjacent frames, thereby effectively improving the display effect of image edges and oblique line information while increasing the display refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without inventive work.

[0021] Figure 1 A schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application.

[0022] Figure 2 A communication network system architecture diagram provided for an embodiment of the present application.

[0023] Figure 3This is a schematic diagram of the time-sharing alternating display of odd and even row information at the same position in high-frequency refresh mode.

[0024] Figure 4 This is a schematic diagram of the display effect of the diagonal lines when the odd and even row information at the same position is displayed alternately in time sharing.

[0025] Figure 5 FIG. 1 is a flow chart of a display driving method according to the first embodiment.

[0026] Figure 6 This is a schematic diagram of the staggered and alternating display of odd and even row information in high-frequency refresh mode.

[0027] Figure 7 This is a schematic diagram comparing the display effects of diagonal lines when odd and even row information is displayed alternately and staggered.

[0028] Figure 8 FIG. 4 is a schematic structural diagram of a display driving circuit according to a second embodiment.

[0029] Figure 9 FIG. 4 is a flow chart of a display driving method according to a third embodiment.

[0030] Figure 10 FIG. 4 is a schematic structural diagram of a display driving circuit according to a fourth embodiment.

[0031] Figure 11 FIG. 5 is a schematic structural diagram of a display driving circuit according to a fifth embodiment.

[0032] Figure 12 FIG. 4 is a schematic structural diagram of a display driving circuit according to a sixth embodiment.

[0033] Figure 13 FIG. 4 is a schematic diagram of a scanning sequence in the first working mode according to the sixth embodiment.

[0034] Figure 14 FIG. 1 is a timing diagram of odd frames in the second working mode according to the sixth embodiment.

[0035] Figure 15 FIG. 1 is a timing diagram of even frames in the second working mode according to the sixth embodiment.

[0036] The purpose of this application, its features, and advantages will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and the accompanying text are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of this application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0038] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0039] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are used solely to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if," as used herein, may be interpreted as "upon," "when," or "in response to a determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising" and "including" indicate the presence of the recited features, steps, operations, elements, components, items, types, and / or groups, but do not preclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or," "and / or," "including at least one of the following," etc., as used herein, may be interpreted as inclusive, meaning any one or any combination. For example, “comprising at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”; and for another example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.

[0040] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0041] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0042] It should be noted that in this article, step codes such as S10 and S20 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the scope of protection of this application.

[0043] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0044] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0045] Smart terminals can be implemented in various forms. For example, the smart terminals described in this application may include smart terminals such as mobile phones, tablet computers, laptop computers, PDAs, portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as fixed terminals such as digital TVs and desktop computers.

[0046] The subsequent description will be made by taking a mobile terminal as an example. It will be understood by those skilled in the art that, in addition to components specifically used for mobile purposes, the configuration according to the embodiments of the present application can also be applied to fixed-type terminals.

[0047] See also Figure 1 , which is a schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application. The mobile terminal 100 may include: an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an A / V (Audio / Video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and a power supply 111. Those skilled in the art will understand that Figure 1 The mobile terminal structure shown in the figure does not constitute a limitation on the smart terminal. The smart terminal may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0048] The following combination Figure 1 A detailed introduction to the various components of the mobile terminal: The RF unit 101 can be used to send and receive information or receive signals during calls. Specifically, it receives downlink information from the base station and transmits it to the processor 110 for processing. It also transmits uplink data to the base station. Typically, the RF unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, and more. Furthermore, the RF unit 101 can communicate with the network and other devices via wireless communication. The above-mentioned wireless communications may use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing- Long Term Evolution), TDD-LTE (Time Division Duplexing- Long Term Evolution) and 5G, etc.

[0049] WiFi is a short-range wireless transmission technology. Mobile terminals can help users send and receive emails, browse web pages, and access streaming media through the WiFi module 102. It provides users with wireless broadband Internet access. Figure 1 The WiFi module 102 is shown, but it is understandable that it is not an essential component of the mobile terminal and can be omitted as needed without changing the essence of the invention.

[0050] The audio output unit 103 can convert audio data received by the RF unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output it as sound when the mobile terminal 100 is in a call signal reception mode, a talk mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Furthermore, the audio output unit 103 can also provide audio output related to a specific function performed by the mobile terminal 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 may include a speaker, a buzzer, or the like.

[0051] The A / V input unit 104 is used to receive audio or video signals. The A / V input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data from still images or videos captured by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the GPU 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the RF unit 101 or the WiFi module 102. The microphone 1042 can receive sound (audio data) in various operating modes, such as phone call mode, recording mode, and voice recognition mode, and process such sound into audio data. In phone call mode, the processed audio (voice) data may be converted into a format that can be transmitted to a mobile communication base station via the RF unit 101. The microphone 1042 may implement various noise cancellation (or suppression) algorithms to eliminate (or suppress) noise or interference generated during the reception and transmission of audio signals.

[0052] The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, or other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor. Optionally, the ambient light sensor can adjust the brightness of the display panel 1061 based on the brightness of the ambient light, and the proximity sensor can turn off the display panel 1061 and / or the backlight when the mobile terminal 100 is brought to your ear. An accelerometer, a type of motion sensor, can detect acceleration in all directions (typically three axes) and, when stationary, can detect the magnitude and direction of gravity. This can be used for applications that recognize the phone's posture (e.g., switching between landscape and portrait modes, related games, magnetometer posture calibration), vibration recognition-related functions (e.g., pedometer, tapping), and other functions. Other sensors that may be configured on a mobile phone, such as a fingerprint sensor, pressure sensor, iris sensor, molecular sensor, gyroscope, barometer, hygrometer, thermometer, infrared sensor, etc., are not described here.

[0053] The display unit 106 is used to display information input by the user or information provided to the user. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0054] The user input unit 107 can be used to receive input digital or character information and generate key signal input related to user settings and function control of the mobile terminal. Optionally, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also known as a touch screen, can detect user touch operations on or near it (for example, operations performed on or near the touch panel 1071 using a finger, stylus, or any other suitable object or accessory) and drive corresponding connected devices according to pre-set programs. The touch panel 1071 may include a touch detection device and a touch controller. Optionally, the touch detection device detects the user's touch position and detects signals generated by the touch operation, transmitting the signals to the touch controller. The touch controller receives the touch information from the touch detection device, converts it into touch point coordinates, and then sends it to the processor 110. The touch controller can also receive and execute commands from the processor 110. Furthermore, the touch panel 1071 can be implemented using various types of sensors, including resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may further include other input devices 1072. Optionally, the other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, power keys, etc.), a trackball, a mouse, a joystick, etc., and the specifics are not limited here.

[0055] Optionally, the touch panel 1071 may cover the display panel 1061. When the touch panel 1071 detects a touch operation on or near it, it transmits the information to the processor 110 to determine the type of touch event. The processor 110 then provides a corresponding visual output on the display panel 1061 according to the type of touch event. Figure 1 In the embodiment, the touch panel 1071 and the display panel 1061 are two independent components to realize the input and output functions of the mobile terminal. However, in some embodiments, the touch panel 1071 and the display panel 1061 can be integrated to realize the input and output functions of the mobile terminal, which is not limited here.

[0056] The interface unit 108 serves as an interface through which at least one external device can be connected to the mobile terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the mobile terminal 100 or may be used to transmit data between the mobile terminal 100 and an external device.

[0057] Memory 109 can be used to store software programs and various data. Memory 109 may primarily include a program storage area and a data storage area. Optionally, the program storage area may store an operating system and at least one application required for a function (such as sound playback or image playback); the data storage area may store data generated based on the use of the phone (such as audio data and a phone book). Memory 109 may also include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0058] Processor 110 is the control center of the mobile terminal, connecting all components of the mobile terminal using various interfaces and circuits. By running or executing software programs and / or modules stored in memory 109 and accessing data stored in memory 109, it executes various functions of the mobile terminal and processes data, thereby providing overall monitoring of the mobile terminal. Processor 110 may include one or more processing units; preferably, processor 110 may integrate an application processor and a modem processor. Optionally, the application processor primarily handles the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into processor 110.

[0059] The mobile terminal 100 may further include a power supply 111 (such as a battery) for supplying power to various components. Preferably, the power supply 111 may be logically connected to the processor 110 via a power management system, thereby enabling the power management system to manage charging, discharging, and power consumption.

[0060] although Figure 1 Not shown, the mobile terminal 100 may further include a Bluetooth module, etc., which will not be described in detail here.

[0061] To facilitate understanding of the embodiments of the present application, the communication network system on which the mobile terminal of the present application is based is described below.

[0062] See also Figure 2 , Figure 2 A communication network system architecture diagram is provided for an embodiment of the present application. The communication network system is an LTE system of universal mobile communication technology. The LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203 and an operator's IP service 204, which are connected in sequence.

[0063] Optionally, UE201 may be the above-mentioned terminal 100, which will not be described in detail here.

[0064] E-UTRAN 202 includes eNodeB 2021 and other eNodeBs 2022 . Optionally, eNodeB 2021 may be connected to other eNodeBs 2022 via a backhaul (eg, an X2 interface). eNodeB 2021 is connected to EPC 203 , and eNodeB 2021 may provide UE 201 with access to EPC 203 .

[0065] The EPC 203 may include an MME (Mobility Management Entity) 2031, an HSS (Home Subscriber Server) 2032, other MMEs 2033, an SGW (Serving GateWay) 2034, a PGW (PDN GateWay) 2035, and a PCRF (Policy and Charging Rules Function) 2036. Optionally, the MME 2031 is a control node that processes signaling between the UE 201 and the EPC 203, providing bearer and connection management. The HSS 2032 provides registers for managing functions such as the Home Location Register (not shown) and stores user-specific information such as service features and data rates. All user data can be sent through SGW2034. PGW2035 can provide IP address allocation and other functions for UE 201. PCRF2036 is the policy and charging control policy decision point for service data flows and IP bearer resources. It selects and provides available policy and charging control decisions for the policy and charging execution function unit (not shown in the figure).

[0066] The IP service 204 may include the Internet, an intranet, an IMS (IP Multimedia Subsystem), or other IP services.

[0067] Although the above introduction takes the LTE system as an example, those skilled in the art should know that this application is not only applicable to the LTE system, but also to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, 5G and future new network systems (such as 6G), etc., which are not limited here.

[0068] Based on the above-mentioned mobile terminal hardware structure and communication network system, various embodiments of the present application are proposed.

[0069] The display panel in this application uses GOA (Gate on Array) technology to replace traditional external gate driver chips, reducing product costs and achieving a narrow bezel design. GOA technology integrates gate driver circuitry directly onto the display panel's array substrate. Cascaded GOA units output corresponding gate scan signals to refresh the display image.

[0070] See also Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the time-sharing alternating display of odd and even row information at the same position in high-frequency refresh mode. Figure 4 This is a schematic diagram of the display effect of the diagonal lines when the odd and even rows of information at the same position are displayed alternately in time. In order to ensure that the pixel charging time is sufficient, the inventors use the method of simultaneously controlling the adjacent odd-row pixel units and even-row pixel units to start scanning synchronously, and inputting the image data of the odd rows or the image data of the even rows to the odd-row pixel units and even-row pixel units that start scanning synchronously, or inputting the image data of the odd rows and the image data of the even rows alternately, so as to achieve the effect of improving the display refresh rate. Figure 3 As shown, when refreshing the odd-numbered frame, the image data of the odd-numbered row (2i-1 row) is input to the odd-numbered row (e.g., row 2i) and even-numbered row (e.g., row 2i) pixel units that start scanning synchronously; when refreshing the even-numbered frame, the image data of the even-numbered row (2i row) is input to the odd-numbered row (2i-1 row) and even-numbered row (2i row) pixel units at the same position. Figure 4 As shown, although this solution can reduce the refresh time of the screen, the image information of even or odd rows is omitted during the refresh process, resulting in obvious jagged edges on the image, especially when diagonal lines are displayed. To address the above technical problems, the present application provides a display driver circuit, display panel, and smart terminal that can improve the display refresh rate while improving the jaggedness problem of image edges and diagonal line information display.

[0071] First embodiment See also Figure 5 、 Figure 6 and Figure 7 , Figure 5 is a flow chart of a display driving method according to the first embodiment. Figure 6 This is a schematic diagram of the alternating display of odd and even row information in high-frequency refresh mode. Figure 7 This is a schematic diagram comparing the display effects of diagonal lines when odd and even row information is displayed alternately and staggered.

[0072] like Figure 5As shown, the display driving method of the embodiment of the present application can be applied to the display panel in the smart terminal, and specifically includes the following steps: Step S110 : when displaying the Mth frame image, writing the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are synchronously turned on for scanning.

[0073] Step S120 : when displaying the M+1th frame image, writing the image data of the 2ith row in the M+1th frame into the pixel units of the 2ith row and the pixel units of the 2i+1th row that are synchronously turned on for scanning.

[0074] It is understood that M and i in the embodiments of the present application are both positive integers. In this embodiment, the Mth frame image may represent an odd-numbered frame during an image refresh process, and the M+1th frame image may represent an even-numbered frame during an image refresh process; or the Mth frame image may represent the first frame in which odd-numbered and even-numbered lines of image information are alternately displayed, and the M+1th frame image may represent the second frame in which odd-numbered and even-numbered lines of image information are alternately displayed.

[0075] like Figure 6 As shown, when displaying an odd-numbered frame, the adjacent odd-numbered row pixel units and even-numbered row pixel units are sequentially synchronized and scanned, and the image data of the odd-numbered row pixel units are written into the synchronously scanned adjacent odd-numbered row pixel units and even-numbered row pixel units, such as writing the image data of the 2i-1th row pixel units and the 2ith row pixel units, and writing the image data of the 2i+1th row pixel units and the 2i+1th row pixel units, respectively. When displaying an even-numbered frame, the adjacent even-numbered row pixel units and odd-numbered row pixel units are sequentially synchronized and scanned, and the image data of the even-numbered row pixel units are written into the synchronously scanned adjacent even-numbered row pixel units and odd-numbered row pixel units, such as writing the image data of the 2ith row pixel units and the 2i+1th row pixel units, and writing the image data of the 2i+2th row pixel units and the 2i+3th row pixel units, respectively.

[0076] In this embodiment, by controlling the synchronization of scanning of two adjacent rows of pixel units, the refresh time of the image is reduced, and by omitting the image information of odd or even rows, the amount of transmitted data is halved. However, when refreshing the second frame of the image in the even frame or the alternating display of odd and even rows, the input image data is shifted downward by one row, such as Figure 7As shown, when displaying diagonal information, the aliasing effect of the staggered alternating display of odd and even line information is significantly improved compared to the staggered alternating display of odd and even line information in the same position. It is understandable that in high-frequency refresh mode, since the refresh frequency is much higher than the fusion threshold of the human eye, the human eye will average the brightness of the two adjacent frames of the image during time integration. Displaying the second frame in which the odd and even line information is alternately displayed is staggered by one line, which is equivalent to compensating for the missing even line information in the same position of the previous frame by the even line data of the subsequent frame, thereby achieving the complementarity of the image information of the two adjacent frames. At the same time, since the even line data in the alternatingly displayed staggered frame supplements the step difference of the odd line data in the previous frame, the vertical quantization step of the diagonal display is reduced from 2 pixels to 1 pixel, so the subjectively perceived aliasing effect is reduced, which can effectively improve the display effect of the image edge and diagonal line information while improving the display refresh rate.

[0077] Second embodiment See also Figure 8 , Figure 8 2 is a schematic diagram of a display driving circuit according to the second embodiment. The display driving circuit of the embodiment of the present application can be applied to a display panel of a smart terminal and can be used to implement the display driving method described in the first embodiment.

[0078] The display driver circuit in this embodiment may include a gate scanning circuit and a source driver circuit. It will be appreciated that the gate scanning circuit is connected to the scan lines corresponding to each row of pixel units in the display area, and controls the pixel units to be turned on via the scan lines. The source driver circuit is connected to the data lines corresponding to each column of pixel units in the display area. After the pixel units are turned on for scanning, the source driver circuit writes the corresponding image data into the pixel units via the data lines to display the image.

[0079] In this embodiment, the gate scan circuit may include a first cascade drive circuit 310. The first cascade drive circuit 310 includes a plurality of mutually cascaded first GOA units and a plurality of mutually cascaded second GOA units. The first GOA units and the second GOA units may be arranged alternately. The first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered pixel unit to input a scan voltage to the corresponding odd-numbered pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered pixel unit to input a scan voltage to the corresponding even-numbered pixel unit.

[0080] For example, Figure 8 As shown, in the first cascade driving circuit 310, a plurality of mutually cascaded first GOA units may include GOA 1a1 、GOA 1a3 、GOA 1a5 . The first GOA unit GOA 1a1The first output end of the first GOA unit GOA 1a3 The first output end of the first GOA unit GOA 1a5 The first output end of the first GOA unit GOA 1a1 The second output end of the first GOA unit GOA 1a3 The input end of the first GOA unit GOA 1a3 The second output end of the first GOA unit GOA 1a5 The input end of the first GOA unit GOA

[0081] The second GOA unit GOA 1a2 , the GOA 1a4 , and the GOA 1a6 The first output end of the second GOA unit GOA 1a2 The first output end of the second GOA unit GOA 1a4 The first output end of the second GOA unit GOA 1a6 The first output end of the second GOA unit GOA 1a2 The second output end of the second GOA unit GOA 1a4 The input end of the second GOA unit GOA 1a4 The second output end of the second GOA unit GOA 1a6 The input end of the second GOA unit GOA

[0082] In the embodiment, the first cascade driving circuit 310 can further include a first control line 311, a first switch element T1 1a , and a plurality of second switch elements T2 1a The control end of the first switch element T1 1a is connected with the first control line 311, the first path end of the first switch element T1 1a is used for receiving the initial scanning signal corresponding to the Mth frame, and the second path end of the first switch element T1 1a is connected with the input end of the first GOA unit GOA 1a1 corresponding to the first odd row pixel unit. The control end of the second switch element T2 1a is connected with the first control line 311, and the second switch element T2 1aThe first path end is connected to the input end of the scan line of the pixel unit in the 2i-1th row (such as the 1st row), and the second switch element T2 1a The second path end is connected to the input end of the scan line of the pixel unit in the 2i-th row (such as the 2nd row).

[0083] In this embodiment, the first cascade driving circuit 310 may further include a second control line 312, a third switch element T3 1a and a plurality of fourth switching elements T4 1a The third switching element T3 1a The control end of the third switch element T3 is connected to the second control line 312. 1a The first channel end is used to receive the initial scanning signal corresponding to the M+1th frame, and the third switch element T3 1a The second channel end is connected to the second GOA unit GOA corresponding to the first even-numbered row pixel unit 1a2 The fourth switch element T4 is connected to the input terminal of 1a The first path end of the fourth switch element T4 is connected to the input end of the scan line of the pixel unit in the 2ith row (such as the 2nd row), and the fourth switch element T4 1a The second path end is connected to the input end of the scan line of the pixel unit in the 2i+1th row (such as the 3rd row).

[0084] In this embodiment, the first control line 311 is used to control the first switch element T1 1a and the second switching element T2 1a The second control line 312 is used to control the on and off of the third switch element T3 1a and the fourth switching element T4 1a The on and off.

[0085] When the first switch element T1 is controlled by the first control line 311 1a and the second switching element T2 1a The third switch element T3 is turned on and controlled by the second control line 312 1a and the fourth switching element T4 1a When disconnected, the gate scanning circuit controls the 2i-1th row of pixel units and the 2ith row of pixel units to start scanning synchronously, and the source driving circuit writes the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are started scanning synchronously, so as to realize the display of the Mth frame image.

[0086] Specifically, since the scan line corresponding to the pixel unit of the odd row (row 2i-1) is turned on by the second switching element T2 1aIt is directly connected to the scan line corresponding to the pixel unit of the next even row (row 2i), so when refreshing the screen, the adjacent odd row (row 2i-1) pixel unit and the even row (row 2i) pixel unit can start scanning synchronously, that is, start scanning synchronously from row 1 and row 2. 1a1 By turning on the first switching element T1 1a An initial scanning signal corresponding to the Mth frame is received, and image data of the 2i-1th row is written into the pixel units of the 2i-1th row and the pixel units of the 2ith row that are synchronously scanned.

[0087] When the first switch element T1 is controlled by the first control line 311 1a and the second switching element T2 1a The third switch element T3 is turned off and controlled by the second control line 312 1a and the fourth switching element T4 1a When turned on, the gate scanning circuit controls the 2i-th row of pixel units and the 2i+1-th row of pixel units to start scanning synchronously, and the source driving circuit writes the image data of the 2i-th row in the M+1-th frame into the 2i-th row of pixel units and the 2i+1-th row of pixel units that are started scanning synchronously, so as to realize the display of the M+1-th frame image.

[0088] Specifically, since the scan line corresponding to the pixel unit of the even row (row 2i) is turned on through the fourth switching element T4 1a It is directly connected to the scan line corresponding to the pixel unit of the next odd row (row 2i+1), so when refreshing the screen, the adjacent even row (row 2i) pixel unit and odd row (row 2i+1) pixel unit can start scanning synchronously, that is, start scanning synchronously from the 2nd row and the 3rd row. 1a2 By turning on the third switching element T3 1a An initial scanning signal corresponding to the M+1th frame is received, and image data of the 2ith row is written into the pixel units of the 2ith row and the pixel units of the 2i+1th row that are started to scan synchronously.

[0089] Optionally, the gate scanning circuit in this embodiment may further include a second cascade driving circuit 320. The second cascade driving circuit 320 and the first cascade driving circuit 310 are respectively arranged on both sides of the pixel unit. The structure of the second cascade driving circuit 320 is the same as that of the first cascade driving circuit 310.

[0090] For example, Figure 3 As shown, the second cascade driving circuit 320 may include a plurality of mutually cascaded first GOA units (such as GOA 1b1 、GOA 1b3 and GOA 1b5 ) and multiple mutually cascaded second GOA units (such as GOA1b2 、GOA 1b4 and GOA 1b6 ), may further include a first control line 321, a first switch element T1 1b and a plurality of second switching elements T2 1b When the Mth frame image is displayed, the first control line 321 is used to control the first switch element T1 1b and the second switching element T2 1b The first switching element T1 is turned on. 1b The second cascade driving circuit 320 may further include a second control line 322, a third switch element T3 1b and a plurality of fourth switching elements T4 1b When the M+1 frame image is displayed, the second control line 322 is used to control the third switch element T3 1b and the fourth switching element T4 1b The third switching element T3 is turned on. 1b It is also used to receive the initial scanning signal corresponding to the M+1th frame. Specifically, the working principle of the second cascade driving circuit 320 can be referred to the first cascade driving circuit 310, which will not be described in detail here.

[0091] In this embodiment, by reconstructing the output path of the odd-even row GOA unit, synchronous driving of the odd and even rows is achieved, which improves the display refresh rate while ensuring sufficient charging time for a single row of pixels. In addition, by staggering the second frame in which the odd and even rows are alternately displayed by one row, the display effect of the image edge and oblique line information is effectively improved.

[0092] Optionally, the switching element in the embodiment of the present application may be a metal oxide semiconductor transistor, or a bipolar transistor, etc., and the present application does not impose any limitation on this.

[0093] Third embodiment See also Figure 9 , Figure 9 FIG. 4 is a flow chart of a display driving method according to a third embodiment.

[0094] The display driving method of the embodiment of the present application can be applied to a display panel in a smart terminal, and specifically includes the following steps: Step S210: Entering the first working mode when the first mode selection signal is enabled.

[0095] Step S220: In the first working mode, the image data of the i-th row in the M-1-th frame is written into the i-th row of pixel units that are turned on for scanning, so as to display the M-1-th frame image.

[0096] Step S230: Entering the second working mode when the second mode selection signal is enabled.

[0097] Step S240: In the second working mode, the image data of the 2i-1th row in the Mth frame is written into the 2i-1th row pixel units and the 2ith row pixel units that are synchronously turned on for scanning to display the Mth frame image; the image data of the 2ith row in the M+1th frame is written into the 2ith row pixel units and the 2i+1th row pixel units that are synchronously turned on for scanning to display the M+1th frame image.

[0098] In this embodiment, the M-1th frame image can represent each frame image refreshed in the first working mode, the Mth frame image can represent the odd frames in the image refresh process in the second working mode, and the M+1th frame image can represent the even frames in the image refresh process in the second working mode.

[0099] Optionally, when the display panel displays a static image or is in a low-power scenario, a first mode selection signal corresponding to the first operating mode may be generated according to a system configuration or an external instruction. By controlling each row of pixel units to start scanning in sequence and inputting image data corresponding to each row of pixel units that are started to scan, the display image is refreshed row by row.

[0100] When the display panel displays a high-dynamic image or is in a gaming scene, a second mode selection signal corresponding to the second operating mode can be generated based on the system configuration or external instructions. By controlling the synchronous scanning of two adjacent rows of pixel units, and coordinating the time-sharing alternating display of odd-numbered and even-numbered row image information, the refresh time of the image can be reduced and the display refresh rate can be improved. At the same time, by staggering the second frame displayed alternately by one row, the complementary image information of the two adjacent frames can be achieved, thereby improving the jagged problem of image edges and diagonal line information display. Please refer to the first embodiment above for the specific implementation process and principle of the second operating mode, which will not be repeated here.

[0101] It is understood that the first operating mode in this embodiment corresponds to a low-frequency refresh mode, and the second operating mode corresponds to a high-frequency refresh mode. In this embodiment, the screen refresh mode can be selected and the screen refresh rate can be switched by setting a mode selection signal according to actual application requirements. This not only improves the intelligence of the display device and enhances the user experience, but also ensures the display effect of image edges and diagonal information in the high-frequency refresh mode.

[0102] Fourth embodiment See also Figure 10 , Figure 10 FIG4 is a schematic diagram of a structure of a display driving circuit according to a fourth embodiment. The display driving circuit of the embodiment of the present application can be applied to a display panel of a smart terminal and can be used to implement the display driving method described in the third embodiment.

[0103] The display driving circuit in this embodiment may include a mode selection module, a gate scanning circuit and a source driving circuit.

[0104] Specifically, the mode selection module is used to generate a first mode selection signal or a second mode selection signal to control the display driver circuit to enter the first operating mode or the second operating mode. The mode selection mode can be performed by an external timing controller, which outputs the first mode selection signal or the second mode selection signal according to the display requirements, so that the display driver circuit seamlessly switches to the corresponding operating mode. In the first operating mode, when the M-1 frame image is displayed, the gate scanning circuit is used to control the i-th row of pixel units to start scanning, and the source driving circuit is used to write the image data of the i-th row in the M-1 frame into the i-th row of pixel units that have started scanning. In the second operating mode, when the Mth frame image is displayed, the gate scanning circuit is used to control the 2i-1th row of pixel units and the 2ith row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are synchronously turned on for scanning; when the M+1th frame image is displayed, the gate scanning circuit is used to control the 2ith row of pixel units and the 2i+1th row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2ith row in the M+1th frame into the 2ith row of pixel units and the 2i+1th row of pixel units that are synchronously turned on for scanning.

[0105] In this embodiment, the gate scanning circuit may include a first cascade driving circuit 410 and a second cascade driving circuit 420. The first cascade driving circuit 410 and the second cascade driving circuit 420 may be respectively disposed on both sides of the pixel unit.

[0106] Specifically, the first cascade driving circuit 410 and the second cascade driving circuit 420 each include a plurality of first GOA units and a plurality of second GOA units cascaded with each other. The first GOA units and the second GOA units can be arranged alternately. The first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit.

[0107] In this embodiment, the first cascade driving circuit 410 may further include a first control line 411, a plurality of first switch elements T1 and a plurality of first control lines T2. 2a , and / or a second control line 412, a plurality of second switching elements T2 2a , a plurality of third switching elements T3 2a Among them, the first switch element T1 2a The control end of the first switch element T1 is connected to the first control line 411. 2a The first channel end is connected to the second output end of the first GOA unit, and the first switch element T12a The second path end of the second switch element T2 is connected to the input end of the second GOA unit. 2a The control ends of the second switch element T2 are connected to the second control line 412. 2a The first channel end is used to receive the initial scanning signal corresponding to the Mth frame, or is connected to the second output end of the first GOA unit, and the second switch element T2 2a The second path end of the third switch element T3 is connected to the input end of the first GOA unit corresponding to the next odd-numbered row of pixel units. 2a The control end of the third switch element T3 is also connected to the second control line 412. 2a The first channel end of the third switching element T3 is connected to the input end of the scanning line of the 2i-1th row of pixel units. 2a The second path end is connected to the input end of the scan line of the 2i-th row of pixel units.

[0108] For example, Figure 10 As shown, in the first cascade driving circuit 410, a plurality of first GOA units may include GOA 2a1 、GOA 2a3 、GOA 2a5 . The first GOA unit GOA 2a1 The first output end of the first GOA unit GOA is connected to the scan line of the first row of pixel units. 2a3 The first output end of the first GOA unit GOA is connected to the scan line of the third row of pixel units. 2a5 The first output end of is connected to the scan line of the 5th row pixel unit. The plurality of second GOA units may include GOA 2a2 、GOA 2a4 、GOA 2a6 . The second GOA unit GOA 2a2 The first output end of the second GOA unit is connected to the scan line of the second row of pixel units. 2a4 The first output end of the GOA is connected to the scan line of the 4th row pixel unit, and the second GOA unit GOA 2a6 The first output end of the GOA unit is connected to the scan line of the 6th row of pixel units. 2a1 The second output terminal is connected to the first switching element T1 2a With the second GOA unit GOA 2a2 The input terminal of the second GOA unit GOA 2a2 The second output terminal is directly connected to the first GOA unit GOA 2a3 The input terminal of the first GOA unit GOA 2a3 The second output terminal is connected to the first switching element T1 2a With the second GOA unit GOA 2a4The input terminal of the second GOA unit GOA 2a4 The second output terminal is directly connected to the first GOA unit GOA 2a5 The input terminal of the first GOA unit GOA 2a5 The second output terminal is connected to the first switching element T1 2a With the second GOA unit GOA 2a6 The first second switching element T2 2a The first channel end is used to receive the initial scanning signal corresponding to the Mth frame, and the second channel end is connected to the first GOA unit GOA corresponding to the first odd-numbered row pixel unit. 2a1 The other second switching element T2 2a The first path end of the previous odd row corresponds to the first GOA unit, such as GOA 2a1 、GOA 2a3 、GOA 2a5 The second output end is connected to the second path end and the first GOA unit corresponding to the next odd row, such as GOA 2a3 、GOA 2a5 The third switching element T3 is connected to the input terminal. 2a The first path end is connected to the input end of the scan line of the 1st, 3rd and 5th rows of pixel units, and the second path end is connected to the input end of the scan line of the 2nd, 4th and 6th rows of pixel units.

[0109] In this embodiment, the second cascade driving circuit 420 includes a first control line 421, a plurality of fourth switch elements T4 2b , and / or a third control line 422, a plurality of fifth switching elements T5 2b , a plurality of sixth switching elements T6 2b The fourth switching element T4 2b The control end of the fifth switch element T5 is connected to the first control line 421. 2b and the sixth switching element T6 2b The control terminals of the fourth switch element T4 are connected to the third control line 422. 2b The first channel end is used to receive the initial scanning signal corresponding to the M-1 frame, or is connected to the second output end of the second GOA unit, and the fourth switch element T4 2b The second path end of the fifth switch element T5 is connected to the input end of the first GOA unit. 2b The first channel end is used to receive the initial scanning signal corresponding to the M+1 frame, or is connected to the second output end of the second GOA unit, and the fifth switch element T5 2b The second path end of the sixth switch element T6 is connected to the input end of the second GOA unit corresponding to the next even-numbered row of pixel units. 2bThe first channel end of the sixth switch element T6 is connected to the input end of the scan line of the 2i-th row pixel unit. 2b The second path end is connected to the input end of the scan line of the 2i+1th row of pixel units.

[0110] For example, Figure 10 As shown, in the second cascade driving circuit 420, the plurality of first GOA units may include GOA 2b1 、GOA 2b3 、GOA 2b5 . The first GOA unit GOA 2b1 The first output end of the first GOA unit GOA is connected to the scan line of the first row of pixel units. 2b3 The first output end of the first GOA unit GOA is connected to the scan line of the third row of pixel units. 2b5 The first output end of is connected to the scan line of the 5th row pixel unit. The plurality of second GOA units may include GOA 2b2 、GOA 2b4 、GOA 2b6 . The second GOA unit GOA 2b2 The first output end of the second GOA unit is connected to the scan line of the second row of pixel units. 2b4 The first output end of the GOA is connected to the scan line of the 4th row pixel unit, and the second GOA unit GOA 2b6 The first output end of the GOA unit is connected to the scan line of the 6th row of pixel units. 2b1 The second output terminal is directly connected to the second GOA unit GOA 2b2 The input terminal of the second GOA unit GOA 2b2 The second output terminal is connected to the fourth switching element T4 2b With the first GOA unit GOA 2b3 The input terminal of the first GOA unit GOA 2b3 The second output terminal is directly connected to the second GOA unit GOA 2b4 The input terminal of the second GOA unit GOA 2b4 The second output terminal is connected to the fourth switching element T4 2b With the first GOA unit GOA 2b5 The input terminal of the first GOA unit GOA 2b5 The second output terminal is directly connected to the second GOA unit GOA 2b6 The first fourth switching element T4 is connected to the input terminal. 2b The first channel end is used to receive the initial scanning signal corresponding to the M-1 frame, and the second channel end is connected to the first GOA unit GOA 2b1 The first fifth switching element T5 is connected to the input terminal of 2bThe first channel end is used to receive the initial scanning signal corresponding to the M+1 frame, and the second channel end is connected to the second GOA unit GOA corresponding to the first even-numbered row pixel unit. 2b2 The other fifth switching element T5 2b The first path end of the second GOA unit corresponding to the previous even row is connected to the GOA 2b2 、GOA 2b4 The second output end is connected to the second GOA unit corresponding to the next even row, such as GOA 2b4 、GOA 2b6 The sixth switch element T6 is connected to the input terminal of 2b The first path end is connected to the input end of the scan line of the 2nd, 4th and 6th rows of pixel units, and the second path end is connected to the input end of the scan line of the 3rd and 5th rows of pixel units.

[0111] In this embodiment, the first control lines 411 and 421 are used to control the first switch element T1. 2a and the fourth switching element T4 2b The second control line 412 is used to control the on and off of the second switch element T2 2a and the third switching element T3 2a The third control line 413 is used to control the on and off of the fifth switch element T5 2b and the sixth switching element T6 2b The on and off.

[0112] When the first switch element T1 is controlled by the first control lines 411 and 421 2a and the fourth switching element T4 2b The second switch element T2 is turned on and controlled by the second control line 412 2a and the third switching element T3 2a The fifth switch element T5 is controlled by the third control line 422. 2b and the sixth switching element T6 2b When disconnected, the display driving circuit in this embodiment operates in the first operating mode.

[0113] Specifically, in the first working mode, due to the first switching element T1 being turned on between the pixel units in the odd row (row 2i-1) and the even row (row 2i), 2a The cascade drive path is turned on, and the fourth switch element T4 is turned on between the pixel units of the even row (row 2i) and the odd row (row 2i+1). 2b The cascade drive path is turned on, so when refreshing the M-1 frame, the initial scanning signal corresponding to the M-1 frame is transmitted from the first turned-on fourth switch element T4. 2b Enter the first GOA unit GOA 2b1In the embodiment, the display driving circuit is controlled to scan pixel units in row 1 in sequence, and the image data of each row in the M-1 frame is sequentially written into the pixel units in each row that are started to be scanned.

[0114] When the first switch element T1 is controlled by the first control lines 411 and 421 2a and the fourth switching element T4 2b The second switch element T2 is turned off and controlled by the second control line 412 2a and the third switching element T3 2a The fifth switch element T5 is turned on through the third control line 422. 2b and the sixth switching element T6 2b When disconnected, the display driver circuit in this embodiment operates in the second operating mode. In this mode, the gate scanning circuit controls the pixel units in the 2i-1th row and the pixel units in the 2ith row to start scanning synchronously, and the source driver circuit writes the image data of the 2i-1th row in the Mth frame into the pixel units in the 2i-1th row and the 2ith row that are simultaneously scanning, thereby refreshing the image of the Mth frame.

[0115] Specifically, the first GOA unit GOA 2a1 The first second switching element T2 is turned on 2a Receive the initial scanning signal corresponding to the Mth frame. The first GOA unit (such as GOA 2a1 ) through the other conductive second switching element T2 2a , across the adjacent even-numbered row of pixel units and the first GOA unit corresponding to the next odd-numbered row of pixel units (such as GOA 2a3 ) is directly connected to turn on the cascade path of the odd rows, thereby realizing the chain drive of the odd rows. The scan line corresponding to the pixel unit of the odd row (row 2i-1) is turned on through the third switch element T3 2a Directly connected to the scan line corresponding to the next even-numbered row (row 2i). Therefore, when refreshing the Mth frame, the adjacent odd-numbered row (row 2i-1) and even-numbered row (row 2i) can start scanning synchronously. That is, scanning starts synchronously from row 1 and row 2, and the image data of row 2i-1 is written to the synchronously scanned pixel units in row 2i-1 and row 2i.

[0116] When the first switch element T1 is controlled by the first control lines 411 and 421 2a and the fourth switching element T4 2b The second switch element T2 is controlled by the second control line 412. 2a and the third switching element T3 2a The fifth switch element T5 is controlled by the third control line 422. 2b and the sixth switching element T6 2bWhen turned on, the display driver circuit in this embodiment still operates in the second operating mode. At this time, the gate scanning circuit controls the pixel units in the 2ith row and the pixel units in the 2i+1th row to start scanning synchronously, and the source driver circuit writes the image data of the 2ith row in the M+1th frame into the pixel units in the 2ith row and the 2i+1th row that are simultaneously scanning, thereby refreshing the image of the M+1th frame.

[0117] Specifically, the second GOA unit GOA 2b2 The fifth switching element T5 is turned on first. 2b Receive the initial scanning signal corresponding to the M+1 frame. The second GOA unit (such as GOA 2b2 ) through the other conductive fifth switching element T5 2b , across the adjacent odd-numbered row of pixel units and the second GOA unit corresponding to the next even-numbered row of pixel units (such as GOA 2a4 ) is directly connected to turn on the cascade path of the even row, thereby realizing the chain drive of the even row. The scan line corresponding to the pixel unit of the even row (row 2i) is turned on through the sixth switch element T6 2b It is directly connected to the scan line corresponding to the pixel unit of the next odd row (row 2i+1), so when refreshing the M+1 frame, the adjacent even row (row 2i) and odd row (row 2i+1) pixel units can start scanning synchronously, that is, the scanning is started synchronously from the 2nd row and the 3rd row, and the image data of the 2ith row is written into the pixel units of the 2ith row and the 2i+1th row that are started scanning synchronously.

[0118] In this embodiment, the coordination of control lines and switching elements reconfigures the output path of the GOA unit, enabling switching between progressive drive and even-odd synchronous drive. Furthermore, during even-odd synchronous drive, the second frame, which alternates between odd and even rows, is displayed offset by one row. This allows the image refresh mode and refresh rate to be selected based on actual application requirements, while also ensuring the display of image edges and diagonal lines in high-frequency refresh mode.

[0119] Fifth embodiment See also Figure 11 , Figure 11 FIG5 is a schematic diagram of a display driving circuit according to a fifth embodiment. The display driving circuit of the embodiment of the present application can be applied to a display panel of a smart terminal and can be used to implement the display driving method described in the third embodiment.

[0120] The display driver circuit in this embodiment includes a mode selection module, a gate scanning circuit, and a source driver circuit. It should be noted that the same parts as those in the fourth embodiment are not described in detail in this embodiment. Only the parts that differ from the fourth embodiment are described below.

[0121] The gate scanning circuit in this embodiment includes a first cascade driving circuit 510. The first cascade driving circuit 510 includes a plurality of first GOA units and a plurality of second GOA units. The first GOA units and the second GOA units can be arranged alternately. The first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit.

[0122] For example, Figure 11 As shown, in the first cascade driving circuit 510, a plurality of first GOA units may include GOA 3a1 、GOA 3a3 、GOA 3a5 . The first GOA unit GOA 3a1 The first output end of the first GOA unit GOA is connected to the scan line of the first row of pixel units. 3a3 The first output end of the first GOA unit GOA is connected to the scan line of the third row of pixel units. 3a5 The first output end of is connected to the scan line of the 5th row pixel unit. The plurality of second GOA units may include GOA 3a2 、GOA 3a4 、GOA 3a6 . The second GOA unit GOA 3a2 The first output end of the second GOA unit is connected to the scan line of the second row of pixel units. 3a4 The first output end of the GOA is connected to the scan line of the 4th row pixel unit, and the second GOA unit GOA 3a6 The first output end is connected to the scan line of the 6th row of pixel units.

[0123] In this embodiment, the first cascade driving circuit 510 may further include a first control line 511 and a plurality of first switching elements T1. 3a The first switching element T1 3a The control end of is connected to the first control line 511. The first GOA unit and the second GOA unit are connected through the first switch element T1. 3a cascaded with each other. Among them, the first switching element T1 3a It is also connected to the input end of the first GOA unit corresponding to the first row of pixel units, and is used to receive the initial scanning signal corresponding to the M-1th frame.

[0124] like Figure 11 As shown, the first switching element T1 3a The first channel end is used to receive the initial scanning signal corresponding to the M-1 frame, and the first first switch element T1 3a The second path end and the first GOA unit GOA 3a1 The first GOA unit GOA3a1 The second output terminal is connected to the first switching element T1 3a With the second GOA unit GOA 3a2 The input terminal of the second GOA unit GOA 3a2 The second output terminal is connected to the first switching element T1 3a With the first GOA unit GOA 3a3 The input terminal of the first GOA unit GOA 3a3 The second output terminal is connected to the first switching element T1 3a With the second GOA unit GOA 3a4 The input terminal of the second GOA unit GOA 3a4 The second output terminal is connected to the first switching element T1 3a With the first GOA unit GOA 3a5 The input terminal of the first GOA unit GOA 3a5 The second output terminal is connected to the first switching element T1 3a With the second GOA unit GOA 3a6 The input terminal is connected through the first switching element T1 3a A plurality of first GOA units and second GOA units are cascaded to form a cascade driving path, thereby realizing the transmission of the scanning signal between two adjacent rows.

[0125] In this embodiment, the first cascade driving circuit 510 may further include a second control line 512, a plurality of second switch elements T2 3a and a plurality of third switching elements T3 3a The second switching element T2 3a and the third switching element T3 3a The control ends of the second switch element T2 are connected to the second control line 512. 3a The first channel end is used to receive the initial scanning signal corresponding to the Mth frame, or is connected to the second output end of the first GOA unit, and the second switch element T2 3a The second path end of the third switch element T3 is connected to the input end of the first GOA unit corresponding to the next odd-numbered row of pixel units. 3a The first channel end of the third switching element T3 is connected to the input end of the scanning line of the 2i-1th row of pixel units. 3a The second path end is connected to the input end of the scan line of the 2i-th row of pixel units.

[0126] For example, Figure 11 As shown, when refreshing the Mth frame, the first second switch element T2 3a The first channel end is used to receive the initial scanning signal corresponding to the Mth frame, and the second channel end is connected to the first GOA unit GOA corresponding to the first odd-numbered row pixel unit. 3a1The input end of the second switch element T2 is connected with the output end of the first switch element T1. 3a The first pass-through end of the second switch element T2 is connected with the first GOA unit corresponding to the first odd row, such as GOA 3a1 , GOA 3a3 , GOA 3a5 The second output end of the second switch element T2 is connected with the first GOA unit corresponding to the next odd row, such as GOA 3a3 , GOA 3a5 The input end of the third switch element T3 is connected with the output end of the second switch element T2. 3a The first pass-through end of the third switch element T3 is connected with the input end of the scan line of the first, third and fifth row pixel units, and the second pass-through end is connected with the input end of the scan line of the second, fourth and sixth row pixel units.

[0127] In the embodiment, the first cascade driving circuit 510 can further include a third control line 513, a plurality of fourth switch elements T4 3a and a plurality of fifth switch elements T5 3a The control end of the fourth switch element T4 3a and the fifth switch element T5 3a is connected with the third control line 513. The first pass-through end of the fourth switch element T4 3a is used for receiving the initial scanning signal corresponding to the M+1 frame, or is connected with the second output end of the second GOA unit, and the second pass-through end of the fourth switch element T4 3a is connected with the input end of the second GOA unit corresponding to the next even row pixel unit. The first pass-through end of the fifth switch element T5 3a is connected with the input end of the scan line of the 2i row pixel unit, and the second pass-through end of the fifth switch element T5 3a is connected with the input end of the scan line of the 2i+1 row pixel unit.

[0128] Exemplarily, as shown in Figure 11 , the first pass-through end of the first fourth switch element T4 3a is used for receiving the initial scanning signal corresponding to the M+1 frame when refreshing the M+1 frame picture, and the second pass-through end of the first fourth switch element T4 3a is connected with the input end of the second GOA unit GOA 3a2 corresponding to the first even row pixel unit. The first pass-through end of the other fourth switch element T4 3a is connected with the second GOA unit, such as GOA 3a2 , GOA 3a4 corresponding to the previous even row, and the second pass-through end is connected with the second GOA unit, such as GOA 3a4 , GOA 3a6 corresponding to the next even row. The input end of the fifth switch element T5 3aThe first path end is connected to the input end of the scan line of the 2nd and 4th rows of pixel units, and the second path end is connected to the input end of the scan line of the 3rd and 5th rows of pixel units.

[0129] In this embodiment, the first control line 511 is used to control the first switch element T1 3a The second control line 512 is used to control the on and off of the second switch element T2 3a and the third switching element T3 3a The third control line 513 is used to control the on and off of the fourth switch element T4 3a and the fifth switching element T5 3a The on and off.

[0130] When the first switch element T1 is controlled by the first control line 511 3a The second switch element T2 is turned on and controlled by the second control line 512 3a and the third switching element T3 3a The fourth switch element T4 is controlled by the third control line 513. 3a and the fifth switching element T5 3a When disconnected, the display driving circuit in this embodiment operates in the first operating mode.

[0131] Specifically, in the first working mode, due to the first switching element T1 between two adjacent rows being turned on 3a The cascade drive path is formed. When refreshing the M-1 frame, the initial scanning signal corresponding to the M-1 frame is transmitted from the first switching element T1. 3a Enter the first GOA unit GOA 3a1 In the embodiment, the display driving circuit is controlled to scan pixel units in row 1 in sequence, and the image data of each row in the M-1 frame is sequentially written into the pixel units in each row that are started to be scanned.

[0132] When the first switch element T1 is controlled by the first control line 511 3a The second switch element T2 is controlled by the second control line 512. 3a and the third switching element T3 3a The fourth switch element T4 is turned on through the third control line 513. 3a and the fifth switching element T5 3a When disconnected, the display driver circuit in this embodiment operates in the second operating mode. In this mode, the gate scanning circuit controls the pixel units in the 2i-1th row and the pixel units in the 2ith row to start scanning synchronously, and the source driver circuit writes the image data of the 2i-1th row in the Mth frame into the pixel units in the 2i-1th row and the 2ith row that are simultaneously scanning, thereby refreshing the image of the Mth frame.

[0133] Specifically, the first GOA unit GOA 3a1 The first second switching element T2 is turned on 3a Receive the initial scanning signal corresponding to the Mth frame. The first GOA unit (such as GOA 3a1 ) through the other conductive second switching element T2 3a , across the adjacent even-numbered row of pixel units and the first GOA unit corresponding to the next odd-numbered row of pixel units (such as GOA 3a3 ) is directly connected to turn on the cascade path of the odd rows, thereby realizing the chain drive of the odd rows. The scan line corresponding to the pixel unit of the odd row (row 2i-1) is turned on through the third switch element T3 3a Directly connected to the scan line corresponding to the next even-numbered row (row 2i). Therefore, when refreshing the Mth frame, the adjacent odd-numbered row (row 2i-1) and even-numbered row (row 2i) can start scanning synchronously. That is, scanning starts synchronously from row 1 and row 2, and the image data of row 2i-1 is written to the synchronously scanned pixel units in row 2i-1 and row 2i.

[0134] When the first switch element T1 is controlled by the first control line 511 3a The second switch element T2 is controlled by the second control line 512. 3a and the third switching element T3 3a The fourth switch element T4 is controlled by the third control line 513. 3a and the fifth switching element T5 3a When turned on, the display driver circuit still operates in the second operating mode. At this time, the gate scanning circuit controls the pixel units in the 2ith row and the pixel units in the 2i+1th row to start scanning synchronously, and the source driver circuit writes the image data of the 2ith row in the M+1th frame into the pixel units in the 2ith row and the 2i+1th row that are started scanning synchronously, so as to refresh the image of the M+1th frame.

[0135] Specifically, the second GOA unit GOA 3a2 The fourth switching element T4 is turned on first. 3a Receive the initial scanning signal corresponding to the M+1 frame. The second GOA unit (such as GOA 3a2 ) through the other conductive fourth switching element T4 3a , across the adjacent odd-numbered row of pixel units and the second GOA unit corresponding to the next even-numbered row of pixel units (such as GOA 3a4 ) is directly connected to turn on the cascade path of the even row, thereby realizing the chain drive of the even row. The scan line corresponding to the pixel unit of the even row (row 2i) is turned on through the fifth switch element T5 3aIt is directly connected to the scan line corresponding to the pixel unit of the next odd row (row 2i+1). Therefore, when refreshing the screen, the adjacent even row (row 2i) pixel unit and odd row (row 2i+1) pixel unit can start scanning synchronously, that is, the scanning is started synchronously from the 2nd row and the 3rd row, and the image data of the 2ith row is written into the pixel units of the 2ith row and the 2i+1th row that are started scanning synchronously.

[0136] Optionally, the gate scanning circuit in this embodiment may further include a second cascade driving circuit 520. The second cascade driving circuit 520 and the first cascade driving circuit 510 are respectively arranged on both sides of the pixel unit. The structure of the second cascade driving circuit 520 is the same as that of the first cascade driving circuit 510.

[0137] For example, Figure 11 As shown, the second cascade driving circuit 520 may include a plurality of first GOA units (such as GOA 3b1 、GOA 3b3 、GOA 3b5 ) and multiple second GOA units (such as GOA 3b2 、GOA 3b4 、GOA 3b6 ), may further include a first control line 521 and a plurality of first switching elements T1 3b In the first working mode, when the M-1 frame image is displayed, the first control line 521 controls the first switch element T1 3b The first switch element T1 is turned on. 3b It is also used to receive the initial scanning signal corresponding to the M-1 frame. The second cascade driving circuit 520 may also include a second control line 522, a plurality of second switching elements T2 3b and a plurality of third switching elements T3 3b In the second working mode, when the Mth frame image is displayed, the second control line 522 controls the second switch element T2 3b and the third switching element T3 3b The first second switch element T2 is turned on. 3b The second cascade driving circuit 520 may further include a third control line 523, a plurality of fourth switching elements T4 3b and a plurality of fifth switching elements T5 3b In the second working mode, when the M+1 frame image is displayed, the third control line 523 controls the fourth switch element T4 3b and the fifth switching element T5 3b The first fourth switch element T4 is turned on. 3bIt is also used to receive the initial scanning signal corresponding to the M+1th frame. Specifically, the working principle of the second cascade driving circuit 520 can be referred to the first cascade driving circuit 510, which will not be described in detail here.

[0138] In this embodiment, the output path of the GOA unit can be reconstructed through the coordination of the control line and the switching element to achieve switching between row-by-row driving and odd-even row synchronous driving. In addition, when the odd-even row synchronous driving is performed, the second frame in which the odd and even rows are alternately displayed is offset by one row for display. In this way, not only can the screen refresh mode and refresh frequency be selected according to actual application requirements, but in the high-frequency refresh mode, the display effect of image edges and oblique line information can also be guaranteed.

[0139] Sixth embodiment See also Figures 12 to 15 , Figure 12 is a schematic structural diagram of a display driving circuit according to a sixth embodiment. Figure 13 is a timing diagram of the first working mode according to the sixth embodiment. Figure 14 1 is a timing diagram of odd frames in the second working mode according to the sixth embodiment. Figure 15 1 is a timing diagram of an even frame in the second working mode according to the sixth embodiment. The display driving circuit of the embodiment of the present application can be applied to the display panel of the smart terminal and can be used to implement the display driving method described in the first embodiment or the third embodiment.

[0140] like Figure 12 As shown, the gate scanning circuit in this embodiment includes a first cascade driving circuit 610 and a second cascade driving circuit 620. The first cascade driving circuit 610 and the second cascade driving circuit 620 can be respectively arranged on both sides of the pixel unit.

[0141] In this embodiment, the first cascade driving circuit 610 includes a plurality of first GOA units connected in cascade, and the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered pixel unit. The second cascade driving circuit 620 includes a plurality of second GOA units connected in cascade, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered pixel unit.

[0142] For example, the plurality of first GOA units may include GOA 4a1 、GOA 4a2 、GOA 4a3 The first output terminal GOA of the first GOA unit 4a1 Connected to the scan line of the first row of pixel units, the first GOA unit GOA 4a2 The first output end of the first GOA unit GOA is connected to the scan line of the third row of pixel units. 4a3The first output end of the first GOA unit is connected with the scan line of the pixel unit in the 5th row. The cascaded first GOA units form a cascaded driving path for the odd rows, so as to realize the transmission of the scan signal between adjacent odd rows. The second GOA units can include GOA 4b1 , GOA 4b2 The second GOA unit GOA 4b1 is connected with the scan line of the pixel unit in the 2nd row, and the second GOA unit GOA 4b2 is connected with the scan line of the pixel unit in the 4th row. The cascaded second GOA units form a cascaded driving path for the even rows, so as to realize the transmission of the scan signal between adjacent even rows.

[0143] When the display driving method as described in the third embodiment is implemented, in the first working mode, when refreshing the image in the M-1th frame, the scan of each row of pixel units is sequentially opened by the timing signals as shown in Figure 13 , i.e., line-by-line scanning (e.g., first controlling the 1st row to open the scan, and then controlling the 2nd row to open the scan), and the image data corresponding to each row of pixel units is sequentially input to each row of pixel units that opens the scan, so as to realize the line-by-line refreshing of the display picture.

[0144] In the second working mode, when refreshing the image in the Mth frame (the Mth frame can represent the odd frame in the second working mode), the timing signals as shown in Figure 14 are used to control the adjacent odd row (2i-1th row) pixel units and even row (2i th row) pixel units to synchronously open the scan, and the image data of the 2i-1th row (i.e., the odd row) is written into the 2i-1th row pixel units and the 2i th row pixel units that synchronously open the scan. For example, the 1st row and the 2nd row are synchronously opened, and the image data of the 1st row is written into the pixel units corresponding to the 1st row and the 2nd row; then the 3rd row and the 4th row are synchronously opened, and the image data of the 3rd row is written into the pixel units corresponding to the 3rd row and the 4th row, and so on, so as to realize the display of the odd row information.

[0145] When refreshing the image in the M+1th frame (the M+1th frame can represent the even frame in the second working mode), the timing signals as shown in Figure 15The timing signals shown in control the synchronous scanning of adjacent even-numbered rows (row 2i) and odd-numbered rows (row 2i+1), and write the image data of row 2i (i.e., the even row) into the synchronously scanned pixel cells of row 2i and row 2i+1. For example, although row 1 is scanned first but the data signal is not written into row 1, the gate scanning circuit starts scanning synchronously with rows 2 and 3, and writes the image data of row 2 into the corresponding pixel cells of rows 2 and 2. It then controls rows 4 and 5 to start scanning synchronously, and writes the image data of row 4 into the corresponding pixel cells of rows 4 and 5. Starting from the second row, the adjacent even-numbered and odd-numbered rows are synchronously scanned, and the corresponding even-numbered row data is written to display the even-numbered row information.

[0146] In this embodiment, by controlling the timing of the scanning signal and the data signal, odd-even row synchronous driving can be achieved, or switching between row-by-row driving and odd-even row synchronous driving can be achieved. In addition, when the odd-even row synchronous driving is performed, the second frame in which the odd and even row information is alternately displayed is offset by one row for display. In this way, not only can the screen refresh mode and refresh frequency be selected according to actual application requirements, but in the high-frequency refresh mode, the display effect of the image edge and oblique line information can also be guaranteed.

[0147] The embodiment of the present application also provides a display panel, including a display driving circuit as shown in the above embodiment, and the display driving circuit is used to implement the steps of the display driving method described in the above embodiment. It can be understood that the above scenario is only an example and does not constitute a limitation on the application scenario of the technical solution provided in the embodiment of the present application. The technical solution of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of system architecture and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

[0148] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0149] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0150] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0151] In this application, the same or similar terminology, technical solutions and / or application scenario descriptions are generally only described in detail the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, for the same or similar terminology, technical solutions and / or application scenario descriptions that are not described in detail later, you can refer to the previous relevant detailed descriptions.

[0152] In this application, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0153] The various technical features of the technical solution of this application can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0154] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as mentioned above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, controlled terminal, or network device, etc.) to execute the method of each embodiment of the present application.

[0155] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted from one storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, storage disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0156] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that: Including gate scanning circuit and source driving circuit, When displaying the Mth frame image, the gate scanning circuit is used to control the 2i-1th row of pixel units and the 2ith row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are started scanning synchronously; When displaying the M+1th frame image, the gate scanning circuit is used to control the 2ith row of pixel units and the 2i+1th row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2ith row in the M+1th frame into the 2ith row of pixel units and the 2i+1th row of pixel units that are started scanning synchronously.

2. The display driving circuit according to claim 1, wherein: The gate scanning circuit includes a first cascade driving circuit and / or a second cascade driving circuit; The first cascade drive circuit and / or the second cascade drive circuit each include a first control line, a first switch element, a plurality of second switch elements, and / or a second control line, a third switch element, a plurality of fourth switch elements; The control ends of the first switch element and the second switch element are both connected to the first control line, and the control ends of the third switch element and the fourth switch element are both connected to the second control line; When the M-th frame image is displayed, the first control line controls the first switching element and the second switching element to be turned on; When the (M+1)th frame image is displayed, the second control line controls the third switching element and the fourth switching element to be turned on.

3. The display driving circuit according to claim 2, wherein: The first cascade driving circuit and / or the second cascade driving circuit further include a plurality of mutually cascaded first GOA units and a plurality of mutually cascaded second GOA units; the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit; The first path end of the first switch element is used to receive the initial scanning signal corresponding to the Mth frame, and the second path end of the first switch element is connected to the input end of the first GOA unit corresponding to the first odd-numbered row of pixel units; The first path end of the second switch element is connected to the input end of the scan line of the pixel unit in the 2i-1th row, and the second path end of the second switch element is connected to the input end of the scan line of the pixel unit in the 2ith row; The first channel end of the third switch element is used to receive the initial scanning signal corresponding to the M+1th frame, and the second channel end of the third switch element is connected to the input end of the second GOA unit corresponding to the first even-numbered row of pixel units; The first channel end of the fourth switch element is connected to the input end of the scan line of the 2i-th row of pixel units, and the second channel end of the fourth switch element is connected to the input end of the scan line of the 2i+1-th row of pixel units.

4. A display driving circuit, characterized in that: Including mode selection module, gate scanning circuit and source driving circuit, The mode selection module is used to generate a first mode selection signal or a second mode selection signal to control the display driving circuit to enter the first operating mode or the second operating mode; In the first operating mode, when the M-1th frame image is displayed, the gate scanning circuit is used to control the i-th row of pixel units to start scanning, and the source driving circuit is used to write the image data of the i-th row in the M-1th frame into the i-th row of pixel units that have started scanning; In the second operating mode, when the Mth frame image is displayed, the gate scanning circuit is used to control the 2i-1th row of pixel units and the 2ith row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2i-1th row in the Mth frame into the 2i-1th row of pixel units and the 2ith row of pixel units that are synchronously turned on for scanning; when the M+1th frame image is displayed, the gate scanning circuit is used to control the 2ith row of pixel units and the 2i+1th row of pixel units to start scanning synchronously, and the source driving circuit is used to write the image data of the 2ith row in the M+1th frame into the 2ith row of pixel units and the 2i+1th row of pixel units that are synchronously turned on for scanning.

5. The display driving circuit according to claim 4, wherein: The gate scanning circuit includes a first cascade driving circuit and a second cascade driving circuit; The first cascade drive circuit includes a first control line, a plurality of first switching elements, and / or a second control line, a plurality of second switching elements, and a plurality of third switching elements; the control end of the first switching element is connected to the first control line, and the control ends of the second switching element and the third switching element are both connected to the second control line; The second cascade drive circuit includes a first control line, a plurality of fourth switching elements, and / or a third control line, a plurality of fifth switching elements, and a plurality of sixth switching elements; the control end of the fourth switching element is connected to the first control line, and the control ends of the fifth switching element and the sixth switching element are both connected to the third control line; In the first working mode, the first control line controls the first switching element and the fourth switching element to be turned on; In the second working mode, when the Mth frame image is displayed, the second control line controls the second switching element and the third switching element to be turned on; when the M+1th frame image is displayed, the third control line controls the fifth switching element and the sixth switching element to be turned on.

6. The display driving circuit according to claim 5, wherein: The first cascade driving circuit and the second cascade driving circuit each include a plurality of first GOA units and a plurality of second GOA units cascaded with each other; the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit; The first path end of the first switch element is connected to the second output end of the first GOA unit, and the second path end of the first switch element is connected to the input end of the second GOA unit; The first path end of the second switch element is used to receive the initial scanning signal corresponding to the Mth frame, or is connected to the second output end of the first GOA unit, and the second path end of the second switch element is connected to the input end of the first GOA unit corresponding to the next odd-numbered row of pixel units; The first channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2i-1th row, and the second channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2ith row; The first path end of the fourth switch element is used to receive the initial scanning signal corresponding to the M-1th frame, or is connected to the second output end of the second GOA unit, and the second path end of the fourth switch element is connected to the input end of the first GOA unit; The first channel end of the fifth switch element is used to receive the initial scanning signal corresponding to the M+1th frame, or is connected to the second output end of the second GOA unit, and the second channel end of the fifth switch element is connected to the input end of the second GOA unit corresponding to the next even-numbered row of pixel units; The first channel end of the sixth switch element is connected to the input end of the scan line of the 2i-th row of pixel units, and the second channel end of the sixth switch element is connected to the input end of the scan line of the 2i+1-th row of pixel units.

7. The display driving circuit according to claim 4, wherein: The gate scanning circuit includes a first cascade driving circuit and / or a second cascade driving circuit; The first cascade drive circuit and / or the second cascade drive circuit each include a first control line, a plurality of first switching elements, and / or a second control line, a plurality of second switching elements, a plurality of third switching elements, and / or a third control line, a plurality of fourth switching elements, and a plurality of fifth switching elements; The control end of the first switch element is connected to the first control line, the control ends of the second switch element and the third switch element are both connected to the second control line, and the control ends of the fourth switch element and the fifth switch element are both connected to the third control line; In the first working mode, the first control line controls the first switching element to be turned on; In the second working mode, when the Mth frame image is displayed, the second control line controls the second switching element and the third switching element to be turned on; when the M+1th frame image is displayed, the third control line controls the fourth switching element and the fifth switching element to be turned on.

8. The display driving circuit according to claim 7, wherein: The first cascade driving circuit and / or the second cascade driving circuit further include a plurality of first GOA units and a plurality of second GOA units, wherein the first GOA units and the second GOA units are cascaded to each other through the first switching element; the first output end of the first GOA unit is connected to the scan line of the corresponding odd-numbered row pixel unit, and the first output end of the second GOA unit is connected to the scan line of the corresponding even-numbered row pixel unit; The first switch element is further connected to the input end of the first GOA unit corresponding to the first row of pixel units, and is used to receive the initial scanning signal corresponding to the M-1th frame; The first path end of the second switch element is used to receive the initial scanning signal corresponding to the Mth frame, or is connected to the second output end of the first GOA unit, and the second path end of the second switch element is connected to the input end of the first GOA unit corresponding to the next odd-numbered row of pixel units; The first channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2i-1th row, and the second channel end of the third switch element is connected to the input end of the scan line of the pixel unit in the 2ith row; The first channel end of the fourth switch element is used to receive the initial scanning signal corresponding to the M+1th frame, or is connected to the second output end of the second GOA unit, and the second channel end of the fourth switch element is connected to the input end of the second GOA unit corresponding to the next even-numbered row of pixel units; The first channel end of the fifth switch element is connected to the input end of the scan line of the 2i-th row of pixel units, and the second channel end of the fifth switch element is connected to the input end of the scan line of the 2i+1-th row of pixel units.

9. A display panel, characterized in that: The display driving circuit comprises the display driving circuit according to any one of claims 1 to 8.

10. An intelligent terminal, characterized in that: Comprising the display panel as claimed in claim 9.

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