Driving scanning circuit and display device
By adjusting the pulse width and timing during the scanning cycle, the first and second scanning control units are activated respectively, thus solving the reliability problem caused by transistor bias voltage stress in the liquid crystal display and improving the display quality.
Patent Information
- Application Number
- CN202520319353.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2026-03-20
- Estimated Expiration
- 2035-02-26
AI Technical Summary
Existing LCD screens have bias voltage stress on their TFT transistors, which reduces their reliability and affects display quality.
During the scan cycle, the first scan control unit and the second scan control unit are activated by the first pulse respectively to avoid continuous input of positive bias voltage during the forward scan or reverse scan phase. By adjusting the pulse width and timing, the transistor characteristic drift problem is solved.
It improves the reliability of TFT transistors, enhances display quality, avoids transistor characteristic drift and signal crosstalk, and improves display effect.
Smart Images
Figure CN224020432U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of transistor characteristic offset technology for driving scanning circuits, and particularly to a driving scanning circuit and a display device. Background Technology
[0002] The bias stress of a TFT transistor in a liquid crystal display (LCD) refers to a physical effect caused by the bias voltage applied between the gate, source, and drain electrodes of the TFT transistor during operation. The principle is as follows: various defects and trapped states exist within and at the interfaces of semiconductor materials. Under bias voltage, charge carriers are trapped, leading to changes in charge distribution and generating bias stress.
[0003] Displays subjected to bias stress pose reliability risks. For example, DC bias may cause drift in the characteristics of some TFTs in the display, leading to abnormal phenomena. Specifically, bias stress can alter the threshold voltage of TFT transistors, changing the voltage conditions for device turn-on and turn-off, affecting display brightness and color uniformity. It may also reduce carrier mobility in the channel, resulting in slower TFT transistor turn-on speed, longer image response time, and ghosting. Furthermore, it can disrupt the normal operating state of transistors, increasing leakage current, power consumption, and causing signal crosstalk between adjacent pixels, thus reducing display quality. Utility Model Content
[0004] Existing TFT transistors in liquid crystal displays suffer from bias voltage stress, which reduces their reliability and lowers display quality.
[0005] To address the aforementioned issues, a driving scanning circuit and display device are proposed. By activating the first scanning control unit with a first pulse and the second scanning control unit with a second pulse during the scanning cycle, the continuous positive bias voltage input to the transistor at the first or third level input terminal is avoided during the forward or reverse scanning phase. This solves the problem of transistor characteristic drift and subsequent display quality degradation caused by existing methods.
[0006] Firstly, a driving scanning circuit includes:
[0007] First scanning control unit and second scanning control unit;
[0008] Drop-down unit;
[0009] Drive output unit;
[0010] The first scanning control unit, the second scanning control unit, the drive output unit, and the first end of the pull-down unit are all connected to a common connection point, and the second end of the pull-down unit is also electrically connected to the drive output unit.
[0011] The first scanning control unit is activated by a first pulse during the scanning cycle, and the second scanning control unit is activated by a second pulse during the scanning cycle. The pulse width is the product of the first pulse and the second pulse by a predetermined multiple.
[0012] In conjunction with the driving scanning circuit described in this utility model, in a first possible embodiment, the first scanning control unit includes:
[0013] First transistor;
[0014] First level input terminal and second level input terminal;
[0015] The first level input terminal is electrically connected to the drain of the first transistor, and the second level input terminal is electrically connected to the gate of the first transistor.
[0016] The source of the first transistor is connected to the common junction.
[0017] The first level input terminal is used to input the first pulse with a specified timing.
[0018] In conjunction with the first possible embodiment of this utility model, in the second possible embodiment, the second scanning control unit includes:
[0019] Second transistor;
[0020] Third-level input terminal and fourth-level input terminal;
[0021] The third level input terminal is electrically connected to the source of the second transistor, and the fourth level input terminal is electrically connected to the gate of the second transistor.
[0022] The drain of the second transistor is connected to the common junction.
[0023] The third level input terminal is used to input the second pulse with a specified timing.
[0024] In conjunction with the second possible implementation of this utility model, in the third possible implementation, the second level input terminal and the fourth level input terminal are respectively the start level input terminal and the reset level input terminal, the start level input terminal is used to start forward scan, and the reset level input terminal is used to start reverse scan.
[0025] In conjunction with the third possible embodiment of this utility model, and in the fourth possible embodiment, the drive output unit includes:
[0026] The third transistor and the first capacitor;
[0027] The gate of the third transistor, the first terminal of the first capacitor, and the common connection point are all connected together.
[0028] The source of the third transistor, the second terminal of the first capacitor, and the second terminal of the pull-down unit are all connected to the output terminal;
[0029] The drain of the third transistor is electrically connected to the fifth level input terminal.
[0030] In conjunction with the fourth and fifth possible embodiments of this utility model, the scanning cycle is 6 times the pulse width, and the time difference between the first pulse and the second pulse is 5 times the pulse width.
[0031] In a second aspect, a display device includes the driving scanning circuit described in the first aspect.
[0032] By implementing the driving scanning circuit and display device described in this utility model, the first scanning control unit is activated by a first pulse and the second scanning control unit is activated by a second pulse during the scanning cycle. This avoids the continuous input of positive bias voltage to the transistor at the first level input terminal or the third level input terminal during the forward scanning or reverse scanning phase, thus solving the existing problem of transistor characteristic drift and resulting in a decrease in display quality. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the module connection of the driving scan circuit in this application;
[0035] Figure 2 This is a schematic diagram of the first embodiment of the driving scanning circuit in this application;
[0036] Figure 3 This is a schematic diagram of a second embodiment of the driving scanning circuit in this application;
[0037] Figure 4 This is a schematic diagram of the driving timing corresponding to the driving scanning circuit in this application. Detailed Implementation
[0038] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0043] Existing TFT transistors in liquid crystal displays suffer from bias voltage stress, which reduces their reliability and lowers display quality.
[0044] To address the above problems, a driving scanning circuit and a display device are proposed.
[0045] Firstly, a driving scanning circuit, such as Figure 1 , Figure 1This is a schematic diagram of the module connection of the driving scanning circuit in this application, including a first scanning control unit 100, a second scanning control unit 200, a pull-down unit 300, and a driving output unit 400. The first terminals of the first scanning control unit 100, the second scanning control unit 200, the driving output unit 400, and the pull-down unit 300 are connected to a common connection point, and the second terminal of the pull-down unit 300 is also electrically connected to the driving output unit 400. The first scanning control unit 100 is turned on with a first pulse during the scanning cycle, and the second scanning control unit 200 is turned on with a second pulse during the scanning cycle. The pulse width is multiplied by a predetermined multiple of the first and second pulses. By turning on the first scanning control unit 100 with a first pulse and the second scanning control unit 200 with a second pulse during the scanning cycle, the continuous positive bias voltage input to the transistor at the first level input terminal CK1 or the third level input terminal CK6 during the forward or reverse scanning phase is avoided, thus solving the existing problem of transistor characteristic drift and resulting in a decrease in display quality.
[0046] Furthermore, such as Figure 2 , Figure 2 This is a schematic diagram of the first embodiment of the driving scan circuit in this application; the first scan control unit 100 includes a first transistor T1; a first level input terminal CK1 and a second level input terminal STV; the first level input terminal CK1 is electrically connected to the drain of the first transistor T1, and the second level input terminal STV is electrically connected to the gate of the first transistor T1; the source of the first transistor T1 is connected to a common junction; the first level input terminal CK1 is used to input a first pulse with a specified timing.
[0047] Furthermore, the second scan control unit 200 includes a second transistor T2; a third-level input terminal CK6 and a fourth-level input terminal RST; the third-level input terminal CK6 is electrically connected to the source of the second transistor T2, and the fourth-level input terminal RST is electrically connected to the gate of the second transistor T2; the drain of the second transistor T2 is connected to a common junction; the third-level input terminal CK6 is used to input a second pulse with a specified timing.
[0048] Furthermore, the second level input terminal STV and the fourth level input terminal RST are the start level input terminal and the reset level input terminal, respectively. The start level input terminal is used to start the forward scan, and the reset level input terminal is used to start the reverse scan.
[0049] Furthermore, the drive output unit 400 includes a third transistor T10 and a first capacitor C1; the gate of the third transistor T10, the first terminal of the first capacitor C1, and the common connection point are connected together; the source of the third transistor T10, the second terminal of the first capacitor C1, and the second terminal of the pull-down unit 300 are connected together to the output terminal; the drain of the third transistor T10 is electrically connected to the fifth level input terminal CK2.
[0050] like Figure 3 , Figure 3 This is a schematic diagram of the second embodiment of the drive scanning circuit in this application; in this embodiment, the pull-down unit 300 includes a level signal input terminal VGL and a level signal input terminal GOFF, transistors (T3, T4, T5, T6, T7, T8, T9), and the pull-down unit is used to pull down point P and output terminal Gout during the actual stage to prevent point P and Gout output from rising.
[0051] like Figure 4 , Figure 4 This is a schematic diagram of the driving timing corresponding to the driving scanning circuit in this application. The scanning period is 6 times the pulse width, and the time difference between the first pulse and the second pulse is 5 times the pulse width. In this embodiment, the scanning period refers to the driving timing of each pulse of CK1-CK6. The forward or reverse scanning period includes multiple scanning periods, such as... Figure 4 The scan cycle within the dashed box in the image.
[0052] In this embodiment, the gate of the first transistor T1 is connected to STV, the drain is connected to CK1, and the source is connected to point P. For the second transistor T2, the gate is connected to RST, the source is connected to CK6, and the source is connected to point P. Combined with the timing, the drain of T1 is an alternating pulse waveform. In one scan cycle, the high level is only 1 / 6 = 16.7%, which is far lower than the long-term DC drive in the prior art. This improves the reliability of the gate drive circuit, avoids T1 characteristic drift, and improves product competitiveness.
[0053] In a second aspect, a display device includes the driving scanning circuit of the first aspect.
[0054] The driving scanning circuit and display device of this utility model solves the problem of transistor characteristic drift and display quality degradation caused by the first scanning control unit 100 being turned on with a first pulse and the second scanning control unit 200 being turned on with a second pulse during the scanning cycle. This avoids the continuous input of positive bias voltage to the transistor by the first level input terminal CK1 or the third level input terminal CK6 during the forward or reverse scanning phase.
[0055] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A driving scanning circuit, characterized in that, include: First scanning control unit and second scanning control unit; Drop-down unit; Drive output unit; The first scanning control unit, the second scanning control unit, the drive output unit, and the first end of the pull-down unit are all connected to a common connection point, and the second end of the pull-down unit is also electrically connected to the drive output unit. The first scanning control unit is activated by a first pulse during the scanning cycle, and the second scanning control unit is activated by a second pulse during the scanning cycle. The pulse width is the product of the first pulse and the second pulse by a predetermined multiple.
2. The driving scanning circuit according to claim 1, characterized in that, The first scanning control unit includes: First transistor; First level input terminal and second level input terminal; The first level input terminal is electrically connected to the drain of the first transistor, and the second level input terminal is electrically connected to the gate of the first transistor. The source of the first transistor is connected to the common junction. The first level input terminal is used to input the first pulse with a specified timing.
3. The driving scanning circuit according to claim 2, characterized in that, The second scanning control unit includes: Second transistor; Third-level input terminal and fourth-level input terminal; The third level input terminal is electrically connected to the source of the second transistor, and the fourth level input terminal is electrically connected to the gate of the second transistor. The drain of the second transistor is connected to the common junction. The third level input terminal is used to input the second pulse with a specified timing.
4. The driving scanning circuit according to claim 3, characterized in that, The second level input terminal and the fourth level input terminal are respectively the start level input terminal and the reset level input terminal. The start level input terminal is used to start forward scan, and the reset level input terminal is used to start reverse scan.
5. The driving scanning circuit according to claim 4, characterized in that, The drive output unit includes: The third transistor and the first capacitor; The gate of the third transistor, the first terminal of the first capacitor, and the common connection point are all connected together. The source of the third transistor, the second terminal of the first capacitor, and the second terminal of the pull-down unit are all connected to the output terminal; The drain of the third transistor is electrically connected to the fifth level input terminal.
6. The driving scanning circuit according to claim 5, characterized in that, The scanning cycle is 6 times the pulse width, and the time difference between the first pulse and the second pulse is 5 times the pulse width.
7. A display device, characterized in that, Includes the driving scanning circuit as described in any one of claims 1-6.