Infrared detector and control method, preparation method thereof

Abstract

This application provides an infrared detector and its control and fabrication methods, relating to the field of infrared imaging equipment technology, and aims to solve the problem of high circuit design and manufacturing costs. The readout circuit of the infrared detector includes N column readout circuits, a row scanning circuit including M sub-scanning circuits, and a connection node array. The connection node array includes M×N pairs of first nodes and second nodes. The first nodes are connected to the column readout circuits via sub-scanning circuits, and the second nodes are connected to a ground terminal via sub-scanning circuits. The first array includes multiple first pixels arranged in P rows and Q columns, where M > P and / or N > Q. The Q columns of first pixels are connected to the Q column readout circuits respectively. The readout circuits are configured to control the Q column readout circuits connected to the first array to read data during row-by-row scanning of the P rows of first pixels. The above-described infrared detector can be used for infrared imaging.

Description

Technical Field

[0001] This application relates to the field of infrared imaging equipment technology, and in particular to an infrared detector and its control and preparation methods. Background Technology

[0002] Infrared detectors typically include a pixel array and readout integration circuits (RIOCs) connected to the pixel array. The pixel array consists of multiple infrared sensing pixels arranged in multiple rows and columns. During operation, the infrared sensing pixels convert the light or heat radiation emitted by the target object into changes in their own resistance value. The readout circuits amplify and read out these changes in resistance value, and finally process and output an infrared image based on the readout results.

[0003] In a pixel array, the actual physical size of each infrared sensing pixel is called the pixel size. The pixel size reflects, to some extent, the infrared detector's light response capability and is a characterization of its sensitivity. For example, the larger the pixel size, the more photons it can receive, and the more charge it generates under the same lighting conditions and exposure time. Therefore, it is more suitable for use in low-light or low-infrared radiation environments. Conversely, the smaller the pixel size, the more pixels can be placed in the same area of ​​the array, resulting in higher pixel resolution and more distinct detail signals, making it more suitable for high-resolution applications.

[0004] Infrared sensors of different sizes can meet different application requirements, but one readout circuit can only be adapted to one type of infrared sensor size. For infrared sensors of different sizes, different readout circuits are required to read out the data, which increases the circuit design and manufacturing cost of the readout circuit and the infrared detector. Summary of the Invention

[0005] This application provides an infrared detector and its control and preparation methods to address the problem of high circuit design and manufacturing costs for infrared detectors.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] On the one hand, an infrared detector is provided, the infrared detector comprising:

[0008] The readout circuit includes column readout circuits, row scanning circuits, and a connection node array. The column readout circuits are arranged with N units corresponding to N columns. The row scanning circuits include M sub-scanning circuits corresponding to M rows. The connection node array includes M×N pairs of first nodes and second nodes arranged in M ​​rows and N columns. The first node is connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node is connected to a ground terminal through the sub-scanning circuit of its row.

[0009] A first array disposed on the readout circuit, the first array comprising P×Q first pixels arranged in P rows of first pixels and Q columns of first pixels;

[0010] Where M, N, P and Q are all positive integers, and M > P and / or N > Q;

[0011] One end of the first pixel in the first pixel column is connected to a column readout circuit through the first node and the sub-scanning circuit, and the other end is connected to the ground terminal through the second node and the sub-scanning circuit;

[0012] Q of the first pixel columns are respectively connected to Q of the column readout circuits;

[0013] The readout circuit is configured to control the Q column readout circuits connected to the first array to read data while controlling the row scanning circuit to scan the P first cell rows in the first array line by line, and to control the column readout circuits not connected to the first array not to read data.

[0014] Using the infrared detector provided in the embodiments of this application, a first array is set on the readout circuit corresponding to the M rows and N columns of the pixel array. The number of rows in the first array is less than M and / or the number of columns is less than N. The size of the first pixel in the first array is larger than the pixel size designed by the readout circuit. This design can get rid of the limitation that a readout circuit can only adapt to infrared sensing pixels of one pixel size, thereby saving the cost of circuit design and manufacturing in the infrared detector.

[0015] In some embodiments, M = K1 × P, N = K2 × Q, where K1 and K2 are both positive integers;

[0016] In the first node of adjacent row K1 and column K2, there is a first node connected to the first cell;

[0017] In the second node of adjacent row K1 and column K2, there is a second node connected to the first cell;

[0018] The first node and the second node, which are connected to the same first cell, are located in different rows and / or different columns of the connected node array.

[0019] In some embodiments, both K1 and K2 are equal to 2.

[0020] In some embodiments, in the connection node array, the first node and the second node are both independent node structures;

[0021] The first node connected to the first pixel (X1, Y1) is A(X A ,Y A ), and the first pixel (X) C Y C The second node connected to ) is B(X) B ,Y B );

[0022] Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column;

[0023] The first node A(X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column;

[0024] The second node B(X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column;

[0025] And satisfy:

[0026] X A =2×X1-1,Y A =2×Y1-1;

[0027] X B =2×X1,Y B = 2 × Y1.

[0028] In some embodiments, in the same column of the connection node array, the first node and the second node in the adjacent next row have the same structure;

[0029] The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B(X). B ,Y B );

[0030] Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column;

[0031] The first node A(X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column;

[0032] The second node B(X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column;

[0033] And satisfy:

[0034] X A =2×X1-1,Y A =2×Y1-1;

[0035] X B =2×X1,Y B = 2 × Y1 - 1.

[0036] In some embodiments, the sub-scanning circuit includes a first row selection switch and a second row selection switch; the two ends of the first row selection switch are respectively connected to the first node and the column readout circuit of the column in which it is located, and the two ends of the second row selection switch are respectively connected to the second node and the ground terminal.

[0037] The row scanning circuit further includes a timing control circuit, which is connected to both the first row selection switch and the second row selection switch, and is configured to perform row-by-row scanning of P first cell rows in the first array by controlling the on and off states of the first row selection switch and the second row selection switch.

[0038] In some embodiments, one first cell row corresponds to K adjacent sub-scanning circuits, where K is a positive integer greater than 1;

[0039] The timing control circuit includes:

[0040] M timing signal receivers, configured to receive row selection timing signals for sequential scanning of the M sub-scanning circuits; and

[0041] P first sub-circuits are set for each of the P first cell rows. One end of the first sub-circuit is connected to the first row selection switch and the second row selection switch connected to the first cell row. The other end of the first sub-circuit is connected to K timing signal receivers. The K timing signal receivers are the part of the M timing signal receivers that correspond to the first cell rows.

[0042] When any of the K timing signal receivers receives a row selection timing signal, the first sub-circuit is configured to control both the first row selection switch and the second row selection switch connected to the first sub-circuit to be turned on.

[0043] In some embodiments, the first sub-circuit includes an OR gate, the output of which is connected to the first row selector switch, and the input of which is connected to the K timing signal receivers.

[0044] In some embodiments, the timing control circuit further includes M second sub-circuits corresponding to the M sub-scanning circuits. One end of the second sub-circuit is connected to the first row selection switch and the second row selection switch in the sub-scanning circuit, and the other end of the second sub-circuit is connected to the timing signal receiving end corresponding to the sub-scanning circuit.

[0045] The second sub-circuit is configured to control the first row selection switch and the second row selection switch connected to the second sub-circuit to be turned on when the row selection timing signal is received;

[0046] The readout circuit further includes a mode switching circuit, which includes a first mode switch and a second mode switch with opposite switching states. The first mode switch is disposed in the first sub-circuit, and the second mode switch is disposed in the second sub-circuit.

[0047] In some embodiments, the column readout circuit includes a circuit bias circuit, an integrator, and a sample-and-hold circuit connected in sequence;

[0048] The readout circuit also includes a mode switching circuit, which includes a third mode switch, and the third mode switch includes a first sub-switch and a second sub-switch with opposite switching states.

[0049] In the column readout circuit not connected to the first cell column, the first sub-switch is disposed between the integrator and the sample-and-hold circuit, and the second sub-switch is disposed between the sample-and-hold circuit and the ground terminal.

[0050] In some embodiments, N = 2 × Q;

[0051] In the N column readout circuits, the column readout circuits in odd-numbered order are connected to the first cell column in the first array.

[0052] On the other hand, another infrared detector is provided, the infrared detector comprising:

[0053] A substrate includes a readout circuit, which comprises column readout circuits, row scanning circuits, and a connection node array. The column readout circuits are arranged with N units corresponding to N columns. The row scanning circuits include M sub-scanning circuits corresponding to M rows. The connection node array includes M×N pairs of first nodes and second nodes arranged with M rows and N columns. The first node is connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node is connected to a ground terminal through the sub-scanning circuit of its row.

[0054] A first array located on one side of the substrate, the first array comprising P×Q first pixels arranged in P rows and Q columns; wherein M, N, P, and Q are all positive integers, M > P and / or N > Q; and

[0055] A connecting pier is disposed between the first array and the substrate, the connecting pier connecting the first pixel and a first node and a second node corresponding to the first pixel in the substrate; one end of the first pixel in the first pixel column is connected to a column readout circuit through the connecting pier, the first node, and the sub-scanning circuit, and the other end is connected to the ground terminal through the connecting pier, the second node, and the sub-scanning circuit; Q first pixel columns are respectively connected to Q column readout circuits;

[0056] The readout circuit is configured to control the row scanning circuit to scan the P first cell rows in the first array row by row, while controlling the Q column readout circuits connected to the first array to read data, and controlling the column readout circuits not connected to the first array not to read data.

[0057] In some embodiments, M = K1 × P, N = K2 × Q, where K1 and K2 are both positive integers;

[0058] In the first node of adjacent row K1 and column K2, there is a first node connected to the first cell;

[0059] In the second node of adjacent row K1 and column K2, there is a second node connected to the first cell;

[0060] The first node and the second node connected to the same first cell are located in different rows and / or different columns of the connected node array;

[0061] The end of the connecting pier closest to the substrate is connected to a first node and a second node connected to the first pixel, and the end of the connecting pier furthest from the substrate is connected to the corresponding first pixel.

[0062] In some embodiments, both K1 and K2 are equal to 2.

[0063] In some embodiments, in the connection node array, the first node and the second node are both independent node structures;

[0064] The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B(X). B ,Y B The first node A(X) A ,Y A ) and the second node B(X) B ,Y B All of them are connected to the connecting piers;

[0065] Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column;

[0066] The first node A(X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column, and satisfying X A =2×X1-1,Y A =2×Y1-1;

[0067] The second node B(X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column, and satisfying X B =2×X1,Y B = 2 × Y1.

[0068] In some embodiments, in the same column of the connection node array, the first node and the second node in the adjacent next row have the same structure;

[0069] The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B(X). B ,Y BThe first node A(X) A ,Y A ) and the second node B(X) B ,Y B All of them are connected to the connecting piers;

[0070] Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column;

[0071] The first node A(X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column, and satisfying X A =2×X1-1,Y A =2×Y1-1;

[0072] The second node B(X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column, and satisfying X B =2×X1,Y B = 2 × Y1 - 1.

[0073] In some embodiments, in the first node and the second node that are not connected to the first cell, some or all of them are left empty, or some or all of them are provided with insulating piers.

[0074] The insulating bridge pier supports the first pixel at the end furthest from the substrate.

[0075] In another aspect, a control method for an infrared detector is provided, applied to the infrared detector described in any of the above embodiments; the control method includes:

[0076] During the process of controlling the row scanning circuit to scan the P first cell rows in the first array line by line, the Q column readout circuits connected to the first array are controlled to read data, while the column readout circuits not connected to the first array are controlled not to read data.

[0077] In some embodiments, in the infrared detector, M = K1 × P, N = K2 × Q; a first pixel row in the first array corresponds to K1 adjacent sub-scanning circuits, and a first pixel column corresponds to K2 adjacent column readout circuits; wherein, K1 and K2 are both positive integers;

[0078] In the control method, the control row scanning circuit performs row-by-row scanning of P first cell rows in the first array, including:

[0079] Receive row selection timing signals for scanning M sub-scanning circuits line by line;

[0080] In the K1 row selection timings corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit;

[0081] The control of the Q column readout circuits connected to the first array to read data, and the control of the column readout circuits not connected to the first array to not read data, includes:

[0082] In the K2 adjacent column readout circuits corresponding to the first pixel column, the column readout circuits connected to the first pixel column are controlled to read data, while the column readout circuits not connected to the first array are controlled not to read data.

[0083] In some embodiments, in the infrared detector, M = 2 × P, N = 2 × Q, and in the N column readout circuits, the column readout circuits in odd order are connected to the first cell column in the first array;

[0084] In the control method, the control row scanning circuit performs row-by-row scanning of P first cell rows in the first array, including:

[0085] Receive row selection timing signals for scanning M sub-scanning circuits line by line;

[0086] In the two row selection timings corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit;

[0087] The control of the Q column readout circuits connected to the first array to read data, and the control of the column readout circuits not connected to the first array to not read data, includes:

[0088] The column readout circuits in odd-numbered order are controlled to read data, while the column readout circuits in even-numbered order are controlled not to read data.

[0089] Furthermore, a method for fabricating an infrared detector is provided, for use in the infrared detector described in any of the above embodiments; the fabrication method includes:

[0090] A substrate is provided; the substrate has a readout circuit, the readout circuit including column readout circuits, row scanning circuits and a connection node array, the column readout circuits being arranged N times corresponding to N columns; the row scanning circuits including M sub-scanning circuits corresponding to M rows; the connection node array including M×N pairs of first nodes and second nodes arranged corresponding to M rows and N columns, the first node being connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node being connected to a ground terminal through the sub-scanning circuit of its row;

[0091] A connecting pier is fabricated on the substrate, and the connecting pier is disposed in the connecting node array and configured as a first node and a second node connected to the first array;

[0092] A first pixel is formed on the side of the connecting pier away from the substrate to form a first array;

[0093] The first array comprises P×Q first pixels arranged in P rows and Q columns; M, N, P and Q are all positive integers, and M > P and / or N > Q. Attached Figure Description

[0094] Figure 1 An architectural diagram of an infrared detector provided for an embodiment of this application;

[0095] Figure 2A This is a schematic diagram of the structure of the second array provided in an embodiment of this application;

[0096] Figure 2B A schematic diagram of the structure of the first array provided in an embodiment of this application;

[0097] Figure 3 This is a schematic diagram illustrating the connection between a readout circuit and a second array, provided in an embodiment of this application.

[0098] Figure 4 for Figure 3 A schematic diagram showing the connection between the readout circuit and the first array;

[0099] Figure 5A This is a schematic diagram illustrating the connection between the connection node array and the second array provided in an embodiment of this application;

[0100] Figure 5B This is a schematic diagram illustrating the connection between the connection node array and the first array provided in an embodiment of this application;

[0101] Figure 6 A partial circuit diagram of a row scanning circuit provided in an embodiment of this application;

[0102] Figure 7A for Figure 6 Timing diagram of the central scanning circuit in the second pixel mode;

[0103] Figure 7B for Figure 6 Timing diagram of the central scanning circuit in the first pixel mode;

[0104] Figure 8 A circuit diagram of a column readout circuit connected to a third mode switch, provided for an embodiment of this application;

[0105] Figure 9 A hierarchical structure diagram of an infrared detector provided in an embodiment of this application;

[0106] Figure 10 This is a schematic diagram showing the connection between another readout circuit and the second array provided in an embodiment of this application;

[0107] Figure 11 for Figure 10 A schematic diagram showing the connection between the readout circuit and the first array;

[0108] Figure 12A This is a schematic diagram illustrating the connection between the connection node array and the second array provided in an embodiment of this application;

[0109] Figure 12B This is a schematic diagram illustrating the connection between the connection node array and the first array provided in an embodiment of this application;

[0110] Figure 13 A hierarchical structure diagram of another infrared detector provided in an embodiment of this application;

[0111] Figure 14 A flowchart illustrating a control method for an infrared detector provided in an embodiment of this application;

[0112] Figure 15 This is a flowchart illustrating a method for fabricating an infrared detector, as provided in an embodiment of this application. Detailed Implementation

[0113] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application. Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", or "some examples", etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned can be included in any suitable manner in any one or more embodiments or examples.

[0114] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0115] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0116] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0117] "A and / or B" includes the following three combinations: A only, B only, and A and B.

[0118] As used herein, depending on the context, the term “if” is optionally interpreted as meaning “when…” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination…” or “if [the stated condition or event] is optionally interpreted as meaning “in response to determination…” or “in response to detection [the stated condition or event]” or “in response to detection [the stated condition or event].” The use of “applies to” or “configured to” herein implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps.

[0119] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0120] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0121] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0122] Figure 1 An architectural diagram of an infrared detector provided in an embodiment of this application is shown below. Figure 1 As shown, the infrared detector 100 includes a pixel array 1 and readout integration circuits (RIOC) 3. The pixel array 1 includes multiple infrared sensing pixels 2 arranged in multiple rows and columns within the array region of the readout integration circuit 3. Each infrared sensing pixel 2 includes a pixel body with pixel resistance and two connection terminals located at the outer periphery of the pixel body. The two connection terminals of the infrared sensing pixel 2 are connected to the readout integration circuit 3 via a conductive structure, thereby establishing the connection between the infrared sensing pixel 2 and the readout integration circuit 3. This conductive structure connecting the infrared sensing pixel 2 and the readout integration circuit 3 is also referred to as a "connection bridge." In other words, the infrared sensing pixels 2 in the pixel array 1 are connected to the readout integration circuit 3 through two connection bridges.

[0123] Each infrared sensor pixel 2 includes a pixel resistor made of a material capable of sensing visible light or infrared radiation energy. The material used to make the pixel resistor can be, for example, vanadium oxide, silicon, or titanium oxide. During operation, the infrared sensor pixel 2 converts the light or heat radiation from the target object into a change in its own resistance value.

[0124] The readout circuit 3 in the infrared detector 100 is used to extract, integrate, sample / hold, and perform analog-to-digital conversion on the resistance changes of the infrared sensing pixels 2 in the pixel array 1, and then output the data to the controller 4. The controller 4 performs infrared imaging based on the received signal. It should be noted that the controller 4 is typically a host computer connected to the infrared detector 100; however, in some scenarios, the controller 4 can be part of the readout circuit 3. Although this embodiment is described using an example where the readout circuit 3 does not include the controller 4, the solution provided in this embodiment is equally applicable to infrared detectors 100 that include the controller 4.

[0125] In the pixel array 1 of the infrared detector 100, the actual physical size of the infrared sensing pixel 2 is the pixel size. The pixel size reflects the light response capability of the infrared detector 100 to a certain extent and is a characterization of the sensitivity of the infrared detector 100. In different application scenarios, the pixel size of the infrared sensing pixel 2 in the infrared detector 100 may be different.

[0126] For example, the larger the pixel size of the infrared sensor 2, the more photons it can receive, and the more charge it generates under the same lighting conditions and exposure time, resulting in a more pronounced response under low light or low radiation conditions. Therefore, infrared sensor 2 with a larger pixel size is more suitable for use in low light or low infrared radiation environments.

[0127] The smaller the pixel size of the infrared sensing pixel 2, the more infrared sensing pixels 2 can be placed in the same area of ​​the array. The more infrared sensing pixels 2 there are, the higher the resolution of the infrared detector 100 and the clearer the detail signals. Therefore, infrared sensing pixels 2 with smaller pixel sizes are more suitable for high-resolution applications.

[0128] For infrared sensing pixels 2 of different pixel sizes, the size of the pixel body is different, and the positions of the two connecting ends located at the outer peripheral edge of the pixel body are also different.

[0129] Infrared detector 100 typically fabricates infrared sensing pixels 2 on a wafer after the readout circuit 3 has been fabricated to form pixel array 1. In related technologies, the readout circuit is designed only for infrared sensing pixels of one pixel size. After fabrication, the readout circuit has connection nodes adapted to infrared sensing pixels of the corresponding pixel size and circuitry connected to these connection nodes. The position of the connection nodes on the readout circuit is fixed. Based on the fixed-position connection nodes, infrared sensing pixels of the corresponding size are fabricated. The connection ends in the infrared sensing pixels are connected to the connection nodes via connection bridges.

[0130] Therefore, the readout circuit after fabrication can only be adapted to infrared sensing pixels of one pixel size. Different readout circuits are required for infrared sensing pixels of different pixel sizes, which leads to an increase in the circuit design and manufacturing cost of infrared detectors.

[0131] In view of this, embodiments of this application provide an infrared detector including a readout circuit that can be adapted to both a first array and a second array. The first array includes multiple first pixels arranged in multiple rows and columns, and the second array includes multiple second pixels arranged in multiple rows and columns. The pixel size of the first pixels is larger than the pixel size of the second pixels. In other words, the readout circuit can adapt to infrared sensing pixels of two different pixel sizes.

[0132] It should be noted that, in this article, "adaptation" means that the two can meet the conditions for connection and can be connected when needed.

[0133] The readout circuit is based on a second pixel design that can adapt to smaller pixel sizes. By improving the design, the readout circuit can also adapt to first pixels with larger pixel sizes, thereby overcoming the limitation that the readout circuit can only adapt to infrared sensing pixels of one pixel size and reducing the circuit design and manufacturing costs of infrared detectors.

[0134] The following sections describe the connection and working principle of the readout circuit with the second array and the connection and working principle of the readout circuit with the first array, respectively, to explain how to improve the readout circuit based on the readout circuit designed for smaller pixel sizes, so that the readout circuit can be adapted to the first pixel with larger pixel sizes.

[0135] For ease of understanding and description, the following example uses the second pixel as a single pixel and the first pixel as a 2×2 pixel. It should be noted that neither a single pixel nor a 2×2 pixel specifically refers to an infrared sensing pixel of a particular size. Single pixel and 2×2 pixel are relative concepts. The pixel size of a 2×2 pixel is equivalent to the size of four single pixels arranged in a 2×2 (two rows and two columns) configuration. The area occupied by one 2×2 pixel can accommodate four single pixels arranged in a 2×2 configuration. For example, when the pixel size of a single pixel is S, the pixel size of a 2×2 pixel is 2×2×S. However, the embodiments of this application do not limit the specific size of a single pixel.

[0136] Figure 2A This is a schematic diagram of the structure of the second array provided in an embodiment of this application, as shown below. Figure 2AAs shown, the second array 6 includes M×N second pixels 61 arranged in M ​​rows and N columns in the array region 5. The M×N second pixels 61 form M second pixel rows 62 and N second pixel columns 63. Each second pixel row 62 includes N second pixels 61 arranged along a first direction X, and each second pixel column 63 includes M second pixels 61 arranged along a second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0137] In this paper, the second pixels (1,1) to (M,N) are used to represent each second pixel 61 of the second array 6. For example, the second pixel (X,Y) represents the second pixel 61 located in the Xth row and Yth column of the second array 6.

[0138] Figure 2B Please refer to the schematic diagram of the first array provided in the embodiment of this application. Figure 2A and Figure 2B As described above, the pixel size of the first pixel 71 is equivalent to the size of four second pixels 61 arranged in a 2×2 configuration. One first pixel 71 can be placed in the area occupied by four second pixels 61 in two adjacent rows and two columns. Therefore, when setting the first pixel 71 in the array area 5 of the second array 6, P×Q first pixels 71 arranged in P rows and Q columns can be set, where M equals 2P and N equals 2Q.

[0139] P×Q first pixels 71 form a first array 7. The first array 7 includes P first pixel rows 72 and Q first pixel columns 73. Each first pixel row 72 includes Q first pixels 71 arranged along a first direction X, and each first pixel column 73 includes P first pixels 71 arranged along a second direction Y.

[0140] Please continue to combine Figure 2A and Figure 2B In the first array 7, a first cell row 72 is in the same position as two adjacent second cell rows 62 in the second array 6; in the first array 7, a first cell column 73 is in the same position as two adjacent second cell columns 63 in the second array 6.

[0141] In this document, each first pixel 71 of the first array 7 is represented by first pixel (1,1) to (P,Q). For example, first pixel (X,Y) represents the first pixel 71 in the first array 7 located in the Xth row and Yth column.

[0142] Figure 3 This is a schematic diagram illustrating the connection between a readout circuit and a second array, provided in an embodiment of this application. Figure 4 for Figure 3 A schematic diagram of the connection between the readout circuit and the first array is shown below. Figure 3 and Figure 4 As shown, the readout circuit 3 includes a column readout circuit 9, a connection node array, a row scanning circuit, a mode switching circuit, and a signal processing circuit 8.

[0143] The column readout circuits 9 are configured with N corresponding to the N second pixel columns 63 in the second array 6. These N column readout circuits 9 are configured to read data from the N second pixel columns 63 in the second array 6, and their outputs are all connected to the signal processing circuit 8. Figure 3 and Figure 4 In the diagram, the N column readout circuits 9 are sequentially represented by CH_1 to CH_N; for example, column readout circuit CH_x represents column readout circuit 9 configured to read data from the second pixel 61 in the xth second pixel column 63 of the second array 6.

[0144] The readout circuit 3 has a connection node array in the array region for connecting the first array 7 or the second array 6 to the designed location of the readout circuit 3.

[0145] The connection node array includes M×N pairs of first nodes and second nodes, comprising M×N first nodes and M×N second nodes. The M×N first nodes and M×N second nodes are arranged in M ​​rows and N columns, with the row direction parallel to the first direction X and the column direction parallel to the second direction Y. In other words, the row and column directions of the M×N first nodes and M×N second nodes are parallel to the row and column directions of the M×N second pixels 61 in the second array 6 and the P×N first pixels 71 in the first array 7.

[0146] The M×N pairs of first and second nodes have a one-to-one correspondence with the M×N second pixels 61 in the second array 6, and each pair of first and second nodes is in a position that matches the corresponding second pixel 61. When the readout circuit 3 is connected to the second array 6, the second pixel 61 can be connected to the corresponding first and second nodes through the connecting pier.

[0147] In this paper, the first node is represented by A(1,1) to A(M,N), and the second node is represented by B(1,1) to B(M,N). The first node A(X,Y) represents the first node in the X-th row and Y-th column of the connecting node array; the second node B(X,Y) represents the second node in the X-th row and Y-th column of the connecting node array. Furthermore, the first node A(X,Y) and the second node B(X,Y) represent the first node and the second node adapted to the second pixel (X,Y), respectively. For example, the first node adapted to the second pixel (1,1) is A(1,1), and the second node adapted to the second pixel (1,1) is B(1,1).

[0148] As described above, a first pixel 71 can be set in the area occupied by four second pixels 61 in two adjacent rows and two columns. Among the first and second nodes corresponding to the four second pixels 61 in two adjacent rows and two columns, one first node and one second node can be adapted to the first pixel 71 in the same position. When the readout circuit 3 is connected to the first array 7, the first pixel 71 in the first array 7 can be connected to the adapted first node and second node through the connecting pier.

[0149] For ease of distinction and description, the first node in the connection node array that adapts to the first pixel 71 can be called the first adapter node, and the second node connected to the first pixel 71 can be called the second adapter node. Therefore, the connection node array includes P×Q pairs of first adapter nodes and second adapter nodes. These P×Q pairs of first adapter nodes and second adapter nodes are used to connect P×Q first pixels 71 in the first array 7, and have a one-to-one correspondence with the P×Q first pixels 71 in the first array 7. Each pair of first adapter nodes and second adapter nodes is positioned to adapt to the corresponding first pixel 71. When the readout circuit 3 is connected to the first array 7, the first pixel 71 in the first array 7 can be connected to its corresponding first adapter node and second adapter node via connecting piers.

[0150] Figure 5A This is a schematic diagram of the connection between the node array and the second pixel in the readout circuit provided in the embodiments of this application, as shown below. Figure 5A As shown, in the connection node array 10, the M×N first nodes and the M×N second nodes are all independent node structures. In each pair of first nodes and second nodes, that is, in the first node and second node that are adapted to the same second pixel 61, the first node and the second node are staggered by a certain distance in the first direction X and the second direction Y, so that there is space between the first node and the second node to allow the second pixel 61 to be set.

[0151] Figure 5B For a schematic diagram of the connection between the node array and the first pixel in the readout circuit provided in this application embodiment, please refer to... Figure 5A and Figure 5B The area occupied by a first pixel 71 is the same as the area occupied by four second pixels 61 arranged in a 2×2 pattern. Among the first and second nodes corresponding to the four second pixels 61 in two adjacent rows and two columns, one first node and one second node are adapted to the first pixel 71 in the same position; when the readout circuit 3 is connected to the first array 7, the first pixel 71 in the first array 7 is connected to the first node and the second node adapted to it.

[0152] For example, first node A(1,1) and second node B(1,1) are adapted to second pixel (1,1); first node A(1,2) and second node B(1,2) are adapted to second pixel (1,2); first node A(2,1) and second node B(2,1) are adapted to second pixel (2,1); and first node A(2,2) and second node B(2,2) are adapted to second pixel (2,2). Among the above four first nodes A(1,1), A(1,2), A(2,1) and A(2,2) and four second nodes B(1,1), B(1,2), B(2,1) and B(2,2), one first node and one second node are adapted to the first pixel (1,1) at the same position.

[0153] In some embodiments, the first node adapted to the first pixel (X1, Y1) is A(X A ,Y A ), and the first pixel (X) C Y C The second node to be adapted is B(X) B ,Y B ). Wherein, the first pixel (X1, Y1) is the first pixel in the first array 7 located in the X1 row and Y1 column; the first node A (X A ,Y A ) is the node in the Xth node of the connected node array 10. A row, Y A The first node of the column; the second node B(X) B ,Y B ) is the node in the Xth node of the connected node array 10. B row, Y B The second node of the column; and satisfying: X A =2×X1-1,Y A =2×Y1-1;X B =2×X1,Y B = 2 × Y1.

[0154] For example, the first node A (1,1) and the second node B (2,2) are adapted to the first pixel (1,1); the first node A (3,1) and the second node B (4,2) are adapted to the first pixel (2,1).

[0155] Please continue to refer to this. Figure 3 and Figure 4 In the readout circuit 3, the row scanning circuit includes a sub-scanning circuit and a timing control circuit. The sub-scanning circuit is configured with M sub-scanning circuits corresponding to M second pixel rows 62 in the second array 6. Each sub-scanning circuit includes a first row selection switch configured for the first node and a second row selection switch configured for the second node.

[0156] The row scanning circuit includes M×N first row selection switches and M×N second row selection switches. The M×N first row selection switches correspond to M×N first nodes. Each first row selection switch is positioned between the corresponding first node and the column readout circuit 9 to which that first node needs to be connected, controlling whether the first node is connected to the column readout circuit 9. When the first node is connected to the column readout circuit 9, the second pixel 61 connected to the first node is also connected to the column readout circuit 9.

[0157] Each sub-scan circuit includes N first row selection switches corresponding to N first nodes. The first row selection switches in the same sub-scan circuit have the same switching state during operation, and a unified symbol is used in this document. The first row selection switches in the M sub-scan circuits are sequentially represented by Row_1_1 to Row_M_1. For example, the first row selection switch Row_x_1 represents the first row selection switch located in the x-th sub-scan circuit. When the readout circuit 3 is connected to the second array 6, the first row selection switch Row_x_1 represents the first row selection switch corresponding to the second pixel 61 in the x-th second pixel row 62 of the second array 6.

[0158] In some embodiments, each sub-scanning circuit includes only one first row selector switch, and N first nodes are all connected to the corresponding column readout circuit 9 through the first row selector switch.

[0159] M×N second row selector switches are configured corresponding to M×N second nodes. Each first row selector switch is located between the corresponding second node and the ground terminal GND, used to control whether the second node is connected to the ground terminal GND. When the second node is connected to the ground terminal GND, the second pixel 61 connected to the second node is grounded.

[0160] Each sub-scan circuit includes N second row selection switches corresponding to N second nodes. The second row selection switches within the same sub-scan circuit have the same switching state during operation, and are represented by a unified notation throughout this document. The second row selection switches in the M sub-scan circuits are sequentially denoted by Row_1_2 to Row_M_2. For example, the second row selection switch Row_x_2 represents the second row selection switch located in the x-th sub-scan circuit. When the readout circuit 3 is connected to the second array 6, the first row selection switch Row_x_2 represents the second row selection switch corresponding to the second pixel 61 in the x-th second pixel row 62 of the second array 6.

[0161] In some embodiments, each sub-scanning circuit includes only one second row selector switch, and N second nodes are all connected to the ground terminal through the second row selector switch.

[0162] In this row scanning circuit, the timing control circuit includes M timing signal receivers, P first sub-circuits, and M second sub-circuits. M row selection timing receivers are configured to receive row selection timing signals from row 1 to row M, respectively, for each of the M sub-scanning circuits. During the row scanning process of the M sub-scanning circuits, the M row selection timing receivers sequentially receive the M row selection timing signals, thereby achieving row-by-row scanning of the M sub-scanning circuits.

[0163] The second sub-circuit is configured with M sub-scanning circuits corresponding to M sub-scanning circuits. One end of the second sub-circuit is connected to the first row selection switch and the second row selection switch in the corresponding sub-scanning circuit, and the other end of the second sub-circuit is connected to the timing signal receiving end of the corresponding sub-scanning circuit. The second sub-circuit is configured to control the first row selection switch and the second row selection switch connected to the second sub-circuit to conduct when the row selection timing signal is received; thereby, when the readout circuit 3 is connected to the second array 6, the second pixel row 62 in the second array 6 is connected to the column readout circuit 9 row by row.

[0164] The first sub-circuit is configured with P first pixel rows 72 corresponding to the first array 7. One end of the first sub-circuit is connected to the first row selection switch and the second row selection switch connected to the corresponding first pixel row 72, and the other end of the first sub-circuit is connected to the corresponding row selection timing receiver.

[0165] As described above, a first cell row 72 in the first array 7 is in the same position as two adjacent second cell rows 62 in the second array 6. Therefore, the first cell row 72 corresponds to two adjacent row selection timing receivers simultaneously; the other end of the first sub-circuit is connected to the corresponding two row selection timing receivers simultaneously.

[0166] The first sub-circuit is configured to turn on both the first row selection switch and the second row selection switch connected to the first pixel 71 in the first pixel row 72 when either of the two connected row selection timing receivers receives the row selection timing signal. Thus, when the readout circuit 3 is connected to the first array 7, during the row-by-row scanning process of the M sub-scanning circuits, it is possible to achieve row-by-row scanning of the P first pixel rows 72 in the first array 7, that is, the first pixel rows 72 in the first array 7 are connected to the column readout circuit 9 row by row.

[0167] In some embodiments, the first sub-circuit uses an OR gate to implement the above function, that is, the output of the OR gate is connected to the first row selection switch and the second row selection switch connected to the corresponding first cell row 72, and the input of the OR gate is connected to the two row selection timing receivers corresponding to the first cell row 72.

[0168] In some embodiments, in two row selection timing receivers connected to an OR gate, the preceding row selection timing receiver may be connected to the OR gate via a buffer.

[0169] To ensure that only one of the first and second sub-circuits in the timing control circuit operates, the readout circuit also includes a mode switching circuit. This circuit comprises a first mode switch and a second mode switch with opposite states. The first mode switch is located in the first sub-circuit, and the second mode switch is located in the second sub-circuit. When the readout circuit 3 is connected to the second array 6, by controlling the second mode switch to be on and the first mode switch to be off, the second sub-circuit operates normally, while the first sub-circuit does not; thus, the second pixel row 62 in the second array 6 is connected row by row to the column readout circuit 9.

[0170] When the readout circuit 3 is connected to the first array 7, by controlling the second mode switch to turn off and the first mode switch to turn on, the second sub-circuit is not working and the first sub-circuit is working; thereby realizing that the first pixel row 72 in the first array 7 is connected to the column readout circuit 9 row by row.

[0171] In some embodiments, the timing control circuit further includes a third sub-circuit, one end of which is connected to a ground terminal, and the other end is connected to a first row selection switch and a second row selection switch that are not connected to the first pixel 71 in the first pixel row 72. The third sub-circuit also includes a first mode switch.

[0172] For example, please refer to Figure 6 The M row selection timing receivers are represented by sel_1 to sel_M sequentially, the second mode switch is represented by Mode, and the first mode switch is represented by Mode_N. Taking the row scanning circuit corresponding to the first row selection switches ROW_1_1 to ROW_4_1 and the second row selection switches ROW_1_2 to ROW_4_1 as an example.

[0173] As described above, the first node A(1,1) and the second node B(2,2) are the first and second adapter nodes adapted to the first pixel 71(1,1), respectively, and the first row selection switch ROW_1_1 and the second row selection switch ROW_2_2 are connected to the first pixel 71(1,1); the first node A(3,1) and the second node B(4,2) are the first and second adapter nodes adapted to the first pixel 71(2,1), respectively, and the first row selection switch ROW_3_1 and the second row selection switch ROW_4_2 are connected to the first pixel 71(2,1).

[0174] like Figure 6As shown, in the second sub-circuit, the row selection timing receiver sel_1 is connected to the first row selection switch ROW_1_1 and the second row selection switch ROW_1_2 through the second mode switch Mode; the row selection timing receiver sel_2 is connected to the first row selection switch ROW_2_1 and the second row selection switch ROW_2_2 through the second mode switch Mode; the row selection timing receiver sel_3 is connected to the first row selection switch ROW_3_1 and the second row selection switch ROW_3_2 through the second mode switch Mode; and the row selection timing receiver sel_4 is connected to the first row selection switch ROW_4_1 and the second row selection switch ROW_4_2 through the second mode switch Mode.

[0175] In the first sub-circuit, the row selection timing receiver sel_1 is connected to the input of the OR gate circuit through a buffer, and the row selection timing receiver sel_2 is connected to the other input of the OR gate circuit; the output of the OR gate circuit is connected to the first row selection switch ROW_1_1 and the second row selection switch ROW_2_2 through the first mode switch Mode_N.

[0176] The row selection timing receiver sel_3 is connected to the input of the OR gate circuit through a buffer, and the row selection timing receiver sel_4 is connected to the other input of the OR gate circuit; the output of the OR gate circuit is connected to the first row selection switch ROW_3_1 and the second row selection switch ROW_4_2 through the first mode switch Mode_N.

[0177] In the third sub-circuit, the ground terminal GND is connected to the second row selection switch ROW_1_2 and the first row selection switch ROW_2_1 via the first mode switch Mode_N. The ground terminal GND is also connected to the second row selection switch ROW_3_2 and the first row selection switch ROW_4_1 via the first mode switch Mode_N.

[0178] Figure 7A for Figure 6 Timing diagram of the central scanning circuit in the second pixel mode, as shown below. Figure 7A As shown, in the second pixel mode where the readout circuit 3 is connected to the second pixel 61, the mode switching circuit controls the second mode switch Mode to be turned on, and the first mode switch Mode_N to be turned off; the second sub-circuit is working, while the first sub-circuit and the third sub-circuit are not working.

[0179] from Figure 7A and Figure 6As can be seen, the switching states of the first row selection switch ROW_1_1 and the second row selection switch ROW_1_2 change synchronously with the timing signal received by the row selection timing receiver sel_1; the switching states of the first row selection switch ROW_2_1 and the second row selection switch ROW_2_2 change synchronously with the timing signal received by the row selection timing receiver sel_2; the switching states of the first row selection switch ROW_3_1 and the second row selection switch ROW_3_2 change synchronously with the timing signal received by the row selection timing receiver sel_3; and the switching states of the first row selection switch ROW_4_1 and the second row selection switch ROW_4_2 change synchronously with the timing signal received by the row selection timing receiver sel_4.

[0180] As described above, during the row scanning process, the row selection timing receivers sel_1 to sel_4 receive timing signals sequentially, and the second array 6 performs row-by-row scanning.

[0181] Figure 7B for Figure 6 The timing diagram of the central scanning circuit in the first pixel mode is as follows: Figure 7B As shown, in the first pixel mode where the readout circuit 3 is connected to the first pixel 71, the mode switching circuit controls the second mode switch Mode to turn off, and the first mode switch Mode_N to turn on; the second sub-circuit does not work, and the first sub-circuit and the third sub-circuit work.

[0182] from Figure 7B and Figure 6 As can be seen, the second row selection switch ROW_1_2, the first row selection switch ROW_2_1, the second row selection switch ROW_3_2, and the first row selection switch ROW_4_1 are grounded. The first row selection switch ROW_1_1 and the second row selection switch ROW_2_2 are both turned on during the periods when the timing signals are received at the row selection timing receivers sel_1 and sel_2. The first row selection switch ROW_3_1 and the second row selection switch ROW_4_2 are both turned on during the periods when the timing signals are received at the row selection timing receivers sel_3 and sel_4.

[0183] As described above, during the row scanning process, the row selection timing receivers sel_1 to sel_4 receive timing signals sequentially, and the first array 7 performs row-by-row scanning; relative to the second pixel row 62 in the second array 6, every two rows are scanned.

[0184] Please continue to refer to this. Figure 3 and Figure 4In this readout circuit 3, the first pixel column 73 in the first array 7 and the two second pixel columns 63 in the second array 6 are in the same position. The first pixel column 73 can be connected to one of the two column readout circuits 9 connected to the two second pixel columns 63 in the same position. In this embodiment, the first pixel column 73 in the first array 7 is connected to the column readout circuit 9 in odd-numbered order among the N column readout circuits 9, and the column readout circuit 9 not connected to the first pixel column 73 is the column readout circuit 9 in even-numbered order among the N column readout circuits 9.

[0185] The mode switching circuit includes a third mode switch, which is located in the column readout circuit 9 that is not connected to the first pixel column 73 in the first array 7. In this embodiment, the third mode switch is located in the column readout circuit 9 in an even-numbered order among the N column readout circuits 9. By turning the third mode switch on and off, the column readout circuit 9 can be controlled to perform data reading or not to perform data reading.

[0186] As can be seen from the above, the readout circuit 3 is equipped with Q third mode switches, which are represented by TS_1 to TS_Q respectively.

[0187] Please refer to Figure 3 , Figure 5A , Figure 6 and Figure 7A In the second pixel mode where the readout circuit 3 is connected to the second array 6, each second pixel 61 is connected to the corresponding node through two connecting piers. The operation process of the readout circuit 3 is as follows:

[0188] The mode switching circuit controls the Q third mode switches TS_1 to TS_Q to be turned on. Each second cell column 63 in the second array 6 is connected to the corresponding column readout circuit 9 and data is read out through the corresponding column readout circuit 9.

[0189] The mode switching circuit controls the first mode switch to turn off and the second mode switch to turn on. The second sub-circuit in the row scanning circuit works, while the first sub-circuit does not work. During the row scanning process, the second sub-circuit controls the second pixel row 62 in the second array 6 to connect with the column readout circuit 9 row by row.

[0190] When the second pixel (1,1) is working, the first row selection switch ROW_1_1 and the second row selection switch ROW_1_2 are turned on. The first node A (1,1) is connected to the column readout circuit 9CH_1 through the first row selection switch ROW_1_1 and read out through the column readout circuit 9CH_1. The second node B (1,1) is grounded through the second row selection switch ROW_1_2.

[0191] When the second pixel (2,1) is working, the first row selection switch ROW_2_1 and the second row selection switch ROW_2_2 are turned on. The first node A (2,1) is connected to the column readout circuit 9CH_2 through the first row selection switch ROW_2_1 and read out through the column readout circuit 9CH_2. The node B (2,1) is grounded through the ROW_1_2 switch.

[0192] Please refer to Figure 4 , Figure 5B , Figure 6 and Figure 7B In the first pixel mode where the readout circuit 3 is connected to the first array 7, each first pixel 71 is connected to the first adapter node and the second adapter node via a connecting pier. The operation of the readout circuit 3 is as follows:

[0193] The mode switching circuit controls the Q third mode switches TS_1 to TS_Q to be turned off, and controls the column readout circuit 9 connected only to the first pixel 71 in the first array 7 to read data, while the column readout circuit 9 not connected to the first pixel 71 in the first array 7 does not read data.

[0194] The mode switching circuit controls the first mode switch to be turned on and the second mode switch to be turned off; the second sub-circuit in the row scanning circuit is not working, and the first sub-circuit is working; during the row scanning process, the first sub-circuit controls the first pixel row 72 in the first array 7 to be connected to the column readout circuit 9 row by row.

[0195] When the first pixel (1,1) is working, the first row selection switch ROW_1_1 and the second row selection switch ROW_2_2 are turned on. The first node A (1,1) is connected to the column readout circuit 9CH_1 through the first row selection switch ROW_1_1 and read out through the column readout circuit 9CH_1. The second node B (2,2) is grounded through the second row selection switch ROW_2_2.

[0196] When the first pixel (2,1) is working, the first row selection switch ROW_3_1 and the second row selection switch ROW_4_2 are turned on. The first node A (3,1) is connected to the column readout circuit 9CH_1 through the first row selection switch ROW_3_1 and read out through the column readout circuit 9CH_1. The second node B (4,2) is grounded through the second row selection switch ROW_4_2.

[0197] As can be seen from the above description, the readout circuit 3 for the infrared detector 100 provided in this application embodiment can simultaneously adapt to two different pixel sizes, the second pixel 61 and the first pixel 71, thereby saving the cost of circuit design and manufacturing.

[0198] Furthermore, by comparing the operation of the readout circuit 3 in the second pixel mode and the first pixel mode, it can be found that for the first pixel 71, the actual line time is twice that of the second pixel 61. Therefore, a gain of twice the integration time can be achieved without changing the frame rate. This increases the effective output of the first pixel 71, achieving the purpose of enhanced low-light detection.

[0199] In order to enable the first pixel row 72 to be turned on in both row selection timings in the first pixel mode and to be read out through a column readout circuit 9, it is necessary to restrict the first node and the second node adapted to the first pixel 71 to correspond to the first pixel in different rows and / or different columns.

[0200] In the readout circuit 3 provided in this application embodiment, the column readout circuit 9 includes a current bias circuit, an integrator, and a sample-and-hold circuit. The input terminal of the current bias circuit is connected to the first node through a first row selector switch, the output terminal of the current bias circuit is connected to the input terminal of the integrator, the output terminal of the integrator is connected to the input terminal of the sample-and-hold circuit, and the output terminal of the sample-and-hold circuit is connected to the signal processing circuit 8.

[0201] In the above description, the third mode switch in the mode switching circuit is set in the even-numbered column readout circuit 9 among the N column readout circuits 9, that is, it is set in the column readout circuit 9 corresponding to the even-numbered second cell column 63 in the second array 6. By turning the third mode switch on and off, the column readout circuit 9 can be controlled to read data or not read data.

[0202] Figure 8 A circuit diagram of a column readout circuit connected to a third mode switch is provided for an embodiment of this application, that is, a circuit diagram of the even-numbered column readout circuits 9 in N column readout circuits 9 and the third mode switch, as shown below. Figure 8 As shown,

[0203] The third-mode switch includes a first sub-switch TS_x and a second sub-switch TS_x_1 with opposite switching states. The column readout circuit 9 includes a current bias circuit 91, an integrator 92, and a sample-and-hold circuit 93. The input of the current bias circuit 91 is connected to the first array, and its output is connected to the input of the integrator 92. The output of the integrator 92 is connected to the first sub-switch TS_x. The input of the sample-and-hold circuit 93 is connected to the other end of the first sub-switch TS_x. By turning the first sub-switch TS_x on and off, the column readout circuit 9 can be controlled to perform data reading or not.

[0204] The second sub-switch TS_x_1 is set between the input terminal of the sample-and-hold circuit 93 and the node terminal GND.

[0205] With this design, in the second pixel mode where the readout circuit 3 is adapted to the second pixel 61, the first sub-switch TS_x is turned on and the second sub-switch TS_x_1 is turned off. Figure 8 The sampling and holding circuit 93 is functioning normally, the sampling integrator 92 outputs voltage, and the column readout circuit 9 is operating normally. In the first pixel mode adapted to the first pixel 71, the first sub-switch TS_x is turned off, and the second sub-switch TS_x_1 is turned on. Figure 8 The sample-and-hold circuit 93 samples the ground signal, and the readout circuit 9 does not work.

[0206] As described above, the readout circuit 3 in the infrared detector 100 can be adapted to both the second array 6 and the first array 7. Therefore, the infrared detector 100 provided in this application includes a readout circuit 3 and a first array 7 or a second array 6 disposed on the readout circuit 3. The connection relationship and working principle of the first array 7 or the second array 6 with the readout circuit 3 can be referred to above, and will not be repeated here.

[0207] This application also provides an infrared detector 100, such as Figure 9 As shown, the infrared detector 100 includes a substrate 110, a first array 7, and a connecting pier 120.

[0208] The substrate 110 is a wafer on which the readout circuit 3 is provided. For a description of the readout circuit 3, please refer to the above.

[0209] The first array 7 is located on one side of the substrate 110 and includes P×Q first pixels 71 arranged in P rows and Q columns. The first pixels 71 can be formed on the substrate 110 using MEMS (Micro Electro Mechanical Systems) manufacturing processes. A description of the first array 7 can be found above and will not be repeated here.

[0210] A connecting pier 120 is disposed between the first array 7 and the substrate 110 to connect the first pixel 71 of the first array 7 and the corresponding first node and second node in the substrate 110. The end of the connecting pier 120 closer to the substrate 110 is connected to the first node and the second node connected to the first pixel 71, and the end of the connecting pier 120 farther from the substrate 110 is connected to the corresponding first pixel 71.

[0211] As described above, among the M×N first nodes and M×N second nodes of the connecting node array 10, there are P×Q first nodes and P×Q second nodes adapted to the first array 7. The first pixel 71 in the first array 7 is connected to the adapted first and second nodes through the connecting pier 120. The first and second nodes in the connecting node array 10 that are not connected to the first array 7 can be partially or completely left unconnected.

[0212] like Figure 9 As shown, taking the first pixel (1,1) and the first pixel (2,1) as examples, the first pixel (1,1) is connected to the first node A (1,1) and the second node B (2,2) respectively through the connecting pier 120. The remaining nodes A (1,2) (not shown), A (2,1), A (2,2) (not shown), B (1,1), B (1,2) (not shown) and B (2,1) are all discarded and not electrically connected.

[0213] The first pixel (2,1) is connected to the first node A (3,1) and the second node B (4,2) respectively through the connecting pier 120. The remaining nodes A (3,2) (not shown), A (4,1), A (4,2) (not shown), B (3,1), B (3,2) (not shown) and B (4,1) (not shown) are all discarded and not electrically connected.

[0214] In some embodiments, insulating piers may be partially or completely provided in the first node and the second node that are not connected to the first pixel 71. The insulating piers are made of insulating material and cannot achieve electrical connection, but can provide support for the first pixel.

[0215] This application also provides another readout circuit. Figure 10 This is a schematic diagram showing the connection between another readout circuit and the second array provided in an embodiment of this application. Figure 11 for Figure 10 A schematic diagram showing the connection between the readout circuit and the first array. Figure 12A This is a schematic diagram showing the connection between the node array and the second array in the readout circuit provided in an embodiment of this application. Figure 12B This is a schematic diagram showing the connection between the node array and the first array in the readout circuit provided in an embodiment of this application. Figure 10 , Figure 11 , Figure 12A and Figure 12BAs shown, the difference between the readout circuit 3 in this embodiment and the readout circuit 3 in the previous embodiment is that, in the same column of the connecting node array 10, the first node and the second node in the next adjacent row are shared nodes. Here, a shared node means that the two are the same node structure. When the readout circuit 3 is connected to the second array 6, the two second pixels 61 in adjacent rows are connected to the shared node through a shared pier. Here, a shared pier refers to a connecting pier that is shared by the two second pixels 61 in adjacent rows. One end of the connecting pier is connected to the shared node, and the other end is connected to the two second pixels 61 in adjacent rows.

[0216] For example, the first node A (2,1) and the second node B (1,1) are shared nodes. When the readout circuit 3 is connected to the second array 6, the second pixel (1,1) and the second pixel (2,1) are connected to the shared node through a shared pier. The first node A (3,1) and the second node B (2,1) are shared nodes. When the readout circuit 3 is connected to the second array 6, the second pixel (2,1) and the second pixel (3,1) are connected to the shared node through a shared pier.

[0217] When the readout circuit 3 is connected to the first array 7, the first node connected to the first pixel (X1, Y1) is A(X1, Y1). A ,Y A The second node connected to the first pixel (X1, Y1) is B(X). B ,Y B );

[0218] Wherein, the first pixel (X1, Y1) is the first pixel in the first array 7 located in the X1 row and Y1 column; the first node A (X A ,Y A ) represents the node in the Xth position of the connected node array. A row, Y A The first node of the column; the second node B(X) B ,Y B ) represents the node in the Xth position of the connected node array. B row, Y B The second node of the column; and satisfying: X A =2×X1-1,Y A =2×Y1-1;X B =2×X1,Y B = 2 × Y1 - 1.

[0219] For example, the first node connected to the first pixel (1,1) is A(1,1), and the second node connected to the first pixel (1,1) is B(2,1). Since the first node A(3,1) and the second node B(2,1) are shared nodes, it can also be understood that the two nodes connected to the first pixel (1,1) are the first node A(1,1) and the first node A(3,1).

[0220] In another example, the first node connected to the first pixel (2,2) is A(3,3), and the second node connected to the first pixel (2,2) is B(4,3). Since the first node A(5,4) and the second node B(4,3) are shared nodes, it can also be understood that the two nodes connected to the first pixel (2,2) are the first node A(3,3) and the first node A(5,4).

[0221] Please refer to Figure 12B In this embodiment, the first node and the second node connected to the first pixel 71 are located on the same side of the first pixel 71. When the first pixel 71 is connected to the readout circuit 3 through the connecting pier, the connecting pier only supports the first pixel 71 on one side of the first pixel, resulting in poor stability of the support for the first pixel 71.

[0222] Therefore, in some embodiments, in other connection nodes (either the first node or the second node) located at the same position as the first pixel 71, insulating piers without electrical connections can be made of insulating material at any one or more connection node locations. These insulating piers support the first pixel 71, thereby improving the stability of the support for the first pixel 71. This method of improving the stability of the first pixel 71 by making insulating piers is also applicable to the implementation of independent nodes in the above embodiments, and will not be repeated here.

[0223] Please refer to Figure 10 and Figure 12A In the second pixel mode where the readout circuit 3 is connected to the second array 6, each second pixel 61 is connected to the corresponding node through two connecting piers. At the shared node position, two second pixels 61 are connected to the shared node through a shared pier. The operation process of the readout circuit 3 can be referred to the operation process of the readout circuit 3 in the second pixel mode in the previous embodiment, and will not be repeated here.

[0224] Please refer to Figure 11 and Figure 12B In the first pixel mode where the readout circuit 3 is connected to the first array 7, each first pixel 71 is connected to the adapted first node and second node via a connecting pier. At the shared node location, two 2×2 pixels are connected to the shared node via a shared pier. The operation of the readout circuit 3 is as follows:

[0225] The mode switching circuit controls all Q first mode switches TS_1 to TS_Q to be turned off, controls the column readout circuit 9 connected only to the first pixel 71 in the first array 7 to read data, and controls the column readout circuit 9 not connected to the first pixel 71 in the first array 7 to not read data.

[0226] The mode switching circuit controls the first mode switch to be turned on and the second mode switch to be turned off; the second sub-circuit in the row scanning circuit is not working, and the first sub-circuit is working; during the row scanning process, the first sub-circuit controls the first pixel row 72 in the first array 7 to be connected to the column readout circuit 9 row by row.

[0227] When the first pixel (1,1) is working, the first row selection switch ROW_1_1 and the second row selection switch ROW_2_2 are turned on. The first node A (1,1) is connected to the column readout circuit 9CH_1 through the first row selection switch ROW_1_1 and read out through the column readout circuit 9CH_1. The second node B (2,1) is grounded through the second row selection switch ROW_2_2.

[0228] When the first pixel (2,1) is working, the first row selection switch ROW_3_1 and the second row selection switch ROW_4_2 are turned on. The first node A (3,1) is connected to the column readout circuit 9CH_1 through the first row selection switch ROW_3_1 and read out through the column readout circuit 9CH_1. The second node B (4,2) is grounded through the second row selection switch ROW_4_2.

[0229] As can be seen from the above description, the readout circuit 3 for the infrared detector 100 provided in this application embodiment can simultaneously adapt to two different pixel sizes, the second pixel 61 and the first pixel 71, thereby saving the cost of circuit design and manufacturing.

[0230] Furthermore, by comparing the operation of the readout circuit 3 in the second pixel mode and the first pixel mode, it can be found that for the first pixel 71, the actual line time is twice that of the second pixel 61. Therefore, a gain of twice the integration time can be achieved without changing the frame rate. This increases the effective output of the first pixel 71, achieving the purpose of enhanced low-light detection.

[0231] Furthermore, shared nodes and shared piers allow for a larger connecting pier area, facilitating connection; independent nodes and independent connecting piers prevent the entire column from malfunctioning due to damage to a single connecting pier. The readout circuit 3 provided in this application embodiment can adapt to both independent connecting piers and shared piers, demonstrating good applicability.

[0232] As described above, the readout circuit 3 in the infrared detector 100 can be adapted to both the second array 6 and the first array 7. Therefore, the infrared detector 100 provided in this application includes a readout circuit 3 and a first array 7 or a second array 6 disposed on the readout circuit 3. When the infrared detector 100 uses a second pixel 61, the second pixel 61 in the second array 6 has a corresponding relationship with the first node and the second node in the connection node array 10. The first connection end of the second pixel 61 is connected to the corresponding first node through a connecting pier, and the first connection end of the second pixel 61 is connected to the corresponding second node through a connecting pier.

[0233] When the infrared detector 100 uses the first pixel 71, the first pixel 71 in the first array 7 corresponds to the first node as the first adapter node and the second node as the second adapter node in the connection node array 10. The first pixel 71 is connected to the corresponding first node and second node through connecting piers. The other first nodes and second nodes in the connection node array 10 are either vacant or equipped with insulating piers.

[0234] The connection relationship and working principle between the first array 7 or the second array 6 and the readout circuit 3 can be referred to the above text, and will not be repeated here.

[0235] It should be noted that when the readout circuit 3 is connected to either the first array 7 or the second array 6, the mode switching circuit can be replaced with a fixed-mode circuit. This fixed-mode circuit corresponds to either the first array 7 or the second array 6 and can be a circuit where the mode switching circuit corresponds to the state of the first array 7 or the second array 6. By setting the fixed-mode circuit, the readout circuit can be fixed in a state adapted to the first array 7 or the second array 6.

[0236] This application also provides an infrared detector 100, such as Figure 13 As shown, the infrared detector 100 includes a substrate 110, a first array 7, and a connecting pier 120.

[0237] The substrate 110 is a wafer on which the readout circuit 3 is provided. For a description of the readout circuit 3, please refer to the above.

[0238] The first array 7 is located on one side of the substrate 110 and includes P×Q first pixels 71 arranged in P rows and Q columns. The first pixels 71 can be formed on the substrate 110 using MEMS (Micro Electro Mechanical Systems) manufacturing processes. A description of the first array 7 can be found above and will not be repeated here.

[0239] A connecting pier 120 is disposed between the first array 7 and the substrate 110 to connect the first pixel 71 of the first array 7 and the corresponding first node and second node in the substrate 110. The end of the connecting pier 120 closer to the substrate 110 is connected to the first node and the second node connected to the first pixel 71, and the end of the connecting pier 120 farther from the substrate 110 is connected to the corresponding first pixel 71.

[0240] As described above, among the M×N first nodes and M×N second nodes of the connecting node array 10, there are P×Q first nodes and P×Q second nodes adapted to the first array 7. The first pixel 71 in the first array 7 is connected to the adapted first and second nodes through the connecting pier 120. The first and second nodes in the connecting node array 10 that are not connected to the first array 7 can be partially or completely left unconnected.

[0241] like Figure 13 As shown, taking the first pixel (1,1) and the first pixel (2,1) as examples, the first pixel (1,1) is connected to the first node A (1,1) and the second node B (2,1) through the connecting piers. The remaining nodes A (1,2) (not shown), A (2,1), A (2,2) (not shown), B (1,1), B (1,2) (not shown) and B (2,2) (not shown) are all discarded and not electrically connected.

[0242] The first pixel (2,1) is connected to the first node A (3,1) and the second node B (4,1) through the connecting pier. The remaining nodes A (3,2) (not shown), A (4,1), A (4,2) (not shown), B (3,1), B (3,2) (not shown) and B (4,2) (not shown) are all discarded and not electrically connected.

[0243] It should be noted that in this embodiment, the first node A (2,1) and the second node B (1,1) are shared nodes; the first node A (3,1) and the second node B (2,1) are shared nodes; and the first node A (4,1) and the second node B (3,1) are shared nodes.

[0244] In some embodiments, insulating piers may be partially or completely provided in the first node and the second node that are not connected to the first pixel 71. The insulating piers are made of insulating material and cannot achieve electrical connection, but can provide support for the first pixel 71.

[0245] In the above embodiments, the connection node array of the readout circuit includes M×N pairs of first nodes and second nodes arranged in M ​​rows and N columns. The second array includes M×N first pixels arranged in M ​​rows and N columns. The first array includes P×Q second pixels arranged in P rows and Q columns. The second pixels are single pixels, and the first pixels are 2×2 pixels. M equals 2P, and N equals 2Q. However, the embodiments of this application are not limited to this.

[0246] For example, in some embodiments, M > P and / or N > Q; that is, the pixel size of the first pixel is larger than the pixel size of the second pixel. Taking the second pixel as a single pixel as an example, the first pixel is not limited to a 2×2 pixel, but can be a 1×2 pixel, a 2×1 pixel, a 3×2 pixel, a 2×3 pixel, and a 3×3 pixel, etc.

[0247] In some embodiments, M = K1 × P, N = K2 × Q, where K1 and K2 are both positive integers. As described above, the area occupied by a first pixel is the same as the area occupied by K1 × K2 second pixels in adjacent K1 rows and K2 columns. Among the first and second nodes corresponding to the K1 × K2 second pixels in adjacent K1 rows and K2 columns, one first node and one second node are adapted to the first pixel at the same position. The first node and second node adapted to the same first pixel are located in different rows and / or different columns of the connecting node array.

[0248] When the readout circuit is connected to the first array, the first cell in the first array is connected to the first node and the second node that are adapted to it.

[0249] That is, the first node in the adjacent row K1 and column K2 includes a first node connected to the first cell;

[0250] In the second node of adjacent row K1 and column K2, there is a second node connected to the first cell;

[0251] The first and second nodes connected to the same first cell are located in different rows and / or different columns of the connected node array.

[0252] In some embodiments, a first cell row corresponds to K adjacent sub-scanning circuits, where K is a positive integer greater than 1;

[0253] The timing control circuit in the row scanning circuit includes M timing signal receivers and P first sub-circuits. The P first sub-circuits correspond to the P first pixel rows. One end of the first sub-circuit is connected to the first row selection switch and the second row selection switch connected to the first pixel row. The other end of the first sub-circuit is connected to K timing signal receivers. The K timing signal receivers correspond to the K sub-scanning circuits corresponding to the first pixel rows. In other words, the K timing signal receivers connected to the first sub-circuit are the K timing signal receivers corresponding to the adjacent K sub-scanning circuits of the first pixel row corresponding to the first sub-circuit.

[0254] The first sub-circuit is configured to turn on both the first row selection switch and the second row selection switch connected to the first sub-circuit when any row selection timing signal is received.

[0255] This application also provides a control method for an infrared detector, applied to the infrared detector in the above embodiments; such as Figure 14 As shown, the control method 200 includes:

[0256] Step S100: During the process of controlling the row scanning circuit to scan the P first cell rows in the first array line by line, the Q column readout circuits connected to the first array are controlled to read data, and the column readout circuits not connected to the first array are controlled not to read data.

[0257] In some embodiments, in the infrared detector, M = K1 × P, N = K2 × Q; a first pixel row in the first array corresponds to K1 adjacent sub-scanning circuits, and a first pixel column corresponds to K2 adjacent column readout circuits; where K1 and K2 are both positive integers;

[0258] In step S100, the control row scanning circuit performs a row-by-row scan of the P first cell rows in the first array, including:

[0259] Receive row selection timing signals for scanning M sub-scanning circuits line by line;

[0260] In the K1 row selection timing corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit.

[0261] In step S100, controlling the Q column readout circuits connected to the first array to read data, and controlling the column readout circuits not connected to the first array not to read data, includes:

[0262] In the K2 adjacent column readout circuits corresponding to the first pixel column, the column readout circuits connected to the first pixel column are controlled to read data, while the column readout circuits not connected to the first array are controlled not to read data.

[0263] In some embodiments, in the infrared detector, M = 2 × P, N = 2 × Q, and in the N column readout circuits, the column readout circuits in odd order are connected to the first cell column in the first array;

[0264] In step S100, the control row scanning circuit performs a row-by-row scan of the P first cell rows in the first array, including:

[0265] Receive row selection timing signals for scanning M sub-scanning circuits line by line;

[0266] In the two row selection timings corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit.

[0267] In step S100, controlling the Q column readout circuits connected to the first array to read data, and controlling the column readout circuits not connected to the first array not to read data, includes:

[0268] The system controls the readout circuits of columns in odd-numbered order to read data, and controls the readout circuits of columns in even-numbered order not to read data.

[0269] This application also provides a control method for an infrared detector, used to prepare any of the infrared detectors described in the above embodiments; such as Figure 15 As shown, the preparation method 300 includes:

[0270] Step S10: Provide a substrate.

[0271] The substrate is a wafer with readout circuitry. For a description of the readout circuitry, please refer to the above text.

[0272] Step S20: Fabricate connecting piers on the substrate. The connecting piers are set in the connecting node array and configured as the first node and the second node connected to the first array.

[0273] The connecting pier is a conductor structure that connects the first pixel in the first array to the readout circuit. It is installed in the connecting node array between the first node and the second node that are adapted to the first array. For information on the connecting node array and its adaptation relationship with the first array, please refer to the above text.

[0274] Step S30: Create a first pixel on the side of the connecting pier away from the substrate to form a first array.

[0275] The first array comprises P×Q first pixels arranged in P rows and Q columns, where M, N, P and Q are all positive integers, and M > P and / or N > Q.

[0276] The first pixel can be formed on a substrate using MEMS (Micro Electro Mechanical Systems) manufacturing processes. A first array is formed by arranging P first pixels in rows and Q first pixels in columns, with P × Q first pixels forming the array. A description of the first array can be found above.

[0277] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An infrared detector, characterized in that, include: The readout circuit includes column readout circuits, row scanning circuits, and a connection node array. The column readout circuits are arranged with N units corresponding to N columns. The row scanning circuits include M sub-scanning circuits corresponding to M rows. The connection node array includes M×N pairs of first nodes and second nodes arranged in M ​​rows and N columns. The first node is connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node is connected to a ground terminal through the sub-scanning circuit of its row. A first array disposed on the readout circuit, the first array comprising P×Q first pixels arranged in P rows of first pixels and Q columns of first pixels; Where M, N, P and Q are all positive integers, and M > P and / or N > Q; One end of the first pixel in the first pixel column is connected to a column readout circuit through the first node and the sub-scanning circuit, and the other end is connected to the ground terminal through the second node and the sub-scanning circuit; Q of the first pixel columns are respectively connected to Q of the column readout circuits; The readout circuit is configured to control the Q column readout circuits connected to the first array to read data while controlling the row scanning circuit to scan the P first cell rows in the first array line by line, and to control the column readout circuits not connected to the first array not to read data.

2. The infrared detector according to claim 1, characterized in that, M = K1 × P, N = K2 × Q, where K1 and K2 are both positive integers; In the first node of adjacent row K1 and column K2, there is a first node connected to the first cell; In the second node of adjacent row K1 and column K2, there is a second node connected to the first cell; The first node and the second node, which are connected to the same first cell, are located in different rows and / or different columns of the connected node array.

3. The infrared detector according to claim 2, characterized in that, Both K1 and K2 are equal to 2.

4. The infrared detector according to claim 3, characterized in that, In the connection node array, the first node and the second node are both independent node structures; The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B (X). B ,Y B ); Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column; The first node A (X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column; The second node B (X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column; And satisfy: X A =2×X1-1,Y A =2×Y1-1; X B =2×X1,Y B =2×Y1。 5. The infrared detector according to claim 3, characterized in that, In the same column of the connected node array, the first node and the second node in the adjacent next row have the same structure; The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B (X). B ,Y B ); Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column; The first node A (X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column; The second node B (X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column; And satisfy: X A =2×X1-1,Y A =2×Y1-1; X B =2×X1,Y B =2×Y1-1。 6. The infrared detector according to any one of claims 1 to 5, characterized in that, The sub-scanning circuit includes a first row selection switch and a second row selection switch; the two ends of the first row selection switch are respectively connected to the first node and the column readout circuit of the column in which it is located, and the two ends of the second row selection switch are respectively connected to the second node and the ground terminal. The row scanning circuit further includes a timing control circuit, which is connected to both the first row selection switch and the second row selection switch, and is configured to perform row-by-row scanning of P first cell rows in the first array by controlling the on and off states of the first row selection switch and the second row selection switch.

7. The infrared detector according to claim 6, characterized in that, One of the first cell rows corresponds to K adjacent sub-scanning circuits, where K is a positive integer greater than 1; The timing control circuit includes: M timing signal receiving terminals are configured to receive row selection timing signals for scanning the M sub-scanning circuits line by line. as well as P first sub-circuits are set for each of the P first cell rows. One end of the first sub-circuit is connected to the first row selection switch and the second row selection switch connected to the first cell row. The other end of the first sub-circuit is connected to K timing signal receivers. The K timing signal receivers are the part of the M timing signal receivers that correspond to the first cell rows. When any of the K timing signal receivers receives a row selection timing signal, the first sub-circuit is configured to control both the first row selection switch and the second row selection switch connected to the first sub-circuit to be turned on.

8. The infrared detector according to claim 7, characterized in that, The first sub-circuit includes an OR gate, the output of which is connected to the first row selection switch, and the input of which is connected to the K timing signal receivers.

9. The infrared detector according to claim 7, characterized in that, The timing control circuit further includes M second sub-circuits corresponding to the M sub-scanning circuits. One end of the second sub-circuit is connected to the first row selection switch and the second row selection switch in the sub-scanning circuit, and the other end of the second sub-circuit is connected to the timing signal receiving end corresponding to the sub-scanning circuit. The second sub-circuit is configured to control the first row selection switch and the second row selection switch connected to the second sub-circuit to be turned on when the row selection timing signal is received; The readout circuit further includes a mode switching circuit, which includes a first mode switch and a second mode switch with opposite switching states. The first mode switch is disposed in the first sub-circuit, and the second mode switch is disposed in the second sub-circuit.

10. The infrared detector according to any one of claims 1 to 5, characterized in that, The column readout circuit includes a circuit bias circuit, an integrator, and a sample-and-hold circuit connected in sequence. The readout circuit also includes a mode switching circuit, which includes a third mode switch, and the third mode switch includes a first sub-switch and a second sub-switch with opposite switching states. In the column readout circuit not connected to the first cell column, the first sub-switch is disposed between the integrator and the sample-and-hold circuit, and the second sub-switch is disposed between the sample-and-hold circuit and the ground terminal.

11. The infrared detector according to any one of claims 1 to 5, characterized in that, N = 2 × Q; In the N column readout circuits, the column readout circuits in odd-numbered order are connected to the first cell column in the first array.

12. An infrared detector, characterized in that, include: A substrate includes a readout circuit, which comprises column readout circuits, row scanning circuits, and a connection node array. The column readout circuits are arranged with N units corresponding to N columns. The row scanning circuits include M sub-scanning circuits corresponding to M rows. The connection node array includes M×N pairs of first nodes and second nodes arranged with M rows and N columns. The first node is connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node is connected to a ground terminal through the sub-scanning circuit of its row. A first array located on one side of the substrate, the first array comprising P×Q first pixels arranged in P rows and Q columns; wherein M, N, P, and Q are all positive integers, M > P and / or N > Q; and A connecting pier is disposed between the first array and the substrate, the connecting pier connecting the first pixel and a first node and a second node corresponding to the first pixel in the substrate; one end of the first pixel in the first pixel column is connected to a column readout circuit through the connecting pier, the first node, and the sub-scanning circuit, and the other end is connected to the ground terminal through the connecting pier, the second node, and the sub-scanning circuit; Q first pixel columns are respectively connected to Q column readout circuits; The readout circuit is configured to control the row scanning circuit to scan the P first cell rows in the first array row by row, while controlling the Q column readout circuits connected to the first array to read data, and controlling the column readout circuits not connected to the first array not to read data.

13. The infrared detector according to claim 12, characterized in that, M = K1 × P, N = K2 × Q, where K1 and K2 are both positive integers; In the first node of adjacent row K1 and column K2, there is a first node connected to the first cell; In the second node of adjacent row K1 and column K2, there is a second node connected to the first cell; The first node and the second node connected to the same first cell are located in different rows and / or different columns of the connected node array; The end of the connecting pier closest to the substrate is connected to a first node and a second node connected to the first pixel, and the end of the connecting pier furthest from the substrate is connected to the corresponding first pixel.

14. The infrared detector according to claim 13, characterized in that, Both K1 and K2 are equal to 2.

15. The infrared detector according to claim 14, characterized in that, In the connection node array, the first node and the second node are both independent node structures; The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B (X). B ,Y B ); the first node A (X) A ,Y A ) and the second node B (X) B ,Y B All of them are connected to the connecting piers; Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column; The first node A (X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column, and satisfying X A =2×X1-1,Y A =2×Y1-1; The second node B (X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column, and satisfying X B =2×X1, Y B =2×Y1.

16. The infrared detector according to claim 14, characterized in that, In the same column of the connected node array, the first node and the second node in the adjacent next row have the same structure; The first node connected to the first pixel (X1, Y1) is A(X A ,Y A The second node connected to the first pixel (X1, Y1) is B (X). B ,Y B ); the first node A (X) A ,Y A ) and the second node B (X) B ,Y B All of them are connected to the connecting piers; Wherein, the first pixel (X1, Y1) is the first pixel in the first array located in the X1 row and Y1 column; The first node A (X) A ,Y A ) is the node in the Xth position of the connection node array. A row, Y A The first node of the column, and satisfying X A =2×X1-1,Y A =2×Y1-1; The second node B (X) B ,Y B ) is the node in the Xth position of the connection node array. B row, Y B The second node of the column, and satisfying X B =2×X1, Y B =2×Y1-1.

17. The infrared detector according to any one of claims 14 to 16, characterized in that, In the first and second nodes that are not connected to the first pixel, some or all of them are empty, or some or all of them are provided with insulating piers. The insulating bridge pier supports the first pixel at the end furthest from the substrate.

18. A control method for an infrared detector, characterized in that, The control method is applied to the infrared detector according to any one of claims 1 to 17; the control method includes: During the process of controlling the row scanning circuit to scan the P first cell rows in the first array line by line, the Q column readout circuits connected to the first array are controlled to read data, while the column readout circuits not connected to the first array are controlled not to read data.

19. The control method according to claim 18, characterized in that, In the infrared detector, M = K1 × P, N = K2 × Q; a first pixel row in the first array corresponds to K1 adjacent sub-scanning circuits, and a first pixel column corresponds to K2 adjacent column readout circuits; where K1 and K2 are both positive integers. In the control method, the control row scanning circuit performs row-by-row scanning of P first cell rows in the first array, including: Receive row selection timing signals for scanning M sub-scanning circuits line by line; In the K1 row selection timings corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit; The control of the Q column readout circuits connected to the first array to read data, and the control of the column readout circuits not connected to the first array to not read data, includes: In the K2 adjacent column readout circuits corresponding to the first pixel column, the column readout circuits connected to the first pixel column are controlled to read data, while the column readout circuits not connected to the first array are controlled not to read data.

20. The control method according to claim 18, characterized in that, In the infrared detector, M=2×P, N=2×Q, and in the N column readout circuits, the column readout circuits in odd order are connected to the first cell column in the first array. In the control method, the control row scanning circuit performs row-by-row scanning of P first cell rows in the first array, including: Receive row selection timing signals for scanning M sub-scanning circuits line by line; In the two row selection timings corresponding to the first pixel row, the first pixel row is controlled to be connected to the corresponding column readout circuit; The control of the Q column readout circuits connected to the first array to read data, and the control of the column readout circuits not connected to the first array to not read data, includes: The column readout circuits in odd-numbered order are controlled to read data, while the column readout circuits in even-numbered order are controlled not to read data.

21. A method for fabricating an infrared detector, characterized in that, The method for preparing the infrared detector according to any one of claims 1 to 17 includes: A substrate is provided; the substrate has a readout circuit, the readout circuit including column readout circuits, row scanning circuits and a connection node array, the column readout circuits being arranged N times corresponding to N columns; the row scanning circuits including M sub-scanning circuits corresponding to M rows; the connection node array including M×N pairs of first nodes and second nodes arranged corresponding to M rows and N columns, the first node being connected to the column readout circuit of its column through the sub-scanning circuit of its row, and the second node being connected to a ground terminal through the sub-scanning circuit of its row; A connecting pier is fabricated on the substrate, and the connecting pier is disposed in the connecting node array and configured as a first node and a second node connected to the first array; A first pixel is formed on the side of the connecting pier away from the substrate to form a first array; The first array comprises P×Q first pixels arranged in P rows and Q columns; M, N, P and Q are all positive integers, and M > P and / or N > Q.

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