Shift register unit and method for driving same, row scanning circuit, and display device

Abstract

A shift register unit and a method for driving same, a row scanning circuit, and a display device. In the shift register unit, a first control circuit (01), under the control of a first clock signal, can control a potential of a first node (n1); a second control circuit (02), under the control of the potential of the first node (n1), a second clock signal, and a first power supply signal, can control a potential of a second node (n2); an adjustment circuit (03), under the control of the potential of the first node (n1), a third clock signal, a control signal, and a target signal, can adjust the potential of the first node (n1), so that the potential of the first node (n1) is stably maintained; and an output circuit (04), under the control of the potentials of the two nodes, can output a fourth clock signal or a second power supply signal via an output terminal (Gout). Thus, by flexibly configuring the clock signals, the shift register unit can flexibly output to a pixel circuit a scanning signal having a high or low potential, thereby meeting the driving requirements of any type of transistor in the pixel circuit.

Description

Shift register unit and its driving method, row scanning circuit, display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, a row scanning circuit, and a display device. Background Technology

[0002] A horizontal scanning circuit is a circuit used to drive pixels in a display panel to emit light. Common horizontal scanning circuits include gate driving circuits. Furthermore, gate drive on array (GOA) technology is typically used to integrate the horizontal scanning circuit onto the panel. Accordingly, the horizontal scanning circuit is also called a GOA circuit.

[0003] Currently, GOA circuits typically include multiple cascaded shift register units, also known as GOA units. Each GOA unit usually includes multiple transistors. When the GOA unit includes P-type transistors, the output signal is typically a low-level shift signal, which can only drive the P-type transistors in the pixel. When the GOA unit includes N-type transistors, the output signal is typically a high-level shift signal, which can only drive the N-type transistors in the pixel. Here, "high" and "low" are relative. That is, the type of transistors in the GOA unit must be the same as the type of transistors in the driven pixel.

[0004] Based on this, it can be seen that the current GOA unit has poor output flexibility. For example, it is not possible to use a GOA unit with all P-type transistors to flexibly output the required signals to the P-type or N-type transistors in the pixel. Summary of the Invention

[0005] A shift register unit and its driving method, a row scanning circuit, and a display device are provided.

[0006] The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] A first control circuit is connected to a first clock terminal, an input terminal, and a first node, respectively, and is used to control the connection and disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal.

[0009] The second control circuit is connected to the first node, the second clock terminal, the first power supply terminal, the first target terminal, and the second node respectively. It is used to control the connection and disconnection between the first power supply terminal and the second node in response to the potential of the first node, the second clock signal provided by the second clock terminal, and the first power supply signal provided by the first power supply terminal. It also controls the connection and disconnection between the first target terminal and the second node. The first target terminal and the second clock terminal share the same second power supply terminal.

[0010] An adjustment circuit is connected to the first node, the third clock terminal, the control terminal, and the second target terminal, respectively, and is used to adjust the potential of the first node in response to the potential of the first node, the third clock signal provided by the third clock terminal, the control signal provided by the control terminal, and the target signal provided by the second target terminal. The control terminal is shared with or connected to the second node, and the second target terminal is shared with or connected to the first power supply terminal.

[0011] The output circuit is connected to the first node, the second node, the second power supply terminal, the fourth clock terminal, and the output terminal respectively. It is used to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the first node and the potential of the second node, and to control the connection and disconnection between the fourth clock terminal and the output terminal.

[0012] Optionally, the adjustment circuit includes:

[0013] The first regulating sub-circuit is connected to the control terminal, the second target terminal and the third node respectively, and is used to control the on / off state of the second target terminal and the third node in response to the control signal;

[0014] The second regulating sub-circuit is connected to the first node, the third clock terminal, and the third node respectively, and is used to control the on / off state of the third clock terminal and the third node in response to the potential of the first node.

[0015] The third regulating sub-circuit is connected to the third node and the first node respectively, and is used to regulate the potential of the first node in response to the potential of the third node.

[0016] Optionally, the first regulating sub-circuit includes: a first transistor;

[0017] The gate of the first transistor is connected to the control terminal, the first electrode of the first transistor is connected to the second target terminal, and the second electrode of the first transistor is connected to the third node.

[0018] Optionally, the second regulating sub-circuit includes: a second transistor;

[0019] The gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the third clock terminal, and the second terminal of the second transistor is connected to the third node.

[0020] Optionally, the third regulating sub-circuit includes: a first capacitor;

[0021] One end of the first capacitor is connected to the third node, and the other end of the first capacitor is connected to the first node.

[0022] Optionally, the third node includes: a first sub-node and a second sub-node; the first adjustment sub-circuit is connected to the first sub-node; the second adjustment sub-circuit is connected to the second sub-node; the third adjustment sub-circuit includes:

[0023] The first adjustment unit is connected to the first sub-node and the second sub-node respectively, and is used to adjust the potential of the first sub-node in response to the potential of the second sub-node;

[0024] The second adjustment unit is connected to the first sub-node and the first node respectively, and is used to control the on / off state of the first sub-node and the first node in response to the potential of the first sub-node, so as to adjust the potential of the first node.

[0025] Furthermore, the control terminal is connected to the second node, and the second target terminal is connected to the first node.

[0026] Optionally, the first adjustment unit includes a first capacitor; the second adjustment unit includes a third transistor.

[0027] One end of the first capacitor is connected to the first child node, and the other end of the first capacitor is connected to the second child node;

[0028] The gate and first electrode of the third transistor are both connected to the first child node, and the second electrode of the third transistor is connected to the first node.

[0029] Optionally, the second control circuit includes:

[0030] The first control sub-circuit is connected to the first node, the first power supply terminal and the second node respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the potential of the first node.

[0031] The second control sub-circuit is connected to the first node, the first power supply terminal, the second clock terminal, and the fourth node respectively. It is used to control the on / off state of the first power supply terminal and the fourth node in response to the potential of the first node, and to adjust the potential of the fourth node in response to the second clock signal.

[0032] The third control sub-circuit is connected to the fourth node, the first target terminal, and the second node respectively, and is used to control the on / off state of the first target terminal and the second node in response to the potential of the fourth node.

[0033] Optionally, the first control sub-circuit includes: a fourth transistor;

[0034] The gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the second node.

[0035] Optionally, the second control sub-circuit includes: a fifth transistor and a second capacitor;

[0036] The gate of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the fourth node.

[0037] One end of the second capacitor is connected to the second clock terminal, and the other end of the second capacitor is connected to the fourth node.

[0038] Optionally, the third control sub-circuit includes: a sixth transistor;

[0039] The gate of the sixth transistor is connected to the fourth node, the first electrode of the sixth transistor is connected to the first target terminal, and the second electrode of the sixth transistor is connected to the second node.

[0040] Optionally, the shift register unit further includes:

[0041] A third control circuit is connected between the first control sub-circuit and the first power supply terminal, and is connected to the fifth clock terminal, for controlling the on / off state of the first control sub-circuit and the first power supply terminal in response to the fifth clock signal provided by the fifth clock terminal; or, it is connected between the first control circuit and the first node, and is connected to the fifth clock terminal, for controlling the on / off state of the first control circuit and the first node in response to the fifth clock signal.

[0042] Furthermore, the control terminal is connected to the second node, and the second target terminal shares power with the first power supply terminal.

[0043] Optionally, the third control circuit includes: a seventh transistor;

[0044] The gate of the seventh transistor is connected to the fifth clock terminal. When the third control circuit is connected between the first control sub-circuit and the first power supply terminal, the first terminal of the seventh transistor is connected to the first control sub-circuit, and the second terminal of the seventh transistor is connected to the first power supply terminal. When the third control circuit is connected between the first control circuit and the first node, the first terminal of the seventh transistor is connected to the first control circuit, and the second terminal of the seventh transistor is connected to the first node.

[0045] Optionally, when the third control circuit is connected between the first control sub-circuit and the first power supply terminal, the fifth clock terminal is shared with the second clock terminal, the third clock terminal is shared with the second clock terminal, and / or the fourth clock terminal is shared with the first clock terminal.

[0046] Optionally, when the third control circuit is connected between the first control circuit and the first node, the fifth clock terminal is independent of the second clock terminal, the third clock terminal is shared with the second clock terminal, and / or the fourth clock terminal is shared with the first clock terminal.

[0047] Optionally, the first control circuit includes: an eighth transistor;

[0048] The gate of the eighth transistor is connected to the first clock terminal, the first terminal of the eighth transistor is connected to the input terminal, and the second terminal of the eighth transistor is connected to the first node.

[0049] Optionally, the output circuit includes:

[0050] The first output sub-circuit is connected to the first node, the second power supply terminal and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the first node.

[0051] The second output sub-circuit is connected to the second node, the fourth clock terminal, and the output terminal respectively. It is used to control the on / off state of the fourth clock terminal and the output terminal in response to the potential of the second node, and also to adjust the potential of the second node based on the fourth clock signal provided by the fourth clock terminal.

[0052] Optionally, the first output sub-circuit includes: a ninth transistor;

[0053] The gate of the ninth transistor is connected to the first node, the first terminal of the ninth transistor is connected to the second power supply terminal, and the second terminal of the ninth transistor is connected to the output terminal.

[0054] Optionally, the second output sub-circuit includes: a tenth transistor and a third capacitor;

[0055] The gate of the tenth transistor is connected to the second node, the first terminal of the tenth transistor is connected to the fourth clock terminal, and the second terminal of the tenth transistor is connected to the output terminal.

[0056] One end of the third capacitor is connected to the fourth clock terminal, and the other end of the third capacitor is connected to the second node.

[0057] Optionally, the shift register unit further includes:

[0058] The first reset circuit is connected to the reset control terminal, the first power supply terminal, and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node in response to the reset control signal provided by the reset control terminal.

[0059] And / or, a second reset circuit, connected to the reset control terminal, the second power supply terminal, and the second node respectively, is used to control the connection and disconnection of the second power supply terminal and the second node in response to the reset control signal.

[0060] Optionally, the first reset circuit includes: an eleventh transistor;

[0061] The gate of the eleventh transistor is connected to the reset control terminal, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the first node.

[0062] Optionally, the second reset circuit includes: a twelfth transistor;

[0063] The gate of the twelfth transistor is connected to the reset control terminal, the first terminal of the twelfth transistor is connected to the second power supply terminal, and the second terminal of the twelfth transistor is connected to the second node.

[0064] Optionally, the first node includes: a third sub-node and a fourth sub-node; both the first control circuit and the second control circuit are connected to the third sub-node; both the adjustment circuit and the output circuit are connected to the fourth sub-node; the second target terminal is connected to the third sub-node; the shift register unit further includes:

[0065] An isolation circuit is connected to the second power supply terminal, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the second power supply signal provided by the second power supply terminal.

[0066] Optionally, the isolation circuit includes: a thirteenth transistor;

[0067] The gate of the thirteenth transistor is connected to the second power supply terminal, the first terminal of the thirteenth transistor is connected to the third sub-node, and the second terminal of the thirteenth transistor is connected to the fourth sub-node.

[0068] Optionally, the first clock terminal and the second clock terminal form one set of clock terminals, and the third clock terminal and the fourth clock terminal form another set of clock terminals. In each set of clock terminals, the clock signals provided by the two clock terminals are inverse signals to each other. At the same time, the pulse width of the fourth clock signal provided by the fourth clock terminal includes the pulse width of the third clock signal provided by the third clock terminal, and the pulse width of the second clock signal provided by the second clock terminal includes the pulse width of the first clock signal provided by the first clock terminal.

[0069] Alternatively, the first clock terminal, the second clock terminal, the third clock terminal, and the fourth clock terminal are the same group of clock terminals, and the potentials of the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the fourth clock signal provided by the fourth clock terminal change sequentially, and two adjacent clock signals that change sequentially have overlapping same potentials.

[0070] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0071] In the first stage, the first control circuit responds to the first clock signal and controls the input terminal to be connected to the first node. The second control circuit responds to the potential of the first node, the second clock signal provided by the second clock terminal, and the first power signal provided by the first power supply terminal and controls the first power supply terminal to be connected to the second node. The adjustment circuit responds to the potential of the first node, the third clock signal provided by the third clock terminal, the control signal provided by the control terminal, and the target signal provided by the second target terminal and adjusts the potential of the first node. The output circuit responds to the potential of the first node and the potential of the second node and controls the second power supply terminal to be connected to the output terminal.

[0072] In the second stage, the first control circuit responds to the first clock signal and controls the input terminal to disconnect from the first node. The second control circuit responds to the potential of the first node, the second clock signal, and the first power signal and controls the first target terminal to conduct with the second node. The adjustment circuit responds to the potential of the first node, the third clock signal, the control signal, and the target signal and adjusts the potential of the first node. The output circuit responds to the potential of the first node and the potential of the second node and controls the fourth clock terminal to conduct with the output terminal.

[0073] In another aspect, a row scanning circuit is provided, the row scanning circuit comprising: a plurality of cascaded shift register units as described in the above aspect.

[0074] In another aspect, a display device is provided, the display device comprising: a display panel, and a line scanning circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0075] The row scanning circuit is connected to the plurality of pixels and is used to transmit scanning signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0077] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0078] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0079] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0080] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0081] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0082] Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0083] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0084] Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0085] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0086] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0087] Figure 11 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0088] Figure 12 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0089] Figure 13 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

[0090] Figure 14 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0091] Figure 15 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0092] Figure 16 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0093] Figure 17 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0094] Figure 18 is a flowchart of a driving method for a shift register unit provided in an embodiment of this application;

[0095] Figure 19 is a timing diagram of a shift register unit provided in an embodiment of this application;

[0096] Figure 20 is a timing diagram of another shift register unit provided in an embodiment of this application;

[0097] Figure 21 is a schematic diagram of the working timing of another shift register unit provided in an embodiment of this application;

[0098] Figure 22 is a schematic diagram of a scanning circuit provided in an embodiment of this application;

[0099] Figure 23 is a schematic diagram of another scanning circuit provided in an embodiment of this application;

[0100] Figure 24 is a schematic diagram of another scanning circuit provided in an embodiment of this application;

[0101] Figure 25 is a schematic diagram of another scanning circuit provided in an embodiment of this application;

[0102] Figure 26 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0103] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0104] It should be noted that the transistors used in the embodiments of this application can all be thin film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, a field-effect transistor can be a metal-oxide-semiconductor (MOS) field-effect transistor, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include any of P-type transistors and N-type transistors. A P-type transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential; an N-type transistor is turned on when the gate is at a high potential and turned off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the whole text.

[0105] Current shift register units are primarily designed for driving P-type TFTs made of low-temperature polysilicon (LTPS) material. Since P-type TFTs conduct under low potential control and are cut off under high potential control, the main function of current shift register units is to perform low-level pulse width shifting, i.e., primarily outputting low-potential active scan shift signals. However, with technological advancements, N-type TFTs made of oxide material are increasingly used in pixel circuits, leading to a growing demand for scan shifting driving of N-type TFTs. Because N-type TFTs conduct under high potential control and are cut off under low potential control, shift register units need to be able to perform high-level pulse width shifting, i.e., output high-potential active scan shift signals.

[0106] Based on this, the embodiments of this application provide a novel shift register unit that can flexibly output the signals required by the TFT in the pixel circuit.

[0107] Figure 1 is a schematic diagram of a shift register unit provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes: a first control circuit 01, a second control circuit 02, an adjustment circuit 03, and an output circuit 04.

[0108] The first control circuit 01 is connected to the first clock terminal CK1, the input terminal IN, and the first node n1. Furthermore, the first control circuit 01 is used to control the on / off state of the input terminal IN and the first node n1 in response to the first clock signal provided by the first clock terminal CK1.

[0109] For example, the first control circuit 01 can, in response to the first clock signal provided by the first clock terminal CK1 at a first potential, control the input terminal IN to be connected to the first node n1. This allows the input signal provided by the input terminal IN to be transmitted to the first node n1. The first control circuit 01 can also, in response to the first clock signal provided by the first clock terminal CK1 at a second potential, control the input terminal IN to be disconnected from the first node n1.

[0110] Optionally, in this embodiment, the first potential can be an effective potential, the second potential can be an ineffective potential, and the effective potential can be a lower potential relative to the ineffective potential. That is, the effective potential can be a low potential, and the ineffective potential can be a high potential. Accordingly, the transistors included in the shift register unit can be P-type transistors. Of course, in some other embodiments, the effective potential can also be a high potential relative to the ineffective potential. Accordingly, the transistors included in the shift register unit can be N-type transistors.

[0111] The second control circuit 02 is connected to the first node n1, the second clock terminal CK2, the first power supply terminal VGH, the first target terminal V1, and the second node n2. Furthermore, the second control circuit 02 is used to control the connection and disconnection between the first power supply terminal VGH and the second node n2 in response to the potential of the first node n1, the second clock signal provided by the second clock terminal CK2, and the first power supply signal provided by the first power supply terminal VGH, and also to control the connection and disconnection between the first target terminal V1 and the second node n2.

[0112] The first target terminal V1 is shared with the second clock terminal CK2, or it is the second power supply terminal VGL. That is, the second control circuit 02 can control the on / off state of the second clock terminal CK2 and the second node n2, or it can control the on / off state of the second power supply terminal VGL and the second node n2 separately.

[0113] Furthermore, it is understood that when the first target terminal V1 and the second clock terminal CK2 are shared, the target signal provided by the first target terminal V1 can be the second clock signal provided by the second clock terminal CK2; when the first target terminal V1 is the second power supply terminal VGL, the target signal provided by the first target terminal V1 can be the second power supply signal provided by the second power supply terminal VGL.

[0114] Optionally, the potential of the first power signal provided by the first power supply terminal VGH can be a high potential, and the potential of the second power signal provided by the second power supply terminal VGL can be a low potential. Here, high potential and low potential are relative terms.

[0115] For example, referring to Figure 1, taking the first target terminal V1 as the second power supply terminal VGL as an example, the second control circuit 02 can, when the potential of the first node n1 is the first potential and the potential of the second clock signal provided by the second clock terminal CK2 is the second potential, respond to the potential of the first node n1, the second clock signal, and the high-potential first power signal provided by the first power supply terminal VGH, control the first power supply terminal VGH to conduct with the second node n2, and control the second power supply terminal VGL to disconnect from the second node n2. In this way, the high-potential first power signal provided by the first power supply terminal VGH can be transmitted to the second node n2, that is, the potential of the second node n2 is controlled to be high. The second control circuit 02 can, when the potential of the first node n1 is the second potential and the potential of the second clock signal provided by the second clock terminal CK2 is the first potential, respond to the potential of the first node n1, the second clock signal, and the high-potential first power signal provided by the first power supply terminal VGH, control the second power supply terminal VGL to conduct with the second node n2, and control the first power supply terminal VGH to disconnect from the second node n2. In this way, the low-potential second power signal provided by the second power supply terminal VGL can be transmitted to the second node n2, that is, the potential of the second node n2 is controlled to be low.

[0116] The adjustment circuit 03 is connected to the first node n1, the third clock terminal CK3, the control terminal Con, and the second target terminal V2. Furthermore, the adjustment circuit 03 is used to adjust the potential of the first node n1 in response to the potential of the first node n1, the third clock signal provided by the third clock terminal CK3, the control signal provided by the control terminal Con, and the target signal provided by the second target terminal V2.

[0117] Among them, the control terminal Con is shared with the first clock terminal CK1 (that is, connected to the first clock terminal CK1) or connected to the second node n2, and the second target terminal V2 is shared with the first power supply terminal VGH (that is, connected to the first power supply terminal VGH) or connected to the first node n1.

[0118] It is understandable that when the control terminal Con is shared with the first clock terminal CK1, the control signal provided by the control terminal Con can be the first clock signal provided by the first clock terminal CK1. When the control terminal Con is connected to the second node n2, the control signal provided by the control terminal Con can be the signal transmitted to the second node n2. Similarly, when the second target terminal V2 is shared with the first power supply terminal VGH, the target signal provided by the second target terminal V2 can be the first power supply signal provided by the first power supply terminal VGH. When the second target terminal V2 is connected to the first node n1, the target signal provided by the second target terminal V2 can be the signal transmitted to the first node n1.

[0119] For example, referring to Figure 1, taking the control terminal Con and the first clock terminal CK1 as shared, and the second target terminal V2 and the first power supply terminal VGH as shared, i.e., the target signal provided by the second target terminal V2 is at a high potential, the adjustment circuit 03 can adjust the potential of the first node n1 to the second potential in response to the potential of the first node n1, the third clock signal, the control signal provided by the control terminal Con, and the third clock signal provided by the third clock terminal CK3. The adjustment circuit 03 can also adjust the potential of the first node n1 to the first potential in response to the potential of the first node n1, the third clock signal, the control signal, and the target signal. In other words, the adjustment circuit 03 can be used to maintain the potential of the first node n1. Accordingly, the adjustment circuit 03 is also called a maintenance circuit.

[0120] Output circuit 04 is connected to the first node n1, the second node n2, the second power supply terminal VGL, the fourth clock terminal CK4, and the output terminal Gout, respectively. Furthermore, output circuit 04 is used to control the switching between the second power supply terminal VGL and the output terminal Gout in response to the potentials of the first node n1 and the second node n2, and also controls the switching between the fourth clock terminal CK4 and the output terminal Gout.

[0121] Optionally, the output terminal Gout of the shift register unit can be connected not only to the pixel circuit but also to the input terminal IN of other cascaded shift register units to control the pixel circuit to drive the light-emitting element to emit light based on the received scan signal, thus achieving cascaded driving. Of course, the input terminal IN of the first-stage shift register unit can be connected to the enable signal terminal STV to receive the enable signal provided by STV and, in response to the enable signal, output the cascaded signal through the output terminal Gout, thus achieving cascaded driving.

[0122] Optionally, the display panel may include multiple rows and columns of pixels. The output terminal Gout of each shift register unit can be connected via a gate line to a data writing transistor included in the pixel circuit of a row of pixels to transmit a gate drive signal to the data writing transistor. In response to the gate drive signal, the data writing transistor controls the data line to transmit a data signal to the driving transistor in the pixel circuit, thereby causing the driving transistor to drive the light-emitting element to emit light based on the data signal. The multi-stage shift register unit can transmit the gate drive signal to multiple rows of pixels row by row to scan the pixels and achieve scan driving. Accordingly, the gate drive signal can also be called a scan signal.

[0123] Optionally, the output Gout of the i-th stage shift register unit can be connected to the input IN of the (i+L)-th stage shift register unit. Here, 1 ≤ i ≤ ML, M is the total number of cascaded shift register units, M ≥ 1, and L is a positive integer greater than or equal to 1. For example, L can be 1, meaning that every two adjacent shift register units can be cascaded together.

[0124] For example, when the potential of the first node n1 is the first potential and the potential of the second node n2 is the second potential, the output circuit 04 can control the second power supply terminal VGL to conduct with the output terminal Gout, and control the fourth clock terminal CK4 to disconnect from the output terminal Gout. In this way, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout, and then output to the pixel circuit via the output terminal Gout. That is, the scan signal transmitted to the pixel circuit at this time can be the low-potential second power supply signal. The output circuit 04 can also control the fourth clock terminal CK4 to conduct with the output terminal Gout, and control the second power supply terminal VGL to disconnect from the output terminal Gout, when the potential of the first node n1 is the second potential and the potential of the second node n2 is the first potential, and control the second clock terminal CK4 to conduct with the output terminal Gout, and control the second power supply terminal VGL to disconnect from the output terminal Gout. In this way, the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the output terminal Gout, and then output to the pixel circuit via the output terminal Gout. That is, the scan signal transmitted to the pixel circuit at this time can be the fourth clock signal. Accordingly, the potential of this fourth clock signal can be flexibly set to output a scan signal with the required potential to the pixel circuit. For example, for the N-type transistor in the pixel circuit, the potential of the fourth clock signal can be set to a high potential to reliably control the N-type transistor to turn on. This achieves a scheme for high-level pulse width shifting using a shift register unit composed entirely of P-type TFTs, without needing to convert the LTPS P-type TFTs in the shift register unit into oxide N-type TFTs.

[0125] In summary, this application provides a shift register unit. In this shift register unit, the first control circuit can control the potential of the first node under the control of the first clock signal. The second control circuit can control the potential of the second node under the control of the potential of the first node, the second clock signal, and the first power supply signal. The adjustment circuit can adjust the potential of the first node under the control of the potential of the first node, the third clock signal, the control signal, and the target signal, so that the potential of the first node is maintained stably. The output circuit can output a fourth clock signal or a second power supply signal through the output terminal under the control of the potentials of the two nodes. Therefore, by flexibly setting the clock signal, the shift register unit can flexibly output high or low potential scan signals to the pixel circuit, meeting the driving requirements of any type of transistor in the pixel circuit.

[0126] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the adjustment circuit 03 may include: a first adjustment sub-circuit 031, a second adjustment sub-circuit 032, and a third adjustment sub-circuit 033.

[0127] The first regulating sub-circuit 031 can be connected to the control terminal Con, the second target terminal V2, and the third node n3, respectively. Furthermore, the first regulating sub-circuit 031 can be used to control the on / off state of the second target terminal V2 and the third node n3 in response to a control signal.

[0128] For example, the first regulating sub-circuit 031 can control the second target terminal V2 to conduct with the third node n3 when the control signal potential is the first potential. This allows the target signal provided by the second target terminal V2 to be transmitted to the third node n3. The first regulating sub-circuit 031 can also control the second target terminal V2 to disconnect from the third node n3 when the control signal potential is the second potential.

[0129] Optionally, in Figure 2, the control terminal Con can be shared with the first clock terminal CK1, and the second target terminal V2 can be shared with the first power supply terminal VGH.

[0130] The second regulating sub-circuit 032 can be connected to the first node n1, the third clock terminal CK3, and the third node n3, respectively. Furthermore, the second regulating sub-circuit 032 can be used to control the switching on and off of the third clock terminal CK3 and the third node n3 in response to the potential of the first node n1.

[0131] For example, the second regulating sub-circuit 032 can control the third clock terminal CK3 to conduct with the third node n3 when the potential of the first node n1 is the first potential. This allows the third clock signal provided by the third clock terminal CK3 to be transmitted to the third node n3. The second regulating sub-circuit 032 can also control the third clock terminal CK3 to disconnect from the third node n3 when the potential of the first node n1 is the second potential.

[0132] The third regulating sub-circuit 033 can be connected to the third node n3 and the first node n1 respectively. Furthermore, the third regulating sub-circuit 033 can be used to regulate the potential of the first node n1 in response to the potential of the third node n3.

[0133] For example, the third regulating circuit 033 can, through coupling, raise the potential of the first node n1 based on the high potential of the third node n3 or lower the potential of the first node n1 based on the low potential of the third node n3.

[0134] Optionally, in some embodiments, as shown in FIG3, the third node n3 may include: a first sub-node n3-1 and a second sub-node n3-2. A first regulating sub-circuit 031 may be connected to the first sub-node n3-1. A second regulating sub-circuit 032 may be connected to the second sub-node n3-2. That is, the first regulating sub-circuit 031 may be used to control the on / off state of the second target terminal V2 and the first sub-node n3-1 in the third node n3 in response to a control signal. The second regulating sub-circuit 032 may be used to control the on / off state of the third clock terminal CK3 and the second sub-node n3-2 in the third node n3 in response to the potential of the first node n1.

[0135] Furthermore, based on this, referring to Figure 3, it can be seen that the third adjustment sub-circuit 033 may include: a first adjustment unit 0331 and a second adjustment unit 0332.

[0136] The first adjustment unit 0331 can be connected to the first child node n3-1 and the second child node n3-2 respectively. Furthermore, the first adjustment unit 0331 can be used to adjust the potential of the first child node n3-1 in response to the potential of the second child node n3-2.

[0137] For example, the first adjustment unit 0331 can, through coupling, raise the potential of the first sub-node n3-1 based on the high potential of the second sub-node n3-2 or lower the potential of the first sub-node n3-1 based on the low potential of the second sub-node n3-2.

[0138] The second adjustment unit 0332 can be connected to the first sub-node n3-1 and the first node n1 respectively. Furthermore, the second adjustment unit 0332 can be used to control the on / off state of the first sub-node n3-1 and the first node n1 in response to the potential of the first sub-node n3-1, so as to adjust the potential of the first node n1.

[0139] For example, the second adjustment unit 0332 can control the first child node n3-1 to be connected to the first node n1 when the potential of the first child node n3-1 is at the first potential. This allows the signal transmitted to the first child node n3-1 to be further transmitted to the first node n1, that is, controlling the potential of the first node n1 to be the same as the potential of the first child node n3-1. The second adjustment unit 0332 can also control the first child node n3-1 to be disconnected from the first node n1 when the potential of the first child node n3-1 is at the second potential.

[0140] It is understandable that, compared to the example shown in Figure 2, by additionally setting the second adjustment unit 0332, it can be ensured that when the potential of the third clock terminal CK3 changes (e.g., from low to high potential), it will not be directly coupled to the first node n1 through the first adjustment unit 0331. That is, the first node n1 and the third node n3 can be isolated by the second adjustment unit 0332, ensuring better potential stability of the first node n1. Furthermore, it can be ensured that the output circuit 04 can respond to the potential of the first node n1 and reliably output the scan signal through the output terminal Gout.

[0141] Furthermore, referring to Figure 3, it can be seen that, based on this embodiment, the control terminal Con can be connected to the second node n2, and the second target terminal V2 can be connected to the first node n1. Of course, this is only an illustrative illustration. For example, the second target terminal V2 can also be shared with the first power supply terminal VGH.

[0142] Optionally, based on Figure 2, and referring to the structural schematic diagram of another shift register unit shown in Figure 4, it can be seen that the second control circuit 02 may include: a first control sub-circuit 021, a second control sub-circuit 022, and a third control sub-circuit 023.

[0143] The first control sub-circuit 021 can be connected to the first node n1, the first power supply terminal VGH, and the second node n2, respectively. Furthermore, the first control sub-circuit 021 can be used to control the switching between the first power supply terminal VGH and the second node n2 in response to the potential of the first node n1.

[0144] For example, the first control sub-circuit 021 can control the first power supply terminal VGH to conduct with the second node n2 when the potential of the first node n1 is the first potential. This allows the high-potential first power signal provided by the first power supply terminal VGH to be transmitted to the second node n2, thus controlling the potential of the second node n2 to be high. The first control sub-circuit 021 can also control the first power supply terminal VGH to disconnect from the second node n2 when the potential of the first node n1 is the second potential.

[0145] The second control sub-circuit 022 can be connected to the first node n1, the first power supply terminal VGH, the second clock terminal CK2, and the fourth node n4, respectively. Furthermore, the second control sub-circuit 022 can control the switching between the first power supply terminal VGH and the fourth node n4 in response to the potential of the first node n1, and adjust the potential of the fourth node n4 in response to the second clock signal.

[0146] For example, the second control sub-circuit 022 can control the first power supply terminal VGH to conduct with the fourth node n4 when the potential of the first node n1 is the first potential. This allows the high-potential first power signal provided by the first power supply terminal VGH to be transmitted to the fourth node n4, thus controlling the potential of the fourth node n4 to be high. The second control sub-circuit 022 can also control the first power supply terminal VGH to disconnect from the fourth node n4 when the potential of the first node n1 is the second potential. Furthermore, the second control sub-circuit 022 can, through coupling, pull the potential of the fourth node n4 high or low based on the second clock signal.

[0147] The third control sub-circuit 023 can be connected to the fourth node n4, the first target terminal V1, and the second node n2, respectively. Furthermore, the third control sub-circuit 023 can be used to control the switching on and off of the first target terminal V1 and the second node n2 in response to the potential of the fourth node n4. Optionally, the first target terminal V1 shown in Figure 3 is the second power supply terminal VGL.

[0148] For example, taking the first target terminal V1 as the second power supply terminal VGL, the third control sub-circuit 023 can control the second power supply terminal VGL to conduct with the second node n2 when the potential of the fourth node n4 is the first potential. In this way, the low-potential second power signal provided by the second power supply terminal VGL can be transmitted to the second node n2, that is, the potential of the second node n2 can be controlled to be low. The third control sub-circuit 023 can also control the second power supply terminal VGL to disconnect from the second node n2 when the potential of the fourth node n4 is the second potential.

[0149] Alternatively, based on Figure 4, and referring to Figure 5, which shows another structural schematic diagram of a shift register unit, the output circuit 04 may include: a first output sub-circuit 041 and a second output sub-circuit 042.

[0150] The first output sub-circuit 041 can be connected to the first node n1, the second power supply terminal VGL, and the output terminal Gout, respectively. Furthermore, the first output sub-circuit 041 can be used to control the switching between the second power supply terminal VGL and the output terminal Gout in response to the potential of the first node n1.

[0151] For example, the first output sub-circuit 041 can control the second power supply terminal VGL to conduct with the output terminal Gout when the potential of the first node n1 is the first potential. This allows the low-potential second power supply signal provided by the second power supply terminal VGL to be output through the output terminal Gout. The first output sub-circuit 041 can also control the second power supply terminal VGL to disconnect from the output terminal Gout when the potential of the first node n1 is the second potential.

[0152] The second output sub-circuit 042 can be connected to the second node n2, the fourth clock terminal CK4, and the output terminal Gout, respectively. Furthermore, the second output sub-circuit 042 can control the switching between the fourth clock terminal CK4 and the output terminal Gout in response to the potential of the second node n2, and can also adjust the potential of the second node n2 based on the fourth clock signal provided by the fourth clock terminal CK4.

[0153] For example, the second output sub-circuit 042 can control the fourth clock terminal CK4 to conduct with the output terminal Gout when the potential of the second node n2 is the first potential. This allows the fourth clock signal provided by the fourth clock terminal CK4 to be output through the output terminal Gout. The second output sub-circuit 042 can also control the fourth clock terminal CK4 to disconnect from the output terminal Gout when the potential of the second node n2 is the second potential. Furthermore, the second output sub-circuit 042 can, through coupling, pull the potential of the second node n2 high or low based on the fourth clock signal.

[0154] Optionally, based on Figure 5, Figures 6 and 7 respectively show schematic diagrams of another shift register unit. Referring to Figures 6 and 7, it can be seen that the shift register unit provided in this embodiment may further include: a third control circuit 05.

[0155] Furthermore, in one embodiment, as shown in FIG6, the third control circuit 05 can be connected between the first control sub-circuit 021 and the first power supply terminal VGH, and can also be connected to the fifth clock terminal CK5. In this connection configuration, the third control circuit 05 can be used to control the on / off state of the first control sub-circuit 021 and the first power supply terminal VGH in response to the fifth clock signal provided by the fifth clock terminal CK5.

[0156] For example, the third control circuit 05 can control the first control sub-circuit 021 to conduct with the first power supply terminal VGH when the potential of the fifth clock signal provided by the fifth clock terminal CK5 is a first potential. This allows the high-potential first power signal provided by the first power supply terminal VGH to be transmitted to the first control sub-circuit 021. Furthermore, the third control circuit 05 can control the first control sub-circuit 021 to disconnect from the first power supply terminal VGH when the potential of the fifth clock signal provided by the fifth clock terminal CK5 is a second potential.

[0157] That is, the third control circuit 05 and the first control sub-circuit 021 can be connected sequentially between the first power supply terminal VGH and the second node n2. Furthermore, the circuit composed of the third control circuit 05 and the first control sub-circuit 021 can be used to control the switching between the first power supply terminal VGH and the second node n2 in response to the fifth clock signal provided by the fifth clock terminal CK5 and the potential of the first node n1. Thus, by flexibly setting the fifth clock signal, the potential of the second node n2 can be reliably and flexibly controlled, thereby controlling the output circuit 04 to flexibly output a scanning signal in response to the potential of the second node n2.

[0158] Alternatively, in another embodiment, as shown in FIG7, the third control circuit 05 can be connected between the first control circuit 01 and the first node n1, and can be connected to the fifth clock terminal CK5. Furthermore, in this connection method, the third control circuit 05 can be used to control the on / off state of the first control circuit 01 and the first node n1 in response to the fifth clock signal.

[0159] For example, the third control circuit 05 can control the first control circuit 01 to conduct with the first node n1 when the potential of the fifth clock signal provided by the fifth clock terminal CK5 is at the first potential. This allows the signal output by the first control circuit 01 (i.e., the input signal) to be transmitted to the first node n1. Furthermore, the third control circuit 05 can control the first control circuit 01 to disconnect from the first node n1 when the potential of the fifth clock signal provided by the fifth clock terminal CK5 is at the second potential.

[0160] That is, the first control circuit 01 and the third control circuit 05 can be connected sequentially between the input terminal IN and the first node n1. Furthermore, the circuit composed of the first control circuit 01 and the third control circuit 05 can be used to control the on / off state of the input terminal IN and the first node n1 in response to the first clock signal provided by the first clock terminal CK1 and the fifth clock signal provided by the fifth clock terminal CK5. Thus, by flexibly setting the fifth clock signal, the potential of the first node n1 can be reliably and flexibly controlled, thereby controlling the output circuit 04 to flexibly output a scanning signal in response to the potential of the first node n1.

[0161] Furthermore, referring to Figures 6 and 7, it can be seen that, based on this embodiment, the control terminal Con can be connected to the second node n2, and the second target terminal V2 can be shared with the first power supply terminal VGH.

[0162] Optionally, referring to Figure 6, when the third control circuit 05 is connected between the first control sub-circuit 021 and the first power supply terminal VGH, the fifth clock terminal CK5 can be shared with the second clock terminal CK2, the third clock terminal CK3 can be shared with the second clock terminal CK2, and / or, the fourth clock terminal CK4 can be shared with the first clock terminal CK1. For example, referring to Figure 6, the first clock terminal CK1 and the fourth clock terminal CK4 can both be connected to the same clock signal line CLK1, and the second clock terminal CK2, the third clock terminal CK3, and the fifth clock terminal CK5 can all be connected to the same other clock signal line CLK2. That is, in one embodiment shown in Figure 6, the shift register unit can be connected to two clock signal lines CLK1 and CLK2 and operate under the drive of the clock signals provided by these two clock signal lines CLK1 and CLK2. Alternatively, the shift register unit can be said to be connected to two clock terminals.

[0163] Optionally, referring to Figure 7, when the third control circuit 05 is connected between the first control circuit 01 and the first node n1, the fifth clock terminal CK5 and the second clock terminal CK2 can be independent of each other, the third clock terminal CK3 and the second clock terminal CK2 can be shared, and / or, the fourth clock terminal CK4 and the first clock terminal CK1 can be shared. For example, referring to Figure 7, the first clock terminal CK1 and the fourth clock terminal CK4 can both be connected to the same clock signal line CLK1, the second clock terminal CK2 and the third clock terminal CK3 can both be connected to the same other clock signal line CLK2, and the fifth clock terminal CK5 can be connected to another third clock signal line CLK3. That is, in another embodiment shown in Figure 7, the shift register unit can be connected to three clock signal lines CLK1, CLK2 and CLK3, and operate under the drive of the clock signals provided by these three clock signal lines CLK1, CLK2 and CLK3. Alternatively, it can be said that the shift register unit can be connected to three clock terminals.

[0164] Furthermore, for either embodiment in Figures 6 and 7, the cascaded shift register units can share four clock lines. That is, each clock input of each shift register unit can be sequentially connected to the adjacent clock lines. It is understood that, in conjunction with the preceding description, each clock input refers to the connection of the clock signal line to which that clock input is connected to the clock line.

[0165] For example, in the structure shown in Figure 6, the two clock signal lines CLK1 and CLK2 connected to the multiple clock terminals of the first-stage shift register unit can be connected to the first clock line CK10 and the second clock line CK20, respectively. Similarly, the two clock signal lines CLK1 and CLK2 connected to the second-stage shift register unit cascaded with the first-stage shift register unit can be connected to the second clock line CK20 and the third clock line CK30, respectively. Likewise, the two clock signal lines CLK1 and CLK2 connected to the third-stage shift register unit cascaded with the second-stage shift register unit can be connected to the third clock line CK30 and the fourth clock line CK40, respectively. And so on.

[0166] Similarly, for the structure shown in Figure 7, the three clock signal lines CLK1, CLK2, and CLK3 connected to the multiple clock terminals of the first-stage shift register unit can be connected to the first clock line CK10, the second clock line CK20, and the third clock line CK30, respectively. The three clock signal lines CLK1, CLK2, and CLK3 connected to the second-stage shift register unit cascaded with the first-stage shift register unit can be connected to the second clock line CK20, the third clock line CK30, and the fourth clock line CK40, respectively. Similarly, the three clock signal lines CLK1, CLK2, and CLK3 connected to the third-stage shift register unit cascaded with the second-stage shift register unit can be connected to the third clock line CK30, the fourth clock line CK40, and the first clock line CK10, respectively. And so on.

[0167] Of course, the above description is merely illustrative. For example, in some other embodiments, five or more clock lines can be provided for multiple cascaded shift register units to share and connect. This can be flexibly configured according to the pulse width of the required output scan signal.

[0168] Optionally, based on the structure shown in Figure 3 and in conjunction with Figure 6, Figure 8 shows a schematic diagram of another shift register unit. As shown in Figure 8, the shift register unit provided in this embodiment may further include: a first reset circuit 06 and / or a second reset circuit 07.

[0169] The first reset circuit 06 can be connected to the reset control terminal NCX, the first power supply terminal VGH, and the first node n1, respectively. Furthermore, the first reset circuit 06 can be used to control the connection and disconnection between the first power supply terminal VGH and the first node n1 in response to the reset control signal provided by the reset control terminal NCX.

[0170] For example, the first reset circuit 06 can control the first power supply terminal VGH to conduct with the first node n1 when the reset control signal provided by the reset control terminal NCX is at a first potential. This allows the high-potential first power signal provided by the first power supply terminal VGH to be transmitted to the first node n1, thus controlling the potential of the first node n1 to be high. The first reset circuit 06 can also control the first power supply terminal VGH to disconnect from the first node n1 when the reset control signal provided by the reset control terminal NCX is at a second potential.

[0171] The second reset circuit 07 can be connected to the reset control terminal NCX, the second power supply terminal VGL, and the second node n2, respectively. Furthermore, the second reset circuit 07 can be used to control the switching on and off of the second power supply terminal VGL and the second node n2 in response to a reset control signal.

[0172] For example, the second reset circuit 07 can control the second power supply terminal VGL to conduct with the second node n2 when the reset control signal provided by the reset control terminal NCX is at the first potential. This allows the low-potential second power signal provided by the second power supply terminal VGL to be transmitted to the second node n2, thus controlling the potential of the second node n2 to be low. The second reset circuit 07 can also control the second power supply terminal VGL to disconnect from the second node n2 when the reset control signal provided by the reset control terminal NCX is at the second potential.

[0173] In this way, by flexibly setting the reset control signal potential to the first potential when the entire machine is powered on (i.e., turned on) or powered off (i.e., turned off), the potential of the first node n1 can be controlled to be high to reset the potential of the first node n1, and / or the potential of the second node n2 can be controlled to be low to reset the potential of the second node n2. When both the potentials of the first node n1 and the second node n2 are reset, it can also be considered that all circuits in the shift register unit are reset. Therefore, it can be ensured that after the initial stage of each power-on, the multiple cascaded shift register units can start working in a unified working state, thereby ensuring good uniformity of the scan signals output to each row of pixel circuits, resulting in good display uniformity.

[0174] Optionally, based on Figure 5, Figure 9 schematically shows a structural diagram of another shift register unit. Based on Figure 6, Figure 10 schematically shows a structural diagram of another shift register unit. Based on Figure 7, Figure 11 schematically shows a structural diagram of another shift register unit. Based on Figure 8, Figure 12 schematically shows a structural diagram of another shift register unit. Referring to Figures 9 to 12, it can be seen that:

[0175] The first node n1 may include a third child node n1-1 and a fourth child node n1-2. The first control circuit 01 and the second control circuit 02 can both be connected to the third child node n1-1. The adjustment circuit 03 and the output circuit 04 can both be connected to the fourth child node n1-2. The second target terminal V2 can be connected to the third child node n1-1.

[0176] That is, the first control circuit 01 can be used to control the switching of the input terminal IN with the third sub-node n1-1 in the first node n1 in response to the first clock signal. The second control circuit 02 can be used to control the switching of the first power supply terminal VGH with the second node n2 and the second power supply terminal VGL with the second node n2 in response to the potential of the third sub-node n1-1 in the first node n1, the second clock signal, and the first power supply signal. The adjustment circuit 03 can be used to adjust the potential of the fourth sub-node n1-2 in the first node n1 in response to the potential of the fourth sub-node n1-2 in the first node n1, the third clock signal, the control signal, and the target signal provided by the second target terminal V2 (e.g., the potential of the third sub-node n1-1). The output circuit 04 can be used to control the switching of the second power supply terminal VGL with the output terminal Gout in response to the potential of the fourth sub-node n1-2 in the first node n1.

[0177] Furthermore, based on this, referring to Figures 9 to 12, it can be seen that the shift register unit may also include: isolation circuit 08.

[0178] The isolation circuit 08 can be connected to the second power supply terminal VGL, the third sub-node n1-1, and the fourth sub-node n1-2, respectively. Furthermore, the isolation circuit 08 can be used to control the switching on and off of the third sub-node n1-1 and the fourth sub-node n1-2 in response to the second power supply signal provided by the second power supply terminal VGL.

[0179] For example, the isolation circuit 08 can control the conduction of the third sub-node n1-1 and the fourth sub-node n1-2 under the control of a low-potential second power supply signal. This isolates the third sub-node n1-1 from the fourth sub-node n1-2, preventing voltage backflow from the output circuit 04 and thus avoiding potential instability in the third sub-node n1-1. This also protects the transistor controlling the potential of the third sub-node n1-1, ensuring better output stability of the shift register unit. Based on this, in some other embodiments, the second node n2 can also be divided into two nodes, and an isolation circuit 08 can be placed between the two nodes to achieve the same isolation effect.

[0180] Optionally, based on Figure 9, Figure 13 schematically shows a structural diagram of another shift register unit. Figure 14 schematically shows a structural diagram of another shift register unit. Based on Figure 10, Figure 15 schematically shows a structural diagram of another shift register unit. Based on Figure 11, Figure 16 schematically shows a structural diagram of another shift register unit. Based on Figure 12, Figure 17 schematically shows a structural diagram of another shift register unit. Referring to Figures 13 to 17, it can be seen that the first regulating sub-circuit 031 may include: a first transistor T1.

[0181] The gate of the first transistor T1 can be connected to the control terminal Con, the first electrode of the first transistor T1 can be connected to the second target terminal V2, and the second electrode of the first transistor T1 can be connected to the third node n3.

[0182] Optionally, as can be seen from the foregoing description and accompanying drawings, in the shift register units with the structures shown in Figures 13 and 14, the control terminal Con can be shared with the first clock terminal CK1, and the second target terminal V2 can be shared with the first power supply terminal VGH. In the shift register units with the structures shown in Figures 15 and 16, the control terminal Con can be connected to the second node n2, and the second target terminal V2 can be shared with the first power supply terminal VGH. In the shift register unit with the structure shown in Figure 17, the control terminal Con can be connected to the second node n2, and the second target terminal V2 can be connected to the first node n1.

[0183] Optionally, referring further to Figures 13 to 17, it can be seen that the second regulating sub-circuit 032 may include: a second transistor T2.

[0184] The gate of the second transistor T2 can be connected to the first node n1, the first terminal of the second transistor T2 can be connected to the third clock terminal CK3, and the second terminal of the second transistor T2 can be connected to the third node n3.

[0185] Optionally, referring further to Figures 13 to 16, it can be seen that, for one embodiment described above, the third regulating sub-circuit 033 may include a first capacitor C1.

[0186] One end of the first capacitor C1 can be connected to the third node n3, and the other end of the first capacitor C1 can be connected to the first node n1.

[0187] Optionally, referring to Figure 17, in another embodiment described above: the first adjustment unit 0331 may include a first capacitor C1. The second adjustment unit 0332 may include a third transistor T3.

[0188] One end of the first capacitor C1 can be connected to the first child node n3-1, and the other end of the first capacitor C1 can be connected to the second child node n3-2.

[0189] The gate and first terminal of the third transistor T3 can both be connected to the first child node n3-1, and the second terminal of the third transistor T3 can be connected to the first node n1.

[0190] Furthermore, as shown in Figure 17, based on dividing the third node n3 into a first child node n3-1 and a second child node n3-2, the second terminal of the first transistor T1 can be connected to the first child node n3-1 in the third node n3. Similarly, the second terminal of the second transistor T2 can be connected to the second child node n3-2 in the third node n3.

[0191] Optionally, referring to Figures 13 to 17, it can be seen that the first control sub-circuit 021 may include: a fourth transistor T4.

[0192] The gate of the fourth transistor T4 can be connected to the first node n1, the first terminal of the fourth transistor T4 can be connected to the first power supply terminal VGH, and the second terminal of the fourth transistor T4 can be connected to the second node n2.

[0193] Furthermore, it is understood that, as shown in Figures 15 and 17, with the third control circuit 05 also provided, the first terminal of the fourth transistor T4 can be indirectly connected to the first power supply terminal VGH through the third control circuit 05.

[0194] Optionally, referring to Figures 13 to 17, it can be seen that the second control sub-circuit 022 may include: a fifth transistor T5 and a second capacitor C2.

[0195] The gate of the fifth transistor T5 can be connected to the first node n1, the first terminal of the fifth transistor T5 can be connected to the first power supply terminal VGH, and the second terminal of the fifth transistor T5 can be connected to the fourth node n4.

[0196] One end of the second capacitor C2 can be connected to the second clock terminal CK2, and the other end of the second capacitor C2 can be connected to the fourth node n4.

[0197] Optionally, referring to Figures 13 to 17, it can be seen that the third control sub-circuit 023 may include: the sixth transistor T6.

[0198] The gate of the sixth transistor T6 can be connected to the fourth node n4, the first terminal of the sixth transistor T6 can be connected to the first target terminal V1, and the second terminal of the sixth transistor T6 can be connected to the second node n2.

[0199] Optionally, as can be seen from the foregoing description and the accompanying drawings, in the shift register unit with the structure shown in Figure 13, the first target terminal V1 is shared with the second clock terminal CK2. In the shift register units with the structures shown in Figures 14 to 17, the first target terminal V1 is the second power supply terminal VGL.

[0200] Optionally, referring to Figures 15 to 17, it can be seen that the third control circuit 05 may include: the seventh transistor T7.

[0201] The gate of the seventh transistor T7 can be connected to the fifth clock terminal CK5. When the third control circuit 05 is connected between the first control sub-circuit 021 and the first power supply terminal VGH, the first terminal of the seventh transistor T7 can be connected to the first control sub-circuit 021, and the second terminal of the seventh transistor T7 can be connected to the first power supply terminal VGH. When the third control circuit 05 is connected between the first control circuit 01 and the first node n1, the first terminal of the seventh transistor T7 can be connected to the first control circuit 01, and the second terminal of the seventh transistor T7 can be connected to the first node n1.

[0202] That is, as shown in Figures 15 and 17, when the third control circuit 05 is connected between the first control sub-circuit 021 and the first power supply terminal VGH, the first terminal of the seventh transistor T7 can be connected to the first terminal of the fourth transistor T4 included in the first control sub-circuit 021, and the second terminal of the seventh transistor T7 can be connected to the first power supply terminal VGH. As shown in Figure 16, when the third control circuit 05 is connected between the first control circuit 01 and the first node n1, the first terminal of the seventh transistor T7 can be connected to the transistor included in the first control circuit 01, and the second terminal of the seventh transistor T7 can be connected to the third sub-node n1-1 included in the first node n1.

[0203] Optionally, referring to Figures 13 to 17, it can be seen that the first control circuit 01 may include: an eighth transistor T8.

[0204] The gate of the eighth transistor T8 can be connected to the first clock terminal CK1, the first terminal of the eighth transistor T8 can be connected to the input terminal IN (e.g., the turn-on signal terminal STV), and the second terminal of the eighth transistor T8 can be connected to the first node n1.

[0205] Furthermore, it is understood that, as shown in Figure 16, based on the additional third control circuit 05, the second terminal of the eighth transistor T8 can be connected to the first terminal of the seventh transistor T7 included in the third control circuit 05, so as to be indirectly connected to the first node n1 through the third control circuit 05.

[0206] Optionally, referring to Figures 13 to 17, it can be seen that the first output sub-circuit 041 may include: the ninth transistor T9.

[0207] The gate of the ninth transistor T9 can be connected to the first node n1, the first terminal of the ninth transistor T9 can be connected to the second power supply terminal VGL, and the second terminal of the ninth transistor T9 can be connected to the output terminal Gout.

[0208] Optionally, referring to Figures 13 to 17, it can be seen that the second output sub-circuit 042 may include: the tenth transistor T10 and the third capacitor C3.

[0209] The gate of the tenth transistor T10 can be connected to the second node n2, the first terminal of the tenth transistor T10 can be connected to the fourth clock terminal CK4, and the second terminal of the tenth transistor T10 can be connected to the output terminal Gout.

[0210] One end of the third capacitor C3 can be connected to the fourth clock terminal CK4, and the other end of the third capacitor C3 can be connected to the second node n2.

[0211] Optionally, referring to Figure 17, the first reset circuit 06 may include an eleventh transistor T11.

[0212] The gate of the eleventh transistor T11 can be connected to the reset control terminal NCX, the first terminal of the eleventh transistor T11 can be connected to the first power supply terminal VGH, and the second terminal of the eleventh transistor T11 can be connected to the first node n1.

[0213] Optionally, referring to Figure 17, the second reset circuit 07 may include a twelfth transistor T12.

[0214] The gate of the twelfth transistor T12 can be connected to the reset control terminal NCX, the first terminal of the twelfth transistor T12 can be connected to the second power supply terminal VGL, and the second terminal of the twelfth transistor T12 can be connected to the second node n2.

[0215] Optionally, referring to Figures 13 to 17, it can be seen that the isolation circuit 08 may include: the thirteenth transistor T13.

[0216] The gate of the thirteenth transistor T13 can be connected to the second power supply terminal VGL, the first terminal of the thirteenth transistor T13 can be connected to the third child node n1-1, and the second terminal of the thirteenth transistor T13 can be connected to the fourth child node n1-2.

[0217] Furthermore, it can be understood that, based on dividing the first node n1 into the third child node n1-1 and the fourth child node n1-2, and referring to Figures 13 to 15 and Figure 17, the second terminal of the eighth transistor T8 can be connected to the third child node n1-1. Referring to Figure 16, the second terminal of the seventh transistor T7 can be connected to the third child node n1-1. Referring to Figures 13 to 17, the gates of the fourth transistor T4 and the fifth transistor T5 can be connected to the third child node n1-1. Referring to Figures 13 to 16, one end of the first capacitor C1 can be connected to the fourth child node n1-2. Referring to Figure 17, the second terminal of the third transistor T3 can be connected to the fourth child node n1-2. Referring to Figures 13 to 17, the gate of the second transistor T2 can be connected to the fourth child node n1-2. Referring to Figure 17, the first terminal of the first transistor T1 can be connected to the third child node n1-1. Furthermore, as can be seen from Figures 13 to 17, the gate of the ninth transistor T9 can be connected to the fourth child node n1-2.

[0218] That is, the shift register unit provided in this application embodiment can be a 9T3C (i.e., including 9 transistors and 3 capacitors) structure circuit as shown in Figures 13 and 14, or a 10T3C (i.e., including 10 transistors and 3 capacitors) structure circuit as shown in Figures 15 and 16, or a 13T3C (i.e., including 13 transistors and 3 capacitors) structure circuit as shown in Figure 17. This application embodiment does not limit this. Furthermore, in the shift register unit provided in this application embodiment, each transistor can be a P-type transistor as shown in Figures 13 to 17, such as a PMOS transistor. Of course, each transistor can also be an N-type transistor, or the shift register unit can include both P-type and N-type transistors.

[0219] Optionally, in some embodiments, the shift register unit described in this application can be divided into four parts: a charging and reset unit, a control unit, a sustaining unit, and an output unit. Furthermore, the shift register unit can operate under the drive of at least two clock signals.

[0220] The charging and reset unit is also known as the first control circuit 01. The control unit is also known as the second control circuit 03. The maintenance unit may include the adjustment circuit 03 and the first output sub-circuit 041 in the output circuit 04. The output unit is also known as the second output sub-circuit 041 in the output circuit 04. Taking the structure shown in Figure 14 as an example:

[0221] The charging and reset unit may include a transistor (i.e., T8), an input terminal IN (e.g., an enable signal terminal STV), and a clock terminal (i.e., a first clock terminal CK1). The charging and reset unit is used to control the potential of the first node n1.

[0222] The control unit may include three transistors (i.e., T4, T5, and T6), a capacitor (i.e., C2), a clock input (i.e., the second clock input CK2), a first power supply terminal VGH, and a second power supply terminal VGL. This control unit is used to control the potential of the second node n2. During the non-operating phase, the potential of the second node n2 is kept high. That is, when the potential of the second clock signal provided by the second clock input CK2 is high, the potential of the second node n2 is kept high; when the potential of the second clock signal provided by the second clock input CK2 is low, the potential of the second node n2 remains high. During the operating phase, regardless of whether the potential of the second clock signal provided by the second clock input CK2 is high or low, the potential of the second node n2 is kept low. It can be understood that the operating phase is the phase in which a scan signal with a valid potential (e.g., high potential) is output through the output terminal Gout. The non-operating phase is any phase other than the operating phase.

[0223] The sustaining unit may include four transistors (e.g., T1, T2, T13, and T9), a capacitor (i.e., C1), two clock terminals (i.e., the first clock terminal CK1 and the third clock terminal CK3), a first power supply terminal VGH, and a second power supply terminal VGL. This sustaining unit can be used during the non-operating phase to maintain the potential of the fourth child node n1-2 in the first node n1 at a low potential, so that the scan signal output through the output terminal Gout is pulled down to the low-potential second power supply signal provided by the second power supply terminal VGL through the ninth transistor T9.

[0224] The output unit may include a transistor (i.e., T10), a capacitor (i.e., C3), and a clock input (i.e., the fourth clock input CK4). This output unit can be used to control the transmission of the fourth clock signal provided by the fourth clock input CK4 to the output input Gout when the potential of the second node n2 is low; that is, the fourth clock signal is output as a scan signal via the output input Gout. Thus, by setting the potential of the fourth clock signal to high during the operating phase, the shift register unit can output a high-potential pulse width signal via the output input Gout, thereby reliably driving the N-type transistor in the pixel circuit to turn on.

[0225] Optionally, in one embodiment, the first clock terminal CK1 and the second clock terminal CK2 can be one set of clock terminals, and the third clock terminal CK3 and the fourth clock terminal CK4 can be another set of clock terminals. Within each set of clock terminals, the clock signals provided by the two clock terminals are inverse signals. Here, inverse signal means that the clock signals provided by the two clock terminals have overlapping opposite potentials during the same time period, rather than being completely inverse. Furthermore, during the same time period, the pulse width of the fourth clock signal provided by the fourth clock terminal CK4 can include the pulse width of the third clock signal provided by the third clock terminal CK3, and the pulse width of the second clock signal provided by the second clock terminal CK2 can include the pulse width of the first clock signal provided by the first clock terminal CK1. Here, pulse width can refer to the duration of a high or low potential within one clock cycle.

[0226] That is, as shown in Figures 13 and 14, the first clock terminal CK1 and the second clock terminal CK2 in one set of clock terminals can be connected to clock signal lines CK and CB respectively, serving as the working clock to drive the shift register unit. The third clock terminal CK3 and the fourth clock terminal CK4 in another set of clock terminals can be connected to clock signal lines GCK and GCB respectively, serving as the load clock to control the scan signal output through the output terminal Gout. In other words, in one embodiment, the working clock and the load clock can be designed separately, and the high and low voltage pulse widths of the working clock and the load clock can be set differently. In this way, since the load clock loading can be smaller, the output of the shift register unit can be more stable. In addition, due to the differentiated pulse width settings, the output of the shift register unit can be more flexible. For example, by flexibly setting the load clock, the shift register unit can flexibly output signals with pulse widths smaller than the clock period. Here, load clock loading can refer to a smaller load that the load clock needs to drive. Optionally, in some embodiments, the clock signals provided by each clock terminal in the different sets of clock terminals can be signals with the same period.

[0227] For example, when the clock signal provided by the clock signal line CK (corresponding to the first clock terminal CK1) is at a low potential, the clock signal provided by the clock signal line GCB (corresponding to the fourth clock terminal CK4) can be at a high potential. The rising edge of the clock signal provided by the clock signal line GCB can be earlier than the falling edge of the clock signal provided by the clock signal line CK, and the falling edge of the clock signal provided by the clock signal line GCB can be later than the rising edge of the clock signal provided by the clock signal line CK. This allows the high potential pulse width of the fourth clock signal provided by the fourth clock terminal CK4 to include the low potential pulse width of the first clock signal provided by the first clock terminal CK1. Furthermore, when the clock signal provided by the clock signal line CB (corresponding to the second clock terminal CK2) is at a low potential, the clock signal provided by the clock signal line GCK (corresponding to the third clock terminal CK3) can be at a high potential, and the rising edge of the clock signal provided by the clock signal line GCK can be earlier than the falling edge of the clock signal provided by the clock signal line CB, and the falling edge of the clock signal provided by the clock signal line GCK can be later than the rising edge of the clock signal provided by the clock signal line CB, so that the high potential pulse width of the third clock signal provided by the third clock terminal CK3 can include the low potential pulse width of the second clock signal provided by the second clock terminal CK2.

[0228] In this way, by flexibly setting the load clock potential, the shift register unit can flexibly output signals with pulse widths shorter than the clock period. For example, if all transistors in the shift register unit are P-type transistors (e.g., PMOS transistors), then when designing the shift register unit using PMOS devices, the shift register unit can output high-level pulse width signals with pulse widths shorter than the clock period. If all transistors in the shift register unit are N-type transistors (e.g., NMOS transistors), then when designing the shift register unit using NMOS devices, the shift register unit can output low-level pulse width signals with pulse widths shorter than the clock period.

[0229] Alternatively, as shown in Figures 15 to 17, the first clock terminal CK1, the second clock terminal CK2, the third clock terminal CK3, and the fourth clock terminal CK4 can be the same set of clock terminals, and the potentials of the first clock signal provided by the first clock terminal CK1, the second clock signal provided by the second clock terminal CK2, the third clock signal provided by the third clock terminal CK3, and the fourth clock signal provided by the fourth clock terminal CK4 change sequentially, and two adjacent clock signals that change sequentially have overlapping same potentials.

[0230] That is, in another embodiment, the distinction between the working clock and the load clock may no longer be necessary. Furthermore, in this embodiment, adjacent clock signals are not completely inverted; for example, the high and low potentials of adjacent clock signals may partially overlap. This ensures a stepless high-potential scan signal output through the output terminal Gout, thus guaranteeing good output stability. Moreover, the high-potential pulse width output through the output terminal Gout can be adjusted within a certain range by flexibly setting the clock signal.

[0231] It is understandable that, based on the preceding description and by comparing Figures 13 to 17, the following can be observed:

[0232] The difference between the structure shown in Figure 14 and the structure shown in Figure 13 is that the first target terminal V1 is replaced by the second clock terminal CK2 with the second power supply terminal VGL.

[0233] The structure shown in Figure 15 differs from that shown in Figure 14 in the following ways: First, the working clock and load clock are no longer separated, and the shift register unit is connected to two clock signal lines (or two clock terminals); Second, a seventh transistor T7 is added between the fourth transistor T4 and the first power supply terminal VGH; Third, the gate of the first transistor T1 is no longer connected to the first clock terminal CK1, but is connected to the second node n2, that is, the control terminal Con is connected to the second node n2.

[0234] The structure shown in Figure 16 differs from that shown in Figure 15 in that: firstly, the shift register unit is connected to three clock signal lines (or three clock terminals); secondly, the seventh transistor T7 is moved to the position between the eighth transistor T8 and the third child node n1-1 in the first node n1.

[0235] The structure shown in Figure 17 differs from that shown in Figure 15 in the following ways: First, a third transistor T3 is added and connected between the first capacitor C1 and the fourth sub-node n1-2 in the first node n1; Second, the first terminal of the first transistor T1 is no longer connected to the first power supply terminal VGH, but is connected to the third sub-node n1-1 in the first node n1, that is, the second target terminal V2 is connected to the first node n1; Third, an eleventh transistor T11 is added and connected between the first power supply terminal VGH and the third sub-node n1-1 in the first node n1, and a twelfth transistor T12 is added and connected between the second power supply terminal VGL and the second node n2. A reset control terminal NCX is added to control the eleventh transistor T11 and the twelfth transistor T12 to reset the shift register unit during power-on and power-off.

[0236] It is also understood that Figures 13 to 17 are merely schematic illustrations of various possible circuit structures, and any circuit structure that satisfies the embodiments of this application can be applied to this application.

[0237] In summary, this application provides a shift register unit. In this shift register unit, the first control circuit can control the potential of the first node under the control of the first clock signal. The second control circuit can control the potential of the second node under the control of the potential of the first node, the second clock signal, and the first power supply signal. The adjustment circuit can adjust the potential of the first node under the control of the potential of the first node, the third clock signal, the control signal, and the target signal, so that the potential of the first node is maintained stably. The output circuit can output a fourth clock signal or a second power supply signal through the output terminal under the control of the potentials of the two nodes. Therefore, by flexibly setting the clock signal, the shift register unit can flexibly output high or low potential scan signals to the pixel circuit, meeting the driving requirements of any type of transistor in the pixel circuit.

[0238] This application also provides a method for driving a shift register unit, which is used to drive the shift register unit as described in the above embodiments. As shown in FIG18, the method includes:

[0239] Step 1801, First Stage: The first control circuit responds to the first clock signal and controls the input terminal to conduct with the first node. The second control circuit responds to the potential of the first node, the second clock signal provided by the second clock terminal, and the first power signal provided by the first power supply terminal, and controls the first power supply terminal to conduct with the second node. The adjustment circuit responds to the potential of the first node, the third clock signal provided by the third clock terminal, the control signal provided by the control terminal, and the target signal provided by the second target terminal, and adjusts the potential of the first node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to conduct with the output terminal.

[0240] Step 1802, Second Stage: The first control circuit responds to the first clock signal and disconnects the control input terminal from the first node; the second control circuit responds to the potential of the first node, the second clock signal, and the first power supply signal and controls the first target terminal to conduct with the second node; the adjustment circuit responds to the potential of the first node, the third clock signal, the control signal, and the target signal and adjusts the potential of the first node; the output circuit responds to the potential of the first node and the potential of the second node and controls the fourth clock terminal to conduct with the output terminal.

[0241] Optionally, in the following embodiments, for the structure shown in FIG14, the working principle of the shift register unit shown in FIG14 is explained by taking the cascaded multiple shift register units sharing four clock lines CK0, CB0, GCB0 and GCK0 as an example, and taking the first clock terminal CK1 (i.e., CK) in each shift register unit as connected to clock line CK0, the second clock terminal CK2 (i.e., CB) as connected to clock line CB0, the third clock terminal CK3 (i.e., GCB) as connected to clock line GCB0, and the fourth clock terminal CK4 (i.e., GCK) as connected to clock line GCK0. For the structures shown in Figures 15 and 17, the working principle of the shift register units shown in Figures 15 and 17 is explained by taking the cascaded shift register units as an example, where multiple shift register units share four clock lines CK10, CK20, CK30, and CK40, and the first clock terminal CK1 and the fourth clock terminal CK4 (i.e., CLK1) shared in the current shift register unit are connected to clock line CK10, and the second clock terminal CK2, the third clock terminal CK3, and the fifth clock terminal CK5 (i.e., CLK2) shared in the current shift register unit are connected to clock line CK20. For the structure shown in Figure 16, the working principle of the shift register unit shown in Figure 16 is explained by taking the cascaded shift register units as an example, where multiple cascaded shift register units share four clock lines CK10, CK20, CK30, and CK40. Specifically, the first clock terminal CK1 and the fourth clock terminal CK4 (i.e., CLK1) shared by the current shift register unit are connected to clock line CK10, the second clock terminal CK2 and the third clock terminal CK3 (i.e., CLK2) shared by the current shift register unit are connected to clock line CK20, and the fifth clock terminal CK5 (i.e., CLK3) is connected to clock line CK30. In the structures shown in Figures 14 to 17, the first target terminal V1 is always the second power supply terminal VGL.

[0242] First, taking the shift register unit shown in Figure 14 as an example, and assuming that all the transistors in the shift register unit are P-type transistors, and that the first potential is lower than the second potential, the working principle of the shift register unit with the structure shown in Figure 14 is explained as follows, in conjunction with the signal timing diagram shown in Figure 19:

[0243] In stage A: the potential of the input signal provided by the input terminal IN (e.g., STV), the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CB), and the potential of the third clock signal provided by the third clock terminal CK3 (i.e., GCB) can all be high, while the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) and the potential of the fourth clock signal provided by the fourth clock terminal CK4 (i.e., GCK) can all be low. This allows both the first transistor T1 and the eighth transistor T8 to be turned on (or conducted). Furthermore, since the potential of the second power supply signal provided by the second power supply terminal VGL is low, the thirteenth transistor T13 can be turned on. Correspondingly, the input terminal IN can be controlled to conduct with the third child node n1-1 in the first node n1, the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to conduct, and the first power supply terminal VGH can be controlled to conduct with the third node n3. Furthermore, the high-potential input signal provided by the input terminal IN can be transmitted to the third sub-node n1-1 via the activated eighth transistor T8, and then to the fourth sub-node n1-2 via the activated thirteenth transistor T13 to charge the first capacitor C1. The high-potential first power signal provided by the first power terminal VGH can also be transmitted to the third node n3 via the activated first transistor T1.

[0244] That is, in stage A, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be high, and the potential of the third node n3 can also be controlled to be high. This allows the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 to be turned off (or cut off). Correspondingly, the third clock terminal CK3 can be disconnected from the third node n3, the first power supply terminal VGH can be disconnected from the second node n2, the first power supply terminal VGH can be disconnected from the fourth node n4, and the second power supply terminal VGL can be disconnected from the output terminal Gout. Based on this, the first capacitor C1 can, through coupling, adjust the potential of the fourth child node n1-2 to maintain a high potential based on the high potential of the third node n3. The second capacitor C2 can, through coupling, adjust the potential of the fourth node n4 to a high potential based on the high potential of the second clock signal provided by the second clock terminal CK2. This allows the sixth transistor T6 to be turned off. Correspondingly, the second power supply terminal VGL can be disconnected from the second node n2.

[0245] That is, in stage A, the potential of the second node n2 can be maintained at the potential of the previous stage. Furthermore, since the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can both be low in the previous stage of stage A, the fourth transistor T4 can be turned on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the second node n2. Furthermore, the high-potential first power signal provided by the first power supply terminal VGH can be transmitted to the second node n2 via the turned-on fourth transistor T4, meaning the potential of the second node n2 can be pulled up to a high potential by the fourth transistor T4. Therefore, in stage A, the potential of the second node n2 can continue to remain high. Thus, the tenth transistor T10 can be turned off. Correspondingly, the fourth clock terminal CK4 can be controlled to disconnect from the output terminal Gout. Furthermore, in stage A, the potential of the scan signal output through the output terminal Gout can be maintained at the potential of the previous stage. Since the potential of the fourth child node n1-2 is low in the previous stage of stage A, the ninth transistor T9 can be turned on. Correspondingly, the second power supply terminal VGL and the output terminal Gout can be turned on. This allows the low-potential second power supply signal provided by the second power supply terminal VGL to be transmitted to the output terminal Gout via the activated ninth transistor T9. That is, in the stage preceding stage A, the potential of the scan signal output through the output terminal Gout is low. Accordingly, in stage A, the potential of the scan signal output by the shift register unit through the output terminal Gout can be maintained at a low potential.

[0246] In stage B: the potentials of the input signal provided by the input terminal IN (e.g., STV), the second clock signal provided by the second clock terminal CK2 (i.e., CB), and the third clock signal provided by the third clock terminal CK3 (i.e., GCB) can all be low, while the potentials of the first clock signal provided by the first clock terminal CK1 (i.e., CK) and the fourth clock signal provided by the fourth clock terminal CK4 (i.e., GCK) can all be high. This allows both the first transistor T1 and the eighth transistor T8 to be turned off. Correspondingly, the input terminal IN can be disconnected from the third sub-node n1-1 in the first node n1, and the first power supply terminal VGH can be disconnected from the third node n3. At this time, since the third sub-node n1-1 and the fourth sub-node n1-2 in the first node n1, as well as the third node n3, have no discharge path, the potentials of the third sub-node n1-1, the fourth sub-node n1-2, and the third node n3 can all remain at the high potential of the previous stage (i.e., stage A). In this way, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 can all remain off. Correspondingly, in the same stage A, the third clock terminal CK3 can be disconnected from the third node n3, the first power supply terminal VGH can be disconnected from the second node n2, the first power supply terminal VGH can be disconnected from the fourth node n4, and the second power supply terminal VGL can be disconnected from the output terminal Gout. Based on this, the first capacitor C1 can continue to adjust the potential of the fourth sub-node n1-2 to maintain a high potential based on the high potential of the third node n3 through coupling. Meanwhile, the second capacitor C2 can adjust the potential of the fourth node n4 to a low potential based on the low potential of the second clock signal provided by the second clock terminal CK2 through coupling.

[0247] That is, in stage B, the potential of the fourth node n4 can be pulled down to a low potential by the second capacitor C2. This allows the sixth transistor T6 to turn on. Correspondingly, the second power supply terminal VGL can be controlled to conduct with the second node n2. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the second node n2 via the turned-on sixth transistor T6.

[0248] That is, in stage B, the potential of the second node n2 can be pulled down to a low potential by the second power supply terminal VGL through the sixth transistor T6. This allows the tenth transistor T10 to turn on. Correspondingly, the fourth clock terminal CK4 and the output terminal Gout can be controlled to conduct. Furthermore, the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the output terminal Gout. Since the potential of the fourth clock signal is high in stage B, it can be known that the fourth clock terminal CK4 can pull up the potential of the scan signal output from the output terminal Gout to a high potential through the tenth transistor T10. In other words, in stage B, the potential of the scan signal output from the shift register unit through the output terminal Gout is high.

[0249] Understandably, during phase B, the high potential of the scan signal output from the output terminal Gout will remain for a period of time until the potential of the fourth clock signal provided by the fourth clock terminal CK4 changes from high to low. Since the potential of the second node n2 is still low when the potential of the fourth clock signal changes to low, it can be known that at the instant the potential of the fourth clock signal changes to low, the potential of the second node n2 will be further pulled down through the coupling effect of the third capacitor C3. This ensures that the tenth transistor T10 can be fully turned on, allowing the low-potential fourth clock signal to be reliably output to the output terminal Gout through the fully turned-on tenth transistor T10. In other words, the potential of the scan signal output from the shift register unit through the output terminal Gout can be pulled down to a low level again.

[0250] In stage C: the potential of the input signal provided by the input terminal IN (e.g., STV) and the potential of the fourth clock signal provided by the fourth clock terminal CK4 (i.e., GCK) can both be low, the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CB) can be high, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can jump from high to low, and the potential of the third clock signal provided by the third clock terminal CK3 (i.e., GCB) can jump from low to high. This allows both the first transistor T1 and the eighth transistor T8 to be turned on. Furthermore, since the potential of the second power supply signal provided by the second power supply terminal VGL is low, the thirteenth transistor T13 can be turned on. Correspondingly, the input terminal IN can be controlled to conduct with the third child node n1-1 in the first node n1, the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to conduct, and the first power supply terminal VGH can be controlled to conduct with the third node n3. Furthermore, the low-potential input signal provided by the input terminal IN can be transmitted to the third sub-node n1-1 via the activated eighth transistor T8, and then to the fourth sub-node n1-2 via the activated thirteenth transistor T13. The high-potential first power signal provided by the first power terminal VGH can be transmitted to the third node n3 via the activated first transistor T1.

[0251] That is, in this stage C, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be low, and the potential of the third node n3 can be controlled to be high. This allows the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 to all be turned on. Correspondingly, the third clock terminal CK3 can be turned on with the third node n3, the first power supply terminal VGH can be turned on with the second node n2, the first power supply terminal VGH can be turned on with the fourth node n4, and the second power supply terminal VGL can be turned on with the output terminal Gout. Furthermore, the high-potential third clock signal provided by the third clock terminal CK3 can be transmitted to the third node n3 via the turned-on second transistor T2; the high-potential first power supply signal provided by the first power supply terminal VGH can be transmitted to the second node n2 via the turned-on fourth transistor T4, and then to the fourth node n4 via the turned-on fifth transistor T5; and the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout via the turned-on ninth transistor T9.

[0252] That is, in stage C, a low-level scan signal can be output through the output terminal Gout, and the potentials of the second node n2 and the fourth node n4 can be pulled up to high levels by the fourth transistor T4 and the fifth transistor T5, respectively. This allows the sixth transistor T6 and the tenth transistor T10 to be turned off. Furthermore, the second power supply terminal VGL can be disconnected from the second node n2, and the fourth clock terminal CK4 can be disconnected from the output terminal Gout. Since the potential of the scan signal output through the output terminal Gout was already pulled down to a low level before the end of the previous stage (i.e., stage B) of stage C, it can be known that the potential of the scan signal output through the output terminal Gout can remain low in stage C. Also, since the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 are both low and in a floating state, and the second transistor T2 is turned on, it can be known that the transition of the third clock signal provided by the third clock terminal CK3 from high to low level can be achieved by pulling down the potential of the third node n3 through the second transistor T2. The potential jump of the third node n3 can further pull down the potential of the fourth child node n1-2 through the coupling effect of the first capacitor C1. This pull-down of the fourth child node n1-2's potential can further turn on the second transistor T2, thereby pulling the potential of the fourth child node n1-2 down to an even lower potential. Ultimately, the potential of the fourth child node n1-2 can be maintained at -2VGL0, ensuring that the ninth transistor T9 can be fully turned on, thus allowing the low-potential second power supply signal provided by the second power supply terminal VGL to be reliably output to the output terminal Gout through the fully turned-on ninth transistor T9. That is, in this stage C, the potential of the scan signal output by the shift register unit through the output terminal Gout can reach VGL0. Here, VGL0 can refer to the potential of the second power supply signal provided by the second power supply terminal VGL.

[0253] This will not be elaborated further. After stage C, each time the potential of the third clock signal provided by the third clock terminal CK3 jumps from a high potential to a low potential, the potential of the fourth sub-node n1-2 will be pulled down under the coupling effect of the first capacitor C1, so that the ninth transistor T9 can be fully turned on, and thus the potential of the scan signal output through the output terminal Gout can be pulled down to VGL0, until the potential of the input signal provided by the input terminal IN jumps from a low potential to a high potential again.

[0254] It is understandable that in Figure 19, stage B is the working stage described above, while stages A and C are the non-working stages described above. Furthermore, as described above, the structure shown in Figure 14 separates the working clock and the load clock. Thus, referring to Figure 19, it can be seen that when all transistors in the shift register unit are PMOS devices, the shift register unit can output a high-level pulse width signal shorter than the clock cycle. Of course, if all transistors in the shift register unit are NMOS devices, the shift register unit can also output a low-level pulse width signal shorter than the clock cycle. In addition, Figure 19 schematically shows the scan signals output by three cascaded shift register units through their respective output terminals Gout. For distinction, the output terminals Gout are labeled Gout-1, Gout-2, and Gout-3, respectively.

[0255] It is also understandable that, since the only difference between the structure shown in Figure 13 and the structure shown in Figure 14 is that the first target terminal V1 and the second clock terminal CK2 are shared, the timing diagram of the structure shown in Figure 13 can be referred to the timing diagram of the structure shown in Figure 14, and will not be repeated here.

[0256] Secondly, taking the shift register unit shown in Figure 15 as an example, and assuming that all transistors in the shift register unit are P-type transistors and the first potential is lower than the second potential, the working principle of the shift register unit with the structure shown in Figure 15 is explained as follows, in conjunction with the signal timing diagram shown in Figure 20:

[0257] In stage A: the input signal provided by the input terminal IN (e.g., STV) can be at a high potential, the first clock signal provided by the first clock terminal CK1 can be at a low potential, and the second clock signal provided by the second clock terminal CK2 can first be at a high potential and then jump to a low potential. Since the third clock terminal CK3 is shared with the second clock terminal CK2, and the fourth clock terminal CK4 is shared with the first clock terminal CK1, it can be known that in stage A, the potential of the third clock signal provided by the third clock terminal CK3 is the same as the potential of the second clock signal, and the potential of the fourth clock signal provided by the fourth clock terminal CK4 is the same as the potential of the first clock signal. Thus, before the potential of the second clock signal jumps to a low potential, the eighth transistor T8 can be turned on, and the seventh transistor T7 can be turned off. Furthermore, since the potential of the second power supply signal provided by the second power supply terminal VGL is low, the thirteenth transistor T13 can be turned on. Correspondingly, the input terminal IN can be controlled to conduct with the third child node n1-1 in the first node n1, and the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to conduct. Furthermore, the high-potential input signal provided by the input terminal IN can be transmitted first through the activated eighth transistor T8 to the third sub-node n1-1, and then through the activated thirteenth transistor T13 to the fourth sub-node n1-2, so as to charge the first capacitor C1.

[0258] That is, in stage A, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be high. This allows the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 to be turned off. Correspondingly, the third clock terminal CK3 can be disconnected from the third node n3, the first power supply terminal VGH can be disconnected from the second node n2, the first power supply terminal VGH can be disconnected from the fourth node n4, and the second power supply terminal VGL can be disconnected from the output terminal Gout.

[0259] As can be understood, as illustrated in the example in Figure 19, since the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 are both low in the previous stage of stage A, the potential of the second node n2 can be pulled up to a high potential. Therefore, in stage A, under the action of the third capacitor C3, the potential of the second node n2 can continue to remain at the high potential of the previous stage. This allows both the first transistor T1 and the tenth transistor T10 to be turned off. Correspondingly, the first power supply terminal VGH can be disconnected from the third node n3, and the fourth clock terminal CK4 can be disconnected from the output terminal Gout. Furthermore, in stage A, the potential of the scan signal output through the output terminal Gout can remain at the potential of the previous stage. Since the potential of the fourth child node n1-2 is low in the previous stage of stage A, the ninth transistor T9 can be turned on. Correspondingly, the second power supply terminal VGL can be turned on and the output terminal Gout can be turned on. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout via the turned-on ninth transistor T9. That is, in the stage preceding stage A, the potential of the scan signal output through the output terminal Gout is low. Correspondingly, in stage A, the potential of the scan signal output by the shift register unit through the output terminal Gout can be maintained at a low potential. Moreover, since both the ninth transistor T9 and the tenth transistor T10 are turned off in stage A, the output terminal Gout can also remain in a floating state.

[0260] Furthermore, since the gate of the sixth transistor T6 (i.e., the fourth node n4) is in a floating state during stage A, after the potential of the second clock signal provided by the second clock terminal CK2 changes from high to low, the potential of the fourth node n4 can be pulled down to a low level under the coupling effect of the second capacitor C2, thus turning on the sixth transistor T6. Correspondingly, the second power supply terminal VGL can be controlled to conduct with the second node n2. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the second node n2 via the turned-on sixth transistor T6. That is, during stage A, when the potential of the second clock signal provided by the second clock terminal CK2 is high, the potential of the second node n2 can remain at the high level of the previous stage, causing the tenth transistor T10 to turn off. And after the potential of the second clock signal provided by the second clock terminal CK2 changes from high to low, the potential of the second node n2 can be controlled to change from high to low, causing both the first transistor T1 and the tenth transistor T10 to turn on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the third node n3, and the fourth clock terminal CK4 can be controlled to conduct with the output terminal Gout. Furthermore, the high-potential first power supply signal provided by the first power supply terminal VGH can be transmitted to the third node n3 via the activated first transistor T1, and the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the output terminal Gout via the activated tenth transistor T10. Since the potential of the fourth clock signal provided by the fourth clock terminal CK4 is still low in stage A, it can be known that the potential of the scan signal output by the shift register unit via the output terminal Gout can still be low in stage A.

[0261] In stage B: the potential of the input signal provided by the input terminal IN can jump from high to low, the potential of the first clock signal provided by the first clock terminal CK1 can jump from low to high, and the potential of the second clock signal provided by the second clock terminal CK2 can first be low and then jump from low to high. Furthermore, as described above, since the third clock terminal CK3 is shared with the second clock terminal CK2, and the fourth clock terminal CK4 is shared with the first clock terminal CK1, it can be known that in stage B, the potential of the third clock signal provided by the third clock terminal CK3 is also the potential of the second clock signal, and the potential of the fourth clock signal provided by the fourth clock terminal CK4 is also the potential of the first clock signal. Thus, before the potential of the second clock signal jumps to high, the eighth transistor T8 can be turned off, and the sixth transistor T6 and the seventh transistor T7 can both be turned on. Correspondingly, the input terminal IN can be disconnected from the third child node n1-1 in the first node n1, the first power supply terminal VGH can be turned on with the fourth transistor T4, and the second power supply terminal VGL can be turned on with the second node n2. Therefore, the low-potential second power signal provided by the second power supply terminal VGL can continue to be transmitted to the second node n2 via the turned-on sixth transistor T6.

[0262] That is, in stage B, the potential of the second node n2 can be controlled to remain low, and the high-potential first power signal provided by the first power supply terminal VGH can be transmitted to the fourth transistor T4 via the turned-on seventh transistor T7. This further allows the first transistor T1 to remain on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the third node n3. Furthermore, the high-potential first power signal provided by the first power supply terminal VGH can be transmitted to the third node n3. And, since the third child node n1-1 and the fourth child node n1-2 in the first node n1, as well as the third node n3, have no discharge path, the potentials of the third child node n1-1, the fourth child node n1-2, and the third node n3 can all be maintained at the high potential of the previous stage (i.e., stage A). Thus, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 can all remain off. Correspondingly, in the same stage A, it is possible to control the third clock terminal CK3 to disconnect from the third node n3, control the first power supply terminal VGH to disconnect from the second node n2, control the first power supply terminal VGH to disconnect from the fourth node n4, and control the second power supply terminal VGL to disconnect from the output terminal Gout.

[0263] Based on this, before the potential of the second clock signal provided by the second clock terminal CK2 jumps to a high potential, the potential of the second node n2 is low, so the tenth transistor T10 can remain on. Correspondingly, the fourth clock terminal CK4 and the output terminal Gout can remain on. Furthermore, the fourth clock signal provided by the fourth clock terminal CK4 can continue to be transmitted to the output terminal Gout. Since the potential of the fourth clock signal is high in stage B, it can be known that the potential of the scan signal output by the shift register unit through the output terminal Gout can be high in stage B. After the potential of the second clock signal jumps to a high potential, the sixth transistor T6 and the seventh transistor T7 can both be turned off. Moreover, under the action of the third capacitor C3, the potential of the second node n2 can remain low. Thus, the tenth transistor T10 can remain on, that is, the fourth clock terminal CK4 and the output terminal Gout can remain on, thereby allowing the high-potential fourth clock signal to continue to be output through the output terminal Gout.

[0264] In stage C: the input signal provided by input terminal IN can remain at a low level, the first clock signal provided by first clock terminal CK1 can transition from a high level to a low level, and the second clock signal provided by second clock terminal CK2 can first be at a high level and then transition from a high level to a low level. Furthermore, as described above, since third clock terminal CK3 is shared with second clock terminal CK2, and fourth clock terminal CK4 is shared with first clock terminal CK1, it can be known that in stage C, the third clock signal provided by third clock terminal CK3 is also at the level of the second clock signal, and the fourth clock signal provided by fourth clock terminal CK4 is also at the level of the first clock signal. Thus, before the second clock signal transitions to a low level, both sixth transistor T6 and seventh transistor T7 can be turned off, and eighth transistor T8 can be turned on. In addition, since the second power supply signal provided by second power supply terminal VGL is at a low level, thirteenth transistor T13 can be turned on. Correspondingly, the input terminal IN can be controlled to conduct with the third child node n1-1 in the first node n1, and the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to conduct. Furthermore, the low-potential input signal provided by the input terminal IN can be transmitted first to the third child node n1-1 via the activated eighth transistor T8, and then to the fourth child node n1-2 via the activated thirteenth transistor T13.

[0265] That is, in stage C, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be low. This allows the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 to all be turned on. Correspondingly, the third clock terminal CK3 can be controlled to conduct with the third node n3, the first power supply terminal VGH can be controlled to conduct with the fourth node n4, and the second power supply terminal VGL can be controlled to conduct with the output terminal Gout. Since the seventh transistor T7 is turned off before the second clock signal's potential jumps to low, even if the fourth transistor T4 is turned on, the first power supply terminal VGH can be controlled to disconnect from the second stage n2. Furthermore, the high-potential third clock signal provided by the third clock terminal CK3 can be transmitted to the third node n3 via the turned-on second transistor T2, the high-potential first power supply signal provided by the first power supply terminal VGH can be transmitted to the fourth node n4 via the turned-on fifth transistor T5, and the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout via the turned-on ninth transistor T9.

[0266] That is, in stage C, a low-level scan signal can be output through the output terminal Gout, and the potential of the fourth node n4 can be pulled up to a high level by the fifth transistor T5. This allows the sixth transistor T6 to be turned off. Furthermore, since the seventh transistor T7 is turned off before the second clock signal's potential jumps to a low level, the potential of the second node n2 can remain at the low level of the previous stage (i.e., stage B) of stage C. This allows the first transistor T1 and the tenth transistor T10 to remain on. Correspondingly, the first power supply terminal VGH can be controlled to remain connected to the third node n3, and the fourth clock terminal CK4 can be controlled to remain connected to the output terminal Gout. Furthermore, the high-level first power supply signal provided by the first power supply terminal VGH can continue to be transmitted to the third node n3 through the on-screen first transistor T1, and the fourth clock signal provided by the fourth clock terminal CK4 can continue to be transmitted to the output terminal Gout through the on-screen tenth transistor T10. Furthermore, since the potential of the fourth clock signal has already transitioned from high to low, the shift register unit can continue to output the low-level fourth clock signal through the output terminal Gout. At the instant the fourth clock signal's potential changes, the potential of the second node n2 is further pulled low through the coupling effect of the third capacitor C3, ensuring that the tenth transistor T10 can be fully turned on. This allows the low-level fourth clock signal to be reliably transmitted to the output terminal Gout through the fully turned-on tenth transistor T10. In other words, the shift register unit can reliably output the low-level scan signal through the output terminal Gout. Furthermore, this eliminates the step voltage when the signal output through the output terminal Gout transitions from high to low, thus eliminating the falling edge of the signal output through the output terminal Gout, ensuring a stepless output signal and good output stability.

[0267] After the second clock signal's potential transitions to a low level, the seventh transistor T7 can be turned on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the second node n2. Furthermore, the high-potential first power supply signal provided by the first power supply terminal VGH can be transmitted sequentially through the turned-on seventh transistor T7 and fourth transistor T4 to the second node n2, thus controlling the potential of the second node n2 to be high. This allows both the tenth transistor T10 and the first transistor T1 to be turned off. Correspondingly, the first power supply terminal VGH can be disconnected from the third node n3, and the fourth clock terminal CK4 can be disconnected from the output terminal Gout. Since the second transistor T2 is turned on at this time, the potential transition of the second clock signal can pull the potential of the fourth sub-node n1-2 down even further through the coupling effect of the first capacitor C1, ensuring that the ninth transistor T9 can be fully turned on. This can be illustrated in the example shown in Figure 19. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be continuously transmitted to the output terminal Gout through the activated ninth transistor T9, pulling down the potential of the scan signal output through the output terminal Gout to an even lower potential. That is, in this stage C, the shift register unit can output a low-potential scan signal through the output terminal Gout.

[0268] This will not be elaborated further. After stage C, each time the potential of the second clock signal provided by the second clock terminal CK2 jumps from a high potential to a low potential, the potential of the fourth sub-node n1-2 will be pulled down under the coupling effect of the first capacitor C1, so that the ninth transistor T9 is fully turned on, and thus the potential of the scan signal output through the output terminal Gout can be pulled down to VGL0, until the potential of the input signal provided by the input terminal IN jumps from a low potential to a high potential again.

[0269] It is understandable that in Figure 20, stage B is the working stage described above, while stages A and C are the non-working stages described above. Furthermore, as can be seen from the previous description, the structure shown in Figure 15 does not separate the working clock and the load clock; instead, it sets adjacent clock signals to have overlapping voltage levels. This allows for flexible setting of the clock signals to output a scan signal with the required pulse width. In addition, Figure 20 schematically shows the scan signals output by two cascaded shift register units through their respective output terminals Gout. For distinction, the output terminals Gout are labeled Gout-1 and Gout-2, respectively.

[0270] Furthermore, taking the shift register unit shown in Figure 16 as an example, and assuming that all transistors in the shift register unit are P-type transistors, and that the first potential is lower than the second potential, the working principle of the shift register unit with the structure shown in Figure 16 is explained as follows, in conjunction with the signal timing diagram shown in Figure 21:

[0271] In stage A: the input signal provided by the input terminal IN (e.g., STV) is at a high potential, the first clock signal provided by the first clock terminal CK1 can be at a low potential, the third clock signal provided by the third clock terminal CK3 can be at a high potential, and the fifth clock signal provided by the fifth clock terminal CK5 is initially at a high potential and then transitions to a low potential. Since the second clock terminal CK2 shares the same potential as the third clock terminal CK3, and the fourth clock terminal CK4 shares the same potential as the first clock terminal CK1, it can be known that in stage A, the potential of the second clock signal provided by the second clock terminal CK2 is the same as the potential of the third clock signal, and the potential of the fourth clock signal provided by the fourth clock terminal CK4 is the same as the potential of the first clock signal. Thus, before the potential of the fifth clock signal transitions to a low potential, the eighth transistor T8 can be turned on. After the potential of the fifth clock signal transitions to a low potential, the seventh transistor T7 can be turned on. Furthermore, since the potential of the second power supply signal provided by the second power supply terminal VGL is low, the thirteenth transistor T13 can be turned on. Correspondingly, the input terminal IN can be controlled to conduct with the third child node n1-1 in the first node n1, and the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to conduct. Furthermore, the high-potential input signal provided by the input terminal IN can be transmitted sequentially through the activated eighth transistor T8 and seventh transistor T7 to the third child node n1-1, and then through the activated thirteenth transistor T13 to the fourth child node n1-2, thereby charging the first capacitor C1.

[0272] That is, in stage A, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be high. This turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9. Correspondingly, the third clock terminal CK3 can be disconnected from the third node n3, the first power supply terminal VGH can be disconnected from the second node n2, the first power supply terminal VGH can be disconnected from the fourth node n4, and the second power supply terminal VGL can be disconnected from the output terminal Gout. Furthermore, in stage A, because the potential of the second clock signal is high, the sixth transistor T6 can be turned off. Correspondingly, the second power supply terminal VGL can be disconnected from the second node n2.

[0273] As can be understood, as illustrated in the example in Figure 19, since the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 are both low in the previous stage of stage A, the potential of the second node n2 can be pulled up to a high potential. Therefore, in stage A, under the action of the third capacitor C3, the potential of the second node n2 can continue to remain at the high potential of the previous stage. This allows both the first transistor T1 and the tenth transistor T10 to be turned off. Correspondingly, the first power supply terminal VGH can be disconnected from the third node n3, and the fourth clock terminal CK4 can be disconnected from the output terminal Gout. Furthermore, in stage A, the potential of the scan signal output through the output terminal Gout can remain at the potential of the previous stage. Since the potential of the fourth child node n1-2 is low in the previous stage of stage A, the ninth transistor T9 can be turned on. Correspondingly, the second power supply terminal VGL can be turned on and the output terminal Gout can be turned on. Therefore, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout via the activated ninth transistor T9. That is, in the stage preceding stage A, the potential of the scan signal output through the output terminal Gout is low. Correspondingly, in stage A, the potential of the scan signal output by the shift register unit through the output terminal Gout can be maintained at a low potential.

[0274] In stage B: the input signal voltage provided by input terminal IN can jump from high to low; the first clock signal voltage provided by first clock terminal CK1 can be high; the third clock signal voltage provided by third clock terminal CK3 can first jump from high to low and then from low to high; and the fifth clock signal voltage provided by fifth clock terminal CK5 is first low and then jumps from low to high. Furthermore, in the same stage A, since second clock terminal CK2 and third clock terminal CK3 are shared, and fourth clock terminal CK4 is shared by first clock terminal CK1, it can be known that in stage B, the voltage of the second clock signal provided by second clock terminal CK2 is also the voltage of the third clock signal, and the voltage of the fourth clock signal provided by fourth clock terminal CK4 is also the voltage of the first clock signal. This allows the eighth transistor T8 to be turned off. Correspondingly, the input terminal IN can be disconnected from the third child node n1-1 in the first node n1. At this time, since neither the third child node n1-1 nor the fourth child node n1-2 in the first node n1 has a discharge path, the potentials of both the third child node n1-1 and the fourth child node n1-2 can be maintained at the high potential of the previous stage (i.e., stage A). This allows the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 to remain off. Correspondingly, in the same stage A, the third clock terminal CK3 can be disconnected from the third node n3, the first power supply terminal VGH can be disconnected from the second node n2, the first power supply terminal VGH can be disconnected from the fourth node n4, and the second power supply terminal VGL can be disconnected from the output terminal Gout.

[0275] Based on this, before the potential of the second clock signal provided by the second clock terminal CK2 jumps from high to low, the potential of the second node n2 can remain at the high potential of the previous stage (i.e., stage A), thus allowing the shift register unit to continue outputting a low-potential scan signal via the output terminal Gout. When the second clock signal provided by the second clock terminal CK2 jumps from high to low, because the gate of the sixth transistor T6 (i.e., the fourth node n4) is in a floating state, the potential of the fourth node n4 can be pulled down to a low potential under the coupling effect of the second capacitor C2, allowing the sixth transistor T6 to turn on. Correspondingly, the second power supply terminal VGL can be controlled to conduct with the second node n2. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be transmitted to the second node n2 via the turned-on sixth transistor T6, that is, the potential of the second node n2 can be controlled to become low. In this way, both the first transistor T1 and the tenth transistor T10 can be turned on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the third node n3, and the fourth clock terminal CK4 can be controlled to conduct with the output terminal Gout. Furthermore, the high-potential first power supply signal provided by the first power supply terminal VGH can be transmitted to the third node n3 via the activated first transistor T1, and the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to the output terminal Gout via the activated tenth transistor T10. Since the potential of the fourth clock signal provided by the fourth clock terminal CK4 is high in stage B, it can be known that the potential of the scan signal output by the shift register unit via the output terminal Gout can be high in stage B. After the potential transitions of the second and fifth clock signals, the sixth and seventh transistors can both be turned off. Thus, the potential of the second node n2 can remain low. Furthermore, the tenth transistor T10 can remain on, that is, the fourth clock terminal CK4 and the output terminal Gout can be controlled to remain conducting, thereby allowing the high-potential fourth clock signal to continue to be output via the output terminal Gout.

[0276] In stage C: the input signal provided by input terminal IN can remain at a low level, the first clock signal provided by first clock terminal CK1 can be at a low level, the third clock signal provided by third clock terminal CK3 can be at a high level, and the fifth clock signal provided by fifth clock terminal CK5 is initially at a high level and then transitions to a low level. Furthermore, in the same stage A, since second clock terminal CK2 and third clock terminal CK3 are shared, and fourth clock terminal CK4 and first clock terminal CK1 are shared, it can be known that in stage C, the second clock signal provided by second clock terminal CK2 is also at the level of the third clock signal, and the fourth clock signal provided by fourth clock terminal CK4 is also at the level of the first clock signal. Thus, the eighth transistor T8 can be turned on, and the seventh transistor T7 can be turned off before the fifth clock signal transitions to a low level. Correspondingly, the input terminal IN can be disconnected from the third child node n1-1 in the first node n1, thereby keeping the potential of the third child node n1-1 at the high potential of the previous stage (i.e., stage B), and thus keeping the potential of the second node n2 at the low potential of the previous stage. In this way, the tenth transistor T10 can remain on. Furthermore, since the fourth clock signal has jumped from the high potential of the previous stage to the low potential, the potential of the second node n2 can be pulled down to an even lower potential through the coupling effect of the third capacitor C3, ensuring that the tenth transistor T10 can be fully turned on. This allows the low-potential fourth clock signal to be reliably transmitted to the output terminal Gout via the fully turned-on tenth transistor T10. That is, the shift register unit can reliably output a low-potential scan signal via the output terminal Gout.

[0277] After the fifth clock signal's potential transitions to a low level, the seventh transistor T7 can be turned on. Furthermore, since the second power supply signal provided by the second power supply terminal VGL is at a low level, the thirteenth transistor T13 can be turned on. Correspondingly, the first power supply terminal VGH can be controlled to conduct with the third child node n1-1 in the first node n1, and the third child node n1-1 and the fourth child node n1-2 in the first node n1 can also be controlled to conduct. Furthermore, the low-level input signal provided by the input terminal IN can be transmitted sequentially through the turned-on eighth transistor T8 and seventh transistor T7 to the third child node n1-1, and then through the turned-on thirteenth transistor T13 to the fourth child node n1-2. That is, the potentials of the third child node n1-1 and the fourth child node n1-2 in the first node n1 can be controlled to be low. Thus, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 can all be turned on. Correspondingly, the third clock terminal CK3 can be controlled to conduct with the third node n3, the first power supply terminal VGH can be controlled to conduct with the second node n2, the first power supply terminal VGH can be controlled to conduct with the fourth node n4, and the second power supply terminal VGL can be controlled to conduct with the output terminal Gout. Furthermore, the high-level third clock signal provided by the third clock terminal CK3 can be transmitted to the third node n3 via the activated second transistor T2, the high-level first power supply signal provided by the first power supply terminal VGH can be transmitted to the second node n2 via the activated fourth transistor T4, and to the fourth node n4 via the activated fifth transistor T5, and the low-level second power supply signal provided by the second power supply terminal VGL can be transmitted to the output terminal Gout via the activated ninth transistor T9. That is, the potentials of the second node n2 and the fourth node n4 can be controlled to be high. Thus, the first transistor T1, the sixth transistor T6, and the tenth transistor T10 can all be turned off. In other words, in this stage C, the shift register unit can output a low-level scan signal via the output terminal Gout.

[0278] In the next stage after stage C, because the second transistor T2 is turned on, when the third clock signal transitions from a high to a low potential, the potential of the fourth child node n1-2 in the first node n1 is pulled down even lower through the coupling effect of the first capacitor C1, ensuring that the ninth transistor T9 can be fully turned on. This can be illustrated in the example shown in Figure 19. Furthermore, the low-potential second power supply signal provided by the second power supply terminal VGL can be continuously transmitted to the output terminal Gout through the turned-on ninth transistor T9, pulling down the potential of the scan signal output through the output terminal Gout to an even lower potential. The shift register unit can maintain a low-potential scan signal output through the output terminal Gout.

[0279] This will not be elaborated further. Subsequently, each time the potential of the third clock signal provided by the third clock terminal CK3 jumps from a high potential to a low potential, the potential of the fourth sub-node n1-2 will be pulled down by the coupling effect of the first capacitor C1, causing the ninth transistor T9 to be fully turned on. This, in turn, allows the potential of the scan signal output through the output terminal Gout to be pulled down to VGL0, until the potential of the input signal provided by the input terminal IN jumps from a low potential to a high potential again.

[0280] Finally, it can be understood that the structure shown in Figure 17, compared to the structure shown in Figure 15, only adds a third transistor T3, an eleventh transistor T11, and a twelfth transistor T12, and connects the first terminal of the first transistor T1 to the third child node n1-2 in the first node n1. Therefore, its working principle is the same as that of the structure shown in Figure 15. That is, the signal timing diagram of the structure shown in Figure 7 can be referred to Figure 20, and will not be repeated here. In addition, it should be noted that, based on the addition of the third transistor T3, when the potential of the second clock signal jumps from low to high, the potential of the third node n3 is pulled high, which can turn off the third transistor T3. In this way, it can be ensured that when the potential of the second clock signal jumps from low to high, it is no longer coupled to the fourth child node n1-2 in the first node n1 through the first capacitor C1, thereby ensuring better potential stability of the fourth child node n1-2. Based on the addition of the eleventh transistor T11 and the twelfth transistor T12, as mentioned above, the shift register unit can be reset during power-on and power-off. By connecting the first terminal of the first transistor T1 to the first node n1, the signal transmitted to the first node n1 can be further transmitted to the third node n3 via the turned-on first transistor T1.

[0281] It is also understandable that in Figure 21, stage B is the working stage described above, while stages A and C are the non-working stages described above. Furthermore, as described above, similar to the structure shown in Figure 15, the structure shown in Figure 16 also does not separate the working clock and load clock, but rather sets adjacent clock signals to have overlapping potentials. This allows for flexible setting of the clock signal to output a scan signal with the required pulse width. In addition, Figure 21 also schematically shows the scan signals output by two cascaded shift register units through their respective output terminals Gout. For distinction, the output terminals Gout are labeled Gout-1 and Gout-2 respectively. Furthermore, the first stage shown in Figure 18 corresponds to the stage before stage A, which is the non-working stage. The second stage corresponds to stage B, which is the working stage. Based on the above embodiments, it can be seen that:

[0282] In one embodiment, as shown in FIG19, the operating clock and the load clock can be designed separately, and the clock signals provided by each clock terminal of the separate design can be differentiated. For example, when the potential of the clock signal provided by clock signal line CK is set to low, the potential of the clock signal provided by clock signal line GCB is set to high, and the rising edge of the clock signal provided by clock signal line GCB is set earlier than the falling edge of the clock signal provided by clock signal line CK, and the falling edge of the clock signal provided by clock signal line GCB is set later than the rising edge of the clock signal provided by clock signal line CK. Similarly, when the potential of the clock signal provided by clock signal line CB is set to low, the potential of the clock signal provided by clock signal line GCK is set to high, and the rising edge of the clock signal provided by clock signal line GCK is set earlier than the falling edge of the clock signal provided by clock signal line CB, and the falling edge of the clock signal provided by clock signal line GCK is set later than the rising edge of the clock signal provided by clock signal line CB. Furthermore, the clock signals provided by clock signal lines CK, CB, GCK, and GCB are configured to have the same period, with the clock signals provided by clock signal lines CK and CB being inverted signals, and the clock signals provided by clock signal lines GCK and GCB being inverted signals. In this way, by flexibly setting the load clock potential, the shift register unit can flexibly output signals with pulse widths shorter than the clock period.

[0283] In another embodiment, as shown in Figures 20 and 21, the operating clock and load clock do not need to be designed separately. That is, adjacent clock signals can be configured not to be completely inverted, but rather their high or low potentials can partially overlap. This ensures that the output scan signal is stepless and that the pulse width of the scan signal is adjustable within a certain range.

[0284] It is understood that since the driving method of the shift register unit can have the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the driving method of the shift register unit will not be described again here for the sake of brevity.

[0285] This application also provides a row scanning circuit. The row scanning circuit includes multiple cascaded shift register units as described in the above embodiments, namely, GOA units, also called GOA. For example, based on the structures shown in Figures 14 to 17, Figures 22 to 25 respectively show schematic diagrams of different scanning circuits.

[0286] As shown in Figure 22, based on the structure shown in Figure 14, multiple cascaded GOA units can share four clock lines: CK0, CB0, GCK0, and GCB0. Furthermore, the first clock terminal CK1 (i.e., CK) of each GOA unit can be connected to clock line CK0, the second clock terminal CK2 (i.e., CB) can be connected to clock line CB0, the third clock terminal CK3 (i.e., GCB) can be connected to clock line GCB0, and the fourth clock terminal CK4 (i.e., GCK) can be connected to clock line GCK0.

[0287] Referring to Figures 23 and 25, based on the structures shown in Figures 15 and 17, multiple cascaded GOA units can share four clock lines: CK10, CK20, CK30, and CK40. Furthermore, the first clock terminal CK1 and the fourth clock terminal CK4 (labeled CLK1) shared by the first GOA unit can be connected to clock line CK10, and the shared second clock terminal CK2, third clock terminal CK3, and fifth clock terminal CK5 (labeled CLK2) can be connected to clock line CK20. Similarly, the second GOA unit cascaded with the first GOA unit can share the first clock terminal CK1 and the fourth clock terminal CK4 (labeled CLK1) to clock line CK20, and the shared second clock terminal CK2, third clock terminal CK3, and fifth clock terminal CK5 (labeled CLK2) can be connected to clock line CK30. The first clock terminal CK1 and the fourth clock terminal CK4 (identified as CLK1) shared by the third GOA unit cascaded with the second GOA unit can be connected to clock line CK30, and the shared second clock terminal CK2, third clock terminal CK3, and fifth clock terminal CK5 (identified as CLK2) can be connected to clock line CK40. These connections are alternated.

[0288] As shown in Figure 24, based on the structure shown in Figure 16, multiple cascaded GOA units can share four clock lines: CK10, CK20, CK30, and CK40. Furthermore, the first GOA unit's shared first clock terminal CK1 and fourth clock terminal CK4 (labeled CLK1) can be connected to clock line CK10, its shared second clock terminal CK2 and third clock terminal CK3 (labeled CLK2) can be connected to clock line CK20, and its fifth clock terminal CK5 (labeled CLK3) can be connected to clock line CK30. Similarly, the second GOA unit cascaded with the first GOA unit shares the first clock terminal CK1 and fourth clock terminal CK4 (labeled CLK1) and can be connected to clock line CK20, its shared second clock terminal CK2 and third clock terminal CK3 (labeled CLK2) can be connected to clock line CK30, and its fifth clock terminal CK5 (labeled CLK3) can be connected to clock line CK40. This connection pattern continues alternately.

[0289] Furthermore, referring to Figure 25, it can be seen that the reset control terminal NCX of each GOA unit can also be connected to the reset control line NCX0. Referring to Figures 22 to 25, it can be seen that the first power supply terminal VGH of each GOA unit can also be connected to the first power supply line VGH0, and the second power supply terminal VGL can also be connected to the second power supply line VGL0. The input terminal IN of each GOA unit can also be connected to the output terminal Gout of the cascaded previous GOA unit. The input terminal IN of the first-stage GOA unit can also be connected to the enable signal terminal STV. Each terminal can receive signals from the connected signal lines.

[0290] It is understood that Figures 22 to 25 schematically illustrate multiple GOA units, GOA-1, GOA-2, GOA-3...GOA-n and GOA-last, respectively. The output Gout of GOA-1 is labeled Gout-1, the output Gout of GOA-2 is labeled Gout-2, the output Gout of GOA-3 is labeled Gout-3, the output Gout of GOA-n is labeled Gout-n, and the output Gout of GOA-last is labeled Gout-last. "Last" refers to the last GOA unit in the cascaded GOA units.

[0291] It is also understood that the multiple GOA units shown in Figures 22 to 25 are all cascaded in pairs of adjacent GOA units. In some other embodiments, odd-numbered GOA units may be cascaded with each other, and even-numbered GOA units may be cascaded with each other; that is, the cascading method is not limited in this application embodiment. Furthermore, the multiple cascaded GOA units shown in Figures 23 to 25 all share 4 clock lines. In some other embodiments, the multiple cascaded GOA units may also share 5 or more clock lines; that is, the number of clock lines connected to the row scan circuit is not limited in this application embodiment.

[0292] It is understandable that since the row scanning circuit can have essentially the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the row scanning circuit will not be described again here for the sake of brevity.

[0293] This application also provides a display device. As shown in FIG26, the display device includes: a display panel 100, and a row scanning circuit 000 as described in the above embodiments.

[0294] The display panel includes multiple pixels (not shown in the figure). The row scanning circuit 000 is connected to the multiple pixels and is used to transmit scanning signals to the multiple pixels to drive the multiple pixels to emit light.

[0295] For example, the row scanning circuit 000 can be connected to multiple rows of pixels through multiple gate lines to provide gate drive signals to the multiple rows of pixels, thereby driving the multiple rows of pixels to emit light.

[0296] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device or an active-matrix organic light-emitting diode (AMOLED) display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0297] It is understood that since the display device can have essentially the same technical effect as the row scanning circuit described in the previous embodiments, the technical effect of the display device will not be described again here for the sake of brevity.

[0298] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0299] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. "Connection" or "coupled" refers to an electrical connection. Similarly, "a" or "one," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. "Comprising" or "including," and similar words mean that the element or object preceding "comprising" or "including" encompasses the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0300] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: A first control circuit is connected to a first clock terminal, an input terminal, and a first node, respectively, and is used to control the connection and disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal. The second control circuit is connected to the first node, the second clock terminal, the first power supply terminal, the first target terminal, and the second node respectively. It is used to control the connection and disconnection between the first power supply terminal and the second node in response to the potential of the first node, the second clock signal provided by the second clock terminal, and the first power supply signal provided by the first power supply terminal. It also controls the connection and disconnection between the first target terminal and the second node. The first target terminal and the second clock terminal share the same second power supply terminal. An adjustment circuit is connected to the first node, the third clock terminal, the control terminal, and the second target terminal, respectively, and is used to adjust the potential of the first node in response to the potential of the first node, the third clock signal provided by the third clock terminal, the control signal provided by the control terminal, and the target signal provided by the second target terminal. The control terminal is shared with or connected to the second node, and the second target terminal is shared with or connected to the first power supply terminal. The output circuit is connected to the first node, the second node, the second power supply terminal, the fourth clock terminal, and the output terminal respectively. It is used to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the first node and the potential of the second node, and to control the connection and disconnection between the fourth clock terminal and the output terminal.

2. The shift register unit according to claim 1, wherein, The regulating circuit includes: The first regulating sub-circuit is connected to the control terminal, the second target terminal and the third node respectively, and is used to control the on / off state of the second target terminal and the third node in response to the control signal; The second regulating sub-circuit is connected to the first node, the third clock terminal, and the third node respectively, and is used to control the on / off state of the third clock terminal and the third node in response to the potential of the first node. The third regulating sub-circuit is connected to the third node and the first node respectively, and is used to regulate the potential of the first node in response to the potential of the third node.

3. The shift register unit according to claim 2, wherein, The first regulating circuit includes: a first transistor; The gate of the first transistor is connected to the control terminal, the first electrode of the first transistor is connected to the second target terminal, and the second electrode of the first transistor is connected to the third node.

4. The shift register unit according to claim 2 or 3, wherein, The second regulating circuit includes: a second transistor; The gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the third clock terminal, and the second terminal of the second transistor is connected to the third node.

5. The shift register unit according to any one of claims 2 to 4, wherein, The third regulating sub-circuit includes: a first capacitor; One end of the first capacitor is connected to the third node, and the other end of the first capacitor is connected to the first node.

6. The shift register unit according to any one of claims 2 to 5, wherein, The third node includes: a first sub-node and a second sub-node; the first adjustment sub-circuit is connected to the first sub-node; the second adjustment sub-circuit is connected to the second sub-node; the third adjustment sub-circuit includes: The first adjustment unit is connected to the first sub-node and the second sub-node respectively, and is used to adjust the potential of the first sub-node in response to the potential of the second sub-node; The second adjustment unit is connected to the first sub-node and the first node respectively, and is used to control the on / off state of the first sub-node and the first node in response to the potential of the first sub-node, so as to adjust the potential of the first node. Furthermore, the control terminal is connected to the second node, and the second target terminal is connected to the first node.

7. The shift register unit according to claim 6, wherein, The first adjustment unit includes: a first capacitor; the second adjustment unit includes: a third transistor; One end of the first capacitor is connected to the first child node, and the other end of the first capacitor is connected to the second child node; The gate and first electrode of the third transistor are both connected to the first child node, and the second electrode of the third transistor is connected to the first node.

8. The shift register unit according to any one of claims 1 to 7, wherein, The second control circuit includes: The first control sub-circuit is connected to the first node, the first power supply terminal and the second node respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the potential of the first node. The second control sub-circuit is connected to the first node, the first power supply terminal, the second clock terminal, and the fourth node respectively. It is used to control the on / off state of the first power supply terminal and the fourth node in response to the potential of the first node, and to adjust the potential of the fourth node in response to the second clock signal. The third control sub-circuit is connected to the fourth node, the first target terminal, and the second node respectively, and is used to control the on / off state of the first target terminal and the second node in response to the potential of the fourth node.

9. The shift register unit according to claim 8, wherein, The first control sub-circuit includes: a fourth transistor; The gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the second node.

10. The shift register unit according to claim 8 or 9, wherein, The second control sub-circuit includes: a fifth transistor and a second capacitor; The gate of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the fourth node. One end of the second capacitor is connected to the second clock terminal, and the other end of the second capacitor is connected to the fourth node.

11. The shift register unit according to any one of claims 8 to 10, wherein, The third control sub-circuit includes: a sixth transistor; The gate of the sixth transistor is connected to the fourth node, the first electrode of the sixth transistor is connected to the first target terminal, and the second electrode of the sixth transistor is connected to the second node.

12. The shift register unit according to any one of claims 8 to 11, wherein, The shift register unit further includes: A third control circuit is connected between the first control sub-circuit and the first power supply terminal, and is connected to the fifth clock terminal, for controlling the on / off state of the first control sub-circuit and the first power supply terminal in response to the fifth clock signal provided by the fifth clock terminal; or, it is connected between the first control circuit and the first node, and is connected to the fifth clock terminal, for controlling the on / off state of the first control circuit and the first node in response to the fifth clock signal. Furthermore, the control terminal is connected to the second node, and the second target terminal shares power with the first power supply terminal.

13. The shift register unit according to claim 12, wherein, The third control circuit includes: a seventh transistor; The gate of the seventh transistor is connected to the fifth clock terminal. When the third control circuit is connected between the first control sub-circuit and the first power supply terminal, the first terminal of the seventh transistor is connected to the first control sub-circuit, and the second terminal of the seventh transistor is connected to the first power supply terminal. When the third control circuit is connected between the first control circuit and the first node, the first terminal of the seventh transistor is connected to the first control circuit, and the second terminal of the seventh transistor is connected to the first node.

14. The shift register unit according to claim 12 or 13, wherein, When the third control circuit is connected between the first control sub-circuit and the first power supply terminal, the fifth clock terminal is shared with the second clock terminal, the third clock terminal is shared with the second clock terminal, and / or the fourth clock terminal is shared with the first clock terminal.

15. The shift register unit according to claim 12 or 13, wherein, When the third control circuit is connected between the first control circuit and the first node, the fifth clock terminal is independent of the second clock terminal, the third clock terminal is shared with the second clock terminal, and / or the fourth clock terminal is shared with the first clock terminal.

16. The shift register unit according to any one of claims 1 to 15, wherein, The first control circuit includes: an eighth transistor; The gate of the eighth transistor is connected to the first clock terminal, the first terminal of the eighth transistor is connected to the input terminal, and the second terminal of the eighth transistor is connected to the first node.

17. The shift register unit according to any one of claims 1 to 16, wherein, The output circuit includes: The first output sub-circuit is connected to the first node, the second power supply terminal and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the first node. The second output sub-circuit is connected to the second node, the fourth clock terminal, and the output terminal respectively. It is used to control the on / off state of the fourth clock terminal and the output terminal in response to the potential of the second node, and also to adjust the potential of the second node based on the fourth clock signal provided by the fourth clock terminal.

18. The shift register unit according to claim 17, wherein, The first output sub-circuit includes: a ninth transistor; The gate of the ninth transistor is connected to the first node, the first terminal of the ninth transistor is connected to the second power supply terminal, and the second terminal of the ninth transistor is connected to the output terminal.

19. The shift register unit according to claim 17 or 18, wherein, The second output sub-circuit includes: a tenth transistor and a third capacitor; The gate of the tenth transistor is connected to the second node, the first terminal of the tenth transistor is connected to the fourth clock terminal, and the second terminal of the tenth transistor is connected to the output terminal. One end of the third capacitor is connected to the fourth clock terminal, and the other end of the third capacitor is connected to the second node.

20. The shift register unit according to any one of claims 1 to 19, wherein, The shift register unit further includes: The first reset circuit is connected to the reset control terminal, the first power supply terminal, and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node in response to the reset control signal provided by the reset control terminal. And / or, a second reset circuit, connected to the reset control terminal, the second power supply terminal, and the second node respectively, is used to control the connection and disconnection of the second power supply terminal and the second node in response to the reset control signal.

21. The shift register unit according to claim 20, wherein, The first reset circuit includes: an eleventh transistor; The gate of the eleventh transistor is connected to the reset control terminal, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the first node.

22. The shift register unit according to claim 20 or 21, wherein, The second reset circuit includes: a twelfth transistor; The gate of the twelfth transistor is connected to the reset control terminal, the first terminal of the twelfth transistor is connected to the second power supply terminal, and the second terminal of the twelfth transistor is connected to the second node.

23. The shift register unit according to any one of claims 1 to 22, wherein, The first node includes: a third sub-node and a fourth sub-node; both the first control circuit and the second control circuit are connected to the third sub-node; both the adjustment circuit and the output circuit are connected to the fourth sub-node; the second target terminal is connected to the third sub-node; the shift register unit further includes: An isolation circuit is connected to the second power supply terminal, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the second power supply signal provided by the second power supply terminal.

24. The shift register unit according to claim 23, wherein, The isolation circuit includes: a thirteenth transistor; The gate of the thirteenth transistor is connected to the second power supply terminal, the first terminal of the thirteenth transistor is connected to the third sub-node, and the second terminal of the thirteenth transistor is connected to the fourth sub-node.

25. The shift register unit according to any one of claims 1 to 24, wherein, The first clock terminal and the second clock terminal form one group of clock terminals, and the third clock terminal and the fourth clock terminal form another group of clock terminals. In each group of clock terminals, the clock signals provided by the two clock terminals are inverse signals to each other. At the same time, the pulse width of the fourth clock signal provided by the fourth clock terminal includes the pulse width of the third clock signal provided by the third clock terminal, and the pulse width of the second clock signal provided by the second clock terminal includes the pulse width of the first clock signal provided by the first clock terminal. Alternatively, the first clock terminal, the second clock terminal, the third clock terminal, and the fourth clock terminal are the same group of clock terminals, and the potentials of the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the fourth clock signal provided by the fourth clock terminal change sequentially, and two adjacent clock signals that change sequentially have overlapping same potentials.

26. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 25; the method comprising: In the first stage, the first control circuit responds to the first clock signal and controls the input terminal to be connected to the first node. The second control circuit responds to the potential of the first node, the second clock signal provided by the second clock terminal, and the first power signal provided by the first power supply terminal and controls the first power supply terminal to be connected to the second node. The adjustment circuit responds to the potential of the first node, the third clock signal provided by the third clock terminal, the control signal provided by the control terminal, and the target signal provided by the second target terminal and adjusts the potential of the first node. The output circuit responds to the potential of the first node and the potential of the second node and controls the second power supply terminal to be connected to the output terminal. In the second stage, the first control circuit responds to the first clock signal and controls the input terminal to disconnect from the first node. The second control circuit responds to the potential of the first node, the second clock signal, and the first power signal and controls the first target terminal to conduct with the second node. The adjustment circuit responds to the potential of the first node, the third clock signal, the control signal, and the target signal and adjusts the potential of the first node. The output circuit responds to the potential of the first node and the potential of the second node and controls the fourth clock terminal to conduct with the output terminal.

27. A row scanning circuit, the row scanning circuit comprising: A cascaded plurality of shift register units as described in any one of claims 1 to 25.

28. A display device, the display device comprising: The display panel, and the row scanning circuit as described in claim 27; The display panel includes multiple pixels; The row scanning circuit is connected to the plurality of pixels and is used to transmit scanning signals to the plurality of pixels to drive the plurality of pixels to emit light.

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