Timing scan circuit for scanning diodes

Abstract

The application discloses a timing scanning circuit for scanning diodes, comprising cathode scanning logic circuits and at least two anode scanning logic circuits; each anode scanning logic circuit is used for configuring a level signal at an anode of a diode and an enable signal for controlling generation of the level signal; the cathode scanning logic circuit is used for configuring a level signal at a cathode of all diodes configured by the anode scanning logic circuits and an enable signal for controlling generation of the level signal, so as to drive part or all of the diodes required to be scanned to light up; wherein the cathodes of all the diodes configured by the anode scanning logic circuits are connected together.

Description

Technical Field

[0001] This application belongs to the technical field of digital logic circuits, and particularly relates to a timing scanning circuit for scanning diodes. Background Technology

[0002] Chinese invention patent application number CN202210756640.X discloses an I / O multiplexing circuit for touch buttons and LED drivers. In multiplexing mode, the I / O multiplexing circuit for touch buttons and LED drivers allows the LED driver unit and the touch button unit to take turns occupying the I / O unit according to the high and low levels of the button timing pins and LED timing pins. Although the multiplexing of I / O units is achieved, timing errors are still prone to occur in the scenario where the touch buttons take turns occupying the I / O unit because there is no enable control for each diode during multiplexing drive. Summary of the Invention

[0003] This application discloses a timing scanning circuit for driving diodes, and the specific technical solution is as follows: A timing scanning circuit for scanning diodes includes a cathode scanning logic circuit, a lighting end indicator circuit, and at least two anode scanning logic circuits. The cathode scanning logic circuit is connected to each anode scanning logic circuit. Each anode scanning logic circuit is used to configure an enable signal generated by a level signal and a control level signal at the anode of a diode. The cathode scanning logic circuit is used to configure an enable signal generated by a level signal and a control level signal at the cathode of all diodes configured by the anode scanning logic circuits, thereby driving some or all of the diodes to be scanned to light up. The cathodes of the diodes configured by all the anode scanning logic circuits are connected together, and the diodes configured by all the anode scanning logic circuits are the diodes to be scanned. Compared with existing technologies, this application drives the diodes at all or some address locations to light up or turn off by setting level signals and enable signals generated at the electrodes by multiple anode scanning logic circuits, and reuses the timing scanning circuit to drive the diodes at unscanned addresses to light up or turn off, thus avoiding errors in lighting timing under different scenarios.

[0004] Specifically, the at least two anode scanning logic circuits include a first anode scanning logic circuit and a second anode scanning logic circuit; the structures of the first anode scanning logic circuit and the second anode scanning logic circuit are identical; the diodes to be scanned currently include the diodes to be configured by the first anode scanning logic circuit and the diodes to be configured by the second anode scanning logic circuit; the cathode scanning logic circuit is used to configure the cathode data signal and cathode enable signal corresponding to the diode to be scanned currently; the first anode scanning logic circuit is used to configure the first anode data signal and first anode enable signal corresponding to the diode to be scanned currently; the second anode scanning logic circuit is used to configure the second anode data signal and second anode enable signal corresponding to the diode to be scanned currently. The anode enable signal; wherein, the level signal at the cathode of the diode configured in the cathode scan logic circuit is the cathode data signal, and the enable signal controlling the generation of the cathode data signal is the cathode enable signal; the level signal at the anode of the diode configured in the first anode scan logic circuit is the first anode data signal, and the enable signal controlling the generation of the first anode data signal is the first anode enable signal; the level signal at the anode of the diode configured in the second anode scan logic circuit is the second anode data signal, and the enable signal controlling the generation of the second anode data signal is the second anode enable signal; wherein, the diodes configured in all the anode scan logic circuits constitute the currently selected diode combination unit; the diode combination unit includes a first unit diode and a second unit diode.

[0005] This application configures the first anode enable signal, the lighting end signal sent to the lighting end indicator circuit, and the rising edge capture signal of the first anode data signal sent to the cathode scanning logic circuit by delaying the first anode data signal and capturing the rising edge signal. At the same time, it configures the first anode data signal and the first anode enable delay target pulse sent to the cathode scanning logic circuit by delaying the first anode enable signal and capturing the rising edge signal. This forms a timing-dependent logic mechanism for the anode data signal, anode enable signal generated in the first anode scanning logic circuit, and the rising edge capture signal and lighting end signal output externally. It considers the accuracy of setting the cathode enable signal and cathode data signal of the diode to be scanned, as well as the accuracy of the anode enable signal and anode data signal of the first unit diode to be scanned. This reduces the overshoot voltage interference caused by the frequent conduction and shutdown of each diode in the same diode combination unit, thereby ensuring the effectiveness of the diode's cathode data signal.

[0006] This application further configures the second anode enable signal, the lighting end signal sent to the lighting end indicator circuit, and the rising edge capture signal of the second anode data signal sent to the cathode scanning logic circuit by delaying the second anode data signal and capturing the rising edge signal. At the same time, it configures the second anode data signal and the second anode enable delay target pulse sent to the cathode scanning logic circuit by delaying the second anode enable signal and capturing the rising edge signal. This forms a timing-dependent logic mechanism for the anode data signal, anode enable signal generated in the second anode scanning logic circuit, and the rising edge capture signal and lighting end signal output externally. It considers the accuracy of setting the cathode enable signal and cathode data signal of the diode to be scanned at the moment, as well as the accuracy of the anode enable signal and anode data signal of the second unit diode to be scanned at the moment. This reduces the overshoot voltage interference caused by the frequent conduction and shutdown of each diode in the same diode combination unit, thereby ensuring the effectiveness of the cathode data signal of the diode. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the module connection of the timing scan circuit for driving diodes disclosed in this application.

[0008] Figure 2 This is a schematic diagram of the connection of the cathode scanning logic circuit disclosed in this application.

[0009] Figure 3 This is a schematic diagram of the connection of the first anode scanning logic circuit disclosed in this application.

[0010] Figure 4 This is a schematic diagram of the connection of the second anode scanning logic circuit disclosed in this application.

[0011] Figure 5 This is a connection diagram of the lighting end indicator circuit disclosed in this application. Detailed Implementation

[0012] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments.

[0013] To avoid errors when switching the diode array to different lighting sequences, this application discloses a timing scanning circuit for scanning diodes. The diodes to be scanned / driven in this application are light-emitting diodes (LEDs). The timing scanning circuit includes a cathode scanning logic circuit and at least two anode scanning logic circuits. Each anode scanning logic circuit is used to configure the enable signal generated by the level signal and control level signal at the anode of a diode, i.e., to configure the anode data signal and anode enable signal. The cathode scanning logic circuit is used to configure the enable signal generated by the level signal and control level signal at the cathode of all diodes configured by the anode scanning logic circuits, so as to drive some or all of the diodes to be scanned to light up. The cathodes of the diodes configured by all anode scanning logic circuits are connected together, and the diodes configured by all anode scanning logic circuits are the diodes to be scanned. The diodes configured by all anode scanning logic circuits form the currently selected diode combination unit. Compared with the prior art, this application uses multiple anode scanning logic circuits to generate level signals and enable signals at the electrodes to drive the diodes at all or part of the address locations to be scanned to light up or turn off, and reuses the timing scanning circuit to drive the diodes at unscanned addresses to light up or turn off, thus avoiding errors in the lighting timing under different scenarios.

[0014] See Figure 1 It is understood that when the at least two anode scanning logic circuits include a first anode scanning logic circuit and a second anode scanning logic circuit, the structures of the first anode scanning logic circuit and the second anode scanning logic circuit are the same; the diodes to be scanned include the diodes to be configured by the first anode scanning logic circuit and the diodes to be configured by the second anode scanning logic circuit; the level signal at the cathode of the diode configured by the cathode scanning logic circuit is the cathode data signal px, and the enable signal controlling the generation of the cathode data signal is the cathode enable signal enx; the level signal at the anode of the diode configured by the first anode scanning logic circuit is the first anode data signal px_1, and the enable signal controlling the generation of the first anode data signal is the first anode enable signal enx_1; the level signal at the anode of the diode configured by the second anode scanning logic circuit is the second anode data signal px_2, and the enable signal controlling the generation of the second anode data signal is the second anode enable signal enx_2.

[0015] Specifically, the timing scanning circuit includes a cathode scanning logic circuit, a first anode scanning logic circuit, a second anode scanning logic circuit, and a lighting end indicator circuit, respectively corresponding to... Figures 2 to 5 The circuit diagram shown is illustrated. (Combined with...) Figure 1It can be seen that the cathode scanning logic circuit is connected to the first anode scanning logic circuit. The cathode scanning logic circuit and the first anode scanning logic circuit establish a signal connection relationship through the first anode enable delay target pulse enx_1_pos_d3. The cathode scanning logic circuit and the first anode scanning logic circuit also establish a signal connection relationship through the rising edge capture signal px_1_pos of the first anode data signal. The cathode scanning logic circuit is also connected to the second anode scanning logic circuit. The cathode scanning logic circuit and the second anode scanning logic circuit establish a signal connection relationship through the second anode enable delay target pulse enx_2_pos_d3. The cathode scanning logic circuit and the second anode scanning logic circuit also establish a signal connection relationship through the rising edge capture signal px_2_pos of the second anode data signal.

[0016] The cathode scanning logic circuit is used to configure the cathode data signal and cathode enable signal corresponding to the diode to be scanned. Specifically, it configures the data signal and enable control signal for the cathodes of the first and second diodes within the same diode combination unit. Schematably, the cathode data signal corresponding to the diode to be scanned is represented as follows: Figure 2 The cathode data signal px in the image, and the cathode enable signal corresponding to the diode to be scanned are represented as follows: Figure 2 The cathode enable signal is enx. When the diode is lit, the cathode data signal px = 0 (i.e., it is at a low level), and the cathode enable signal enx = 0.

[0017] The first anode scanning logic circuit is used to configure the first anode data signal and the first anode enable signal corresponding to the diode to be scanned. Specifically, it configures the data signal and enable control signal for the anode of the first unit diode. Schematically, the first anode data signal corresponding to the diode to be scanned is represented as follows: Figure 3 The first anode data signal px_1 in the current scan is represented by the first anode enable signal corresponding to the diode to be scanned. Figure 3 The first anode enable signal is enx_1. The diode to be scanned currently configured by the first anode scan logic circuit is the first unit diode. When the first unit diode is lit, the first anode data signal px_1 = 1 (i.e., it is at a high level), and the first anode enable signal enx_1 = 0.

[0018] The second anode scanning logic circuit is used to configure the second anode data signal and the second anode enable signal corresponding to the diode to be scanned. Specifically, it configures the data signal and enable control signal for the anode of the second unit diode. Schematically, the second anode data signal corresponding to the diode to be scanned is represented as follows: Figure 4The second anode data signal px_2 in the current scan is represented by the second anode enable signal corresponding to the diode to be scanned. Figure 4 The second anode enable signal is enx_2. The diode to be scanned currently configured by the second anode scan logic circuit is the second unit diode. When the second unit diode is lit, the second anode data signal px_2 = 1 (i.e., it is at a high level), and the second anode enable signal enx_2 = 0.

[0019] The timing scanning circuit can drive two diodes to light up simultaneously, or light up only one diode, or not light up any diode in the same state. The specific lighting method is determined by the cathode data signal, cathode enable signal, anode data signal, and anode enable signal corresponding to the diode to be scanned at the moment.

[0020] It should be noted that the currently selected diode combination unit is composed of diodes configured by all anode scan logic circuits within the timing scan circuit; the diode combination unit includes a first unit diode and a second unit diode. Within the same diode combination unit, the level signal at the cathode of the diode configured by the cathode scan logic circuit is the cathode data signal, and the enable signal controlling the cathode of the diode to generate the cathode data signal (actually inputting the cathode data signal into the cathode of the diode) is the cathode enable signal; the level signal at the anode of the diode configured by the first anode scan logic circuit is the first anode data signal, and the enable signal controlling the anode of the diode to generate the first anode data signal (actually inputting the first anode data signal into the cathode of the diode) is the first anode enable signal; the level signal at the anode of the diode configured by the second anode scan logic circuit is the second anode data signal, and the enable signal controlling the anode of the diode to generate the second anode data signal (actually inputting the second anode data signal into the anode of another diode) is the second anode enable signal.

[0021] The logic devices inside the first anode scanning logic circuit are connected in the same way as those inside the second anode scanning logic circuit; only the input and output signals are different.

[0022] Based on the foregoing embodiments, the method for configuring the cathode data signal corresponding to the diode to be scanned by the cathode scanning logic circuit includes: the cathode scanning logic circuit, after pre-determining that the diode combination unit containing the diode to be scanned is the currently selected diode combination unit, both the first anode scanning logic circuit and the second anode scanning logic circuit determine the electrode signals and lighting times of each diode in the diode combination unit containing the diode to be scanned from the pre-configured lighting information, and combine... Figures 2 to 4It can be seen that the first anode scanning logic circuit and the second anode scanning logic circuit delay the rising edge signal of the first anode enable signal enx_1 and the rising edge signal of the second anode enable signal enx_2 by at least 3 system clock cycles in the currently selected diode combination unit, respectively, to obtain the first anode enable delay target pulse and the second anode enable delay target pulse.

[0023] The cathode scanning logic circuit is used to determine that the second unit diode in the diode combination unit is currently lit when it is pre-determined that the diode with the longest lighting time in the currently selected diode combination unit is the second unit diode and the second lighting flag signal two_led_flag is valid (two_led_flag=1). The circuit then configures the second anode enable delay target pulse enx_2_pos_d3 as the cathode flag signal px_flag1, so that the second unit diode preempts the enable control right of the cathode data signal output.

[0024] The cathode scanning logic circuit is used to determine that the first unit diode of the diode combination unit is currently lit when it is pre-determined that the diode with the longest lighting time in the currently selected diode combination unit is the first unit diode, the first lighting flag signal first_led_flag is valid (first_led_flag=1) and the second lighting flag signal two_led_flag is invalid (two_led_flag=0). Then, it configures the first anode enable delay target pulse enx_1_pos_d3 as the cathode flag signal px_flag1, so that the first unit diode preempts the enable control right of the cathode data signal output.

[0025] It is worth noting that the cathode flag signal px_flag1 is initially at a low level; or, if the first anode enable delay target pulse enx_1_pos_d3 or the second anode enable delay target pulse enx_2_pos_d3 cannot be configured as the cathode flag signal px_flag1, the cathode flag signal px_flag1 remains at a low level. It should be noted that if at least the first diode in the currently selected diode combination unit needs to be lit, the first lighting flag signal is enabled, setting first_led_flag=1, and the second diode may also be lit simultaneously; if at least the second diode in the currently selected diode combination unit needs to be lit, the second lighting flag signal is enabled, setting two_led_flag=1, and the first diode may also be lit simultaneously.

[0026] The cathode scanning logic circuit is configured to set the cathode data signal px corresponding to the diode to be scanned to a high level when the rising edge of the system clock led_clk arrives and the cathode flag signal px_flag1 is high. This means that the cathode of the diode to be scanned is set to a high level, temporarily turning off the diodes in the currently selected diode combination unit to avoid interference from overshoot voltage. Until the lighting start signal is valid (start=1), the rising edge of the lighting start signal is input, and the cathode data signal px corresponding to the diode to be scanned is set to a low level. Based on this, when the diode with the longest lighting time in the currently selected diode combination unit finishes lighting, the cathode flag signal px_flag1 is set to a high level, the diode cathode enters an invalid state, and the cathode data signal px is pulled high. Otherwise, during the lighting period of the diode with the longest lighting time in the currently selected diode combination unit, the cathode flag signal px_flag1 is set to a low level and the cathode data signal px is pulled low. In this way, regardless of the on / off status of the two diodes within the diode combination unit, the cathode data signal of the diode with the longer illumination time is selected for output. This allows for the setting of the validity of the cathode data signal of the diode with the longer illumination time to be scanned, based on the timing logic relationship between the rising edge delay of the anode enable signals of the two diodes in the currently selected diode combination unit, thereby improving the accuracy of the diode's cathode data signal.

[0027] Based on the above embodiments, the method of configuring the cathode enable signal corresponding to the diode to be scanned by the cathode scanning logic circuit, combined with... Figure 2 It can be seen that this includes: The cathode scanning logic circuit is used to select the rising edge signal px_2_pos of the second anode data signal as the cathode enable signal enx_flag0 when the second lighting flag signal is valid (corresponding to two_led_flag=1), set enx_flag0=1, and determine that at least one second unit diode in a diode combination unit needs to be lit.

[0028] The cathode scanning logic circuit is used to select the rising edge signal px_1_pos of the first anode data signal as the cathode enable flag signal enx_flag0 when the first lighting flag signal is valid (corresponding to first_led_flag=1) and the second lighting flag signal is invalid (corresponding to two_led_flag=0), set enx_flag0=1, and determine that at least one unit diode in a diode combination unit needs to be lit.

[0029] The cathode scanning logic circuit is configured to set the low level as the cathode enable flag signal enx_flag0 when both the first and second lighting flag signals are invalid (corresponding to first_led_flag=0) and the second lighting flag signal is invalid (corresponding to two_led_flag=0). Simultaneously, the cathode flag signal px_flag1 is set to a low level. Then, when the rising edge of the system clock led_clk arrives and the cathode enable flag signal enx_flag0 is high, the cathode enable signal enx is enabled, setting enx=0. The cathode enable signal enx is the enable signal sent to the corresponding driver IO terminal and controls the output of the cathode data signal from that driver IO terminal. Simultaneously, the cathode flag signal px_flag1 is set to a low level, so the cathode data signal px corresponding to the diode to be scanned can be toggled to a low level, making the cathode of the diode to be scanned active. At this time, the diode with the longest lighting time in the currently selected diode combination unit has not yet finished lighting up. Furthermore, when the cathode enable signal enx=1 (i.e., invalid), the cathode data signal px corresponding to the diode to be scanned should not be output from the driver I / O terminal. In summary, by selecting the rising edge signal of the anode data signal of the two diodes within the diode combination unit, the accuracy of the cathode enable signal of the diode to be scanned is set, reducing overshoot voltage interference caused by frequent switching on and off of diodes within the same diode combination unit, thereby ensuring the validity of the diode's cathode data signal.

[0030] A schematic diagram illustrating the connections between specific hardware logic devices within the cathode scanning logic circuit is shown below. Figure 2As shown, the cathode scanning logic circuit includes a first flip-flop DFF1, a second flip-flop DFF2, a first selector MUX1, a second selector MUX2, and a third selector MUX3. The zero input terminal 0 of the first selector MUX1 is used to input the second anode enable delay target pulse enx_2_pos_d3, the first input terminal 1 of the first selector MUX1 is used to input the first anode enable delay target pulse enx_1_pos_d3, and the selection terminal of the first selector MUX1 is used to input the lighting time comparison result. The output terminal of the first selector MUX1 is connected to the first input terminal 1 of the third selector MUX3 to output the rising edge delay result enx_2_pos_d3_tmp of the anode enable signal of the diode with the longest lighting time in the diode combination unit to the third selector MUX3. When the lighting time of the first diode ledx_1_time is greater than or equal to the lighting time of the second diode ledx_2_time, the lighting time comparison result is high, and the first selector MUX1 selects the first anode enable delay target pulse enx_1_pos_d3, outputting enx_2_pos_d3_tmp. When the lighting time of the first diode ledx_1_time is less than the lighting time of the second diode ledx_2_time, the lighting time comparison result is low, and the first selector MUX1 selects the second anode enable delay target pulse enx_2_pos_d3, outputting enx_2_pos_d3_tmp. enx_2_pos_d3_tmp represents the rising edge delay result of the anode enable signal of the diode with the longest lighting time in the diode combination unit.

[0031] The zero input terminal 0 of the second selector MUX2 is input with a low level. The first input terminal 1 of the second selector MUX2 is connected to the first input terminal 1 of the first selector MUX1 to jointly input the first anode enable delay target pulse enx_1_pos_d3. The selection terminal of the second selector MUX2 is used to input the first lighting flag signal first_led_flag. The second selector MUX2 is used to select the output of the first anode enable delay target pulse enx_1_pos_d3 when the first unit diode is lit according to the first lighting flag signal first_led_flag. The selection terminal of the third selector MUX3 is used to input the second lighting flag signal two_led_flag. The zero input terminal 0 of the third selector MUX3 is connected to the output terminal of the second selector MUX2 so that the zero input terminal 0 of the third selector MUX3 receives the result of the selection by the second selector MUX2, but the premise is that the second lighting flag signal two_led_flag triggers the third selector MUX3 to select its zero input terminal 0.

[0032] The output of the third selector MUX3 is used to select its first input 1 when the second light-up flag signal two_led_flag is valid. The second anode enable delay target pulse enx_2_pos_d3 is output as the cathode flag signal px_flag1 through enx_2_pos_d3_tmp, so that the second unit diode preempts the enable control right of the cathode data signal output.

[0033] The output of the third selector MUX3 is also used to output the first anode enable delay target pulse enx_1_pos_d3 as the cathode flag signal px_flag1 when the second lighting flag signal two_led_flag is invalid and the first lighting flag signal first_led_flag is valid, so that the first unit diode preempts the enable control right of the cathode data signal output.

[0034] The output of the third selector MUX is connected to the first flip-flop DFF1. The enable terminal of the first flip-flop DFF1 is used to input the light-on start signal start. The output terminal of the first flip-flop DFF1 is used to output the cathode data signal px. The cathode data signal px, which is pre-stored in the first flip-flop DFF1, is at a low level and can be triggered to flip to a high level. Therefore, when the rising edge of the system clock led_clk arrives and the cathode flag signal px_flag1 is at a high level, the output cathode data signal px is at a high level, which disables the cathode level of the diode. Then, when the light-on start signal start arrives, the output cathode data signal px is at a low level, which enables the cathode level of the diode.

[0035] like Figure 2 As shown, the cathode scanning logic circuit also includes a second flip-flop DFF2, a fourth selector MUX4, and a fifth selector MUX5. The zero input terminal 0 of the fourth selector MUX4 is used to input a low level, the first input terminal 1 of the fourth selector MUX4 is used to input the rising edge capture signal px_1_pos of the first anode data signal, the selection terminal of the fourth selector MUX4 is used to input the first lighting flag signal first_led_flag, the output terminal of the fourth selector MUX4 is connected to the zero input terminal 0 of the fifth selector MUX5, and the selection terminal of the fifth selector MUX5 is used to input the second lighting flag signal two_led_flag. The output signal of the fourth selector MUX4 is transmitted to the fifth selector MUX5 only when the second lighting flag signal two_led_flag selects the zero input terminal 0 of the fifth selector MUX5.

[0036] The first input terminal 1 of the fifth selector MUX5 is used to input the rising edge capture signal px_2_pos of the second anode data signal. The output terminal of the fifth selector MUX5 is used to select the rising edge capture signal of the second anode data signal as the cathode enable flag signal enx_flag0 when the second lighting flag signal two_led_flag is valid. The output terminal of the fifth selector MUX5 is also used to select the rising edge capture signal of the first anode data signal as the cathode enable flag signal when the first lighting flag signal first_led_flag is valid and the second lighting flag signal two_led_flag is invalid. The output terminal of the fifth selector MUX5 is also used to select a low level output as the cathode enable flag signal enx_flag0 when the first lighting flag signal first_led_flag is invalid and the second lighting flag signal two_led_flag is invalid.

[0037] The output of the fifth selector MUX5 is connected to the second flip-flop DFF2. The output of the second flip-flop DFF2 is used to output the cathode enable signal enx. The cathode enable signal enx, which is pre-stored in the second flip-flop DFF2, is high and can be triggered to toggle to a low level. The output of the second flip-flop DFF2 is used to configure the cathode enable signal enx to be valid when the rising edge of the system clock led_clk arrives and the cathode enable flag signal enx_flag0 is high. This results in a low output, enabling the corresponding driver I / O terminal to output the cathode data signal. If the cathode flag signal px_flag1 is configured low, the cathode data signal px corresponding to the diode to be scanned is low, making the cathode of the diode to be scanned valid. If the cathode flag signal px_flag1 is configured high, the cathode data signal px corresponding to the diode to be scanned is high, making the cathode of the diode to be scanned invalid.

[0038] In summary, the cathode scanning logic circuit uses triggers and multi-level selectors to select the cathode data signal and its enable signal output of the corresponding diode based on the first and second lighting indicator signals when the relevant indicator signals are valid. This reduces overshoot voltage interference caused by frequent switching on and off of diodes within the same diode combination unit, thereby ensuring the validity of the diode's cathode data signal.

[0039] As one embodiment, the method of configuring the first anode scan logic circuit to generate the first anode data signal corresponding to the diode to be scanned is combined with... Figure 3 It can be seen that this includes: The first anode scanning logic circuit, after determining the diode combination unit where the diode to be scanned is located, controls the first anode enable signal enx_1 to be delayed by one system clock cycle to output a first anode enable delay signal enx_1_d1 within the currently selected diode combination unit. Then, it controls the first anode enable delay signal enx_1_d1 to be delayed by one system clock cycle to output a first second anode enable delay signal enx_1_d2. Finally, it controls the first second anode enable delay signal enx_1_d2 to be delayed by one system clock cycle to output a first third anode enable delay signal enx_1_d3. The circuit then obtains the rising edge capture signal of the first second anode enable delay signal through logical operations between the first second anode enable delay signal enx_1_d2 and the first third anode enable delay signal enx_1_d3, and configures the rising edge capture signal of the first second anode enable delay signal as the first anode enable delay target pulse enx_1_pos_d3. When implemented using hardware circuitry, the first anode enable signal enx_1 is sequentially passed through two cascaded flip-flops for delay and timing output signal enx_1_d2 according to the system clock cycle, and then through one flip-flop for delay and timing output signal enx_1_d3. Then, logical operations are performed on signals enx_1_d2 and enx_1_d3 to capture the rising edge of signal enx_1_d2, obtaining the rising edge capture signal of enx_1_d2, which is the first anode enable delayed target pulse enx_1_pos_d3. The first anode enable delayed target pulse enx_1_pos_d3 is then sent to the cathode scanning logic circuit to determine the cathode data signal that needs to be configured.

[0040] The first anode scanning logic circuit is configured to, when the lighting start signal `start` is valid and the first lighting flag signal `first_led_flag` is valid, if the rising edge of the system clock `led_clk` arrives, set the first anode data signal `px_1` to a high level, keeping the anode level of the first unit diode high. Since the lighting start signal is valid, the cathode data signal of the first unit diode is configured to a low level, thus lighting the first unit diode. It should be noted that the cathode scanning logic circuit predetermines that the diode with the longest lighting time in the currently selected diode combination unit is the first unit diode, the first lighting flag signal `first_led_flag` is valid, and the second lighting flag signal `two_led_fl` is valid. When 'ag' is invalid, the first anode enable delay target pulse enx_1_pos_d3 is configured as the cathode flag signal. If the cathode flag signal px_flag1 is invalid (px_flag1=0), the anode level of the first unit diode remains high and the cathode level (cathode data signal) of the first unit diode remains low. When the first anode enable delay target pulse enx_1_pos_d3 is valid (enx_1_pos_d3=1), the first anode data signal px_1 is set to low, indicating that the diode with the longest lighting time in the same diode combination unit needs to stop lighting. The cathode flag signal px_flag1 becomes valid, and then the cathode level (cathode data signal) of the first unit diode is pulled high, driving the first unit diode to turn off.

[0041] Based on the above embodiments, the method for configuring the first anode enable signal corresponding to the diode to be scanned by the first anode scanning logic circuit includes: the first anode scanning logic circuit, after determining the diode combination unit where the diode to be scanned is located, within the currently selected diode combination unit, controls the first anode data signal px_1 to delay by one system clock cycle to output a first anode delay signal px_1_d1, and then controls the first anode delay signal px_1_d1 to delay by one system clock cycle to output a first second anode delay signal px_1_d2. When implemented using hardware logic circuits, starting from the first anode data signal px_1, the first anode delay signal px_1_d1 and the first second anode delay signal px_1_d2 are sequentially delayed and output through two levels of flip-flops; then, the rising edge capture signal px_1_d1_pos of the first anode delay signal is obtained through logical operations between the first anode delay signal px_1_d1 and the first second anode delay signal px_1_d2, for example, controlling... The rising edge of the first anode delay signal px_1_d1 is captured by performing an AND logic operation between the first anode delay signal px_1_d1 and the first anode delay signal px_1_d2. Additionally, the rising edge capture signal px_1_pos and the falling edge capture signal of the first anode data signal are obtained through logical operations between the first anode data signal px_1 and the first anode delay signal px_1_d1. The AND operation result of the first anode data signal px_1 and the first anode delay signal px_1_d1 can be obtained through an AND logic operation. The rising edge signal of the AND operation result is recorded as the rising edge capture signal px_1_pos of the first anode data signal, and the falling edge signal of the AND operation result is recorded as the falling edge capture signal of the first anode data signal. At this time, the falling edge capture signal of the first anode data signal is configured as the lamp-on end signal endx_1 corresponding to the first unit diode, and the rising edge capture signal px_1_pos of the first anode data signal is sent to the cathode scanning logic circuit to configure the cathode enable signal.

[0042] The first anode scanning logic circuit is used to, when the rising edge of the system clock led_clk arrives, if the rising edge capture signal px_1_d1_pos of the first anode delay signal is high and the first lighting flag signal first_led_flag is valid (first_led_flag=1), then set the first anode enable signal enx_1 to be valid (enx_1=0), control the first anode data signal to be output to the corresponding driver IO terminal, and then drive the first counter CNT1 to start counting until the count value of the first counter CNT1 reaches the first lighting time ledx_1_time, then set the first anode enable signal enx_1 to be invalid (enx_1=1). Specifically, when the first counter CNT1 counts to the first lighting time ledx_1_time, it generates a counting enable signal cond1, clears the count value of the first counter CNT1 to zero, sets the first anode enable signal enx_1 to be invalid, and controls the first anode data signal not to be output to the corresponding driver IO terminal.

[0043] In summary, by delaying the first anode data signal and capturing its rising edge, the first anode enable signal, the lighting end signal sent to the lighting end indicator circuit, and the rising edge capture signal of the first anode data signal sent to the cathode scanning logic circuit are configured. Simultaneously, by delaying the first anode enable signal and capturing its rising edge, the first anode data signal and the first anode enable delay target pulse sent to the cathode scanning logic circuit are configured. This creates a timing-dependent logic mechanism that mutually constrains the anode data signal, anode enable signal generated within the first anode scanning logic circuit, and the rising edge capture signal and lighting end signal output externally. This considers both the accuracy of setting the cathode enable signal and cathode data signal of the diode to be scanned, and the accuracy of the anode enable signal and anode data signal of the first unit diode to be scanned. This reduces overshoot voltage interference caused by frequent switching on and off of diodes within the same diode combination unit, thereby ensuring the effectiveness of the diode's cathode data signal.

[0044] A schematic diagram showing the connections between specific hardware logic devices within the first anode scanning logic circuit, as shown below. Figure 3 As shown, the first anode scanning logic circuit includes a third flip-flop DFF3, a fourth flip-flop DFF4, a fifth flip-flop DFF5, a sixth flip-flop DFF6, and a first AND gate.

[0045] The data input terminal of the third flip-flop DFF3 is used to input the first anode enable signal enx_1, and then delay the first anode enable signal enx_1 by one system clock cycle to output the first anode enable delay signal enx_1_d1; the data output terminal of the third flip-flop DFF3 is connected to the data input terminal of the fourth flip-flop DFF4; the data output terminal of the third flip-flop DFF3 is used to provide the first anode enable delay signal enx_1_d1 to the data input terminal of the fourth flip-flop DFF4; the fourth flip-flop DFF4 is used to delay the first anode enable delay signal enx_1_d1 by one system clock cycle. The clock cycle is used to output the first two-anode enable delay signal enx_1_d2; the data output terminal of the fourth flip-flop DFF4 is connected to the data input terminal of the fifth flip-flop DFF5. The data output terminal of the fourth flip-flop DFF4 is used to provide the first two-anode enable delay signal enx_1_d2 to the data input terminal of the fifth flip-flop DFF5; the fifth flip-flop DFF5 is used to delay the first two-anode enable delay signal enx_1_d2 by one system clock cycle, and then output the first three-anode enable delay signal enx_1_d3; thus, the first anode enable signal enx_1 is delayed through three cascaded flip-flops.

[0046] The data output terminal of the fifth flip-flop DFF5 is connected to the first input terminal of the first AND gate. The fifth flip-flop DFF5 is used to provide the first tri-anode enable delay signal enx_1_d3 to the first input terminal of the first AND gate. The data output terminal of the fourth flip-flop DFF4 is connected to the second input terminal of the first AND gate. The fourth flip-flop DFF4 is used to provide the first di-anode enable delay signal enx_1_d2 to the second input terminal of the first AND gate. The first AND gate is used to control the first di-anode enable delay signal enx_1_d2 and the first tri-anode enable delay signal enx_1_d3 to perform an AND logic operation to obtain the rising edge capture signal of the first di-anode enable delay signal. The rising edge capture signal of the first di-anode enable delay signal is configured as the first anode enable delay target pulse enx_1_pos_d3 to be output, so as to configure the first anode data signal px_1 and send it to the cathode scanning logic circuit to configure the cathode data signal px.

[0047] The output of the first AND gate is connected to the enable terminal of the sixth flip-flop DFF6. The output of the first AND gate is used to provide the first anode enable delay target pulse enx_1_pos_d3 to the enable terminal of the sixth flip-flop DFF6. The sixth flip-flop DFF6 is used to set the first anode data signal px_1 to a high level when the rising edge of the system clock led_clk arrives, in the case that the lighting start signal start is valid and the first lighting flag signal first_led_flag is valid (first_led_flag=1), so that the anode level of the first unit diode is kept high. Since the lighting start signal start is valid, the cathode data signal px of the first unit diode can be configured to a low level through the cathode scanning logic circuit to light up the first unit diode. When the first anode enable delay target pulse enx_1_pos_d3 is valid (enx_1_pos_d3=1), the first anode enable signal enx_1 is set to a high level, the cathode flag signal px_flag1 is valid, and then the cathode level (cathode data signal px) of the first unit diode is pulled high to drive the first unit diode to turn off.

[0048] Based on the above embodiments, the first anode scanning logic circuit further includes a seventh flip-flop DFF7, an eighth flip-flop DFF8, a ninth flip-flop DFF9, a second AND gate, and a third AND gate; the data output terminal of the sixth flip-flop DFF6 is connected to the data input terminal of the seventh flip-flop DFF7, and the data output terminal of the sixth flip-flop DFF6 is used to provide a first anode data signal px_1 set in real time to the data input terminal of the seventh flip-flop DFF7. The data input terminal of the seventh flip-flop DFF7 is used to input the first anode data signal px_1, and then delay the first anode data signal px_1 by one system clock cycle to output the first anode delay signal px_1_d1; the data output terminal of the seventh flip-flop DFF7 is connected to the data input terminal of the eighth flip-flop DFF8; the data output terminal of the seventh flip-flop DFF7 is used to provide the first anode delay signal px_1_d1 to the data input terminal of the eighth flip-flop DFF8; the eighth flip-flop DFF8 is used to delay the first anode delay signal px_1_d1 by one system clock cycle to output the first anode delay signal px_1_d2. The data output of the eighth flip-flop DFF8 is connected to the first input of the second AND gate. The data output of the eighth flip-flop DFF8 is used to provide the first two-anode delay signal px_1_d2 to the first input of the second AND gate. The data output of the seventh flip-flop DFF7 is connected to the second input of the second AND gate. The data output of the seventh flip-flop DFF7 is used to provide the first one-anode delay signal px_1_d1 to the second input of the second AND gate. The second AND gate is used to control the first one-anode delay signal px_1_d1 and the first two-anode delay signal px_1_d2 to perform an AND logic operation to obtain the rising edge capture signal px_1_d1_pos of the first one-anode delay signal. The rising edge of the first one-anode delay signal is captured by two-stage delay and timing.

[0049] The output of the second AND gate is connected to the first input of the third AND gate. The output of the second AND gate provides the rising edge capture signal px_1_d1_pos of the first anode delay signal to the first input of the third AND gate. The second input of the third AND gate is used to input the first LED indicator signal first_led_flag. The third AND gate performs an AND operation on the rising edge capture signal px_1_d1_pos and the first LED indicator signal first_led_flag to obtain a first AND result signal. The first AND result signal is high only when the rising edge capture signal of the first anode delay signal is high and the first LED indicator signal is valid. The third AND gate is used to determine the validity of the rising edge capture signal px_1_d1_pos and the first LED indicator signal first_led_flag.

[0050] The output of the third AND gate is connected to the enable terminal of the ninth flip-flop DFF9. The output of the third AND gate is used to provide the first AND result signal to the enable terminal of the ninth flip-flop DFF9. The ninth flip-flop DFF9 is used to set the first anode enable signal enx_1 to be valid (enx_1=0) when the rising edge of the system clock led_clk arrives, if the rising edge capture signal px_1_d1_pos of the first anode delay signal is high and the first light-up flag signal first_led_flag is valid.

[0051] The ninth flip-flop DFF9 is also connected to the counting output of the first counter CNT1. The first counter CNT1 is used to input the first lighting flag signal first_led_flag. When the rising edge of the system clock led_clk arrives, if the rising edge capture signal px_1_d1_pos of the first anode delay signal is high and the first lighting flag signal first_led_flag is valid (first_led_flag=1), then the first anode enable signal enx_1 is set to valid (enx_1=0), driving the first anode data signal px_1 to be output to the corresponding drive IO terminal. When the first anode enable signal enx_1 is set to valid, the first counter CNT1 starts counting until the count value of the first counter CNT1 reaches the first lighting time ledx_1_time. At this time, the counting output of the first counter CNT1 generates a counting enable signal cond1 and outputs it to the ninth flip-flop DFF9, while driving the ninth flip-flop DFF9 to invalidate its pre-stored first anode enable signal enx_1. Therefore, the ninth flip-flop DFF9 is used to invalidate the first anode enable signal (enx_1=1) when the count value of the first counter reaches the first lighting time ledx_1_time, so as to indicate that the anode of the currently scanned first unit diode does not accept level configuration.

[0052] It should be noted that the first counter is a counter built into the first anode scanning logic circuit, used to time the time when the first anode enable signal enx_1 is kept valid or the lighting time of the first unit diode currently being scanned. Each time the first anode enable signal enx_1 is set to valid (enx_1=0), the count is incremented by one; otherwise, the original count value remains unchanged.

[0053] The data output terminal of the ninth flip-flop DFF9 is connected to the data input terminal of the third flip-flop DFF3. The data output terminal of the ninth flip-flop DFF9 provides a real-time set first anode enable signal enx_1 to the data input terminal of the third flip-flop DFF3. This enables the data output terminal of the ninth flip-flop DFF9 to provide delayed original enable signals for the third flip-flop DFF3, the fourth flip-flop DFF4, and the fifth flip-flop DFF5, thereby updating the first anode enable delayed target pulse and the first anode data signal subsequently provided to the cathode scanning logic circuit. Based on this, the data output terminal of the sixth flip-flop DFF6 provides a real-time set first anode data signal px_1 to the data input terminal of the seventh flip-flop DFF7. This enables the data output terminal of the sixth flip-flop DFF6 to provide delayed original data signals for the seventh flip-flop DFF7 and the eighth flip-flop DFF8, thereby updating the first anode enable signal enx_1.

[0054] like Figure 3 As shown, the first anode scanning logic circuit further includes a fourth AND gate; the data input terminal of the seventh flip-flop DFF7 is connected to the first input terminal of the fourth AND gate, and the first input terminal of the fourth AND gate is used to input the first anode data signal px_1; the data output terminal of the seventh flip-flop DFF7 is connected to the second input terminal of the fourth AND gate, and the data output terminal of the seventh flip-flop DFF7 is used to provide a first anode delay signal px_1_d1 to the second input terminal of the fourth AND gate; the fourth AND gate is used to perform a logical AND operation on the first anode data signal px_1 and the first anode delay signal px_1_d1 to obtain a pulse result signal, and then the rising edge of the pulse result signal is regarded as the rising edge capture signal px_1_pos of the first anode data signal, and the rising edge of the pulse result signal is regarded as the falling edge capture signal of the first anode data signal, and the falling edge capture signal of the first anode data signal is configured as the lighting end signal endx_1 corresponding to the first unit diode. When the data output terminal of the sixth flip-flop DFF6 is used to update the first anode data signal px_1 for the data input terminal of the seventh flip-flop DFF7, the rising edge capture signal px_1_pos of the first anode data signal subsequently provided to the cathode scanning logic circuit, and the lighting end signal endx_1 corresponding to the first unit diode subsequently provided to the lighting end indicator circuit are all updated.

[0055] It should be noted that the system clock period of the first anode scan logic circuit is determined by `led_clk`. The main component driving the system clock `led_clk` to be delayed by several system clock cycles in the first anode scan logic circuit is a flip-flop. The flip-flop outputs its registered data signal according to the time delay of `led_clk`. All signals toggle on the rising edge of this system clock `led_clk`. The currently selected diode combination unit contains a first unit diode and a second unit diode. The anode enable signal of the first unit diode is the first anode enable signal, and the anode data signal of the second unit diode is the second anode data signal. The anode enable signal of the second unit diode is the second anode enable signal.

[0056] Since the structures of the first anode scanning logic circuit and the second anode scanning logic circuit are the same, therefore, combining Figure 4 It can be seen that the method by which the second anode scanning logic circuit configures the second anode data signal corresponding to the diode to be scanned includes: The second anode scanning logic circuit, after determining the diode combination unit where the diode to be scanned is located, controls the second anode enable signal enx_2 to be delayed by one system clock cycle to output a second first anode enable delay signal enx_2_d1 within the currently selected diode combination unit. Then, it controls the second first anode enable delay signal enx_2_d1 to be delayed by one system clock cycle to output a second second anode enable delay signal enx_2_d2. Then, it controls the second second anode enable delay signal enx_2_d2 to be delayed by one system clock cycle to output a second third anode enable delay signal enx_2_d3. Finally, it obtains the rising edge capture signal of the second second anode enable delay signal through the logical operation between the second second anode enable delay signal enx_2_d2 and the second third anode enable delay signal enx_2_d3, and configures the rising edge capture signal of the second second anode enable delay signal as the second anode enable delay target pulse enx_2_pos_d3. When implemented using hardware circuitry, the second anode enable signal enx_2 is sequentially delayed and output as enx_2_d2 by two cascaded flip-flops according to the system clock cycle, and then delayed and output as enx_2_d3 by one flip-flop. Logical operations are then performed on signals enx_2_d2 and enx_2_d3 to capture the rising edge of enx_2_d2, obtaining the second anode enable delayed target pulse enx_2_pos_d3. This second anode enable delayed target pulse enx_2_pos_d3 is then sent to the cathode scanning logic circuit to determine the cathode data signal to be configured.

[0057] The second anode scanning logic circuit, when the lighting start signal `start` is valid and the second lighting flag signal `two_led_flag` is valid, if the rising edge of the system clock `led_clk` arrives, sets the second anode data signal `px_2` to a high level, keeping the anode level of the second unit diode high. Since the lighting start signal is valid, the cathode data signal of the second unit diode is configured to a low level, thus lighting the second unit diode. It should be noted that the cathode scanning logic circuit pre-determines that the diode with the longest lighting time in the currently selected diode combination unit is the second unit diode, and that the first lighting flag signal `first_led_flag` is invalid and the second lighting flag signal `two_led_flag` is not valid. When the lamp flag signal two_led_flag is valid, the second anode enable delay target pulse enx_2_pos_d3 is configured as the cathode flag signal. If the cathode flag signal px_flag1 is invalid (px_flag1=0), the anode level of the second unit diode remains high and the cathode level (cathode data signal) of the second unit diode remains low. When the second anode enable delay target pulse enx_2_pos_d3 is valid, the second anode data signal enx_1 is set to low, indicating that the diode with the longest lighting time in the same diode combination unit needs to stop lighting. Then, the cathode level (cathode data signal) of the second unit diode is pulled high, driving the second unit diode to turn off.

[0058] Based on the above embodiments, the method for configuring the second anode enable signal corresponding to the diode to be scanned by the second anode scanning logic circuit includes: the second anode scanning logic circuit is used to control the second anode data signal px_2 to delay by one system clock cycle and output a second first anode delay signal px_2_d1 within the currently selected diode combination unit, and then control the second first anode delay signal px_2_d1 to delay by one system clock cycle and output a second second anode delay signal px_2_d2. Then, through logical operations between the second first anode delay signal px_2_d1 and the second second anode delay signal px_2_d2, the rising edge capture signal px_2_d1_pos of the second first anode delay signal is obtained. Additionally, through logical operations between the second anode data signal px_2 and the second second anode delay signal px_2_d2, the rising edge capture signal px_2_d1_pos of the second first anode delay signal is obtained. The logical operation between signals px_2_d1 yields the rising edge capture signal px_2_pos of the first anode data signal and the falling edge capture signal of the second anode data signal. The AND operation result of the second anode data signal px_2 and the second anode delay signal px_2_d1 can be obtained through AND logic operation. The rising edge signal of the AND operation result is recorded as the rising edge capture signal px_2_pos of the second anode data signal, and the falling edge signal of the AND operation result is recorded as the falling edge capture signal of the second anode data signal. The falling edge capture signal of the second anode data signal is configured as the lamp-on end signal endx_2 corresponding to the second unit diode. At the same time, the rising edge capture signal px_2_pos of the second anode data signal is sent to the cathode scanning logic circuit to configure the cathode enable signal.

[0059] The second anode scanning logic circuit is configured to enable the second anode enable signal enx_2 when the rising edge of the system clock led_clk arrives, provided that the rising edge capture signal px_2_d1_pos of the second anode delay signal is high and the second lighting flag signal two_led_flag is valid. Then, it drives the second counter CNT2 to start counting until the count value reaches the second lighting time ledx_2_time, at which point the second anode enable signal enx_2 is disabled. Specifically, the second counter CNT2 is a built-in counter in the second anode scanning logic circuit used to time the duration the second anode enable signal remains valid. When the second counter CNT2 counts to the second lighting time ledx_2_time, it generates a counting enable signal cond2, clears the count value of the second counter CNT2, disables the second anode enable signal enx_2, and prevents the second anode data signal from being output to the corresponding driver I / O terminal.

[0060] In summary, by delaying the second anode data signal and capturing its rising edge, the second anode enable signal, the lighting end signal sent to the lighting end indicator circuit, and the rising edge capture signal of the second anode data signal sent to the cathode scanning logic circuit are configured. Simultaneously, by delaying the second anode enable signal and capturing its rising edge, the second anode data signal and the second anode enable delay target pulse sent to the cathode scanning logic circuit are configured. This creates a timing-dependent logic mechanism that mutually constrains the anode data signal, anode enable signal generated within the second anode scanning logic circuit, and the rising edge capture signal and lighting end signal output externally. This considers the accuracy of setting the cathode enable signal and cathode data signal of the diode to be scanned, as well as the accuracy of the anode enable signal and anode data signal of the second unit diode to be scanned. This reduces overshoot voltage interference caused by frequent switching on and off of diodes within the same diode combination unit, thereby ensuring the validity of the diode's cathode data signal.

[0061] like Figure 4 As shown, the second anode scan logic circuit includes a tenth flip-flop DFF10, an eleventh flip-flop DFF11, a twelfth flip-flop DFF12, a thirteenth flip-flop DFF13, a fourteenth flip-flop DFF14, a fifteenth flip-flop DFF15, a sixteenth flip-flop DFF16, a fifth AND gate, a sixth AND gate, a seventh AND gate, and an eighth AND gate. The data input terminal of the tenth flip-flop DFF10 is used to input the second anode enable signal enx_2, and then delays the second anode enable signal enx_2 by one system clock cycle to output the second anode enable delay signal enx_2_d1. The data output terminal of the tenth flip-flop DFF10 is connected to the data input terminal of the eleventh flip-flop DFF11. The data output terminal of the tenth flip-flop DFF10 is used to provide the second anode enable delay signal enx_2_d1 to the data input terminal of the eleventh flip-flop DFF11. The eleventh flip-flop DFF11 is used to delay the second anode enable delay signal enx_2_d1 by one system clock cycle. After one clock cycle, the second two-anode enable delay signal enx_2_d2 is output; the data output terminal of the eleventh flip-flop DFF11 is connected to the data input terminal of the twelfth flip-flop DFF12. The data output terminal of the eleventh flip-flop DFF11 is used to provide the second two-anode enable delay signal enx_2_d2 to the data input terminal of the twelfth flip-flop DFF12; the twelfth flip-flop DFF12 is used to delay the second two-anode enable delay signal enx_2_d2 by one clock cycle, and then output the second three-anode enable delay signal enx_2_d3; thus, the second anode enable signal enx_2 is delayed through three cascaded flip-flops.

[0062] The data output of the twelfth flip-flop DFF12 is connected to the first input of the fifth AND gate. The twelfth flip-flop DFF12 is used to provide the second tri-anode enable delay signal enx_2_d3 to the first input of the fifth AND gate. The data output of the eleventh flip-flop DF11 is connected to the second input of the fifth AND gate. The eleventh flip-flop DF11 is used to provide the second bi-anode enable delay signal enx_2_d2 to the second input of the fifth AND gate. The fifth AND gate is used to control the second bi-anode enable delay signal enx_2_d2 and the second tri-anode enable delay signal enx_2_d3 to perform an AND logic operation to obtain the rising edge capture signal of the second bi-anode enable delay signal. The rising edge capture signal of the second bi-anode enable delay signal is configured as the second anode enable delay target pulse enx_2_pos_d3 to be output, so as to configure the second anode data signal px_2 and send it to the cathode scanning logic circuit to configure the cathode data signal px.

[0063] The output of the fifth AND gate is connected to the thirteenth flip-flop DFF13. The output of the fifth AND gate is used to provide the second anode enable delay target pulse enx_2_pos_d3 to the thirteenth flip-flop DFF13. The two inputs of the sixth AND gate are respectively input to the lighting start signal start and the lighting flag signal two_led_flag. The sixth AND gate is used to control the lighting start signal start and the lighting flag signal two_led_flag to perform an AND logic operation to obtain the start flag signal. When the lighting start signal is valid and the second lighting flag signal two_led_flag=1, the second anode data signal px_2 needs to be configured to a high level. The output of the sixth AND gate is connected to the thirteenth flip-flop DFF13. The output of the sixth AND gate is used to provide the start flag signal to the thirteenth flip-flop DFF13 to provide feedback on the arrival of the lighting start signal and the validity of the first lighting flag signal.

[0064] The thirteenth flip-flop, DFF13, is used to set the second anode data signal px_2 to a high level when the rising edge of the system clock led_clk arrives, provided that the starting signal start is valid and the second lighting flag signal two_led_flag is valid. This keeps the anode level of the second unit diode high. Since the starting signal start is valid, the cathode data signal px of the second unit diode can be configured to a low level through the cathode scanning logic circuit to light up the second unit diode. This continues until the second anode enable delay target pulse enx_2_pos_d3 is valid (enx_2_pos_d3=1), at which point the second anode data signal enx_2 is set to a high level, and then the cathode level (cathode data signal px) of the second unit diode is pulled high, driving the second unit diode to turn off.

[0065] The data output of the thirteenth flip-flop DFF13 is connected to the data input of the fifteenth flip-flop DFF15. The data output of the thirteenth flip-flop DFF13 is used to provide the second anode data signal px_2 to the data input of the fifteenth flip-flop DFF15. The data input of the fifteenth flip-flop DFF15 is used to input the second anode data signal px_2, and then delay the second anode data signal px_2 by one clock cycle to output the second anode delayed signal px_2_d1. The data output of the fifteenth flip-flop DFF15 is connected to the data input of the sixteenth flip-flop DFF16. The data output of the fifteenth flip-flop DFF15 is used to provide the second anode delayed signal px_2_d1 to the data input of the sixteenth flip-flop DFF16. The sixteenth flip-flop DFF16 is used to delay the second anode delayed signal px_2_d1 by one system clock cycle to output the second anode delayed signal px_2_d2. The data output of the sixteenth flip-flop DFF16 is connected to the first input of the seventh AND gate. The data output of the sixteenth flip-flop DFF16 is used to provide the second dianode delay signal px_2_d2 to the first input of the seventh AND gate. The data output of the fifteenth flip-flop DFF15 is connected to the second input of the seventh AND gate. The data output of the fifteenth flip-flop DFF15 is used to provide the second monoanode delay signal px_2_d1 to the second input of the seventh AND gate. The seventh AND gate is used to control the second monoanode delay signal px_2_d1 and the second dianode delay signal px_2_d2 to perform an AND logic operation to obtain the rising edge capture signal px_2_d1_pos of the second monoanode delay signal. The rising edge of the second monoanode delay signal is captured by two-stage delay timing.

[0066] The output of the seventh AND gate is connected to the first input of the eighth AND gate. The output of the seventh AND gate provides the rising edge capture signal px_2_d1_pos of the second anode delay signal to the first input of the eighth AND gate. The second input of the eighth AND gate is used to input the second LED indicator signal two_led_flag. The eighth AND gate performs an AND operation on the rising edge capture signal px_2_d1_pos and the second LED indicator signal two_led_flag to obtain the second AND result signal. The second AND result signal is high only when the rising edge capture signal px_2_d1_pos is high and the second LED indicator signal two_led_flag is valid. The eighth AND gate is used to determine the validity of the rising edge capture signal px_2_d1_pos and the second LED indicator signal two_led_flag.

[0067] The output of the eighth AND gate is connected to the fourteenth flip-flop DFF14. The output of the eighth AND gate is used to provide the second AND result signal to the fourteenth flip-flop DFF14. The second AND result signal includes the signal configuration that the rising edge capture signal px_2_d1_pos of the second anode delay signal is high and the second light-on flag signal two_led_flag is valid. The fourteenth flip-flop DFF14 is used to set the second anode enable signal enx_2 to valid (enx_2=0) when the rising edge of the system clock led_clk arrives, if the rising edge capture signal px_2_d1_pos of the second anode delay signal is high and the second light-on flag signal two_led_flag is valid.

[0068] The fourteenth flip-flop DFF14 is also connected to the counting output of the second counter CNT2. The second counter CNT2 is used to input the second lighting flag signal two_led_flag. When the rising edge of the system clock led_clk arrives, if the rising edge capture signal px_2_d1_pos of the second anode delay signal is high and the second lighting flag signal two_led_flag is valid (two_led_flag=1), then the second anode enable signal enx_2 is set to valid (enx_2=0), driving the second anode data signal px_2 to be output to the corresponding drive IO terminal. Then, when the second anode enable signal enx_2 is set to valid, the second counter CNT2 starts counting until the count value of the second counter CNT2 reaches the second lighting time ledx_2_time. At this time, the counting output of the second counter CNT2 generates a counting enable signal cond2 and outputs it to the fourteenth flip-flop DFF14, while driving the fourteenth flip-flop DFF14 to invalidate its pre-stored second anode enable signal enx_2. Therefore, the fourteenth flip-flop DFF14 is used to invalidate the second anode enable signal enx_2 (enx_2=1) when the count value of the second counter CNT2 reaches the second lighting time ledx_2_time, so as to indicate that the anode of the currently scanned second unit diode does not accept level configuration.

[0069] It should be noted that the second counter is a built-in counter in the second anode scanning logic circuit. It is used to increment the count by one whenever the rising edge of the system clock arrives and the second anode enable signal enx_2 is valid, otherwise the original count value remains unchanged.

[0070] The data output terminal of the fourteenth flip-flop DFF14 is connected to the data input terminal of the tenth flip-flop DFF10. The data output terminal of the tenth flip-flop DFF10 provides a second anode enable signal enx_2 to the data input terminal of the fourteenth flip-flop DFF14. This enables the data output terminal of the fourteenth flip-flop DFF14 to provide the original enable signal for the tenth flip-flop DFF10, the eleventh flip-flop DFF11, and the twelfth flip-flop DFF12 after delay processing, thereby updating the second anode enable delay target pulse and the second anode data signal subsequently provided to the cathode scanning logic circuit. Based on this, the data output terminal of the thirteenth flip-flop DFF13 provides a real-time set second anode data signal px_2 to the data input terminal of the fifteenth flip-flop DFF15. This enables the data output terminal of the thirteenth flip-flop DFF13 to provide the original data signal for the fifteenth flip-flop DFF15 and the sixteenth flip-flop DFF16 after delay processing, thereby updating the second anode enable signal.

[0071] like Figure 4 As shown, the second anode scanning logic circuit also includes a ninth AND gate; the data input terminal of the fifteenth flip-flop DFF15 is connected to the first input terminal of the ninth AND gate, and the first input terminal of the ninth AND gate is used to input the second anode data signal px_2; the data output terminal of the fifteenth flip-flop DFF15 is connected to the second input terminal of the ninth AND gate, and the data output terminal of the fifteenth flip-flop DFF15 is used to provide a second anode delay signal px_2_d1 to the second input terminal of the ninth AND gate; the ninth AND gate is used to perform a logical AND operation on the second anode data signal px_2 and the second anode delay signal px_2_d1 to obtain a pulse result signal, and then the rising edge of the pulse result signal is regarded as the rising edge capture signal px_2_pos of the second anode data signal, and the rising edge of the pulse result signal is regarded as the falling edge capture signal of the second anode data signal and the falling edge capture signal of the second anode data signal is configured as the lighting end signal endx_2 corresponding to the second unit diode. When the data output terminal of the fifteenth flip-flop DFF15 is used to update the second anode data signal px_2 for the data input terminal of the sixteenth flip-flop DFF16, the rising edge capture signal px_2_pos of the second anode data signal subsequently provided to the cathode scanning logic circuit, and the lighting end signal endx_2 corresponding to the second unit diode subsequently provided to the lighting end indicator circuit are all updated.

[0072] As one embodiment, to indicate how the diodes in a diode combination unit are lit, the timing scanning circuit is further used to input a single-lamp flag signal `one_flag` and a specified lighting flag signal `one_flag_secd`, which are then processed by the corresponding digital logic circuit to obtain the first lighting flag signal `first_led_flag` and the second lighting flag signal `two_led_flag`. The timing scanning circuit is used to light only one diode in the currently selected diode combination unit when the single-lamp flag signal `one_flag` is valid (considered as a high level), including lighting only the first or second diode in the unit; and to light all diodes in the currently selected diode combination unit when the single-lamp flag signal `one_flag` is invalid (low level). Since it is impossible to determine which diode is lit when the single-lamp flag signal one_flag is valid, a designated lighting flag signal one_flag_secd is set for further identification. The timing scanning circuit is used to light up only the second unit diode in the currently selected diode combination unit when the designated lighting flag signal one_flag_secd is valid (considered as high level). The timing scanning circuit is also used to light up only the first unit diode in the currently selected diode combination unit when the designated lighting flag signal one_flag_secd is invalid (considered as low level).

[0073] If at least the first diode in the currently selected diode combination unit needs to be lit, the first lighting flag signal is enabled, setting `first_led_flag=1`, and the second diode may also be lit simultaneously. If at least the second diode in the currently selected diode combination unit needs to be lit, the second lighting flag signal is enabled, setting `two_led_flag=1`, and the first diode may also be lit simultaneously. Therefore, when the single-lamp flag signal `one_flag` is enabled (considered high) and the designated lighting flag signal `one_flag_secd` is disabled (considered low), or when the single-lamp flag signal `one_flag` is disabled (considered low) and the designated lighting flag signal `one_flag_secd` is disabled (considered low), the first lighting flag signal `first_led_flag` is enabled, and the first diode is lit.

[0074] Preferably, when the single-lamp flag signal one_flag is invalid, both the first lighting flag signal first_led_flag and the second lighting flag signal two_led_flag are valid, and both the first unit diode and the second unit diode are lit.

[0075] When the single-lamp flag signal one_flag is invalid and the designated lighting flag signal one_flag_secd is valid, or when both the single-lamp flag signal one_flag and the designated lighting flag signal one_flag_secd are valid, the second lighting flag signal two_led_flag is valid, and the second unit diode is lit.

[0076] In some hardware circuit implementations, the single-lamp flag signal one_flag and the designated lighting flag signal one_flag_secd can be input into a two-input NAND gate logic circuit to output the first lighting flag signal first_led_flag; while when the designated lighting flag signal one_flag_secd is valid, the single-lamp flag signal one_flag and the designated lighting flag signal one_flag_secd can be input into a two-input OR gate logic circuit to output the second lighting flag signal two_led_flag.

[0077] Specifically, the timing scanning circuit is used to illuminate only the second diode in the currently selected diode combination unit when both the single-lamp indicator signal and the designated lighting indicator signal are valid, and to determine that the second lighting indicator signal is valid, which can be set to a high level. The timing scanning circuit is also used to illuminate only the first diode in the currently selected diode combination unit when both the single-lamp indicator signal and the designated lighting indicator signal are invalid, and to determine that the first lighting indicator signal is valid, which can be set to a high level. Furthermore, the timing scanning circuit is used to illuminate at least the second diode in the currently selected diode combination unit when either the single-lamp indicator signal or the designated lighting indicator signal is invalid, and to determine that the second lighting indicator signal is valid, which can be set to a high level. Finally, the timing scanning circuit is used to illuminate at least the first diode in the currently selected diode combination unit when either the single-lamp indicator signal or the designated lighting indicator signal is invalid, and to determine that the first lighting indicator signal is valid, which can be set to a high level. Therefore, within the same diode combination unit, the second lighting indicator signal is valid when at least the second diode is illuminated; the second lighting indicator signal is invalid when the second diode is not illuminated. Within the same diode combination unit, the first illuminated indicator signal is valid when at least the first unit diode is driven to light up; the first illuminated indicator signal is invalid when the first unit diode is not driven to light up.

[0078] As one example, such as Figure 1As shown, the timing scanning circuit also includes a lighting end indicator circuit, which is connected to each anode scanning logic circuit. The lighting end indicator circuit is used to select the lighting end signal corresponding to the longest lighting time among the diodes configured in all anode scanning logic circuits and output it to the state controller to drive all diodes to be scanned to turn off before proceeding to the next round of scanning. Then, based on the anode data signal, anode enable signal, cathode data signal, and cathode enable signal configured in the next round, the diode at the new address is driven to light up or turn off.

[0079] Specifically, the lighting end indicator circuit is connected to the first anode scanning logic circuit and the second anode scanning logic circuit respectively. The lighting end indicator circuit and the first anode scanning logic circuit establish a signal connection relationship through the lighting end signal endx_1 corresponding to the first unit diode, and the lighting end indicator circuit and the second anode scanning logic circuit establish a signal connection relationship through the lighting end signal endx_2 corresponding to the second unit diode.

[0080] The LED illumination end indicator circuit is used to select and output the illumination end signal corresponding to the longest illumination time among the diodes to be scanned, based on a pre-determined longest illumination time. Specifically, the diodes to be scanned include a first unit diode and a second unit diode. If a single diode is lit and the second unit diode is also lit, the illumination end signal corresponding to the longest illumination time is endx_2 for the second unit diode. If a single diode is lit and the first unit diode is also lit, the illumination end signal corresponding to the longest illumination time is endx_1 for the first unit diode. If both diodes are lit and the illumination time of the first unit diode is longer than that of the second unit diode, the illumination end signal corresponding to the longest illumination time is endx_1 for the first unit diode. If both diodes are lit and the illumination time of the first unit diode is shorter than that of the second unit diode, the illumination end signal corresponding to the longest illumination time is endx_2 for the second unit diode.

[0081] In scenarios using state machine control, the lighting end indicator circuit selects the lighting end signal corresponding to the longest lighting time and outputs it to the state machine. This triggers the state machine to maintain the driving operation of the two diodes to be scanned in the current state for the longest lighting time. At least during the longest lighting time, no state transition can occur until the lighting end signal corresponding to the longest lighting time is detected to have flipped from invalid to valid. At this point, the lighting timing operation of the two diodes to be scanned in the current state is determined to be complete, reducing the probability of lighting timing errors. Therefore, based on the first anode scanning logic circuit and the second anode scanning logic circuit, an electrode signal that can be configured to simultaneously light up two diodes or only light up one diode is implemented, driving diodes at different positions to light up sequentially. Furthermore, by reusing the lighting end signal corresponding to the longest lighting time among the diodes to be scanned currently generated by the timing scanning circuit, state transitions are performed, avoiding lighting timing errors in different scenarios.

[0082] Specifically, when the lighting end indicator circuit determines the longest lighting time among the diodes configured in all anode scanning logic circuits, it selects the lighting end signal corresponding to the longest lighting time for output. This method is applicable when the diodes configured in all anode scanning logic circuits are diodes configured in the first anode scanning logic circuit (first unit diode) and diodes configured in the second anode scanning logic circuit (second unit diode). Specifically, the lighting end indicator circuit, upon receiving the lighting time comparison result, selects the lighting end signal corresponding to the diode with the longest lighting time among the diodes currently being scanned, based on the lighting time comparison result. (Illustratively, as shown...) Figure 5 As shown, when the lighting time of the first unit diode ledx_1_time is greater than or equal to the lighting time of the second unit diode ledx_2_time, ledx_1_time>=ledx_2_time, the lighting time comparison result is high level, which serves as the selection control signal; when the lighting time of the first unit diode ledx_1_time is less than the lighting time of the second unit diode ledx_2_time, the lighting time comparison result is low level, which serves as another selection control signal.

[0083] The lighting end indicator circuit is also used to select the lighting end signal output corresponding to the first unit diode when the single lamp indicator signal is valid and the designated lighting indicator signal is invalid; combined with Figures 2 to 5 It can be seen that when the single-lamp flag signal one_flag is high and the designated lighting flag signal one_flag_secd is low, only the first unit diode is lit, and the output endx_1 is used as the final determined lighting end signal end, which is also equivalent to the falling edge signal of the first anode data signal.

[0084] The lighting end indicator circuit is also used to select the lighting end signal output corresponding to the second unit diode when both the single lamp indicator signal and the designated lighting indicator signal are high; combined with Figures 2 to 5 It can be seen that when the single-lamp flag signal one_flag is high and the designated lighting flag signal one_flag_secd is high, only the second unit diode is lit, and the output endx_2 is used as the final determined lighting end signal end, which is also equivalent to the falling edge signal of the second anode data signal.

[0085] The lighting end indicator circuit is also used to select the diode with the longest lighting time among the diodes currently being scanned when the single-lamp indicator signal is invalid, and output the lighting end signal corresponding to that diode. The lighting end signal corresponding to the diode with the longest lighting time among the diodes currently being scanned is selected based on the lighting time comparison result. Combined with... Figures 2 to 5 It can be seen that when the single-lamp flag signal one_flag is low, the first unit diode and the second unit diode are lit simultaneously. When the first unit diode and the second unit diode are lit simultaneously, if the software determines that ledx_1_time>=ledx_2_time, it selects the lighting end signal endx_1 corresponding to the first unit diode as the end output shown in the figure. If the lighting time ledx_1_time of the first unit diode is less than the lighting time ledx_2_time of the second unit diode, it selects the lighting end signal endx_2 corresponding to the second unit diode as the end output shown in the figure, so as to drive all the diodes that need to be scanned to turn off. Therefore, this embodiment uses the lighting end indicator circuit to mark the end of the lighting sequence operation of a certain diode or all diodes in the same diode combination unit, so as to support the control of different lighting times.

[0086] The specific hardware circuit connection structure inside the indicator circuit for the end of illumination is as follows: Figure 5 As shown, the lighting end indicator circuit includes a sixth selector MUX6, a seventh selector MUX7, and an eighth selector MUX8. The zero input terminal 0 of the sixth selector MUX6 and the first input terminal 1 of the seventh selector MUX7 are connected to input the lighting end signal endx_2 corresponding to the second unit diode. The first input terminal 1 of the sixth selector MUX6 and the zero input terminal 0 of the seventh selector MUX7 are connected to input the lighting end signal endx_1 corresponding to the first unit diode, so that the selection terminals of the sixth selector MUX6 and the seventh selector MUX7 select different types of input terminal signal outputs at the same level.

[0087] The selection terminal of the sixth selector MUX6 is used to input the lighting time comparison result; the sixth selector MUX6 is used to output the lighting end signal corresponding to the diode with the longest lighting time among the diodes currently being scanned; wherein, when the lighting time comparison result is low, the sixth selector MUX6 outputs the lighting end signal endx_2 corresponding to the second unit diode, as the lighting end signal end_tmp corresponding to the lighting time comparison result; when the lighting time comparison result is high, it corresponds to... Figure 5 The selection control signal generated when ledx_1_time>=ledx_2_time is shown. The sixth selector MUX6 outputs the lighting end signal endx_1 corresponding to the first unit diode, which serves as the lighting end signal end_tmp corresponding to the lighting time comparison result.

[0088] The selection terminal of the seventh selector MUX7 is used to input the specified lighting flag signal one_flag_secd; when the specified lighting flag signal one_flag_secd is invalid, the seventh selector MUX7 selects the lighting end signal endx_1 corresponding to the first unit diode and outputs it to the eighth selector MUX8; when the specified lighting flag signal one_flag_secd is valid, the seventh selector MUX7 selects the lighting end signal endx_2 corresponding to the second unit diode and outputs it to the eighth selector MUX8. This implements the use of the specified lighting flag signal one_flag_secd to select the lighting end signal corresponding to a single diode as a candidate lighting end signal.

[0089] The zero input terminal 0 of the eighth selector MUX8 is connected to the output terminal of the sixth selector MUX6, and the first input terminal 1 of the eighth selector MUX8 is connected to the output terminal of the seventh selector MUX7. Thus, the eighth selector MUX8 and the sixth selector MUX6 (or the seventh selector MUX7) are connected to form a two-stage cascaded selector. The output terminal of the eighth selector MUX8 is connected to the state controller. The selection terminal of the eighth selector MUX8 is used to input the single-lamp flag signal one_flag. When the single-lamp flag signal one_flag is invalid, the eighth selector MUX8 selects the lighting end signal end_tmp output by the sixth selector MUX6 as the end output shown in the diagram to the state controller. When the single-lamp flag signal one_flag is valid, the eighth selector MUX8 selects the candidate lighting end signal output by the seventh selector MUX7 as the end output shown in the diagram. In summary, the lighting end indicator circuit, through the combined design of the sixth, seventh, and eighth selectors, directly outputs the lighting end signal corresponding to the diode selected by the specified lighting indicator signal when the single-lamp indicator signal is valid, and outputs the lighting end signal corresponding to the diode with the longest lighting time based on the lighting time comparison result when the single-lamp indicator signal is invalid.

[0090] Based on the foregoing embodiments, this application also discloses a diode array driving circuit, which includes a diode array and the timing scanning circuit disclosed in the foregoing embodiments; this application may also propose an electronic device including a diode array driving circuit, which is manufactured as a driving device for an LED array, wherein the electronic device may be a smart home device.

[0091] The following illustration uses an n x m diode array as an example. The diode array includes n columns of diode groups, where n represents the target scan quantity. Each column of diode groups includes m diodes. The timing scan circuit is equipped with m+1 drive I / O terminals to connect to the two poles of the corresponding diodes in the diode array. It is worth noting that the n x m diode array belongs to the prior art disclosed n column m row diode array. The different diode connection diagrams and their connection diagrams with the m+1 drive I / O terminals do not need to be elaborated.

[0092] Each diode is used to receive the corresponding two electrode signals and the corresponding enable signal configured by the timing scan circuit through the drive I / O terminal. Specifically, these are the cathode data signal, cathode enable signal, anode data signal, and anode enable signal corresponding to the diode to be scanned. A single diode can form a drive signal group. n and m are both integers, but they are not necessarily equal.

[0093] The m+1 driving I / O terminals are distributed row-by-row according to the same column of diodes, starting from 0 and sequentially labeled as driving I / O terminal zero to driving I / O terminal m. The address and on / off state of each diode in the diode array are configurable. The level signals of the driving I / O terminals connected to each diode can be matched according to the differences in the matrix type to be scanned, and the enable signals for each diode drive can be automatically synchronized. The address of the current diode is automatically loaded before driving the diode to be scanned.

[0094] In the i-th column of the diode group, the first electrode of each diode is connected to the (i-1)-th driving IO terminal, and the second electrode of each diode is connected to each driving IO terminal except the (i-1)-th driving IO terminal. The second electrodes of different diodes are not repeatedly connected to the same driving IO terminal, so that each driving IO terminal in the i-th column of the diode group except the (i-1)-th driving IO terminal is connected. Here, i is an integer greater than or equal to 1, i is less than or equal to n, n is an integer greater than or equal to 1, and n is less than or equal to m+1.

[0095] The timing scanning circuit controls the lighting or extinguishing of each diode by configuring the cathode data signal and anode data signal of the driving IO terminal connected to the two poles of each diode respectively; when the first pole is the anode, the second pole is the cathode; or, when the first pole is the cathode, the second pole is the anode.

[0096] In some embodiments, when n=m, the diode array is an m×m diode lighting array, which enables the timing scanning circuit to scan the m×m matrix type diode lighting array; the diodes in the m×m diode lighting array are connected to m+1 driving I / O ports, and the m×m diode lighting array has m rows and m columns of diodes; when m is odd or even, i is greater than or equal to 1 and i is less than or equal to m.

[0097] In the diode group of column i, the anodes of the diodes in rows i to m are all connected to the (i-1)th driving IO terminal; in the diode group of column i, the cathodes of the diodes in row j are connected to the jth driving IO terminal; j is greater than or equal to i, and j is less than or equal to m; in the diode group of column i, the diodes whose anodes are connected to the (i-1)th driving IO terminal are marked as positive diodes, such that: the positive diodes in row i are set in columns 1 to i; in row i, the cathodes of the positive diodes in columns 1 to i are all connected to the ith driving IO terminal; in row i, the anodes of the diodes in column p are connected to the (p-1)th driving IO terminal; p is greater than or equal to 1, and p is less than or equal to i.

[0098] When i is greater than or equal to 2, in the diode group of column i, the anodes of the diodes from row 1 to row i-1 are all connected to the i-th driving IO terminal; in the diode group of column i, the cathodes of the diodes in row k from row 1 to row i-1 are connected to the k-1 driving IO terminal, where k is counted from 1 to i-1; in the diode group of column i, the diodes whose anodes are connected to the i-1 driving IO terminal are marked as reverse-connected diodes, such that: in row i1, the reverse-connected diodes are set in columns i1+1 to m, where i1 is counted from 1 to m-1; in row i1, the cathodes of the reverse-connected diodes in columns i1+1 to m are all connected to the i1-1 driving IO terminal; in row i1, the anodes of the diodes in column q from column i1+1 to m are connected to the q-th driving IO terminal, where q is counted from 2 to m.

[0099] In other embodiments, when n=m+1, the diode array is an m×m+1 diode lighting array, which enables the timing scanning circuit to scan the m×m+1 matrix type diode lighting array; the diodes in the m×m+1 diode array are connected to m+1 driving I / O ports, and the m×m+1 diode lighting array has m rows and m+1 columns of diodes; where m is odd or even, ix is ​​greater than or equal to 1 and ix is ​​less than or equal to m+1; iy is greater than or equal to 1 and iy is less than or equal to m.

[0100] In column ix, the anodes of diodes from row iy to row m are all connected to the iy-1 driving IO terminal; in column ix, among the diodes from row iy to row m, the cathode of the diode in row j is connected to the j driving IO terminal; j is greater than or equal to iy, and j is less than or equal to m; in column ix, diodes whose anodes are connected to the iy-1 driving IO terminal are marked as positive diodes, such that: positive diodes in row iy are set in columns 1 to iy; in row iy, the cathodes of positive diodes from column 1 to column iy are all connected to the iy driving IO terminal; in row iy, among the positive diodes from column 1 to column iy, the anode of the diode in column p is connected to the p-1 driving IO terminal; where p is greater than or equal to 1, and p is less than or equal to iy.

[0101] When ix is ​​greater than or equal to 2, in column ix, the anodes of diodes from row 1 to row ix-1 are all connected to the ixth driving IO terminal; in column ix, among the diodes from row 1 to row ix-1, the cathode of the diode in row k is connected to the k-1 driving IO terminal, k is greater than or equal to 1, and k is less than or equal to ix-1; in column ix, diodes whose anodes are connected to the ix-1 driving IO terminal are marked as reverse-connected diodes, such that: in row iy1, reverse-connected diodes are set in columns iy1+1 to m+1; iy1 is greater than or equal to 1, and iy1 is less than or equal to m+1; in row iy1, the cathodes of reverse-connected diodes from column iy1+1 to column m+1 are all connected to the iy1-1 driving IO terminal; in row iy1, among the reverse-connected diodes from column iy1+1 to column m+1, the anode of the diode in column q is connected to the q driving IO terminal, q is greater than or equal to 2, and q is less than or equal to m+1.

[0102] The number of diodes required to be configured in the diode combination unit within the diode array is equal to the number of anode scan logic circuits required to be designed within the timing scan circuit.

[0103] Within the diode array: in the same row, a diode combination unit is composed of two adjacent columns of forward-connected diodes or two adjacent columns of reverse-connected diodes; in the same row, the diodes in two adjacent diode combination units do not overlap; a diode combination unit is composed of two adjacent diodes whose cathodes are connected together in the diode array, and the diode combination unit includes a first unit diode and a second unit diode, wherein the first unit diode and the second unit diode are forward-connected diodes in two adjacent columns, or the first unit diode and the second unit diode are reverse-connected diodes in two adjacent columns.

[0104] In the same row of the diode array, starting from the first column, the positive-connected diodes of two adjacent columns are sequentially combined to form a diode combination unit, and the diodes in the two adjacent diode combination units formed sequentially are not repeated; if there is only one positive-connected diode in the same row, it is not combined into a diode combination unit; if there is only one positive-connected diode remaining in the same row and it is not combined into a diode combination unit, then the remaining positive-connected diode is not combined into a diode combination unit.

[0105] In the same row of the diode array, starting from the first column, the reverse-connected diodes of adjacent columns are sequentially combined to form a diode combination unit, and the diodes in the two adjacent diode combination units formed sequentially are not repeated; if there is only one reverse-connected diode in the same row, it is not combined to form a diode combination unit; if there is only one remaining reverse-connected diode in the same row and it is not combined to form a diode combination unit, then the remaining reverse-connected diode is not combined to form a diode combination unit.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A timing scanning circuit for scanning diodes, characterized in that, The timing scanning circuit includes a cathode scanning logic circuit and at least two anode scanning logic circuits; The cathode scanning logic circuit is connected to each anode scanning logic circuit; Each anode scan logic circuit is used to configure the enable signal generated by the level signal and control level signal at the anode of a diode. The cathode scan logic circuit is used to configure the enable signal generated by the level signal and control level signal at the cathode of all diodes configured by the anode scan logic circuits, so as to drive some or all of the diodes to be scanned to light up. The cathodes of the diodes configured by all anode scan logic circuits are connected together, and the diodes configured by all anode scan logic circuits are the diodes to be scanned.

2. The timing scanning circuit according to claim 1, characterized in that, The at least two anode scanning logic circuits include a first anode scanning logic circuit and a second anode scanning logic circuit; the structure of the first anode scanning logic circuit and the structure of the second anode scanning logic circuit are the same; The diodes to be scanned currently include the diodes required for the first anode scan logic circuit and the diodes required for the second anode scan logic circuit. The cathode scanning logic circuit is used to configure the cathode data signal and cathode enable signal corresponding to the diode to be scanned. The first anode scanning logic circuit is used to configure the first anode data signal and the first anode enable signal corresponding to the diode to be scanned. The second anode scanning logic circuit is used to configure the second anode data signal and the second anode enable signal corresponding to the diode to be scanned. In this circuit, the voltage level signal at the cathode of the diode configured in the cathode scanning logic circuit is the cathode data signal, and the enable signal that controls the generation of the cathode data signal is the cathode enable signal; the voltage level signal at the anode of the diode configured in the first anode scanning logic circuit is the first anode data signal, and the enable signal that controls the generation of the first anode data signal is the first anode enable signal; the voltage level signal at the anode of the diode configured in the second anode scanning logic circuit is the second anode data signal, and the enable signal that controls the generation of the second anode data signal is the second anode enable signal. The diode combination unit is composed of diodes configured by all anode scan logic circuits; the diode combination unit includes a first unit diode and a second unit diode.

3. The timing scanning circuit according to claim 2, characterized in that, The method for configuring the cathode data signal corresponding to the diode to be scanned by the cathode scanning logic circuit includes: The cathode scanning logic circuit is used to configure the second anode enable delay target pulse as the cathode flag signal when it is pre-determined that the diode with the longest lighting time in the currently selected diode combination unit is the second unit diode and the second lighting flag signal is valid. The cathode scanning logic circuit is used to configure the first anode enable delay target pulse as the cathode flag signal when it is pre-determined that the diode with the longest lighting time in the currently selected diode combination unit is the first unit diode, the first lighting flag signal is valid and the second lighting flag signal is invalid. The cathode scanning logic circuit is used to configure the cathode data signal corresponding to the diode to be scanned to a high level when the rising edge of the system clock arrives and the cathode flag signal is high, until the lamp start signal is valid, and then configure the cathode data signal corresponding to the diode to be scanned to a low level.

4. The timing scanning circuit according to claim 3, characterized in that, The method by which the cathode scanning logic circuit configures the cathode enable signal corresponding to the diode to be scanned includes: The cathode scanning logic circuit is used to select the rising edge capture signal of the second anode data signal as the cathode enable signal when the second lighting indicator signal is valid. The cathode scanning logic circuit is used to select the rising edge capture signal of the first anode data signal as the cathode enable signal when the first lighting indicator signal is valid and the second lighting indicator signal is invalid. The cathode scanning logic circuit is used to configure a low level as a cathode enable signal when both the first and second light-up indicator signals are invalid. The cathode scanning logic circuit is used to configure the cathode enable signal to be valid when the rising edge of the system clock arrives and the cathode enable flag signal is high.

5. The timing scanning circuit according to claim 4, characterized in that, The cathode scanning logic circuit includes a first flip-flop, a first selector, a second selector, and a third selector; The zero input terminal of the first selector is used to input the second anode enable delay target pulse, the first input terminal of the first selector is used to input the first anode enable delay target pulse, and the selection terminal of the first selector is used to input the lamp lighting time comparison result. The output of the first selector is connected to the first input of the third selector. When the lighting time of the first diode is greater than or equal to the lighting time of the second diode, the lighting time comparison result is a high level to select the first anode and enable the delayed target pulse output to the first input of the third selector. When the lighting time of the first diode is less than the lighting time of the second diode, the lighting time comparison result is a low level to select the second anode and enable the delayed target pulse output to the zero input of the third selector. The zero input of the second selector is low. The first input of the second selector is connected to the first input of the first selector to jointly input the first anode enable delay target pulse. The selection terminal of the second selector is used to input the first lighting indicator signal. The selection terminal of the third selector is used to input the second lighting indicator signal. The zero input of the third selector is connected to the output of the second selector. The output of the third selector is used to output the second anode enable delay target pulse as a cathode indicator signal when the second lighting indicator signal is valid. The output of the third selector is also used to output the first anode enable delay target pulse as a cathode indicator signal when the second lighting indicator signal is invalid and the first lighting indicator signal is valid. The output of the third selector is connected to the first flip-flop. The enable terminal of the first flip-flop is used to input the light-on start signal. The output terminal of the first flip-flop is used to output the cathode data signal. Specifically, the output terminal of the first flip-flop is used to output the cathode data signal at a high level when the rising edge of the system clock arrives and the cathode flag signal is high. The output terminal of the first flip-flop is used to output the cathode data signal at a low level when the light-on start signal is valid.

6. The timing scanning circuit according to claim 5, characterized in that, The cathode scanning logic circuit also includes a second flip-flop, a fourth selector, and a fifth selector; The zero input of the fourth selector is used to input a low level. The first input of the fourth selector is used to input the rising edge capture signal of the first anode data signal. The selection input of the fourth selector is used to input the first light-on flag signal. The output of the fourth selector is connected to the zero input of the fifth selector. The selection input of the fifth selector is used to input the second light-on flag signal. The first input of the fifth selector is used to input the rising edge capture signal of the second anode data signal. The output of the fifth selector is used to select the rising edge capture signal of the second anode data signal as the cathode enable flag signal when the second light-on flag signal is valid. The output of the fifth selector is also used to select the rising edge capture signal of the first anode data signal as the cathode enable flag signal when the first light-on flag signal is valid and the second light-on flag signal is invalid. The output of the fifth selector is connected to the second flip-flop, and the output of the second flip-flop is used to output the cathode enable signal. Specifically, the output of the second flip-flop is used to configure the cathode enable signal to be valid and output when the rising edge of the system clock arrives and the cathode enable flag signal is high.

7. The timing scanning circuit according to claim 2, characterized in that, The method by which the first anode scanning logic circuit configures the first anode data signal corresponding to the diode to be scanned includes: The first anode scanning logic circuit is used to control the first anode enable signal to be delayed by one system clock cycle to output a first anode enable delay signal, then control the first anode enable delay signal to be delayed by one system clock cycle to output a first second anode enable delay signal, then control the first second anode enable delay signal to be delayed by one system clock cycle to output a first third anode enable delay signal, then obtain the rising edge capture signal of the first second anode enable delay signal through the logical operation between the first second anode enable delay signal and the first third anode enable delay signal, and configure the rising edge capture signal of the first second anode enable delay signal as the first anode enable delay target pulse; The first anode scanning logic circuit is used to set the first anode data signal to a high level when the rising edge of the system clock arrives, provided that the lighting start signal and the first lighting flag signal are valid, and the first anode data signal is set to a low level when the first anode enable delay target pulse is valid.

8. The timing scanning circuit according to claim 7, characterized in that, The method by which the first anode scan logic circuit configures the first anode enable signal corresponding to the diode to be scanned includes: The first anode scanning logic circuit is used to control the first anode data signal to delay by one system clock cycle to output a first anode delay signal, and then control the first anode delay signal to delay by one system clock cycle to output a first second anode delay signal. The rising edge capture signal of the first anode delay signal is obtained through the logical operation between the first anode delay signal and the first second anode delay signal. The rising edge capture signal and the falling edge capture signal of the first anode data signal are obtained through the logical operation between the first anode data signal and the first anode delay signal, respectively. The falling edge capture signal of the first anode data signal is configured as the lamp-on end signal corresponding to the first unit diode. The first anode scanning logic circuit is configured to enable the first anode enable signal when the rising edge of the system clock arrives, if the rising edge capture signal of the first anode delay signal is high and the first light-up flag signal is valid, and drive the first counter to start counting until the count value of the first counter reaches the first light-up time, and then configure the first anode enable signal to be invalid; wherein, the first counter is a counter built into the first anode scanning logic circuit.

9. The timing scanning circuit according to claim 8, characterized in that, The first anode scan logic circuit includes a third flip-flop, a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, and a first AND gate; The data input terminal of the third flip-flop is used to input the first anode enable signal, and then delay the first anode enable signal by one system clock cycle to output the first anode enable delay signal; the data output terminal of the third flip-flop is connected to the data input terminal of the fourth flip-flop; the data output terminal of the third flip-flop is used to provide the first anode enable delay signal to the data input terminal of the fourth flip-flop; the fourth flip-flop is used to delay the first anode enable delay signal by one system clock cycle to output the first second anode enable delay signal; the data output terminal of the fourth flip-flop is connected to the data input terminal of the fifth flip-flop; the data output terminal of the fourth flip-flop is used to provide the first second anode enable delay signal to the data input terminal of the fifth flip-flop; the fifth flip-flop is used to delay the first second anode enable delay signal by one system clock cycle to output the first third anode enable delay signal; The data output terminal of the fifth flip-flop is connected to the first input terminal of the first AND gate. The fifth flip-flop is used to provide the first tri-anode enable delay signal to the first input terminal of the first AND gate. The data output terminal of the fourth flip-flop is connected to the second input terminal of the first AND gate. The fourth flip-flop is used to provide the first dual-anode enable delay signal to the second input terminal of the first AND gate. The first AND gate is used to control the first two anode enable delay signal and the first three anode enable delay signal to perform an AND logic operation to obtain the rising edge capture signal of the first two anode enable delay signal, and configure the rising edge capture signal of the first two anode enable delay signal as the first anode enable delay target pulse output; The output of the first AND gate is connected to the enable terminal of the sixth flip-flop. The output of the first AND gate is used to provide the first anode enable delay target pulse to the enable terminal of the sixth flip-flop. The sixth flip-flop is used to set the first anode data signal to a high level when the rising edge of the system clock arrives, provided that the lighting start signal is valid and the first lighting flag signal is valid, until the first anode enable delay target pulse is valid, at which point the first anode data signal is set to a low level.

10. The timing scanning circuit according to claim 9, characterized in that, The first anode scan logic circuit also includes a seventh flip-flop, an eighth flip-flop, a ninth flip-flop, a second AND gate, and a third AND gate; The data output terminal of the sixth flip-flop is connected to the data input terminal of the seventh flip-flop. The data output terminal of the sixth flip-flop is used to provide the first anode data signal for real-time setting to the data input terminal of the seventh flip-flop. The data input terminal of the seventh flip-flop is used to input the first anode data signal, and then delay the first anode data signal by one system clock cycle to output the first anode delayed signal; The data output terminal of the seventh flip-flop is connected to the data input terminal of the eighth flip-flop; the data output terminal of the seventh flip-flop is used to provide the first anode delay signal to the data input terminal of the eighth flip-flop; the eighth flip-flop is used to delay the first anode delay signal by one system clock cycle and then output the first anode delay signal. The data output terminal of the eighth flip-flop is connected to the first input terminal of the second AND gate, and the data output terminal of the eighth flip-flop is used to provide a first dual-anode delay signal to the first input terminal of the second AND gate. The data output terminal of the seventh flip-flop is connected to the second input terminal of the second AND gate, and the data output terminal of the seventh flip-flop is used to provide a first anode delay signal to the second input terminal of the second AND gate. The second AND gate is used to control the first anode delay signal and the first second anode delay signal to perform an AND logic operation to obtain the rising edge capture signal of the first anode delay signal; The output of the second AND gate is connected to the first input of the third AND gate. The output of the second AND gate is used to provide the rising edge capture signal of the first anode delay signal to the first input of the third AND gate. The second input of the third AND gate is used to input the first light-up indicator signal; the third AND gate is used to perform an AND logic operation on the rising edge capture signal of the first anode delay signal and the first light-up indicator signal to obtain the first AND result signal. The output of the third AND gate is connected to the enable terminal of the ninth flip-flop. The output of the third AND gate is used to provide the first AND result signal to the enable terminal of the ninth flip-flop. The ninth flip-flop is used to configure the first anode enable signal to be valid when the rising edge of the system clock arrives, if the rising edge capture signal of the first anode delay signal is high and the first light-up flag signal is valid. The ninth flip-flop is connected to the counting output of the first counter. The ninth flip-flop is used to configure the first anode enable signal to be invalid when the count value of the first counter reaches the first lighting time. The first counter is used to count once each time the rising edge of the system clock arrives and the first anode enable signal is valid, until the count value reaches the first lighting time, at which point the count value is cleared. The data output terminal of the ninth flip-flop is connected to the data input terminal of the third flip-flop. The data output terminal of the ninth flip-flop is used to provide the first anode enable signal for real-time setting of the data input terminal of the third flip-flop.

11. The timing scanning circuit according to claim 10, characterized in that, The first anode scanning logic circuit further includes a fourth AND gate; the data input terminal of the seventh flip-flop is connected to the first input terminal of the fourth AND gate, and the first input terminal of the fourth AND gate is used to input the first anode data signal; the data output terminal of the seventh flip-flop is connected to the second input terminal of the fourth AND gate, and the data output terminal of the seventh flip-flop is used to provide a first anode delay signal to the second input terminal of the fourth AND gate; the fourth AND gate is used to perform a logical AND operation on the first anode data signal and the first anode delay signal to obtain the rising edge capture signal and the falling edge capture signal of the first anode data signal, respectively.

12. The timing scanning circuit according to claim 2, characterized in that, The method for configuring the second anode scan logic circuit to generate the second anode data signal corresponding to the diode to be scanned includes: The second anode scanning logic circuit is used to control the second anode enable signal to be delayed by one system clock cycle to output a second first anode enable delay signal, then control the second first anode enable delay signal to be delayed by one system clock cycle to output a second second anode enable delay signal, then control the second second anode enable delay signal to be delayed by one system clock cycle to output a second third anode enable delay signal, then obtain the rising edge capture signal of the second second anode enable delay signal through the logical operation between the second second anode enable delay signal and the second third anode enable delay signal, and configure the rising edge capture signal of the second second anode enable delay signal as the second anode enable delay target pulse; The second anode scanning logic circuit is used to set the second anode data signal to a high level when the rising edge of the system clock arrives, provided that the lighting start signal is valid and the second lighting flag signal is valid, until the second anode enable delay target pulse is valid, at which point the second anode data signal is set to a low level.

13. The timing scanning circuit according to claim 12, characterized in that, The method by which the second anode scan logic circuit configures the second anode enable signal corresponding to the diode to be scanned includes: The second anode scanning logic circuit is used to control the second anode data signal to delay by one system clock cycle to output a second first anode delayed signal, and then control the second first anode delayed signal to delay by one system clock cycle to output a second second anode delayed signal. The rising edge capture signal of the second first anode delayed signal is obtained through the logical operation between the second first anode delayed signal and the second second anode delayed signal. The rising edge capture signal of the first anode data signal and the falling edge capture signal of the second anode data signal are also obtained through the logical operation between the second anode data signal and the second first anode delayed signal. The falling edge capture signal of the second anode data signal is configured as the lamp-on end signal corresponding to the second unit diode. The second anode scanning logic circuit is configured to enable the second anode enable signal when the rising edge of the system clock arrives, provided that the rising edge capture signal of the second anode delay signal is high and the second light-up flag signal is valid. This enables the second counter to start counting until the count value reaches the second light-up time, at which point the second anode enable signal is disabled. The second counter is a built-in counter in the second anode scanning logic circuit used to time the duration for which the second anode enable signal remains valid.

14. The logic control circuit according to claim 3, characterized in that, The timing scanning circuit is also used to input single-lamp indicator signals and designated lighting indicator signals; The timing scanning circuit is used to illuminate only one diode in the currently selected diode combination unit when the single-lamp indicator signal is valid, and to illuminate all diodes in the currently selected diode combination unit when the single-lamp indicator signal is invalid. The timing scanning circuit is used to illuminate only the second diode in the currently selected diode combination unit when the specified illumination flag signal is valid, and to illuminate only the first diode in the currently selected diode combination unit when the specified illumination flag signal is invalid.

15. The timing scanning circuit according to claim 14, characterized in that, The timing scanning circuit is used to illuminate only the second unit diode in the currently selected diode combination unit when both the single lamp indicator signal and the specified lighting indicator signal are valid, and to determine that the second lighting indicator signal is valid. The timing scanning circuit is used to illuminate only the first unit diode in the currently selected diode combination unit when the single lamp indicator signal is valid and the specified lighting indicator signal is invalid, and to determine that the first lighting indicator signal is valid. The timing scanning circuit is used to illuminate at least the second unit diode in the currently selected diode combination unit when the single lamp indicator signal is invalid or the designated lighting indicator signal is valid, and to determine that the second lighting indicator signal is valid. The timing scanning circuit is used to illuminate at least the first unit diode in the currently selected diode combination unit when the single lamp indicator signal is invalid or the designated lighting indicator signal is valid, and to determine that the first lighting indicator signal is valid.

16. The timing scanning circuit according to claim 15, characterized in that, The timing scanning circuit also includes a lamp-on end indicator circuit; the lamp-on end indicator circuit is connected to each anode scanning logic circuit. The lighting end indicator circuit is used to select the lighting end signal output corresponding to the longest lighting time among the diodes configured in all anode scanning logic circuits in advance, so as to drive all the diodes to be scanned at the moment to turn off.

17. The timing scanning circuit according to claim 16, characterized in that, The method by which the lighting end indicator circuit selects the lighting end signal output corresponding to the longest lighting time among all diodes configured in the anode scan logic circuit when determining the lighting end time includes: l The lighting end indicator circuit is used to receive the lighting time comparison result and, based on the lighting time comparison result, select the lighting end signal corresponding to the diode with the longest lighting time among the diodes currently to be scanned. The lighting end indicator circuit is also used to select the lighting end signal corresponding to the first unit diode to output when the single lamp indicator signal is valid and the designated lighting indicator signal is invalid. The lighting end indicator circuit is also used to select the lighting end signal output corresponding to the second unit diode when the single lamp indicator signal is valid and the designated lighting indicator signal is valid; The lighting end indicator circuit is also used to select the diode with the longest lighting time among the diodes currently being scanned and output the lighting end signal when the single lamp indicator signal is invalid.

18. The timing scanning circuit according to claim 17, characterized in that, The lighting end indicator circuit includes a sixth selector, a seventh selector, and an eighth selector; The zero input terminal of the sixth selector is connected to the first input terminal of the seventh selector to input the lighting end signal corresponding to the second unit diode; the first input terminal of the sixth selector and the zero input terminal of the seventh selector are connected to input the lighting end signal corresponding to the first unit diode. The selection terminal of the sixth selector is used to input the comparison result of the lighting time; The sixth selector is used to output the lighting end signal of the diode with the longest lighting time among the diodes currently being scanned; The selection terminal of the seventh selector is used to input the specified illuminated flag signal; The seventh selector is used to select the lighting end signal output corresponding to the first unit diode when the specified lighting indicator signal is invalid; The seventh selector is used to select the lighting end signal output corresponding to the second unit diode when the specified lighting indicator signal is valid; The zeroth input of the eighth selector is connected to the output of the sixth selector, and the first input of the eighth selector is connected to the output of the seventh selector. The selection terminal of the eighth selector is used to input the single-lamp indicator signal; the eighth selector is used to select the lighting end signal output by the sixth selector when the single-lamp indicator signal is invalid. The eighth selector is used to select the lighting end signal output from the seventh selector when the single-lamp indicator signal is valid.

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