Display device

Abstract

A display device includes a display panel having an active area and a non-active area, and including a circuit area in which a scan circuit supplying a scan signal to a sub-pixel is positioned and a pixel area having the sub-pixel within the active area, the pixel area and the circuit area being alternately disposed, an inverter circuit located in the non-active area and configured to receive a clock signal supplied to the scan circuit, invert the clock signal, and output an inverted clock signal, a clock line to which the clock signal is applied and which extends along the circuit area and is connected to the scan circuit, and an inverted clock line to which the inverted clock signal is applied and which extends from the inverter circuit along the circuit area, wherein the inverted clock line is adjacent to the clock line and extends in the same direction.

Description

Cross-references to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0011977, filed on January 24, 2025, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] With the development of the information society, the demand for display devices used to display images is increasing in various forms.

[0004] Organic light-emitting display devices (one of various types of display devices) are widely used because of their advantages of low power consumption, small size, light weight, and thinness. Recently, electroluminescent display devices with gate-in-panel (GIP) structures have been widely used, in which scanning circuits that generate scanning signals to be supplied to the gate electrodes of switching transistors included in pixels are formed directly on both sides of the active region.

[0005] However, in order to achieve narrow bezels in display devices, gate driver structures in active regions (GIAs) have recently been developed, in which scanning circuitry is distributed within the active region.

[0006] However, the problem with the GIA structure is that the scanning circuit needs to be placed in a very narrow space within the active area and directly adjacent to the pixel, and therefore the clock signal supplied to the scanning circuit is coupled to the data line of the pixel, which degrades image quality. Summary of the Invention

[0007] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems due to the limitations and disadvantages of related technologies.

[0008] The purpose of this disclosure is to provide a display device for reducing signal interference, such as coupling that may occur due to clock lines located in the circuit area.

[0009] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will become apparent in part to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display panel having an active region and an active region, and comprising: a plurality of pixel regions located within the active region, and a plurality of sub-pixels positioned within the plurality of pixel regions; and a plurality of circuit regions alternately disposed within the active region, and a scanning circuit supplying a scanning signal to the plurality of sub-pixels located within the plurality of circuit regions; an inverter circuit located within the active region and configured to receive a clock signal supplied to the scanning circuit, invert the received clock signal, and output an inverted clock signal; a clock line to which the clock signal is applied, and the clock line extends along the circuit regions and is connected to the scanning circuit; and an inverted clock line to which the inverted clock signal is applied, and the inverted clock line extends along the circuit regions from the inverter circuit, wherein the inverted clock line is adjacent to the clock line and extends in the same direction.

[0011] The inverter circuit may include a first inverter transistor and a second inverter transistor. The first inverter transistor may include a gate electrode connected to the clock line, a first electrode to which a high gate voltage is applied, and a second electrode connected to the inverting clock line. The second inverter transistor may include a gate electrode connected to the clock line, a first electrode to which a low gate voltage is applied, and a second electrode connected to the inverting clock line. The first inverter transistor may be a PMOS transistor, and the second inverter transistor may be an NMOS transistor.

[0012] The inverter circuit can receive the clock signal with the gate high voltage and output the inverted clock signal with the gate low voltage, and the inverter circuit can receive the clock signal with the gate low voltage and output the inverted clock signal with the gate high voltage.

[0013] Each of the plurality of sub-pixels may include: a driving transistor located in the pixel region and electrically connected to a light-emitting element; and a switching transistor located in the pixel region and connected to the driving transistor, and the clock line may be located on an insulating layer, wherein the source and drain electrodes of each of the driving transistor and the switching transistor are located on the insulating layer.

[0014] The inverted clock line can extend parallel to the clock line while maintaining a predetermined distance from the clock line.

[0015] The inverting clock line can be located on a different layer than the layer where the clock line is located within the circuit region.

[0016] The inverting clock line may be located on: an insulating layer, with a metal layer positioned on the insulating layer, the metal layer positioned below and overlapping the semiconductor layer of the driving transistor; an insulating layer, with a metal layer positioned on the insulating layer, the metal layer positioned below and overlapping the semiconductor layer of the switching transistor; or an insulating layer, with the electrode plate of the storage capacitor connected to the driving transistor positioned on the insulating layer.

[0017] The inverting clock line and the clock line can be located on the same layer within the circuit region and spaced apart from each other.

[0018] The inverting clock line and the clock line may be spaced apart from each other on the insulating layer.

[0019] The inverting clock line can be positioned on both sides of the clock line and spaced apart from the two sides of the clock line.

[0020] The plurality of circuit regions may include a first circuit region and a second circuit region. The plurality of pixel regions may include a first pixel region and a second pixel region that are alternately positioned with the first circuit region and the second circuit region. Each of the first pixel region and the second pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged sequentially in a direction away from each of the first circuit region and the second circuit region. The first sub-pixel, the second sub-pixel, and the third sub-pixel, as well as the first data line, the second data line, and the third data line connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel, may be disposed in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.

[0021] Multiple constant voltage lines can be positioned at the two edges of each of the first circuit region and the second circuit region, and the clock line can be positioned between the multiple constant voltage lines.

[0022] The first circuit region may include an open area, the plurality of constant voltage lines are not positioned on the open area, and the clock line faces the first pixel region, and the second circuit region may not include the open area.

[0023] A line electrically connected to the first sub-pixel and having a constant voltage can be disposed between the first data line and the first circuit area, and disposed in the first sub-pixel area of ​​the first pixel area that is directly adjacent to the empty area.

[0024] The first data line disposed in the first sub-pixel region of each of the first pixel region and the second pixel region may be positioned on the side of the first sub-pixel away from the first circuit region and the second circuit region, and the third data line disposed in the third sub-pixel region of each of the first pixel region and the second pixel region may be positioned on the other side of the third sub-pixel away from the first circuit region and the second circuit region.

[0025] The second data line may be disposed adjacent to the first data line or the third data line, and a shielding line to which a constant voltage is applied may be disposed between the second data line and the data line adjacent to the second data line among the first data line and the third data line.

[0026] The first data line, the second data line, and the third data line in the first pixel region, as well as the first data line, the second data line, and the third data line in the second pixel region, can be symmetrically arranged with respect to the second circuit region.

[0027] Each of the first data line, the second data line, and the third data line in the second pixel region may be disposed on one side or the other side of the first sub-pixel, the second sub-pixel, and the third sub-pixel in the second pixel region adjacent to the second circuit region; and each of the first data line, the second data line, and the third data line in the first pixel region may be disposed on one side or the other side of the first sub-pixel, the second sub-pixel, and the third sub-pixel in the first pixel region adjacent to the second circuit region.

[0028] The display device may further include: a multiplexer circuit located in the non-active region adjacent to the first pixel region and the second pixel region; receiving data signals from a data driver; and sequentially outputting data voltages to the first data lines of the first pixel region and the first data lines of the second pixel region.

[0029] The multiplexer circuit may include: a first multiplexing transistor having a gate electrode to which a first multiplexing signal is applied, a first electrode connected to a data channel of the data driver, and a second electrode connected to a first sub-pixel located in the first pixel region via the first data line; and a second multiplexing transistor having a gate electrode to which a second multiplexing signal is applied, a first electrode connected to the data channel, and a second electrode connected to a second sub-pixel located in the second pixel region via the second data line.

[0030] The data signal input to the data channel may include a first data signal applied to the first sub-pixel through the first data line of the first pixel region and a second data signal applied to the second sub-pixel through the second data line of the second pixel region.

[0031] When the first multiplexed signal has an on-state voltage, the first data signal can be output to the first data line of the first pixel region, and when the second multiplexed signal has the on-state voltage, the second data signal can be output to the second data line of the second pixel region.

[0032] The inverting clock line may be located on the insulating layer and spaced apart from the clock line on both sides of the clock line, and the line width of the inverting clock line is equal to or less than the line width of the clock line.

[0033] The multiple constant voltage lines can be extended in the same manner as the clock lines.

[0034] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0035] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments (one or more) of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0036] Figure 1 This is a block diagram illustrating an example of the display device described in this specification;

[0037] Figure 2 It is shown Figure 1 The diagram shows the equivalent circuit and operation timing of the sub-pixels provided in the pixel shown;

[0038] Figures 3 to 6 It is used to describe Figure 2A diagram showing a specific operation of the sub-pixel equivalent circuit;

[0039] Figure 7 This is a diagram showing the arrangement structure of the data lines DL of the display panel according to a first embodiment of the present disclosure;

[0040] Figure 8 This is a diagram illustrating the arrangement structure of the data line DL of a display panel according to a modified example of the first embodiment of the present disclosure;

[0041] Figure 9 This is a diagram illustrating a multiplexer circuit MX according to an example of this disclosure;

[0042] Figure 10 It is shown Figure 9 Timing diagram of the operation method of the multiplexer circuit MX;

[0043] Figure 11 It shows that Figure 9 A diagram showing an example of a multiplexer circuit MX applied to a display panel;

[0044] Figure 12 This is a diagram illustrating a first example of a structure according to a second embodiment of the present disclosure, wherein the display panel has an inverter circuit IVC;

[0045] Figure 13 It is shown in detail Figure 12 The diagram shows the inverter circuit IVC;

[0046] Figure 14 It shows the basis Figure 12 A cross-sectional view of the display panel of the first example of the second embodiment of this disclosure;

[0047] Figure 15 This is a diagram illustrating a second example of a structure in which the display panel has an inverter circuit according to a second embodiment of the present disclosure;

[0048] Figure 16 It shows the basis Figure 15 A cross-sectional view of the display panel of a second example of a second embodiment of the present disclosure;

[0049] Figure 17 This is a diagram illustrating a third example of a structure in which the display panel has an inverter circuit according to a second embodiment of the present disclosure;

[0050] Figure 18 It shows the basis Figure 17 A cross-sectional view of the display panel of the third example of the second embodiment of this disclosure is shown. Detailed Implementation

[0051] Preferred embodiments will be described in detail below with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same parts. In the following description, detailed descriptions will be omitted where it is determined that detailed descriptions of known functions or configurations relevant to this disclosure may unnecessarily obscure the subject matter of this disclosure.

[0052] The same reference numerals refer to the same parts. Furthermore, some figures may be exaggerated to effectively describe the thickness, proportions, and dimensions of the parts. For ease of description, the scale of the parts shown in the figures differs from the actual scale and is not limited to the scale shown in the figures.

[0053] In this disclosure, when a component (or region, layer, section, etc.) is referred to as being “on”, “connected to”, or “coupled to” another component, it means that the component may be directly connected to / coupled to the other component, or a third component may be disposed between them.

[0054] "And / or" covers all possible combinations of the constituent parts.

[0055] Although the terms "first," "second," etc., can be used to describe various components, the components are not limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of this embodiment, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0056] The terms “below,” “under,” “above,” and “upper” are used to describe the relationship between components depicted in the accompanying drawings. These terms are relative concepts and are described based on the directions shown in the drawings. For example, one or more other components may be located between two components unless “immediately” or “directly” is used. The spatially relative terms “below,” “under,” “lower,” “above,” and “upper” can be used to readily describe the relationship between one element or component and other elements or components as depicted in the accompanying drawings. Thus, for example, “below” and “lower” relative to a first element may be in the opposite direction to “above” and “upper” relative to the first element.

[0057] Spatial relative terms should be understood as terms that include elements in different orientations during use or operation, in addition to the orientations depicted in the accompanying drawings. For example, when an element depicted in the accompanying drawings is inverted, an element described as being "below" or "under" another element may be placed "above" another element. Thus, the exemplary term "below" can include both the above and below orientations.

[0058] It should be understood that the terms "comprising" or "having" are intended to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0059] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be interconnected and operated in various technical ways, and the embodiments may be implemented independently of each other or may be implemented in an interconnected relationship.

[0060] Figure 1 This is a block diagram illustrating an example of a display device according to the present disclosure.

[0061] like Figure 1 As shown, a display device according to an embodiment of the present disclosure may include a display panel 10, a timing controller 11, a power circuit 12, a data driver 13, a gate driver (e.g., GIA), and a pixel circuit P.

[0062] like Figure 1 As shown, the display panel 10 may include an active region AA and an passive region NA. The passive region NA may be set along the edge of the display panel 10 and may be set around the active region AA of the display panel 10.

[0063] The active area AA can display an image based on the image signal, and the non-active area NA can include the border area of ​​the display panel 10 where no image is displayed.

[0064] An active region AA can include multiple pixel regions AP and multiple circuit regions AS.

[0065] Multiple pixel regions AP and multiple circuit regions AS can be arranged alternately in a first direction x (e.g., a horizontal direction), and thus the multiple circuit regions AS can be arranged between the multiple pixel regions AP. The multiple pixel regions AP and the multiple circuit regions AS can extend in a second direction y (e.g., a vertical direction) intersecting the first direction x.

[0066] In the following text, an example will be described in which the first direction x is the horizontal direction in which the pixel region AP and the circuit region AS are arranged alternately, and the second direction y is the vertical direction in which the pixel region AP and the circuit region AS extend.

[0067] Subpixels P can be arranged in multiple pixel regions AP, and scanning circuits GIA can be distributed in multiple circuit regions AS. Although for ease of understanding... Figure 1The diagram shows a scan circuit GIA and a pixel P, but multiple pixel circuits P can be set in multiple pixel regions AP, and multiple scan circuits GIA included in the gate driver can be distributed in multiple circuit regions AS.

[0068] In the active region AA, multiple data lines DL extending in the first direction x can intersect with multiple gate lines GL extending in the second direction y, and pixel circuits P can be arranged in a matrix at the intersection points to form a pixel array. For ease of understanding, in Figure 1 The image shows an example of a data line DL and a gate line GL intersecting each other on a pixel circuit P.

[0069] The data lines DL can be connected to the adjacent pixel circuit P in the second direction y, and the gate lines GL can be connected to the adjacent pixel circuit P in the first direction x. The data lines DL can be electrically isolated from each other, and the gate lines GL can also be electrically isolated from each other.

[0070] For example, each data line DL can be configured to extend in a first direction x within a pixel region AP, and each gate line GL can be configured to extend in a second direction y, while overlapping with multiple pixel regions AP and multiple circuit regions AS.

[0071] A pixel P can represent a variety of colors. Figure 1 The pixel P shown is an example of a unit pixel, and unit pixels can be configured by grouping multiple subpixels. For example, when a group of pixels used for color representation is defined as a unit pixel, a unit pixel can include red (R), green (G), and blue (B) subpixels, or it can include R, G, B, and white (W) subpixels.

[0072] Each subpixel may include an OLED light-emitting element and a driving element that generates a light-emitting current based on the gate-source voltage to drive the OLED light-emitting element.

[0073] An OLED (Optical Display Cell) may include an anode, a cathode, and an organic compound layer formed therebetween. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a pixel current flows through the OLED, holes passing through the hole transport layer and electrons passing through the electron transport layer move to the emitter layer, thereby generating excitons, and thus, the emitter layer can emit visible light. The organic compound layer can be replaced with an inorganic compound layer.

[0074] The driving element for each subpixel may include a low-temperature polycrystalline silicon (LTPS) or oxide thin-film transistor based on an organic substrate (or a plastic substrate), but this disclosure is not limited thereto.

[0075] The driving elements of a subpixel need to have uniform electrical characteristics (e.g., threshold voltage, electron mobility, etc.) across all pixels, but these characteristics can differ between pixels P due to variations in manufacturing processes and element properties. The electrical characteristics of the driving elements can change over display driving time, and the degree of degradation can vary between pixels P.

[0076] To compensate for this change in the electrical characteristics of the driving element, an internal compensation method can be applied to an electroluminescent display device. The internal compensation method compensates for the change in the electrical characteristics of the driving element by including an internal compensator in the pixel circuit P, such that the change does not affect the emission current. The internal compensator may include multiple switching elements implemented as thin-film transistors and at least one capacitor.

[0077] The timing controller 11 can supply digital image data D-DATA sent from the host system (not shown) to the data driver 13. The timing controller 11 can receive timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, and point clock signals from the host system, and generate timing control signals for the operation timing of the control panel drive circuit.

[0078] The timing control signals may include a gate timing control signal GDC for controlling the operating timing of the gate driver GIA, a data timing control signal DDC for controlling the operating timing of the data driver 13, and a power timing control signal for controlling the operating timing of the power circuit 12.

[0079] The host system can be an application processor (AP) in a mobile device, wearable device, or virtual / augmented reality device. Furthermore, the host system can be a motherboard of a television system, a set-top box, a navigation system, a personal computer, or a home theater system, but is not limited to these.

[0080] The data driver 13 can be connected to multiple pixels P via multiple data lines DL. The data driver 13 can generate the analog voltage required to drive the pixels P and supply that analog voltage to the data lines DL.

[0081] The data driver 13 can sample and latch the digital image data D-DATA input from the timing controller 11 based on the data timing control signal DDC to convert it into parallel data. The digital image data D-DATA is then converted into an analog data voltage according to the gamma compensation voltage in the digital-to-analog converter (DAC), and the data voltage is supplied to the pixel P via the data line DL. The data voltage can be an analog voltage value of different voltage levels and corresponds to the image grayscale level to be represented in the pixel P.

[0082] Data driver 13 may include multiple source driver ICs (not shown) connected to multiple data lines DL disposed in the active region. The source driver ICs may include shift registers, latches, level shifters, DACs, and output buffers.

[0083] The gate driver GIA may include a scan circuit GIA for generating scan signals, and may also include an EM driver (not shown) for generating transmit control signals, although in Figure 1 Not shown in the image.

[0084] The pixel circuit P can receive scan signals and emission control signals, and control the emission of the light-emitting element OLED disposed in the pixel. In the display device disclosed herein, the scan circuit GIA and the EM driver can be distributed in multiple circuit regions AS, or the scan circuit GIA can be distributed in multiple circuit regions AS, and the EM driver can be connected to each gate line GL in the non-active region.

[0085] The level shifter can receive the gate timing control signal GDC from the timing controller 11, and convert the voltage of the gate timing signal GDC into the gate turn-on voltage and the gate turn-off voltage. The level-converted gate timing signal GDC can be used as the clock signal input for the EM driver and the scan circuit GIA.

[0086] The scanning circuit GIA can sequentially supply scanning signals to the gate line GL in sync with the data voltage under the control of the timing controller 11.

[0087] Each scan signal generated by the scanning circuit GIA can be produced as a pulse signal that oscillates between the gate on-voltage and the gate off-voltage.

[0088] The gate turn-on voltage can be set to a voltage greater than the transistor's threshold voltage, and the gate turn-off voltage can be set to a voltage less than the transistor's threshold voltage. The transistor provided in the scan circuit GIA can turn on in response to the gate turn-on voltage and turn off in response to the gate turn-off voltage.

[0089] When the transistor provided in the scanning circuit GIA is a PMOS transistor, the gate turn-on voltage can be a gate low voltage (VGL), and the gate turn-off voltage can be a gate high voltage (VGH). When the transistor provided in the scanning circuit GIA is an NMOS transistor, the gate turn-on voltage can be a gate high voltage (VGH), and the gate turn-off voltage can be a gate low voltage (VGL).

[0090] The power circuit 12 can process the input power according to the power timing control signal PDC to generate a fixed high-level voltage VDD and a low-level voltage VSS, and supply them to the pixel circuit P.

[0091] Figure 2 It is shown in Figure 1 The diagram shows the equivalent circuitry and operating timing for each sub-pixel provided in the pixel diagram. Figure 2 (a) is an example of a sub-pixel equivalent circuit, and Figure 2 (b) is Figure 2 Example of the operating timing of the equivalent circuit shown in (a).

[0092] although Figure 2 (a) shows a case where the subpixel equivalent circuit includes a PMOS transistor, but this disclosure is not limited thereto, and the subpixel equivalent circuit can be applied to a case where the subpixel equivalent circuit includes an NMOS transistor or includes both a PMOS transistor and an NMOS transistor.

[0093] like Figure 2 As shown in (a), the sub-pixel equivalent circuit according to an example of this disclosure may include transistors T1 to T5, a storage capacitor Cst, a driving transistor DT, and a light-emitting element OLED.

[0094] Transistor T1 may include a gate electrode that receives a first scan signal S1 via a gate line GL, a first electrode that receives a data voltage Vdata via a data line DL, and a second electrode connected to a first node N1. Transistor T1 may supply the data voltage Vdata to the first node N1 in response to the first scan signal S1 having a gate on voltage.

[0095] The storage capacitor Cst can be connected between the first node N1 and the second node N2, and can store the voltage difference between the voltage of the first node N1 and the voltage of the second node N2.

[0096] The driving transistor DT may include a gate electrode connected to the second node (N2), a first electrode to which a driving voltage VDD is applied, and a second electrode electrically connected to the light-emitting element OLED. The driving transistor DT can receive the driving voltage VDD and generate a driving current corresponding to the voltage of the second node N2. The magnitude of the driving current may depend on the voltage of the second node N2.

[0097] Transistor T2 may include a gate electrode for receiving a second scan signal S2, a first electrode connected to a second electrode of the driving transistor DT, and a second electrode connected to a second node N2. Transistor T2 can electrically connect the second electrode of the driving transistor DT and the second node N2 in response to the second scan signal S2 having a gate on-state voltage. That is, when transistor T2 is turned on, transistor T2 can operate as a diode connecting the second electrode of the driving transistor DT to the second node N2.

[0098] Transistor T3 may include a gate electrode for receiving a transmit control signal EM, a first electrode for receiving a reference voltage Vref, and a second electrode connected to the first node N1. Transistor T3 can initialize the first node N1 by supplying the reference voltage Vref to the first node N1 in response to the transmit control signal EM having a gate on-voltage.

[0099] Transistor T4 may include a gate electrode for receiving an emission control signal EM, a first electrode connected to a driving transistor DT, and a second electrode connected to a light-emitting element OLED. Transistor T4 may supply the driving current generated in the driving transistor DT to the light-emitting element OLED in response to the emission control signal EM having a gate on-voltage.

[0100] Transistor T5 may include a gate electrode for receiving a transmit control signal EM, a first electrode for receiving a reference voltage Vref, and a second electrode connected to the anode of the light-emitting element OLED. Transistor T5 may supply the reference voltage Vref to the anode of the light-emitting element OLED in response to a second scan signal S2 having a gate on voltage, thereby initializing the anode of the light-emitting element OLED.

[0101] like Figure 2 As shown in (b), the operation of the sub-pixel equivalent circuit may include an initialization period P1, a programming period P2, a holding period P3, and an emission period P4.

[0102] During initialization P1, the second scan signal S2 and the emission control signal EM have gate turn-on voltages, and therefore the reference voltage Vref is supplied to the first node N1, the second node N2 and the anode of the light-emitting element OLED to initialize the first node N1, the second node N2 and the anode.

[0103] During programming phase P2, the threshold voltage Vth of the driving transistor DT can be sampled, and the data voltage Vdata can be programmed to the second node N2. Specifically, during programming phase P2, the first scan signal S1 and the second scan signal S2 have gate turn-on voltages, and therefore the data voltage Vdata is supplied to the first node N1, and the sum of the driving voltage VDD and the threshold voltage Vth of the driving transistor DT is supplied to the second node N2 and stored in the storage capacitor Cst.

[0104] During the hold period P3, the first scan signal S1 and the second scan signal S2, as well as the transmit control signal EM, have gate turn-off voltages, and therefore the first node N1 and the second node N2 connected to the storage capacitor Cst can be floated.

[0105] During the light-emitting period P4, the emission control signal EM has a gate turn-on voltage, and therefore the driving transistor DT can generate a driving voltage based on the level of the voltage at the second node N2 connected to the storage capacitor Cst, and supply the driving voltage to the light-emitting element OLED.

[0106] Figures 3 to 6 It is used to describe Figure 2 A diagram showing a specific operation of the sub-pixel equivalent circuit.

[0107] like Figure 3 As shown, during the initialization period, P1, the second scan signal S2, and the transmit control signal EM have gate turn-on voltages, and therefore transistors T2, T3, T4, and T5 can be turned on. Thus, the reference voltage Vref can be supplied to the first node N1 through transistor T3, to the anode of the OLED through transistor T5, and to the second node N2 through transistors T5, T4, and T2.

[0108] Therefore, during the initialization period P1, the first node N1, the second node N2, and the anode of the OLED light-emitting element can be initialized to the reference voltage Vref.

[0109] Subsequently, during programming period P2, the first scan signal S1 and the second scan signal S2 have gate on-voltages, such as... Figure 4 As shown, transistors T1 and T3, as well as the driving transistor DT, can be turned on.

[0110] Therefore, the data voltage Vdata supplied to the data line DL can be supplied to the first node N1 through transistor T1. Furthermore, when the drive voltage VDD is supplied to the second node N2 through drive transistors DT and T2, the voltage VDD+Vth, which is the sum of the drive voltage VDD and the threshold voltage Vth of drive transistor DT, can be supplied to the second node N2. At this time, the threshold voltage Vth of drive transistor DT can be sampled.

[0111] Therefore, during programming period P2, the difference between the voltage Vdata of the first node N1 and the voltage VDD+Vth of the second node N2 can be stored in the storage capacitor Cst.

[0112] like Figure 5As shown, during the hold period P3, the first scan signal S1, the second scan signal S2, and the transmit control signal EM have gate turn-off voltages, and therefore transistors T2, T3, and T5 can be turned on. Consequently, the first node N1 and the second node N2 to which the storage capacitor Cst is connected can be floated, the voltage of the first node N1 remains at Vdata, and the voltage of the second node N2 remains at VDD+Vth. Therefore, the voltage stored in the storage capacitor Cst during the programming period P2 can remain unchanged during the hold period P3.

[0113] like Figure 6 As shown, during the emission period P4, the emission control signal EM has a gate turn-on voltage, and therefore drives transistor DT, as well as transistors T3 and T4, to turn on. Thus, the reference voltage Vref can be supplied to the first node N1 through transistor T3, and the reference voltage Vref supplied to the first node N1 can be reflected by the storage capacitor Cst, and therefore the voltage of the second node N2 becomes Vref - Vdata + VDD + Vth.

[0114] Therefore, the driving transistor DT can generate a driving current based on the voltage (Vref-Vdata+VDD+Vth) of the second node N2. The generated driving current can be supplied to the light-emitting element OLED through transistor T4, and the light-emitting element OLED can emit light according to the supplied driving current.

[0115] In the display device according to this disclosure, the scanning circuits GIA can be arranged in a distributed manner within the circuit region AS of the active region. Since the scanning circuits GIA are positioned adjacent to the pixel circuits P, such as... Figure 2 As shown, the data line DL connected to the pixel circuit P can therefore be adjacent to the clock line of the scanning circuit GIA.

[0116] In this situation, because the data line DL is positioned adjacent to the clock line, they may couple with each other, and the data voltage Vdata applied through the data line DL may be distorted due to the coupling. Therefore, the image displayed on the display panel may be distorted.

[0117] In particular, this distortion of the data voltage Vdata can become more severe when the data voltage Vdata is time-divided and supplied to multiple data lines DL through the MUX circuit.

[0118] To reduce the number of source driver ICs in high-resolution display panels, the data voltage Vdata can be time-divided and applied to both the data line DL connected to one sub-pixel and the data line DL connected to another sub-pixel. In this case, the data line DL to which the data voltage Vdata is first applied by time-division can become floating. At this time, the data voltage Vdata applied to the floating data line DL can be distorted due to coupling with adjacent clock lines, and therefore relatively severe image distortion can occur.

[0119] To minimize or at least reduce the coupling between the clock line connected to the scanning circuit GIA and the data line DL connected to the sub-pixel, the data line DL can be arranged away from the clock line.

[0120] The following text describes the arrangement of the data lines DL of the subpixels within the pixel region AP.

[0121] Figure 7 This is a diagram illustrating the arrangement structure of the data lines DL of the display panel according to a first embodiment of the present disclosure.

[0122] Figure 7 The multiple circuit regions AS and multiple pixel regions AP shown correspond to Figure 1 The display panel shown is a portion of the display panel, and this disclosure is not necessarily limited to... Figure 7 .

[0123] In the following text, for ease of description, the left side of a component is described as one side, and the right side of a component is described as the other side.

[0124] like Figure 7 As shown, the display panel of this disclosure may include multiple pixel regions AP and multiple circuit regions AS located within the active region AA.

[0125] Multiple circuit regions AS may include a first circuit region AS1 and a second circuit region AS2, and multiple pixel regions AP may include a first pixel region AP1 and a second pixel region AP2 that are alternately positioned with the first circuit region AS1 and the second circuit region AS2. Figure 7 The first circuit region AS1 and the second circuit region AS2, as well as the first pixel region AP1 and the second pixel region AP2 shown, can be repeated in the first direction x and the second direction y.

[0126] like Figure 7 As shown, multiple scanning circuits GIA1 and GIA2 disposed in the first circuit region AS1 and the second circuit region AS2, and multiple sub-pixels SP1 and SP2 disposed in the first pixel region AP1 and the second pixel region AP2, can be electrically connected by a gate line GL extending in the first direction x.

[0127] The scan circuit GIA, which generates the scan signal to be supplied to the gate line GL, can be located in each of the first circuit region AS1 and the second circuit region AS2. For example, the first scan circuit GIA1 can be located in the first circuit region AS1, and the second scan circuit GIA2 can be located in the second circuit region AS2. The first scan circuit GIA1 and the second scan circuit GIA2 can each generate a scan signal and transmit the scan signal (e.g., Figure 2 The first scan circuit GIA1 and the second scan circuit GIA2 can be electrically connected to each other to generate a scan signal, and the scan signal generated by the first scan circuit GIA1 and the second scan circuit GIA2 can be supplied to the gate line GL.

[0128] In the first and second circuit regions AS1 and AS2, the multiple clock lines CLK1 to CLK4 and the multiple constant voltage lines VDD1 to VDD4 required by the first scan circuit GIA1 and the second scan circuit GIA2 can extend in the second direction y and be connected to the first and second scan circuits GIA1 and GIA2.

[0129] The clock signals required for the operation of the first scanning circuit GIA1 and the second scanning circuit GIA2 can be applied to each of the multiple clock lines CLK1 to CLK4, and the high-level constant voltage or low-level constant voltage required for the operation of the first scanning circuit GIA1 and the second scanning circuit GIA2 can be applied to the multiple constant voltage lines VDD1 to VDD4.

[0130] Multiple constant voltage lines VDD1 to VDD4 can be positioned at the two edges of the first circuit region AS1 and the second circuit region AS2, and multiple clock lines CLK1 to CLK4 can be positioned between the constant voltage lines (e.g., VDD1 and VDD2 in AS1 and VDD3 and VDD4 in AS2) in the first circuit region AS1 and the second circuit region AS2. Therefore, the multiple clock lines CLK1 to CLK4 can minimize or at least reduce coupling with data lines (e.g., DL11 and DL21) positioned in adjacent pixel regions AP1 and AP2.

[0131] The first pixel region AP1 and the second pixel region AP2 may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged sequentially in a direction away from the first circuit region AS1 and the second circuit region AS2.

[0132] For example, such as Figure 7As shown, the first pixel region AP1 located on the other side of the first circuit region AS1 may include first, second and third sub-pixel regions AP11 to AP13 arranged sequentially in a direction away from the first circuit region AS1, and the second pixel region AP2 located on the other side of the second circuit region AS2 may include first, second and third sub-pixel regions AP21 to AP23 arranged sequentially in a direction away from the second circuit region AS2.

[0133] In each of the first, second, and third sub-pixel regions AP11 to AP13 of the first pixel region AP1 and the second pixel region AP2, first, second, and third sub-pixels SP1 and SP2, and first, second, and third data lines DL1 and DL2 connected to each of the first, second, and third sub-pixels, can be set.

[0134] For example, such as Figure 7 As shown, the first sub-pixel SP1(R), the second sub-pixel SP1(G), and the third sub-pixel SP1(B), as well as the first data line DL11, the second data line DL12, and the third data line DL13, can be respectively set in the first, second, and third sub-pixel regions AP11 to AP13 of the first pixel region AP1, and the first sub-pixel SP2(R), the second sub-pixel SP2(G), and the third sub-pixel SP2(B), as well as the first data line DL21, the second data line DL22, and the third data line DL3, can be respectively set in the first, second, and third sub-pixel regions AP21 to AP23 of the second pixel region AP2.

[0135] In the first pixel region AP1 and the second pixel region AP2, the first, second, and third data lines DL1 and DL2 can be connected to the first, second, and third sub-pixels SP1 and SP2, respectively. The first, second, and third sub-pixels SP1 and SP2 can each have... Figure 2 The sub-pixel equivalent circuit is shown. The first, second, and third sub-pixels SP1 and SP2 of the first pixel region AP1 and the second pixel region AP2 can emit different colors.

[0136] For example, in the first pixel region AP1 and the second pixel region AP2, the first sub-pixels SP1(R) and SP2(R) of the first sub-pixel regions AP11 and AP21 can emit red (R), the second sub-pixels SP1(G) and SP2(G) of the second sub-pixel regions AP12 and AP22 can emit green (G), and the third sub-pixels SP1(B) and SP2(B) of the third sub-pixel regions AP13 and AP23 can emit blue (B).

[0137] When the first circuit region AS1 and the second circuit region AS2, as well as the first pixel region AP1 and the second pixel region AP2 are arranged alternately, such as Figure 7 As shown, in order to minimize or at least reduce the coupling between the multiple clock lines CLK1 to CLK4 disposed in the first circuit region AS1 and the second circuit region AS2 and the multiple data lines DL11, DL13, DL21 and DL23 disposed in the first pixel region AP1 and the second pixel region AP2, the present disclosure may arrange the first and third data lines DL11, DL13, DL21 and DL23 disposed in the first pixel region AP1 and the second pixel region AP2 to be spaced apart from the clock lines CLK1 to CLK4 disposed in the first circuit region AS1 and the second circuit region AS2.

[0138] In each of the first, second, and third sub-pixel regions AP11 to AP23 of the first pixel region AP1 and the second pixel region AP2, a reference voltage line Vref with a constant voltage and a drive voltage line VDD with a constant voltage can be set. The reference voltage line Vref and the drive voltage line VDD can be connected to each sub-pixel.

[0139] In the first and third sub-pixel regions AP11, AP13, AP21 and A23 of the first and second pixel regions AP1 and AP2, the reference voltage line Vref and the drive voltage line VDD can be set between the first and second circuit regions AS1 and AS2 and the first and third data lines DL11, DL13, DL21 and DL23.

[0140] For example, the first data line DL11, which is provided in the first sub-pixel region AP11 of the first pixel region AP1, can be positioned on the side of the first sub-pixel SP1(R) that is further away from the first circuit region AS1 than the other side, and the third data line DL13, which is provided in the third sub-pixel region AP13 of the first pixel region AP1, can be positioned on the side of the third sub-pixel SP1(B) that is further away from the second circuit region AS2.

[0141] Additionally, the first data line DL21, which is provided in the first sub-pixel region AP21 of the second pixel region AP2, can be positioned on the side of the second sub-pixel SP2(R) further away from the second circuit region AS2, and the third data line DL23, which is provided in the third sub-pixel region AP23 of the second pixel region AP2, can be positioned on the side of the third sub-pixel SP2(B) further away from the second circuit region AS1.

[0142] In this case, the second data lines DL12 and DL22 can be configured to be adjacent to the first data lines DL11 and DL21 or the third data lines DL13 and DL23 in the first pixel region AP1 and the second pixel region AP2. For example, in Figure 7 In order to minimize signal interference with the second data lines DL12 and DL22, in this disclosure, a shield line LS may be provided between the second data lines DL12 and DL22 and their adjacent data lines (e.g., DL11 and DL21). Such a shield line LS is not connected to each sub-pixel, and a constant voltage is applied to the shield line LS.

[0143] In addition, to minimize or at least reduce coupling, multiple clock lines CLK1 to CLK4 can be arranged between multiple constant voltage lines VDD1 to VDD4 in the first circuit region AS1 and the second circuit region AS2.

[0144] For example, clock lines CLK1 and CLK2 can be located between constant voltage lines VDD1 and VDD2 in the first circuit region AS1, and clock lines CLK3 and CLK4 can be located between constant voltage lines VDD3 and VDD4 in the second circuit region AS2.

[0145] Therefore, a constant voltage line can be used to minimize or at least reduce interference caused by clock lines in the first circuit region AS1 and the second circuit region AS2.

[0146] However, due to the area limitation of the display panel caused by the sub-pixels and scanning circuits provided together in a small space, at least one of the first circuit region AS1 and the second circuit region AS2 may have an open region AO in which the constant voltage line does not extend.

[0147] For example, such as Figure 7 As shown, the second circuit region AS2 may not include the open area AO, but the first circuit region AS1 may include the open area AO in which the constant voltage line VDD2 does not extend.

[0148] Specifically, such as Figure 7 As shown, in the second circuit region AS2, constant voltage lines VDD3 and VDD4 can extend in the same manner as clock lines CLK3 and CLK4, and therefore clock lines CLK3 and CLK4 do not directly face the third sub-pixel region AP13 of the adjacent first pixel region AP1 and the first sub-pixel region AP21 of the second pixel region AP2. Therefore, signal interference caused by clock lines CLK3 and CLK4 can be minimized or at least reduced by shielding from the constant voltage lines VDD3 and VDD4.

[0149] However, in Figure 7 In the first circuit region AS1, a constant voltage line (e.g., VDD2) may extend in the second direction y, but may not extend into the open region AO. In this case, a specific clock line (e.g., CLK2) may face the first sub-pixel region AP11 of the first pixel region AP1, and may be coupled between the clock line (e.g., CLK2) and the first data line DL11 of the first pixel region AP1.

[0150] To minimize or at least reduce coupling, this disclosure may place lines with constant voltage (e.g., Vref and VDD) between the first data line DL11 and the empty area AO of the first circuit region AS1 and in the first sub-pixel region AP11. Here, the lines with constant voltage (e.g., Vref and VDD) may be electrically connected to the first sub-pixel SP1(R).

[0151] In this manner, the second and third data lines (e.g., DL12, DL13, DL22, and DL23) are positioned on one side of each sub-pixel in the first pixel region AP1 and the second pixel region AP2 of this disclosure. However, considering that the first circuit region AS1 has an open area AO, the first data lines DL11 and DL21 can be positioned on the opposite side of the first sub-pixels SP1(R) and SP2(R) to the second and third data lines in the first pixel region AP1 and the second pixel region AP2. Therefore, this disclosure can reduce coupling due to the clock line of the first circuit region AS1.

[0152] However, this disclosure is not necessarily limited to Figure 7 The structure. For example, this disclosure may arrange the first data line, the second data line, and the third data line in the first pixel region AP1 and the second pixel region AP2, such that the first data line, the second data line, and the third data line are relatively far from the first circuit region AS1 having an empty region AO, and adjacent to the second circuit region AS2 without an empty region AO. This will refer to Figure 8 The description is as follows.

[0153] Figure 8 This is a diagram illustrating the arrangement structure of the data line DL of a display panel according to a modified example of the first embodiment of the present disclosure.

[0154] Omit Figure 7 and Figure 8 Redundant descriptions in, and will be Figure 8 The main description and Figure 7 The differences.

[0155] like Figure 8As shown, the first, second, and third data lines DL1 and DL2 of the first pixel region AP1 and the second pixel region AP2 can be designed to be symmetrical about the second circuit region AS2, which has no empty region AO. Figure 8 In the above, the first circuit region AS1 can have the characteristics described above. Figure 7 The open area AO described in the text, and the second circuit area AS2 may not have an open area AO.

[0156] The first data line DL11, the second data line DL12, and the third data line DL13 of the first pixel region AP1 can be disposed on the side of the first, second, and third sub-pixels SP1 adjacent to the second circuit region AS2. That is, the first data line DL11, the second data line DL12, and the third data line DL13 of the first pixel region AP1 can be disposed on the other side of the first, second, and third sub-pixels SP1, which is separated from the first circuit region AS1 having an empty region AO.

[0157] Additionally, the first data line DL21, the second data line DL22, and the third data line DL23 of the second pixel region AP2 can be disposed on the side of the first, second, and third sub-pixels SP2 of the second pixel region AP2 adjacent to the second circuit region AS2.

[0158] In this way, in this disclosure, the first, second, and third data lines DL1 of the first pixel region AP1 and the first, second, and third data lines DL2 of the second pixel region AP2 can be configured symmetrically about the second circuit region AS2. Therefore, during product inspection of the display panel, the first pixel region AP1 and the second pixel region AP2 can be inspected as a single set area, thereby further improving inspection efficiency.

[0159] exist Figure 8 In this case, the reference voltage line Vref and the drive voltage line VDD can be set between the second data line DL and the first data line DL and the third data line DL in each of the first pixel region AP1 and the second pixel region AP2, and therefore can be omitted. Figure 7 The shielded line LS is described in the text.

[0160] When operating a high-resolution display panel via multiplexed data lines (DL), Figure 7 and Figure 8 The arrangement of the data lines DL described herein can more effectively prevent distortion of the data voltage Vdata by minimizing or at least reducing the coupling used for the floating data lines DL. This will refer to... Figures 9 to 11 To describe.

[0161] Figure 9 This is a diagram illustrating a multiplexer circuit MX according to an example of this disclosure. Figure 10 It is used to describe Figure 9 The timing diagram shows the operation method of the multiplexer circuit MX, and Figure 11 It shows that there will be Figure 9 A diagram illustrating an example of a multiplexer circuit MX applied to a display panel.

[0162] Figure 11 This illustrates the application of the multiplexer circuit MX of this disclosure to a device having, according to Figure 7 The example shown is a display panel with a data line DL arrangement structure according to the first embodiment, but this disclosure is not limited thereto. For example, the multiplexer circuit MX of this disclosure can be applied to a display panel having a data line DL arrangement structure according to the first embodiment. Figure 8 The display panel with the data line DL arrangement structure shown in the second embodiment can also be applied to display panels with other data line DL arrangement structures.

[0163] In the following text, for ease of explanation, the multiplexer circuit MX of this disclosure will be described as having, according to Figure 7 An example of the arrangement structure of the data line DL in the first embodiment is shown, such as Figure 11 As shown.

[0164] In the case of high-resolution display panels, the number of data lines (DL) increases significantly, and as the number of data lines (DL) increases, the number of source driver ICs that apply the data voltage (Vdata) may also increase.

[0165] In the case of a high-resolution display panel, this disclosure allows the multiplexer circuit MX to be placed in the non-active region AA, such as... Figure 9 As shown, this is to reduce the number of source driver ICs.

[0166] The multiplexer circuit MX can be set in the non-active region AA, and can be located in the region adjacent to the first pixel region AP1 and the second pixel region AP2.

[0167] The multiplexer circuit MX can receive data signals from the source driver IC included in the data driver 13 and sequentially output the data voltage Vdata to the first data line DL1 of the first pixel region AP1 and the first data line DL2 of the second pixel region AP2.

[0168] The first pixel region AP1 and the second pixel region AP2 can be, for example... Figure 7 or Figure 8 In the pixel region described, the first data line DL1 can be a data line set in a sub-pixel region of the first pixel region AP1, and the second data line DL2 can be a data line set in a sub-pixel region of the second pixel region AP2.

[0169] For example, subpixels emitting the same color can be set in the first subpixel region AP1 and the second subpixel region AP2, and the first data line DL1 and the second data line DL2 can be included in different unit pixels and connected to the subpixels emitting the same color.

[0170] like Figure 9 As shown, the multiplexer circuit MX may include a first MUX transistor MT1 and a second MUX transistor MT2, which have input terminals that are commonly connected to the data channel CHD of the source driver IC included in the data driver 13 and output terminals that are connected to data lines of different pixel regions.

[0171] The first MUX transistor MT1 may include a gate electrode for receiving the first MUX signal Mux1, a first electrode connected to the data channel CHD of the data driver 13, and a second electrode connected to a first sub-pixel located in the first pixel region AP1 via a first data line DL1. The second electrode of the first MUX transistor may be the first output terminal OT1 of a multiplexer circuit.

[0172] The second MUX transistor MT2 may include a gate electrode for receiving the second MUX signal Mux2, a first electrode connected to the data channel CHD, and a second electrode connected to the second sub-pixel located in the second pixel region AP2 via the second data line DL2. The second electrode of the second MUX transistor may be the second output terminal OT2 of a multiplexer circuit.

[0173] The first electrodes of the first MUX transistor MT1 and the second MUX transistor MT2 can be input terminals of the multiplexer circuit MX, and can be connected together to a channel CHD provided in the source driver IC. The first output terminal OT1 of the multiplexer circuit MX can be connected to the first data line DL1 of the first sub-pixel SP1, and the second output terminal OT2 of the multiplexer circuit MX can be connected to the second data line DL2 of the second sub-pixel SP2.

[0174] Here, the first sub-pixel SP1 can be a sub-pixel located in one of the multiple sub-pixel regions AP11 to AP13 disposed in the first pixel region AP1, and the second sub-pixel SP2 can be a sub-pixel located in one of the multiple sub-pixel regions AP21 to AP23 disposed in the second sub-pixel region AP2. Here, the first and second sub-pixels can emit the same color and can be connected to the same gate line GL to receive the same first scan signal S1.

[0175] The data signals input to the data channel CHD may include a first data signal Vdata1 and a second data signal Vdata2. The first data signal Vdata1 can be applied to the first sub-pixel through the first data line DL1 of the first pixel region AP1, and the second data signal Vdata2 can be applied to the sub-pixel through the second data line DL2 of the second pixel region AP2.

[0176] like Figure 9 and Figure 10 As shown, when the first MUX signal Mux1 has a conduction voltage in the first MUX period MP1, the first data signal Vdata1 can be output to the first data line DL1 of the first pixel region AP1 through the first MUX transistor MT1, and when the second MUX signal Mux2 has a conduction voltage in the second MUX period MP2, the second data signal Vdata2 can be output to the second data line DL2 of the second pixel region AP2 through the second MUX transistor MT2.

[0177] During the first MUX period MP1, the first data line DL1 to which the first data signal Vdata1 has been applied can be floated until the first scan signal S1 with a conduction voltage is applied to the gate line GL.

[0178] Subsequently, when the second data signal Vdata2 is applied to the second data line DL2 during the second MUX period MP2 and in Figures 2 to 6 When the first scan signal S1 with a conduction voltage is applied to the gate line GL during the programming period P2 described herein, the first data voltage Vdata of the first data line DL1 can be input to the first sub-pixel, and the second data voltage Vdata of the second data line DL2 can be input to the second sub-pixel in response to the first scan signal S1.

[0179] The aforementioned multiplexer circuit MX can be connected to the first, second, and third sub-pixel regions AP11 to AP23, which are included in the first pixel region AP1 and the second pixel region AP2, as follows: Figure 11 As shown.

[0180] For example, the input terminal of the first multiplexer circuit MX1 can be connected to the first data channel CH-R of the source driver IC, the first output terminal OT11 of the first multiplexer circuit MX1 can be connected to the first data line DL11, the first data line DL11 is connected to the first sub-pixel SP1-(R) of the first pixel area AP1, and the second output terminal OT12 of the first multiplexer circuit MX1 can be connected to the first data line DL21, the first data line DL21 is connected to the first sub-pixel SP2-(R) of the second pixel area AP2.

[0181] The input terminal of the second multiplexer circuit MX2 can be connected to the second data channel CHD-G of the source driver IC. The first output terminal OT21 of the second multiplexer circuit MX2 can be connected to the second data line DL12, which is connected to the second sub-pixel SP1-(G) of the first pixel area AP1. The second output terminal OT22 of the second multiplexer circuit MX2 can be connected to the second data line DL22, which is connected to the second sub-pixel SP2-(G) of the second pixel area AP2.

[0182] The input terminal of the third multiplexer circuit MX3 can be connected to the third data channel CH-B of the source driver IC. The first output terminal OT31 of the third multiplexer circuit MX3 can be connected to the third data line DL13. The third data line DL13 is connected to the third sub-pixel SP1-(B) of the first pixel area AP1. The second output terminal OT32 of the third multiplexer circuit MX3 can be connected to the third data line DL23. The third data line DL23 is connected to the third sub-pixel SP2-(B) of the second pixel area AP2.

[0183] When the first, second, and third multiplexer circuits MX1 to MX3 are applied to the non-active area NA of the display panel, such as Figure 11 As shown, after each of the first, second, and third multiplexer circuits MX1 to MX3 outputs the first data voltage Vdata to each of the first, second, and third data lines DL1 located in the first pixel region AP1, the first, second, and third data lines DL1 can be floated until the first scan signal S1 is applied to the gate line GL.

[0184] Each of the first, second, and third multiplexer circuits MX3 outputs a second data voltage Vdata to each of the first, second, and third data lines DL2 located in the second pixel region AP2. When the on-state voltage of the first scan signal S1 is applied to the gate line GL, the first data voltage Vdata1 of each of the first, second, and third data lines DL1 located in the first pixel region AP1 and the second data voltage Vdata2 of each of the first, second, and third data lines DL2 located in the second pixel region AP2 can be input to each of the sub-pixels SP1 and SP2.

[0185] In this case, the first data voltage Vdata1 of each of the first, second and third data lines DL1 located in the first pixel region AP1 may become unstable due to floating until the first scan signal S1 is applied.

[0186] In particular, since the first sub-pixel region AP11 is directly adjacent to the open area AO of the first circuit region AS1, the first data line DL11 of the first sub-pixel region AP11 can be relatively greatly affected by the coupling attributable to the clock line (e.g., CLK2) of the first circuit region AS1.

[0187] However, this disclosure takes this into account, and the coupling effect attributable to the clock line (e.g., CLK2) of the first circuit region AS1 can be minimized or at least reduced by setting the first data line DL11 located in the first sub-pixel region AP11 on the other side of the first sub-pixel SP1(R) relatively away from the first circuit region AS1 and setting the reference voltage line Vref and the drive voltage line VDD between the first data line DL11 and the empty area AO of the first circuit region AS1.

[0188] A configuration has been described in which the arrangement of data lines DL disposed in pixel region AP is improved to reduce signal interference, such as coupling caused by clock lines located in circuit region AS. However, this disclosure is not limited thereto.

[0189] In the following, another example of a structure according to this disclosure for reducing signal interference, such as coupling caused by clock lines located in circuit region AS, will be described.

[0190] Figure 12 This is a diagram illustrating a first example of a structure according to a second embodiment of the present disclosure, wherein the display panel includes an inverter circuit IVC, and Figure 13 It is shown in detail Figure 12 The diagram shows the inverter circuit IVC.

[0191] Figure 12 (a) is a schematic diagram showing the structure in which an inverter circuit IVC is provided on the display panel 10, and Figure 12 (b) is an example used to describe the clock signal CLK applied to the clock line CL and the inverted clock signal ICLK applied to the inverted clock line IL.

[0192] In a first example of a structure in which the display panel 10 includes an inverter circuit IVC according to a second embodiment of the present disclosure, such as Figure 12 As shown in (a), multiple pixel regions and multiple circuit regions AS1 and AS2 are alternately arranged in the active region AA, while at least one inverter circuit IVC can be set in the non-active region NA. Figure 12 (a) shows an example in which the inverter circuit IVC includes a first inverter circuit IVC1 and a second inverter circuit IVC2 and is disposed on the display panel 10.

[0193] In circuit regions AS1 and AS2, the clock line CL and the inverting clock line IL are arranged adjacent to each other and can extend in the second direction y. That is, the inverting clock line IL can be arranged adjacent to the clock line CL in the same circuit regions AS1 and AS2 and extends in the second direction y parallel to the clock line CL.

[0194] The inverting clock line IL can extend along the clock line CL within circuit regions AS1 and AS2. That is, the inverting clock line IL can extend parallel to the clock line CL while maintaining a predetermined distance. For example, when the clock line CL bends within circuit regions AS1 and AS2, the inverting clock line IL can also bend at the point where the clock line CL bends.

[0195] The clock line CL and the inverting clock line IL can extend parallel to each other in the second direction y in the circuit regions AS1 and AS2, and the inverting clock line IL can extend away from the clock line CL in the first direction x (i.e., the horizontal direction) or the thickness direction z.

[0196] The clock line CL, to which the clock signal CLK is applied, can extend along circuit regions AS1 and AS2 and connect to scan circuits GIA1 and GIA2. Similarly, the inverted clock line IL, to which the inverted clock signal ICLK is applied, can extend along circuit regions AS1 and AS2 from the first inverter circuit IVC1 and the second inverter circuit IVC2. The inverted clock line IL may not be connected to scan circuits GIA1 and GIA2, and the ends of the inverted clock line IL in circuit regions AS1 and AS2 may be disconnected and not connected to any circuit.

[0197] like Figure 12 As shown in (b), the clock signal CLK can be applied to the clock line CL, and the inverted clock signal ICLK can be applied to the inverted clock line IL. That is, when the clock signal CLK has a gate high voltage, the inverted clock signal ICLK has a gate low voltage, and when the clock signal CLK has a gate low voltage, the inverted clock signal ICLK has a gate high voltage.

[0198] The inverter circuit IVC is positioned adjacent to the area where the clock line CL and the inverted clock line IL are located in the non-active region NA, and can receive the clock signal CLK supplied to the scanning circuits GIA1 and GIA2, invert the clock signal CLK, and output the inverted clock signal ICLK.

[0199] although Figure 12 (a) shows an example of an inverter circuit IVC located adjacent to each circuit region AS1 and AS2 in the non-active region NA, but this disclosure is not necessarily limited to this. Figure 12(a). For example, the inverter circuit IVC can be selectively arranged adjacent to a circuit region with an empty area AO in one of the multiple circuit regions AS1 and AS2.

[0200] For example, in Figure 12 In (a), if the first circuit region AS1 has an empty region AO and the second circuit region AS2 does not have an empty region AO, the second inverter circuit IVC2 in the first inverter circuit IVC1 and the second inverter circuit IVC2 can be omitted.

[0201] For example, when Figure 12 (a) The first inverter circuit IVC1 and the second inverter circuit IVC2 shown are applied to Figure 7 When the display panel 10 is shown, the first inverter circuit IVC1 can be arranged adjacent to the first circuit region AS1 having a free space region AO, and the second inverter circuit IVC2 can be arranged adjacent to another circuit region having a free space region AO. In this case, the clock line CL1 connected to the output terminal of the first inverter circuit IVC1 can be... Figure 7 The second clock line CLK2 is shown.

[0202] Furthermore, in the case where each of the multiple circuit regions AS1 and AS2 includes an open region AO, the first inverter circuit IVC1 and the second inverter circuit IVC2 can be positioned in the non-active region NA as adjacent to the circuit regions AS1 and AS2, such as... Figure 12 As shown in (a), but this disclosure is not necessarily limited to Figure 12 (a). With Figure 12 (b) Unlike other clock signals, when the first clock signal CLK1 and the second clock signal CLK2 are synchronized with each other, the function can be omitted. Figure 12 (a) One of the first inverter circuit IVC1 and the second inverter circuit IVC2.

[0203] More specifically, with Figure 12 (b) In the case where the second clock signal CLK2 has a gate high voltage when the first clock signal CLK1 has a gate high voltage and the second clock signal CLK2 has a gate low voltage when the first clock signal CLK1 has a gate low voltage, for example, the second inverter circuit IVC2 in the first inverter circuit IVC1 and the second inverter circuit IVC2 can be omitted, and the output terminal of the first inverter circuit IVC1 can be commonly connected to the first inverted clock line IL1 extending to the first circuit region AS1 and the second inverted clock line IL2 extending to the second circuit region AS2, such that the first inverted clock signal ICLK1 of the first inverter circuit IVC1 is applied to the present disclosure. Figure 12(a) The first inverted clock line IL1 and the second inverted clock line IL2.

[0204] like Figure 12 As shown in (a), when an inverter circuit IVC and an inverting clock line IL are provided, if there is an empty area AO in the circuit regions AS1 and AS2 where the clock line CL is provided, the signal interference caused by the clock line CL applied to the adjacent pixel region can be reduced.

[0205] For example, in this disclosure, if there is an empty area AO in the first circuit region AS1 and the second circuit region AS2 due to area limitations, the waveform of the clock signal CLK is offset by the waveform of the inverted clock signal ILK through the inverted clock line IL, which extends parallel to and adjacent to the clock line CL, thereby minimizing or at least reducing signal interference caused by coupling that can be applied by the clock signal CLK of the clock line CL to the pixels of the pixel regions AP1 to AP3 adjacent to the first circuit region AS1 and the second circuit region AS2.

[0206] like Figure 13 As shown in (a), the inverter circuit IVC may include a first inverter transistor TI1 and a second inverter transistor TI2, which have an input terminal commonly connected to the clock line CL and an output terminal commonly connected to the inverting clock line IL.

[0207] The first inverter transistor TI1 may have a gate electrode connected to the clock line CL, a first electrode to which a gate high voltage VGH is applied, and a second electrode connected to the inverting clock line IL. The second inverter transistor TI2 may have a gate electrode connected to the clock line CL, a first electrode to which a gate low voltage VGL is applied, and a second electrode connected to the inverting clock line IL. Here, the first inverter transistor TI1 may be a PMOS transistor, and the second inverter transistor TI2 may be an NMOS transistor.

[0208] like Figure 13 As shown in (b), when a clock signal CLK with a gate low voltage VGL is applied to the clock line CL connected to the input terminal of the inverter circuit IVC, the first inverter transistor TI1 is turned on, and therefore the inverted clock signal ICLK with a gate high voltage VGH can be output to the inverted clock line IL.

[0209] Furthermore, when a clock signal CLK with a gate high voltage VGH is applied to clock line CL, the second inverter transistor TI2 is turned on, and therefore an inverted clock signal ICLK with a gate low voltage VGL can be output to inverted clock line IL.

[0210] Therefore, an inverted clock signal ICLK with a voltage opposite to that of the clock signal CLK can be output to the inverted clock line IL connected to the output terminal of the inverter circuit IVC.

[0211] This disclosure allows the inverting clock line IL to be positioned adjacent to the clock line CL to eliminate noise signals caused by the clock signal CLK. In this case, as referenced above... Figure 7 As stated, when there is an empty area AO in the circuit area AS1, the noise signal caused by the clock signal CLK can be eliminated to prevent the data voltage supplied to the sub-pixel adjacent to the empty area AO from being unstable due to the clock signal CLK.

[0212] In the following text, reference will be made to Figure 14 The description includes the cross-sectional structure of the display panel 10 comprising the clock line CL and the inverting clock line IL of this disclosure.

[0213] The clock line CL and the inverting clock line IL of this disclosure can extend and be spaced apart in the horizontal or thickness direction z of the display panel 10 as described above. Figure 14 The diagram describes the structure in which the clock line CL and the inverting clock line IL are spaced apart in the thickness direction z in circuit regions AS1 and AS2.

[0214] Figure 14 It shows the basis Figure 12 A cross-sectional view of an example display panel of a first example of a second embodiment of the present disclosure is shown.

[0215] In the following text, for ease of description, the pixel area AP of the display panel 10 will be described first, and then the circuit area AS of the display panel 10 will be described. Although Figure 14 The circuit region AS in the diagram does not show transistor elements, but the circuit region AS may also include transistors that constitute the scanning circuit GIA. However, in Figure 14 Transistors are omitted, and for ease of understanding, only the clock line CL and the inverting clock line IL are shown.

[0216] according to Figure 14 In the embodiments of this disclosure shown, the substrate 100, substrate buffer layer 110, first gate insulating film 120, lower interlayer insulating film 130, element buffer layer 140, second gate insulating film 150, upper interlayer insulating film 200, planarization film 300, intermediate electrodes SD2a and SD2b, embankment BK, light-emitting element OLED, and encapsulation layer 500 can be disposed in the pixel region AP and circuit region AS of the display panel 10.

[0217] Additionally, the switching transistor ST, storage capacitor Cst, and driving transistor DT can be located in the pixel region AP, and the clock line CL and inverting clock line IL extending in the second direction y can be located in the circuit region AS. The switching transistor ST of the pixel region AP can be referenced above. Figures 2 to 6 The transistors T1 through T5 are described.

[0218] The substrate 100 can be formed of a flexible plastic material and can be flexible. The substrate 100 may also include a thin glass with flexibility. The substrate 100 can be placed in the active region AA and the non-active region NA of the display panel 10.

[0219] The substrate 100 may have a multilayer structure including an insulating material. For example, the substrate 100 may include a polymer material such as polyimide (PI) and an insulating material.

[0220] A substrate buffer layer 110 can be disposed on the substrate 100 in the active region AA and the non-active region NA. The substrate buffer layer 110 can be disposed on the substrate 100 to protect the structures on the substrate 100 that are susceptible to moisture penetration from the outside and to make the surface of the substrate 100 flat.

[0221] The substrate buffer layer 110 may include an insulating material, which may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and may include a multilayer structure containing the same or different materials.

[0222] For example, the substrate buffer layer 110 may include a multi-buffer layer 111 containing different insulating materials and an active buffer layer 112, wherein the multi-buffer layer 111 and the active buffer layer 112 are stacked.

[0223] The first gate insulating film 120 may be disposed on the active buffer layer 112 of the substrate buffer layer 110. The first gate insulating film 120 may include at least one inorganic insulating material selected from silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

[0224] The lower interlayer insulating film 130 may be disposed on the first gate insulating film 120. The lower interlayer insulating film 130 may contain inorganic insulating materials and may include one or more inorganic films selected from silicon oxide film (SiOx), silicon nitride film (SiNx), and silicon oxynitride film (SiOxNy).

[0225] The component buffer layer 140 may be disposed on the underlying interlayer insulating film 130. The component buffer layer 140 may include an inorganic insulating material. For example, the component buffer layer 140 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0226] The second gate insulating film 150 may be disposed on the first element buffer layer 140 (141), and the second gate insulating film 150 may include at least one inorganic insulating material selected from silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiOxNy).

[0227] The upper interlayer insulating film 200 can be disposed on the second gate insulating film 150 and can be formed as a multilayer structure including insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiOxNy).

[0228] The planarization film 300 can be disposed on the upper interlayer insulating film 200 and can include an insulating material. The planarization film 300 can remove the stepped portions caused by the multiple transistors disposed in each sub-pixel SP. The upper surface of the planarization film 300 can be flat and can include a material with high fluidity. For example, the planarization film 300 can include an organic insulating material.

[0229] The planarization film 300 may have a multilayer structure in which multiple layers are stacked, and for example, the planarization film 300 may include a first planarization film 310 and a second planarization film 320 stacked sequentially.

[0230] The first planarization film 310 can remove the stepped portions caused by drive circuitry such as the switching transistor ST and the drive transistor DT. The first planarization film 310 and the second planarization film 320 can have flat surfaces. For this purpose, the first planarization film 310 and the second planarization film 320 can comprise the same or different fluidic organic insulating materials.

[0231] The first intermediate electrode SD2a and the second intermediate electrode SD2b can be disposed between the first planarization film 310 and the second planarization film 320. The first intermediate electrode SD2a and the second intermediate electrode SD2b can include conductive materials, and can include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first intermediate electrode SD2a can be positioned in the pixel region AP, and the second intermediate electrode SD2b can be positioned in the circuit region AS.

[0232] The first intermediate electrode SD2a can electrically connect the light-emitting element OLED and the driving transistor DT in each sub-pixel SP. For example, the first intermediate electrode SD2a can electrically connect the driving transistor DT and the first electrode E1 (anode) of the light-emitting element OLED by penetrating the first planarization film 310 and the second planarization film 320.

[0233] The embankment BK can be located on the planarization film 300. The embankment BK can define the emission region of each sub-pixel, and the region of each sub-pixel can be defined by the embankment BK. The light-emitting element OLED can be located in the emission region.

[0234] The dam portion BK may include an organic insulating material. The dam portion BK may cover the edge of the first electrode 610 (e.g., the anode). The emitting layer EL and the second electrode E2 (e.g., the cathode) may be stacked on the portion of the first electrode E1 exposed by the dam portion BK.

[0235] The light-emitting element (OLED) is positioned on the planarization film 300 and may include a first electrode E1, an emitting layer EL, and a second electrode E2. The OLED can emit any one of the colors red (R), green (G), and blue (B).

[0236] For example, the first electrode E1, used as the anode, may comprise a conductive material. The first electrode E1 may have high reflectivity. For example, the first electrode E1 may comprise metals such as aluminum (Al) and silver (Ag). The first electrode E1 may have a multilayer structure. For example, the first electrode E1 may have a structure in which a reflective electrode made of metal is positioned between transparent electrodes made of transparent conductive materials such as ITO and IZO.

[0237] The emitting layer EL can generate light with a brightness corresponding to the voltage difference between the first electrode E1 and the second electrode E2. For example, the emitting layer EL may include an emitting material layer (EML) containing an emitting material. The emitting material may include organic materials, inorganic materials, or a mixture of materials. For example, the emitting layer EL may include an emitting material layer made of organic materials.

[0238] The emitter layer EL may include at least one of a first emitter common layer (not shown) positioned between the emitter layer EL and the first electrode E1, and a second emitter common layer (not shown) positioned between the emitter layer EL and the second electrode E2. The first emitter common layer (not shown) and the second emitter common layer (not shown) may each include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0239] The second electrode E2, used as the cathode, may include, for example, a conductive material. The second electrode E2 may include a material different from the first electrode E1. For example, the second electrode E2 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. The second electrode E2 may have a higher transmittance than the first electrode E1. Therefore, in the display panel 10 according to an embodiment of this disclosure, light generated by the emitting layer EL can pass through the second electrode E2 and be emitted.

[0240] The encapsulation layer 500 can be positioned on the light-emitting element OLED. The encapsulation layer 500 can prevent damage to the light-emitting element OLED due to external impact and moisture. The encapsulation layer 500 can have a multilayer structure. For example, the encapsulation layer 500 can be formed by alternately stacking encapsulation layers 500 made of inorganic insulating materials and encapsulation layers 500 made of organic insulating materials. Therefore, in the display panel 10 according to the embodiments of the present disclosure, damage to the light-emitting element OLED due to external impact and moisture can be effectively prevented.

[0241] The storage capacitor Cst can be positioned on the first gate insulating film 120 of the pixel region AP. For example, the storage capacitor Cst can have a first electrode plate C1a and a second electrode plate C1b. The first electrode plate C1a can be disposed between the first gate insulating film 120 and the lower interlayer insulating film 130, and the second electrode plate C1b can be disposed between the lower interlayer insulating film 130 and the element buffer layer 140. The first electrode plate C1a and the second electrode plate C1b can be insulated from each other through the lower interlayer insulating film 130.

[0242] In the storage capacitor Cst, the first electrode plate C1a can be connected to the electrode of another switching element (not shown), and the second electrode plate C1b can be electrically connected to one of the source and drain electrodes DSD1a of the driving transistor DT, as shown. Figure 14 As shown.

[0243] The switching transistor ST can be electrically connected to the driving transistor DT, and can form a configuration. Figure 2 One of the transistors in the pixel equivalent circuit shown in (a).

[0244] The switching transistor ST may include a first gate electrode G1, a first semiconductor layer ACT1, a first source electrode SSD1a, a first drain electrode SSD1b, and a first metal layer M1.

[0245] The first gate electrode G1 can be disposed between the first gate insulating film 120 and the lower interlayer insulating film 130. The first gate electrode G1 can be located in the same layer as the first electrode plate C1a of the storage capacitor Cst, and can include the same conductive material, such as a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W).

[0246] The first semiconductor layer ACT1 overlaps with the first gate electrode G1 and can be disposed between the substrate buffer layer 110 and the first gate insulating film 120, and may include low-temperature polycrystalline silicon (LTPS) semiconductor material. The first semiconductor layer ACT1 can be insulated from the first gate electrode G1 through the first gate insulating film 120.

[0247] The first source electrode SSD1a and the first drain electrode SSD1b can be disposed between the upper interlayer insulating film 200 and the planarization film 300, and can penetrate the upper interlayer insulating film 200 and the first gate insulating film 120 to contact the first semiconductor layer ACT1.

[0248] The first metal layer M1 can be disposed between the substrate 100 and the substrate buffer layer 110, and can block light incident on the first semiconductor layer ACT1 of the switching transistor ST. Although not shown, the first metal layer M1 can be connected to a voltage source supplying a constant voltage, or it can be connected to one of the first gate electrode G1 or the first source electrode SSD1a and the first drain electrode SSD1b of the switching transistor ST.

[0249] The driving transistor DT can control the driving current supplied to the light-emitting element OLED, and may include a second gate electrode G2, a second semiconductor layer ACT2, a second source electrode DSD1a, a second drain electrode DSD1b, and a second metal layer M2.

[0250] The second gate electrode G2 can be disposed between the second gate insulating film 150 and the upper interlayer insulating film 200. The second semiconductor layer ACT2 can be disposed between the element buffer layer 140 and the second gate insulating film 150, and can include an oxide semiconductor material. The oxide semiconductor material can include, for example, any of the following: IZO (InZnO) based materials, IGO (InGaO) based materials, ITO (InSnO) based materials, IGZO (InGaZnO) based materials, IGZTO (InGaZnSnO) based materials, GZTO (GaZnSnO) based materials, GZO (GaZnO) based materials, ITZO (InSnZnO) based materials, and FIZO (FeInZnO) based materials. The second semiconductor layer ACT2 can be insulated from the second gate electrode G2 through the second gate insulating film 150.

[0251] The second source electrode DSD1a and the second drain electrode DSD1b can be disposed between the upper interlayer insulating film 200 and the planarization film 300, and can penetrate the upper interlayer insulating film 200 and the second gate insulating film 150 to contact the second semiconductor layer ACT2.

[0252] The second metal layer M2 can be disposed between the lower interlayer insulating film 130 and the element buffer layer 140, and can block light incident on the second semiconductor layer ACT2 of the driving transistor DT. Although not shown, the second metal layer M2 can be connected to a voltage source supplying a constant voltage, or it can be connected to one of the second gate electrode G2 or the second source electrode DSD1a and the second drain electrode DSD1b of the driving transistor DT.

[0253] The second metal layer M2 can be located in the same layer as the second electrode plate C1b of the storage capacitor Cst, and can include the same conductive material, such as metals like aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W).

[0254] The first intermediate electrode SD2a can electrically connect the light-emitting element OLED and the driving transistor DT in each sub-pixel SP. The driving current generated by the driving transistor DT can be applied to the first intermediate electrode SD2a.

[0255] In addition, such as Figure 14 As shown, the third intermediate electrode SD2c can be disposed in the same layer as the first intermediate electrode SD2a and spaced apart from the first intermediate electrode SD2a, and the third intermediate electrode SD2c can be used as a data line DL to supply data voltage Vdata to the sub-pixel SP.

[0256] Furthermore, although not shown, another intermediate electrode (not shown) may be further disposed in the pixel region AP and spaced apart from the first intermediate electrode SD2a and the third intermediate electrode SD2c on the same layer. A high-level voltage VDD or a reference voltage Vref may be applied to such another intermediate electrode (not shown).

[0257] The second intermediate electrode SD2b can be disposed between the first planarization film 310 and the second planarization film 320 in the circuit region AS. For example, the driving voltage supplied to the sub-pixel can be applied to the second intermediate electrode SD2b, and the low-level driving voltage VSS supplied to the second electrode E2 (cathode) of the light-emitting element OLED can be applied to the second intermediate electrode SD2b.

[0258] Clock lines (e.g., CL1) can be positioned on an insulating layer, and the source electrodes SSD1a and DSD1a and the drain electrodes SSD1b and DSD1b of the driving transistor DT and the switching transistor ST can be positioned on the insulating layer.

[0259] For example, such as Figure 14 As shown, the clock line (e.g., CL1) is disposed between the upper interlayer insulating film 200 and the planarization film 300, and is located on the same layer where the source and drain electrodes of each of the driving transistor DT and the switching transistor ST are disposed, and may comprise a conductive material of the same material as the source and drain electrodes of each of the driving transistor DT and the switching transistor ST.

[0260] The inverting clock line (e.g., IL1) can be located on a different layer than the clock line CL within the circuit region AS. That is, the inverting clock line IL can be set separately from the clock line CL in the thickness direction z.

[0261] Specifically, the inverting clock line (e.g., IL1) can be located on the insulating layer where the first metal layer M1 of the switching transistor ST is located, the insulating layer where the second metal layer M2 of the driving transistor DT is located, or the insulating layer where the electrode plate of the storage capacitor Cst connected to the driving transistor DT is located.

[0262] For example, such as Figure 14 As shown, the inverting clock line (e.g., IL1) can be disposed between the substrate 100 and the substrate buffer layer 110, and is located in the same layer as the first metal layer M1 of the switching transistor ST, and can include a conductive material of the same material as the first metal layer M1.

[0263] The clock line (e.g., CL1) and the inverting clock line (e.g., IL1) may overlap with the second intermediate electrode SD2b located in the circuit region AS, and the inverting clock line (e.g., IL1) may overlap with the clock line (e.g., CL1).

[0264] As described above, the display device according to embodiments of the present disclosure includes an inverting clock line IL extending in the same direction as the clock line below the clock line (e.g., CL1) in the circuit region AS, such as... Figure 14 As shown, the coupling between the clock line (e.g., CL1) and the data line DL is reduced by using an inverted clock signal (e.g., ICLK1) to offset the clock signal (e.g., CLK1), thereby minimizing the signal interference of the clock line (e.g., CL1) to the data line DL.

[0265] like Figure 15 As shown, this disclosure can eliminate noise signals caused by the clock signal CLK by setting the inverting clock line IL adjacent to the bottom of the clock line CL. Therefore, this disclosure can reduce coupling noise that can be caused by the clock line CL.

[0266] Figure 15 This is a diagram illustrating a second example of a structure according to a second embodiment of the present disclosure, wherein the display panel has an inverter circuit, and Figure 16 Showing according to Figure 15 An example of a cross-section of a display panel of a second example of a second embodiment of the present disclosure is shown.

[0267] like Figure 15 As shown, in a second example of the structure in which the display panel 10 includes an inverter circuit IVC according to the second embodiment, the constant voltage line VL to which a constant voltage is applied can be disposed on one side of the clock line CL, and the inverting clock line IL can be disposed on the other side of the clock line CL or on the adjacent upper or lower side in the thickness direction z.

[0268] A gate high voltage or a gate low voltage can be applied to a constant voltage line VL. Figure 15 An example is shown in which a gate high voltage VGH is applied to a first constant voltage line VL1 of a first inverter circuit IVC1 and a gate low voltage VGL is applied to a second constant voltage line VL2 of a second inverter circuit IVC2.

[0269] like Figure 15 As shown, when the constant voltage line VL is set on one side of the clock line CL and the inverting clock line IL is set on the other side above or below the clock line CL, the signal interference on one side of the clock line CL is shielded by the constant voltage line VL, and the signal interference on the other side of the clock line CL is shielded by the inverting clock line IL. Therefore, the noise signal caused by the clock line CL can be eliminated, and the noise coupling caused by the clock line CL can be reduced.

[0270] When the constant voltage line VL is located on one side of the clock line CL, the constant voltage line VL can be located on the same layer as the clock line CL. Specifically, the constant voltage line VL can be positioned on an insulating layer, and the source electrodes SSD1a and DSD1a and the drain electrodes SSD1b and DSD1b of the driving transistor DT and the switching transistor ST are positioned separately from the clock line CL in the horizontal direction on this insulating layer.

[0271] For example, such as Figure 16 As shown, a constant voltage line (e.g., VL1) can be disposed between the upper interlayer insulating film 200 and the planarization film 300, and positioned on the same layer as the source and drain electrodes of the driving transistor DT and the switching transistor ST, and can include the same conductive material as the source and drain electrodes of the driving transistor DT and the switching transistor ST.

[0272] When the constant voltage line VL is positioned on one side of the clock line CL, it can be located between the clock line CL and the third intermediate electrode SD2c, which serves as the data line DL. Therefore, signal interference from the clock line CL to the data line DL can be reduced more effectively.

[0273] The inverting clock line (e.g., IL1) can be configured to be spaced apart from the clock line (CL1) in the thickness direction z, such as... Figure 16 As shown. A constant voltage line (e.g., VL1), a clock line (e.g., CL1), and an inverting clock line (e.g., IL1) can be positioned in the circuit region AS and overlap with the second intermediate electrode SD2b, and the inverting clock line (e.g., IL1) can overlap with the clock line (e.g., CL1). Since it has already been... Figure 14 The reverse clock line (e.g., IL1) is described in detail in the code, so its description is omitted.

[0274] Although the case where the inverting clock line IL is spaced apart from the clock line CL in the thickness direction z has been described as an example, this disclosure is not limited thereto. For example, the inverting clock line IL may also be spaced apart from the clock line CL in the horizontal direction x. This will be described below.

[0275] Figure 17 This is a diagram illustrating a third example of a structure according to a second embodiment of the present disclosure, wherein the display panel includes an inverter circuit. Figure 18 Showing according to Figure 17 An example of a cross-section of a display panel of a third example of a second embodiment of this disclosure is shown.

[0276] In a third example of a structure according to a second embodiment of the present disclosure, wherein the display panel 10 includes an inverter circuit IVC, the inverting clock line IL can be positioned on both sides of the clock line CL and spaced apart from it, as shown below. Figure 17 As shown.

[0277] like Figure 17 As shown, when the inverting clock line IL is positioned on both sides of the clock line CL and spaced apart from both sides of the clock line CL, noise signals caused by the clock line CL due to the clock signal CLK applied to the clock line CL can be eliminated more reliably. Figure 17 As shown, when the inverting clock line IL is positioned on both sides of the clock line CL and spaced apart from both sides of the clock line CL, the inverting clock line IL can be positioned on the same layer as the clock line CL and spaced apart from the clock line CL in the circuit regions AS1 and AS2.

[0278] For example, such as Figure 18 As shown, when the clock line CL is positioned between the upper interlayer insulating film 200 and the planarization film 300, it is similar to the source electrodes SSD1a and DSD1a and the drain electrodes SSD1b and DSD1b of the driving transistor DT and the switching transistor ST. The inverting clock line IL can also be positioned between the upper interlayer insulating film 200 and the planarization film 300, similar to the source electrodes and drain electrodes of the driving transistor DT and the switching transistor ST, and spaced apart from the clock line CL.

[0279] like Figure 18 As shown, the clock line (e.g., CL1) and the inverted clock lines (e.g., IL1) on both sides of it can overlap with the second intermediate electrode SD2b located in the circuit region AS.

[0280] In this way, the display device according to an embodiment of the present disclosure includes a clock line (e.g., CL1) extending along the circuit region AS and an inverted clock line IL extending adjacent to it in the same direction, and minimizes the signal interference of the clock line (e.g., CL1) to the data line DL by offsetting the clock signal of the clock line (e.g., CL1) by using the inverted clock signal (e.g., ICLK1) of the inverted clock line (e.g., IL1).

[0281] The linewidth of the inverting clock line (e.g., IL1) can be optimally designed to eliminate coupling between the clock signal (e.g., CLK1) applied to the clock line (e.g., CL1) and the third intermediate electrode SD2c used as the data line DL.

[0282] For example, Figure 18 In this disclosure, the linewidth of the inverting clock line (e.g., IL1) is shown to be the same as the linewidth of the clock line (e.g., CL1), but this disclosure is not limited thereto.

[0283] If the linewidth of the inverting clock line (e.g., IL1) is the same as the linewidth of the clock line (e.g., CL1), then the coupling between the inverting clock line (e.g., IL1) and the data line DL is greater than the coupling between the clock line (e.g., CL1) and the data line DL, and therefore the data voltage of the data line DL can be inverted.

[0284] With this in mind, if the inverting clock line (e.g., IL1) is positioned on both sides of the clock line (e.g., CL1), for example, as Figure 18 As shown, considering the resistance, parasitic capacitance, etc. of the line, the line width of the inverting clock line (e.g., IL1) can be designed to be smaller than the line width of the clock line (e.g., CL1).

[0285] Furthermore, the display device according to the embodiments of the present disclosure can improve the arrangement structure of the data lines of the pixel region AP disposed adjacent to the clock line CL of the circuit region (AS) to reduce the possible coupling between the data lines and the clock line CL and prevent the degradation of the image quality of the display panel 10.

[0286] The display device according to an embodiment of the present disclosure has an inverted clock line extending in the same direction as the clock line extending along a circuit region adjacent to the clock line, and uses the inverted clock signal of the inverted clock line to offset the clock signal of the clock line, thereby minimizing signal interference caused by the clock line disposed in the circuit region.

[0287] The display device according to embodiments of the present disclosure can reduce the possible coupling between the data lines and the clock lines by improving the arrangement structure of the data lines in the pixel region located adjacent to the clock lines of the circuit region, thereby preventing the degradation of the image quality of the display panel.

[0288] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from the spirit or scope thereof. Therefore, this disclosure is intended to cover any modifications and variations thereof that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A display panel having an active region and an inactive region, and comprising: Multiple pixel regions, the multiple pixel regions being located within the active region, and multiple sub-pixels being positioned within the multiple pixel regions; and Multiple circuit regions are alternately arranged with the multiple pixel regions in the active region, and the scanning circuit that supplies scanning signals to the multiple sub-pixels is located in the multiple circuit regions; An inverter circuit, located in the non-active region and configured to receive a clock signal supplied to the scanning circuit, invert the received clock signal, and output an inverted clock signal. A clock line, to which the clock signal is applied, and the clock line extends along the circuit region and is connected to the scan circuit; and An inverting clock line, to which an inverting clock signal is applied, and which extends along the circuit region from the inverter circuit. The inverted clock line is adjacent to the clock line and extends in the same direction.

2. The display device according to claim 1, wherein, The inverter circuit includes a first inverter transistor and a second inverter transistor. The first inverter transistor includes a gate electrode connected to the clock line, a first electrode to which a high gate voltage is applied, and a second electrode connected to the inverting clock line. The second inverter transistor includes a gate electrode connected to the clock line, a first electrode to which a gate low voltage is applied, and a second electrode connected to the inverting clock line. The first inverter transistor is a PMOS transistor, and the second inverter transistor is an NMOS transistor.

3. The display device according to claim 1, wherein, The inverter circuit receives the clock signal having the gate high voltage and outputs the inverted clock signal having the gate low voltage. The inverter circuit receives the clock signal having the gate low voltage and outputs the inverted clock signal having the gate high voltage.

4. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes: A driving transistor, the driving transistor being located in the pixel region and electrically connected to a light-emitting element; and A switching transistor, located in the pixel region and connected to the driving transistor. The clock line is located on the insulating layer, and the source and drain electrodes of each of the driving transistor and the switching transistor are located on the insulating layer.

5. The display device according to claim 1, wherein, The inverted clock line extends parallel to the clock line while maintaining a predetermined distance from the clock line.

6. The display device according to claim 1, wherein, The inverting clock line is located on a different layer than the layer on which the clock line is located within the circuit region.

7. The display device according to claim 4, wherein, The inverting clock line is located at, On the insulating layer, a metal layer is positioned on the insulating layer, the metal layer being positioned below the semiconductor layer of the driving transistor and overlapping the semiconductor layer of the driving transistor; On the insulating layer, a metal layer is positioned on the insulating layer, the metal layer being positioned below the semiconductor layer of the switching transistor and overlapping the semiconductor layer of the switching transistor; or On the insulating layer, the electrode plate of the storage capacitor connected to the driving transistor is positioned on the insulating layer.

8. The display device according to claim 1, wherein, The inverting clock line and the clock line are located on the same layer within the circuit region and are spaced apart from each other.

9. The display device according to claim 4, wherein, The inverting clock line and the clock line are spaced apart from each other on the insulating layer.

10. The display device according to claim 1, wherein, The inverting clock line is positioned on both sides of the clock line and spaced apart from the two sides of the clock line.

11. The display device according to claim 1, wherein, The plurality of circuit regions include a first circuit region and a second circuit region, and The plurality of pixel regions include a first pixel region and a second pixel region that are alternately located with the first circuit region and the second circuit region. Each of the first pixel region and the second pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged sequentially in a direction away from each of the first circuit region and the second circuit region. The first sub-pixel, the second sub-pixel, and the third sub-pixel, as well as the first data line, the second data line, and the third data line connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel, are disposed in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.

12. The display device according to claim 11, wherein, Multiple constant voltage lines are disposed at the two edges of each of the first circuit region and the second circuit region, and the clock line is disposed between the multiple constant voltage lines.

13. The display device according to claim 11, wherein, The first data line, located in the first sub-pixel region of each of the first pixel region and the second pixel region, is positioned on the side of the first sub-pixel away from the first circuit region and the second circuit region, and The third data line, which is disposed in the third sub-pixel region of each of the first pixel region and the second pixel region, is positioned on the opposite side of the third sub-pixel away from the first circuit region and the second circuit region.

14. The display device according to claim 11, wherein, The first data line, the second data line, and the third data line in the first pixel region, and the first data line, the second data line, and the third data line in the second pixel region are symmetrically arranged with respect to the second circuit region.

15. The display device of claim 11 further includes a multiplexer circuit located in the non-active region adjacent to the first pixel region and the second pixel region, receiving data signals from a data driver and sequentially outputting data voltages to the first data line of the first pixel region and the first data line of the second pixel region.

16. The display device according to claim 15, wherein, The multiplexer circuit includes: A first multiplexing transistor has a gate electrode to which a first multiplexing signal is applied, a first electrode connected to a data channel of the data driver, and a second electrode connected via the first data line to a first sub-pixel located in the first pixel region; and The second multiplexing transistor has a gate electrode to which a second multiplexing signal is applied, a first electrode connected to the data channel, and a second electrode connected to the second sub-pixel located in the second pixel region via the second data line.

17. The display device according to claim 16, wherein, The data signals input to the data channel include a first data signal applied to the first sub-pixel through the first data line of the first pixel region and a second data signal applied to the second sub-pixel through the second data line of the second pixel region.

18. The display device according to claim 17, wherein, When the first multiplexed signal has an on-state voltage, the first data signal is output to the first data line of the first pixel region, and when the second multiplexed signal has the on-state voltage, the second data signal is output to the second data line of the second pixel region.

19. The display device according to claim 4, wherein, The inverting clock line is located on the insulating layer and is on both sides of the clock line and spaced apart from the clock line, and the line width of the inverting clock line is equal to or less than the line width of the clock line.

20. The display device according to claim 12, wherein, The multiple constant voltage lines extend in the same manner as the clock lines.

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