Low-power-consumption asynchronous handshake circuit with test circuit

Abstract

The invention relates to the technical field of chips, in particular to a low-power-consumption asynchronous handshake circuit with a test circuit, which comprises a clock control circuit, a third selector, a first trigger, a second trigger, a third trigger, an AND gate and an OR gate, the function of the low-power-consumption asynchronous handshake circuit is realized in the functional mode, and the test of the low-power-consumption asynchronous handshake circuit is realized in the test mode. According to the invention, the power consumption of the asynchronous handshake circuit is reduced on the premise of satisfying the test of the asynchronous handshake circuit, and the time sequence convergence speed of the asynchronous handshake circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, especially to a low-power asynchronous handshake circuit with a test circuit. BACKGROUND

[0002] An asynchronous circuit is a digital circuit that operates without relying on a global clock signal. Asynchronous circuit data transmission and processing can be performed at any time point, without being limited by the clock signal. Asynchronous circuits do not rely on a global clock signal, but coordinate the operation of various components through an asynchronous handshake circuit. The existing asynchronous handshake circuit needs to check the setup time and hold time of the flip-flop, and also needs to check the recovery time and removal time of the flip-flop. Therefore, the existing asynchronous handshake circuit has a complex structure, high power consumption, and slow timing convergence. In addition, the prior art also needs to additionally set up a test circuit to test the asynchronous handshake circuit, further increasing the complexity of the circuit structure and the power consumption. Therefore, how to reduce the power consumption of the asynchronous handshake circuit while meeting the asynchronous handshake circuit test and improve the timing convergence speed of the asynchronous handshake circuit has become a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a low-power asynchronous handshake circuit with a test circuit, which reduces the power consumption of the asynchronous handshake circuit while meeting the asynchronous handshake circuit test and improves the timing convergence speed of the asynchronous handshake circuit.

[0004] The present application provides a low-power asynchronous handshake circuit with a test circuit, comprising a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, and an OR gate. The clock control circuit is used to transmit a single pulse signal to the clock port of the first flip-flop, transmit a second clock signal to the clock port of the second flip-flop and the clock port of the third flip-flop in the functional mode, and the clock control circuit is also used to transmit a test clock signal to the clock port of the first flip-flop, the clock port of the second flip-flop and the clock port of the third flip-flop in the test mode. The data port of the first flip-flop is connected with vdd, the output port of the first flip-flop is connected with the data port of the second flip-flop, and the output port of the second flip-flop is connected with the data port of the third flip-flop. If the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, the output port of the third flip-flop is connected with the data port of the inverter, and the output port of the inverter is connected with the first input pin of the OR gate. If the first flip-flop is an asynchronous high-level active reset port, the output port of the third flip-flop is directly connected to the first input pin of the OR gate; The second input pin of the OR gate is used for receiving a test mode signal, the output pin of the OR gate and the first input pin of the AND gate are connected, the second input pin of the AND gate is connected to the output pin of the third selector, and the output pin of the AND gate is connected to the reset port of the first flip-flop; The first selection pin of the third selector is connected to a high-level signal, the second pin of the third selector is used for receiving a test reset signal, and the enable pin of the third selector is used for receiving a test mode signal; when the test mode signal is high level, the second selection pin of the third selector is enabled; when the test mode signal is low level, the first selection pin of the third selector is enabled; the test mode signal is high level in the test mode and low level in the functional mode.

[0005] Compared with the prior art, the low-power asynchronous handshake circuit with a test circuit provided by the application has obvious advantages and beneficial effects. The low-power asynchronous handshake circuit with a test circuit provided by the application has considerable technical progress and practicability and has wide industrial utilization value, and at least has the following beneficial effects: The asynchronous handshake circuit has simple structure and low power consumption. In the functional mode, the asynchronous handshake circuit realizes the handshake function, and in the test mode, the asynchronous handshake circuit is tested. In the functional mode, the clock port of the first flip-flop is controlled by a single pulse signal, the data port of the first flip-flop is connected to vdd, the setup time check and the hold time check between the data port and the clock port of the first flip-flop are not needed, the clear time check and the recovery time check between the reset port and the clock port of the first flip-flop are not needed, and the clock of the first flip-flop does not need to be defined. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit under the premise of meeting the test of the asynchronous handshake circuit. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0007] Figure 1 The low-power asynchronous handshake circuit with a test circuit provided by the application is a low-power asynchronous handshake circuit with a test circuit with an asynchronous low-level active reset port. DETAILED DESCRIPTION

[0008] Clearly, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the present application.

[0009] The embodiment of the present application provides a low-power-consumption asynchronous handshake circuit with a test circuit, which comprises a clock control circuit, a third selector (M3), a first flip-flop (R0), a second flip-flop (R1), a third flip-flop (R2), an AND gate (I1) and an OR gate (I0).

[0010] The clock control circuit is used for transmitting a single pulse signal to the clock port of the first flip-flop, transmitting a second clock signal to the clock port of the second flip-flop and the clock port of the third flip-flop in the functional mode, and the clock control circuit is also used for transmitting a test clock signal to the clock port of the first flip-flop, the clock port of the second flip-flop and the clock port of the third flip-flop in the test mode.

[0011] As an embodiment, as shown in FIG. 1, the low-power-consumption asynchronous handshake circuit with a test circuit comprises a clock control circuit, a third selector (M3), a first flip-flop (R0), a second flip-flop (R1), a third flip-flop (R2), an AND gate (I1) and an OR gate (I0). Figure 1As shown, the clock control circuit comprises a first selector (M1) and a second selector (M2), a first selection pin of the first selector is used for receiving the second clock signal, and a second selection pin of the first selector is used for receiving the test clock signal. An enable pin of the first selector is used for receiving a test mode signal (AT), and the second selection pin of the first selector is enabled when the test mode signal is at a high level. The first selection pin of the first selector is enabled when the test mode signal is at a low level. The test mode signal is at a high level in a test mode and is at a low level in a functional mode. In the functional mode, the low-power asynchronous handshake circuit with a test circuit realizes a handshake function. In the test mode, the low-power asynchronous handshake circuit with a test circuit realizes testing on the handshake function circuit. Output pins of the first selector are connected to a second selection pin of the second selector, a clock port of the second flip-flop and a clock port of the third flip-flop respectively. A first selection pin of the second selector is used for receiving a single pulse signal generated based on the first clock, and the first clock and the second clock are asynchronous clocks. An enable pin of the second selector is used for receiving the test mode signal, and the second selection pin of the second selector is enabled when the test mode signal is at a high level, and the first selection pin of the second selector is enabled when the test mode signal is at a low level. An output pin of the second selector is connected to the clock port of the first flip-flop. In the functional mode, the clock port of the first flip-flop is controlled by the single single pulse signal. It needs to be noted that the clock port of the traditional handshake circuit is controlled by a continuous pulse signal, i.e., a clock signal. The clock port of the first flip-flop in the embodiment of the present application is controlled by the single single pulse signal, and the clock of the first flip-flop does not need to be defined, thereby improving the timing convergence speed of the asynchronous handshake circuit.

[0012] As another embodiment, the clock control circuit comprises a first selector and a second selector, wherein a first selection pin of the first selector is used for receiving the second clock signal, and a second selection pin of the first selector is used for receiving the test clock signal. An enable pin of the first selector is used for receiving a test mode signal, and the second selection pin of the first selector is enabled when the test mode signal is at a high level, and the first selection pin of the first selector is enabled when the test mode signal is at a low level. Output pins of the first selector are connected to a clock port of the second flip-flop and a clock port of the third flip-flop respectively. A first selection pin of the second selector is used for receiving a single pulse signal generated based on the first clock, a second selection pin of the second selector is used for receiving the test clock signal, and an enable pin of the second selector is used for receiving the test mode signal. The second selection pin of the second selector is enabled when the test mode signal is at a high level, and the first selection pin of the second selector is enabled when the test mode signal is at a low level. An output pin of the second selector is connected to the clock port of the first flip-flop.

[0013] The data port of the first flip-flop is connected with vdd, and the setup time and the hold time between the clock port and the data port of the first flip-flop in the functional mode cannot appear the timing violation, and if appearing, will cause the circuit to be unable to work normally. In the embodiment of the present application, the data port of the first flip-flop is connected with vdd, and vdd represents a positive power voltage, and the data port of the first flip-flop is connected with vdd, so that the data port of the first flip-flop is always tie1, that is, always pulled high, and the timing violation of the setup time and the hold time between the clock port and the data port of the first flip-flop cannot appear.

[0014] If the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter (I2), as shown in Figure 1 The output port of the third flip-flop is connected with the data port of the inverter, and the output port of the inverter is connected with the first input pin of the or gate. The asynchronous low-level effective reset port means that the reset port is an asynchronous reset port, and is a low-level effective reset port. The asynchronous reset port means that when the reset signal comes, the flip-flop can be reset even if there is no clock. The low-level effective reset port means that when the reset port of the first flip-flop is low, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1, and when the reset port of the first flip-flop is high, the first flip-flop is in a release state, and the next handshake operation can be performed.

[0015] If the first flip-flop is an asynchronous high-level effective reset port, the output port of the third flip-flop is directly connected with the first input pin of the or gate. The asynchronous reset port means that when the reset signal comes, the flip-flop can be reset even if there is no clock. The high-level effective reset port means that when the reset port of the first flip-flop is high, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1, and when the reset port of the first flip-flop is low, the first flip-flop is in a release state, and the next handshake operation can be performed.

[0016] The second input pin of the or gate is used for receiving a test mode signal, and the output pin of the or gate and the first input pin of the and gate are connected. It needs to be explained that by setting the or gate and the test mode signal, the signal output by the inverter in the test mode is blocked, so as to avoid the influence of the output of the inverter in the test mode on the reset of the reset port of the first flip-flop.

[0017] The second input pin of the and gate is connected with the output pin of the third selector, and the output pin of the and gate is connected with the reset port of the first flip-flop.

[0018] The first selection pin of the third selector is connected with a high level signal, the second pin of the third selector is used for receiving a test reset signal, the enable pin of the third selector is used for receiving a test mode signal, when the test mode signal is high level, the second selection pin of the third selector is enabled, and when the test mode signal is low level, the first selection pin of the third selector is enabled. It should be noted that, by setting the AND gate and the third selector, the reset port of the first flip-flop is controlled by the test reset signal in the test mode, and in the functional mode, if the first flip-flop is an asynchronous low level active reset port, the reset port of the first flip-flop is controlled by the output signal of the inverter; if the first flip-flop is an asynchronous high level active reset port, the reset port of the first flip-flop is controlled by the output port of the third flip-flop. In this way, the reset port of the first flip-flop is controllable in the functional mode and the test mode.

[0019] As an embodiment, in the functional mode, the first pin of the third selector is connected, or the second input pin of the OR gate always inputs low level, the second input pin of the AND gate always inputs high level, and the output of the AND gate always keeps consistent with the level of the output of the inverter.

[0020] The first flip-flop is an asynchronous low-level effective reset port. In the functional mode, if the first flip-flop is in a handshake initial state, i.e., the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is high, when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd, the value stored in the first flip-flop is updated to 1, when the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop, the value stored in the second flip-flop is updated to 1, when the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop, the value stored in the third flip-flop is updated to 1. It should be noted that in this process, after the value stored in the first flip-flop is updated to 1, it is always 1, which is equivalent to expanding the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly collect the single pulse signal received by the clock port of the first flip-flop. The inverter obtains 1 from the third flip-flop and outputs low level, and the reset port of the first flip-flop receives the low level output by the AND gate, which is equivalent to that the third flip-flop sends a clear signal to the first flip-flop through the inverter after completing sampling, so that the high level of the reset port of the first flip-flop is cleared, and the value stored in the first flip-flop is reset to 0; that is, the high level of the first flip-flop is pulled down, preparing for the next handshake operation. When the third rising edge of the second clock arrives, the second flip-flop obtains the 0 stored in the first flip-flop, and the value stored in the second flip-flop is updated to 0, when the fourth rising edge of the second clock arrives, the third flip-flop obtains the 0 stored in the second flip-flop, and the value stored in the third flip-flop is updated to 0, the inverter obtains 0 from the third flip-flop and outputs high level, the reset port of the first flip-flop receives the high level output by the AND gate, and the first flip-flop is released, completing a handshake operation and preparing for the next handshake operation. In addition, the release of the first flip-flop can prepare for the next handshake operation, when the clock port of the first flip-flop receives a single pulse signal again, the next handshake operation can be performed according to the above process.

[0021] As another embodiment, the first flip-flop is an asynchronous high-level effective reset port, in the functional mode, if the first flip-flop is in the handshake initial state, that is, the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is low, when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd, and the value stored in the first flip-flop is updated to 1. When the first rising edge of the second clock comes, the second flip-flop obtains the 1 stored in the first flip-flop, and the value stored in the second flip-flop is updated to 1. When the second rising edge of the second clock comes, the third flip-flop obtains the 1 stored in the second flip-flop, and the value stored in the third flip-flop is updated to 1. It should be noted that after the value stored in the first flip-flop is updated to 1, it is always 1, which is equivalent to expanding the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly collect the single pulse signal received by the clock port of the first flip-flop. The output port of the third flip-flop sends a high level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0. When the third rising edge of the second clock comes, the second flip-flop obtains the 0 stored in the first flip-flop, and the value stored in the second flip-flop is updated to 0. When the fourth clock rising edge of the second clock comes, the third flip-flop obtains the 0 stored in the second flip-flop, and the value stored in the third flip-flop is updated to 0. The output port of the third flip-flop sends a low level to the reset port of the first flip-flop, and releases the first flip-flop, completing a handshake operation.

[0022] In the initial state, the value stored in the first flip-flop can be 0 or 1. If the value stored in the first flip-flop is 0 in the initial state, the first flip-flop can immediately perform handshake transmission. If the value stored in the first flip-flop is 1 in the initial state, the first flip-flop needs to be reset to 0 after waiting for two clock periods corresponding to the second clock. As an embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level effective reset port, the reset port of the first flip-flop is high, and if the first flip-flop is an asynchronous high-level effective reset port, the reset port of the first flip-flop is low. If the value stored in the first flip-flop is 0, it is determined that the first flip-flop is in the handshake initial state. If the value stored in the first flip-flop is 1, the reset signal of the second clock domain is removed, and then the state of the first flip-flop after waiting for two clock periods corresponding to the second clock is determined as the handshake initial state.

[0023] In order to ensure reliable operation of the asynchronous handshake circuit, as another embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low active reset port, the reset port of the first flip-flop is high, and if the first flip-flop is an asynchronous high active reset port, the reset port of the first flip-flop is low; in the initial state of the asynchronous handshake circuit, the reset signal of the second clock domain is removed, and then the state of the first flip-flop after two clock cycles corresponding to the second clock is determined as the handshake initial state.

[0024] In addition, in the digital circuit, due to the timing problem, some signals are in an uncertain state at the sampling time, that is, a metastable state occurs, which may cause abnormal circuit function or data error. The structure of the second flip-flop and the third flip-flop also plays a role in removing the metastable state, ensuring the stability of the circuit function and the correctness of the collected data.

[0025] As a preferred embodiment, the clock frequency of the first clock is greater than or equal to the clock frequency of the second clock, that is, the first clock is a fast clock, and the second clock is a slow clock.

[0026] As an embodiment, the asynchronous handshake circuit further comprises a finite state machine (FSM) connected to the first clock, for generating a single pulse signal based on the first clock and transmitting the single pulse signal to the clock port of the first flip-flop.

[0027] In the functional mode, the reset port of the first flip-flop is not allowed to appear timing violation of the clear time and the recovery time when sending a low level, and once it appears, it will cause the circuit to malfunction. Therefore, in the prior art, it is necessary to check whether the timing violation of the clear time and the recovery time occurs between the reset port and the clock port of the first flip-flop. In order to avoid the timing violation of the clear time and the recovery time when the inverter sends a low level to the reset port of the first flip-flop, as an embodiment, the time interval of the single pulse signal generated by the first clock is greater than the preset time interval, and the preset time interval is twice the second clock period, so that the time interval of the two single pulse signals generated by the first clock is large enough, and the timing violation of the recovery time and the removal time between the clock port of the first flip-flop and the reset port of the first flip-flop does not occur. Therefore, it is not necessary to check the recovery time and the removal time of the flip-flop.

[0028] It should be noted that the convergence of the asynchronous handshake circuit needs to converge two aspects of timing: first, the setup and hold check between the data port of the first flip-flop (i.e., the data port) and the clock port of the first flip-flop; second, the removal and recovery check between the reset port of the first flip-flop and the clock port of the first flip-flop. In the embodiment of the present application, by connecting the data port of the first flip-flop to vdd at all times, and being able to stagger the interval between the clock reset and the clock, i.e., when there is a pulse to the first flip-flop, there is no reset signal. When there is a reset signal, there is no clock signal, so the asynchronous handshake circuit described in the embodiment of the present application does not need to check the two timing of the first flip-flop. It can be understood that since the two timing does not need to be checked, the timing of the one-step handshake circuit of the present application meets the requirements, so there is no need to define a clock constraint for the clock port of the first flip-flop, thereby improving the timing convergence speed of the asynchronous handshake circuit.

[0029] As an embodiment, in the test mode, the second selection pin of the first selector is turned on, the second selection pin of the second selector is turned on, and the clock ports of the first flip-flop, the second flip-flop, and the third flip-flop are all used to receive a test clock signal controlled by the test clock signal.

[0030] In the test mode, the test mode signal is high, or the output of the or gate is always high, and the output of the and gate is controlled by the output of the third selector, the second selection pin of the third selector is turned on, and the reset port of the first flip-flop is controlled by the test reset signal.

[0031] As an embodiment, the asynchronous handshake circuit further comprises a fourth selector (M4), a first selection pin of the fourth selector is used to receive a second clock reset signal, a second selection pin of the fourth selector is used to receive a test reset signal, an enable pin of the fourth selector is used to receive a test mode signal, when the test mode signal is high, the second selection pin of the fourth selector is turned on, and when the test mode signal is low, the first selection pin of the fourth selector is turned on; the output pin of the fourth selector is connected to the reset port of the second flip-flop and the reset port of the third flip-flop, respectively. As shown in the example, Figure 1 It should be noted that when the first flip-flop is set as an asynchronous high-level active reset port, the reset port of the second flip-flop and the reset port of the third flip-flop can also be set as an asynchronous high-level active reset port. For example, Figure 1 As shown in the example, In test mode, the second selection pin of the fourth selector is turned on, and the reset ports of the second and third flip-flops are controlled by a test reset signal. During testing, when a reset operation is required on the reset ports of the second and third flip-flops, a low-level signal is sent to the reset ports of the second and third flip-flops via the test reset signal.

[0032] by Figure 1 Taking the example shown as an example, in functional mode, the first selection pin of the fourth selector is turned on, and the reset port of the second trigger and the reset port of the third trigger are controlled by the second clock reset signal. Specifically, when the second trigger and the third trigger need to be reset in the initial state or during operation, the second clock reset signal is set to a low level. It should be noted that, in the initial state, the values ​​stored in the second trigger and the third trigger need to be set to 0, so the second clock reset signal needs to be set to a low level. During operation, if the second trigger and / or the third trigger have an abnormal situation such as a fault and need to be reset, the second clock reset signal is also directly set to a low level to quickly reset the second trigger and the third trigger. At other operating moments, the second clock reset signal is set to a high level, so that the second trigger and the third trigger are in a released state and can work normally.

[0033] The asynchronous handshake circuit of the embodiment of the present invention has a simple structure and low power consumption. In functional mode, the asynchronous handshake circuit realizes the handshake function, and in test mode, it realizes the test of the asynchronous handshake circuit. In functional mode, the clock port of the first trigger is controlled by a single pulse signal, and the data port of the first trigger is connected to vdd. There is no need to perform a setup time check and a hold time check between the data port and the clock port of the first trigger, nor is there a need to perform a clear time check and a recovery time check between the reset port of the first trigger and the clock port of the first trigger, and there is no need to define a clock at the clock port of the first trigger. The present invention reduces the power consumption of the asynchronous handshake circuit while meeting the test requirements of the asynchronous handshake circuit, and improves the timing convergence speed of the asynchronous handshake circuit.

[0034] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A low-power asynchronous handshake circuit with a test circuit, characterized in that: It includes a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, and an OR gate; The clock control circuit is configured to transmit a single pulse signal to a clock port of the first flip-flop in a functional mode, and to transmit a second clock signal to a clock port of the second flip-flop and a clock port of the third flip-flop; and the clock control circuit is further configured to transmit a test clock signal to the clock port of the first flip-flop, the clock port of the second flip-flop, and the clock port of the third flip-flop in a test mode. The data port of the first flip-flop is connected to VDD, the output port of the first flip-flop is connected to the data port of the second flip-flop, and the output port of the second flip-flop is connected to the data port of the third flip-flop; If the first flip-flop is an asynchronous active low reset port, the asynchronous handshake circuit further includes an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the first input pin of the OR gate; If the first flip-flop is an asynchronous active-high reset port, the output port of the third flip-flop is directly connected to the first input pin of the OR gate; The second input pin of the OR gate is used to receive a test mode signal, the output pin of the OR gate is connected to the first input pin of the AND gate, the second input pin of the AND gate is connected to the output pin of the third selector, and the output pin of the AND gate is connected to the reset port of the first trigger; The first selection pin of the third selector is connected to a high-level signal, the second pin of the third selector is used to receive a test reset signal, and the enable pin of the third selector is used to receive a test mode signal. When the test mode signal is high, the second selection pin of the third selector is selected, and when the test mode signal is low, the first selection pin of the third selector is selected. The test mode signal is high in test mode and low in functional mode.

2. The asynchronous handshake circuit according to claim 1, wherein: The clock control circuit includes a first selector and a second selector, wherein the first selection pin of the first selector is used to receive the second clock signal, and the second selection pin of the first selector is used to receive the test clock signal; the enable pin of the first selector is used to receive the test mode signal, when the test mode signal is at a high level, the second selection pin of the first selector is enabled, and when the test mode signal is at a low level, the first selection pin of the first selector is enabled, and the output pin of the first selector is respectively connected to the second selection pin of the second selector, the clock port of the second flip-flop, and the clock port of the third flip-flop; The first selection pin of the second selector is used to receive a single pulse signal generated based on the first clock; the enable pin of the second selector is used to receive a test mode signal, when the test mode signal is at a high level, the second selection pin of the second selector is selected, and when the test mode signal is at a low level, the first selection pin of the second selector is selected; the output pin of the second selector is connected to the clock port of the first trigger.

3. The asynchronous handshake circuit according to claim 1, wherein: The clock control circuit includes a first selector and a second selector, wherein the first selection pin of the first selector is used to receive the second clock signal, and the second selection pin of the first selector is used to receive the test clock signal; the enable pin of the first selector is used to receive the test mode signal, when the test mode signal is at a high level, the second selection pin of the first selector is enabled, and when the test mode signal is at a low level, the first selection pin of the first selector is enabled; the output pin of the first selector is connected to the clock port of the second flip-flop and the clock port of the third flip-flop respectively; The first selection pin of the second selector is used to receive a single pulse signal generated based on the first clock, the second selection pin of the second selector is used to receive a test clock signal, and the enable pin of the second selector is used to receive a test mode signal. When the test mode signal is at a high level, the second selection pin of the second selector is selected, and when the test mode signal is at a low level, the first selection pin of the second selector is selected; the output pin of the second selector is connected to the clock port of the first trigger.

4. The asynchronous handshake circuit according to claim 2 or 3, characterized in that: The clock frequency of the first clock is greater than or equal to the clock frequency of the second clock; the time interval for the first clock to generate a single pulse signal is greater than a preset time interval, and the preset time interval is twice the second clock period.

5. The asynchronous handshake circuit according to claim 4, characterized in that: In functional mode, the first pin of the third selector is turned on, the second input pin of the OR gate always inputs a low level, the second input pin of the AND gate always inputs a high level, and the output of the AND gate always keeps consistent with the level of the inverter output.

6. The asynchronous handshake circuit according to claim 5, characterized in that: The first flip-flop is an asynchronous low-level active reset port. In functional mode, if the first flip-flop is in a handshake initial state, the handshake initial state is a state where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is at a high level, then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. When the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. The inverter obtains 1 from the third flip-flop and outputs a low level. The reset port of the first flip-flop receives the low level output by the AND gate, and the first flip-flop resets the stored value to 0. When the third rising edge of the second clock arrives, the second trigger obtains the 0 stored in the first trigger and updates the value stored in the second trigger to 0. When the fourth clock rising edge of the second clock arrives, the third trigger obtains the 0 stored in the second trigger and updates the value stored in the third trigger to 0. The inverter obtains 0 from the third trigger and outputs a high level. The reset port of the first trigger receives the high level output by the AND gate, releases the first trigger, and completes a handshake operation.

7. The asynchronous handshake circuit according to claim 5, characterized in that: The first trigger is an asynchronous high-level active reset port. In functional mode, if the first trigger is in a handshake initial state, the handshake initial state is a state where the value stored in the first trigger is 0 and the reset port of the first trigger is at a low level, then when the clock port of the first trigger receives a single pulse signal, the data port of the first trigger obtains the value of vdd and updates the value stored in the first trigger to 1. When the first rising edge of the second clock arrives, the second trigger obtains the 1 stored in the first trigger and updates the value stored in the second trigger to 1. When the second rising edge of the second clock arrives, the third trigger obtains the 1 stored in the second trigger and updates the value stored in the third trigger to 1. The output port of the third trigger sends a high level to the reset port of the first trigger, and the first trigger resets the stored value to 0. When the third rising edge of the second clock arrives, the second trigger obtains the 0 stored in the first trigger and updates the value stored in the second trigger to 0. When the fourth rising edge of the second clock arrives, the third trigger obtains the 0 stored in the second trigger and updates the value stored in the third trigger to 0. The output port of the third trigger sends a low level to the reset port of the first trigger, releasing the first trigger and completing a handshake operation.

8. The asynchronous handshake circuit according to claim 4, wherein: In the test mode, the second selection pin of the first selector is turned on, the second selection pin of the second selector is turned on, and the clock ports of the first flip-flop, the second flip-flop, and the third flip-flop are all used to receive the test clock signal and are controlled by the test clock signal; In test mode, the test mode signal is high, the output of the OR gate is always high, the output of the AND gate is controlled by the output of the third selector, the second selection pin of the third selector is turned on, and the reset port of the first trigger is controlled by the test reset signal.

9. The asynchronous handshake circuit according to claim 1, wherein: The asynchronous handshake circuit also includes a fourth selector, the first selection pin of the fourth selector is used to receive a second clock reset signal, the second selection pin of the fourth selector is used to receive a test reset signal, and the enable pin of the fourth selector is used to receive a test mode signal. When the test mode signal is at a high level, the second selection pin of the fourth selector is enabled, and when the test mode signal is at a low level, the first selection pin of the fourth selector is enabled; the output pins of the fourth selector are respectively connected to the reset port of the second trigger and the reset port of the third trigger.

10. The asynchronous handshake circuit according to claim 9, characterized in that: In the test mode, the second selection pin of the fourth selector is turned on, and the reset port of the second flip-flop and the reset port of the third flip-flop are controlled by the test reset signal; In the functional mode, the first selection pin of the fourth selector is turned on, and the reset port of the second flip-flop and the reset port of the third flip-flop are controlled by the second clock reset signal.

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