Data acquisition method, device and system, chip and electronic equipment

Abstract

The invention discloses a data acquisition method, device and system, a chip and electronic equipment, and relates to the technical field of wireless communication, node data acquisition of a communication baseband chip can be realized through hardware, the method comprises the following steps: receiving first frame data and second frame data, the first frame data and the second frame data being continuous data frames; storing the first frame data in a first storage space; and in response to reading at least part of the first frame data, storing the second frame data in a second storage space which is not overlapped with the first storage space. In this way, software participation can be reduced, system overhead can be reduced, and power consumption of system operation can be saved. And for two continuous frames of data, the storage spaces are not overlapped, so that the risk of data coverage caused by software reset is avoided, the error risk caused by excessive intervention of software is released, and the real-time performance of the system is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a data acquisition method, device, system, chip and electronic device. Background Art

[0002] Communication baseband chips are key components of mobile communication devices, responsible for processing wireless communication signals. Node data collection from communication baseband chips is a primary means of solving positioning problems.

[0003] Currently, related technologies require frequent software intervention during the process of collecting node data from communication baseband chips, increasing system overhead and power consumption. In addition, in some cases, there is a risk of data being overwritten due to software resetting the base address. Summary of the Invention

[0004] In view of this, the present application provides a data acquisition method, device, system, chip and electronic device. The node data acquisition of the communication baseband chip can be realized by hardware. Specifically, for the node data of the communication baseband chip, it can be realized to receive the first frame data and the second frame data, and the first frame data and the second frame data are continuous data frames; the first frame data is stored in the first storage space; in response to reading at least part of the first frame data, the second frame data is stored in the second storage space, and the second storage space does not overlap with the first storage space. In this way, software participation can be reduced, system overhead can be reduced, and power consumption of system operation can be saved. In addition, for two consecutive frames of data, their storage spaces do not overlap, avoiding the risk of data being overwritten due to software reset, while releasing the risk of errors caused by excessive software intervention, significantly improving the real-time performance of the system.

[0005] In a first aspect, the present application provides a data collection method, comprising:

[0006] receiving a first frame of data and a second frame of data, where the first frame of data and the second frame of data are consecutive data frames;

[0007] storing the first frame data in a first storage space;

[0008] In response to reading at least a portion of the first frame data, the second frame data is stored in a second storage space, where the second storage space does not overlap with the first storage space.

[0009] Optionally, the first storage space and the second storage space are continuous storage spaces.

[0010] Optionally, the second storage space is the storage space remaining after the data frame is read.

[0011] Optionally, the receiving the first frame data and the second frame data includes:

[0012] Receiving the first frame data and the second frame data is controlled based on a first control signal and a second control signal, wherein the first control signal is used to determine the start of receiving the frame data, and the second control signal is used to determine the end of receiving the frame data.

[0013] Optionally, the method further includes:

[0014] Determine a first node corresponding to the first frame data and a second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

[0015] Optionally, the method further includes:

[0016] In response to the cache space corresponding to the first node being full, suspending storage of the frame data of the first node; and / or,

[0017] In response to the cache space corresponding to the second node being full, storing the frame data of the second node is suspended.

[0018] Optionally, the first frame data and the second frame data respectively include a timestamp, and the method includes:

[0019] Calculate the time interval between the first frame data and the second frame data based on the timestamp;

[0020] The pre-allocated size of the second storage space is dynamically adjusted according to the time interval.

[0021] Optionally, the method further includes:

[0022] Acquire a data access frequency of the first frame data;

[0023] Determining the data retention period based on the data access frequency;

[0024] According to the data retention time, resources of at least a portion of the first frame data that has been read in the first storage space are released.

[0025] In a second aspect, the present application provides a data acquisition device, comprising:

[0026] A receiving unit, configured to receive a first frame of data and a second frame of data, wherein the first frame of data and the second frame of data are consecutive data frames;

[0027] A storage unit is connected to the receiving unit, and is used to store the first frame data in a first storage space; in response to reading at least a portion of the first frame data, store the second frame data in a second storage space, and the second storage space does not overlap with the first storage space.

[0028] Optionally, the device further includes:

[0029] A determination unit, the determination unit is connected to the receiving unit, and the determination unit is used to determine a first node corresponding to the first frame data and a second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

[0030] Optionally, the storage unit is further used to suspend storage of the frame data of the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of the frame data of the second node in response to the cache space corresponding to the second node being full.

[0031] Optionally, the first frame data and the second frame data respectively include a timestamp;

[0032] The storage unit is further configured to calculate a time interval between the first frame data and the second frame data based on the timestamp; and dynamically adjust a pre-allocated size of the second storage space according to the time interval.

[0033] Optionally, the storage unit is also used to obtain the data access frequency of the first frame data; determine the data retention period based on the data access frequency; and release resources of at least part of the first frame data that has been read in the first storage space according to the data retention period.

[0034] In a third aspect, the present application provides a data acquisition system, comprising:

[0035] A data acquisition device, the data acquisition device is used to receive a first frame of data and a second frame of data from a communication baseband chip, the first frame of data and the second frame of data being consecutive data frames; and store the first frame of data in a first storage space;

[0036] A data moving device is connected to the data acquisition device, and is used to read at least a portion of the first frame data into the memory; the data acquisition device is also used to store the second frame data into a second storage space in response to the data moving device reading at least a portion of the first frame data, and the second storage space does not overlap with the first storage space.

[0037] Optionally, the data acquisition device is also used to determine the first node corresponding to the first frame data, and the second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

[0038] Optionally, the data acquisition device is also used to suspend storage of frame data of the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of frame data of the second node in response to the cache space corresponding to the second node being full.

[0039] Optionally, the first frame data and the second frame data respectively include a timestamp;

[0040] The data acquisition device is further configured to calculate a time interval between the first frame data and the second frame data based on the timestamp; and dynamically adjust a pre-allocated size of the second storage space according to the time interval.

[0041] Optionally, the data acquisition device is also used to obtain the data access frequency of the first frame data; determine the data retention period based on the data access frequency; and release resources of at least part of the first frame data that has been read in the first storage space according to the data retention period.

[0042] In a fourth aspect, the present application provides a chip, which is configured to execute the data acquisition method described in the first aspect.

[0043] In a fifth aspect, the present application provides a chip comprising the data acquisition device described in the second aspect, or the data acquisition system described in the third aspect.

[0044] In a sixth aspect, the present application provides an electronic device comprising the data acquisition device described in the second aspect, or the data acquisition system described in the third aspect, or the chip described in the fourth aspect, or the chip described in the fifth aspect.

[0045] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0048] Figure 1 A structural schematic diagram of a data acquisition device provided by an embodiment of the present application is shown.

[0049] Figure 2 A structural schematic diagram of a data acquisition system provided by an embodiment of the present application is shown.

[0050] Figure 3 A flow schematic diagram of a data acquisition method provided by an embodiment of the present application is shown.

[0051] Figure 4 A schematic diagram of an example provided by an embodiment of the present application is shown.

[0052] Figure 5 A schematic diagram of another example provided by an embodiment of the present application is shown.

[0053] Figure 6 A schematic diagram of yet another example provided by an embodiment of the present application is shown.

[0054] Figure 7 A schematic diagram of still another example provided by an embodiment of the present application is shown.

[0055] Figure 8 A schematic diagram of still another example provided by an embodiment of the present application is shown.

[0056] Figure 9 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown.

[0057] Figure 1 In the drawings:

[0058] 11 - receiving unit, 12 - storage unit. DETAILED DESCRIPTION

[0059] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0061] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they can refer to fixed connection, detachable connection, or integral connection; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0062] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0063] The following combination Figure 1 The data acquisition device provided in the embodiments of the present application may be referred to as a data acquisition module, a data processing device, a data processing module, etc. The data acquisition device may be configured based on an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), etc.

[0064] The embodiment of the present application provides a data acquisition device, such as Figure 1 As shown, it includes: a receiving unit 11 and a storage unit 12.

[0065] In some embodiments, the receiving unit 11 can be used to receive frame data from each node of the communication baseband chip. These nodes may include a modem, a channel codec, a large-scale multiple-input multiple-output (MIMO) processor, and the like. Among them, the modem is responsible for converting digital information into an analog signal suitable for wireless transmission (modulation), and the receiving end recovers the original information from the received signal (demodulation). The channel codec handles channel coding and decoding tasks to improve the reliability and efficiency of data transmission. Errors are detected and corrected by adding redundant information. The large-scale MIMO processor uses multiple antennas to send and receive data to increase network capacity and improve spectrum efficiency. In addition, the node may also include an RF front-end module (RF Front-End Module), etc., which may specifically include components such as filters, amplifiers, and switches, and is responsible for processing the sending and receiving of RF signals.

[0066] In some examples, for node data of a communication baseband chip, the receiving unit 11 may be configured to receive a first frame of data and a second frame of data, wherein the first frame of data and the second frame of data are continuous data frames, that is, two continuous data frames.

[0067] In some embodiments, as Figure 1 As shown, the storage unit 12 is connected to the receiving unit 11, and the storage unit 12 is used to store the collected frame data of each node of the communication baseband chip.

[0068] In some examples, the storage unit 12 can be used to store the first frame data in a first storage space, for example, by packetizing the received frame data according to a preset packet length, and storing the packetized data packets, thereby meeting the storage requirements of the frame data; the storage unit 12 stores the second frame data in a second storage space in response to reading at least part of the first frame data, wherein the second storage space does not overlap with the first storage space.

[0069] In some examples, the first storage space and the second storage space can be contiguous. For example, the next frame of data can be stored at the location where the previous frame of data storage ended. This caching of the next frame of data continues at the location where the previous frame of data cache ended, avoiding the risk of data being overwritten due to a software reset and improving the accuracy and intelligence of data collection.

[0070] In some examples, the second storage space is the storage space that is free after the data frame is read. For example, as the data is read, the storage space occupied by the read portion of the data is marked as "releasable" or "free", that is, free space, and the second frame of data can be stored in the free space, and the second storage space does not overlap with the data area that has not been read from the first frame of data, ensuring the correctness of the reading operation. The disclosed embodiment can realize the parallel execution of data reading and storage operations, such as reading the remaining part of the first frame of data and writing the second frame of data to the free space at the same time. When the first frame of data is completely read, all the space it occupies is released and can be used for the storage of subsequent data frames. By reusing the free space of the read data, the demand for additional storage areas is reduced, and the storage utilization rate is significantly improved.

[0071] In some embodiments, the data acquisition device also includes: a determination unit, which can be connected to the receiving unit 11, wherein the determination unit can be used to determine the first node corresponding to the first frame data, and the second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

[0072] For example, each node of a communication baseband chip, such as a modem, a channel codec, and a massive MIMO processor, has its own corresponding cache space, and frame data from different nodes is stored separately without causing mutual interference. The storage unit 12 can be used to store the first frame data received from a first node (e.g., any node) in the storage space corresponding to the first node, and store the second frame data received from a second node different from the first node in the storage space corresponding to the second node. This embodiment can automatically complete the concurrent data collection of each node through hardware for multiple nodes of the communication baseband chip.

[0073] In some examples, the storage unit 12 is further configured to suspend storage of frame data from the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of frame data from the second node in response to the cache space corresponding to the second node being full. In this manner, data in the storage space is prevented from being contaminated, and storage can resume when free space is available in the storage space.

[0074] In some embodiments, the first frame data and the second frame data may respectively include timestamps; accordingly, the storage unit 12 can also be used to calculate the time interval between the first frame data and the second frame data based on the timestamp; and then dynamically adjust the pre-allocated size of the second storage space according to the time interval.

[0075] For example, each data frame contains a timestamp indicating its generation time, or related information for determining the generation time, etc. After receiving the first frame data and the second frame data, the embodiment of the present application extracts the timestamps (T1 and T2) of the two frames and calculates the time interval ΔT = T2-T1. The pre-allocated size of the second storage space is then dynamically adjusted according to ΔT, such as establishing a mapping relationship: short time interval → pre-allocate a larger space (to cope with high-speed data influx); long time interval → pre-allocate a smaller space (to avoid waste of resources). In this way, resource utilization can be optimized. In low frame rate scenarios, the pre-allocated space is automatically reduced to release resources for other tasks; in high frame rate scenarios, the space is dynamically increased to accommodate burst data to avoid data loss.

[0076] Further optionally, the embodiment of the present application may also pre-allocate the initial size of the second storage space based on historical data or default configuration. For example, if the current ΔT is less than the historical average ΔT, the pre-allocated size of the second storage space is increased (e.g., expanded by 1.5 times); if the current ΔT is greater than the historical average ΔT, the pre-allocated size of the second storage space is reduced (e.g., shrunk to 0.7 times). In addition, an adjustment threshold may be introduced (e.g., adjustment is triggered only when ΔT changes by more than 20%). This adjustment mechanism can avoid frequent fluctuations.

[0077] In some examples, the pre-allocated size of the adjusted second storage space may prioritize the use of free space released after the first frame of data is read, and new storage space may be allocated for the insufficient space.

[0078] In some embodiments, the storage unit 12 can also be used to obtain the data access frequency of the first frame data; determine the data retention time based on the data access frequency; and then release resources for at least part of the first frame data that has been read in the first storage space according to the data retention time.

[0079] For example, the number of times and frequency of accessing the first frame data is monitored and recorded. Specifically, a counter can be set, and the counter value is increased each time the first frame data is read, while recording the timestamp of each access. The data access frequency is calculated by the number of accesses within a certain time window. For example, if the first frame data is accessed 5 times within 10 seconds, then its access frequency is 0.5 times / second. According to the obtained data access frequency, and according to the pre-set rules or algorithms to determine the data retention period, such as the data access frequency and the retention period are positively correlated: if the first frame data is frequently accessed, it means that it may still be used later, and accordingly, a longer data retention period will be allocated to it. For example, for data with an access frequency of more than 1 time / second, the retention period is set to 30 minutes. If the data access frequency is very low or even no access for a long time, it means that the possibility of using the data later is small, and accordingly, the retention period will be shortened. For example, for data with an access frequency of less than 0.1 times / second, the retention period is only 5 minutes.

[0080] According to the determined data retention period, the system can perform a resource release operation on the at least part of the first frame data that has been read in the first storage space. For example, the time is counted from when the first frame data is first read, and when the counting reaches the data retention period, and the data is not accessed again within the retention period, the storage space occupied by the data is marked as a releasable state. The released storage space resource can be marked and included in the idle space pool for storing new data (such as second frame data) in the future. If the data is accessed again within the retention period, the retention period is recalculated, and the retention time of the data in the storage space is extended. By determining the data retention period according to the access frequency, the long-term occupation of the storage space by low-access-frequency data is avoided, and the storage space can be more efficiently utilized.

[0081] Optionally, the data acquisition device can be used to start collecting a frame of data based on a first control signal, and to end collecting the frame of data based on a second control signal. For example, the first control signal can be a SOP (Start of Frame) control signal, and the second control signal can be an EOP (End of Frame) control signal. SOP is a control signal for starting the collection of a frame of data, and is used to mark the start of a new frame. When SOP is detected, it is determined that the next data belongs to a new frame, and the collection of the data of the frame is prepared to start. EOP is a control signal for ending the collection of a frame, and marks the completion of the data transmission of the current frame. After receiving the EOP signal, the system will stop collecting the data of the frame. The present embodiment can realize automatic recognition of the frame boundary and continuous storage of the address by establishing a processing mechanism based on SOP / EOP.

[0082] Compared to current technologies, the embodiments of this application can implement node data collection for communication baseband chips through hardware, reducing software involvement, lowering system overhead, and saving system power consumption. Furthermore, the storage space for two consecutive frames of data does not overlap, avoiding the risk of data being overwritten due to software resets. This also reduces the risk of errors caused by excessive software intervention, significantly improving system real-time performance.

[0083] The following combination Figure 2 A data acquisition system provided in an embodiment of the present application is described.

[0084] The embodiment of the present application provides a data acquisition system, such as Figure 2 As shown, it includes: a data moving device and Figure 1 The data acquisition device shown.

[0085] The data acquisition device can be used to collect frame data of each node of the communication baseband chip, such as receiving the first frame data and the second frame data of the communication baseband chip, where the first frame data and the second frame data are consecutive data frames; and storing the first frame data in the first storage space.

[0086] A data moving device, or a data moving module, may be a direct memory access (DMA) module, etc. The data moving device may be connected to a data acquisition device. The data moving module is used to move the frame data stored in the data acquisition device to a memory, for example, reading at least part of the first frame data into a memory, such as a double data rate synchronous dynamic random access memory (DDR SDRAM). The frame data in the memory is used to generate log data for a communication baseband chip, and the log data may be used for problem location in maintenance test tools.

[0087] The data acquisition device is further configured to store a second frame of data in a second storage space in response to the data transfer device reading at least a portion of the first frame of data, wherein the second storage space does not overlap with the first storage space. For example, the data acquisition device can interact with the data transfer device via a pointer to transfer the collected frame data to a memory via the data transfer device. The frame data in the memory is used to generate log data for the communication baseband chip, and the log data can be used by maintenance test tools to troubleshoot problems.

[0088] In some embodiments, the data acquisition device is further configured to determine a first node corresponding to the first frame of data and a second node corresponding to the second frame of data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node. This embodiment can automatically complete concurrent data acquisition for multiple nodes of a communication baseband chip through hardware.

[0089] In some embodiments, the data collection device is further configured to suspend storage of frame data from the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of frame data from the second node in response to the cache space corresponding to the second node being full. In this manner, data in the storage space is prevented from being contaminated, and storage can resume when free space is available in the storage space.

[0090] In some embodiments, the first frame data and the second frame data each include a timestamp; accordingly, the data acquisition device is further configured to calculate the time interval between the first frame data and the second frame data based on the timestamp; then dynamically adjust the pre-allocated size of the second storage space based on the time interval. This approach optimizes resource utilization. In low frame rate scenarios, the pre-allocated space is automatically reduced to free up resources for other tasks; while in high frame rate scenarios, the space is dynamically increased to accommodate bursts of data, preventing data loss.

[0091] In some embodiments, the data acquisition device is also used to obtain the data access frequency of the first frame data; determine the data retention time based on the data access frequency; and then release resources for at least part of the first frame data that has been read in the first storage space according to the data retention time.

[0092] It should be noted that for the specific explanation of the data acquisition device, please refer to Figure 1 The contents of the embodiment shown will not be repeated here.

[0093] Through the data acquisition system of the embodiment of the present application, the data of each node of the communication baseband chip is automatically collected based on hardware, which can reduce software participation, reduce system overhead, and save power consumption of system operation.

[0094] Furthermore, an embodiment of the present application provides a chip, which may include: Figure 1 The data acquisition device shown, or Figure 2 The data acquisition system shown in the embodiment of the present application automatically collects data from each node of the communication baseband chip based on hardware, which can reduce software involvement, lower system overhead, and save power consumption of system operation.

[0095] Furthermore, the present invention also provides a data acquisition method, which can be executed by the above-mentioned data acquisition device, such as Figure 3 As shown, the method includes:

[0096] Step 201: Receive a first frame of data and a second frame of data.

[0097] The embodiment of the present application can collect frame data of each node of the communication baseband chip, such as first frame data and second frame data, where the first frame data and the second frame data are continuous data frames.

[0098] In certain embodiments, the first frame data and the second frame data can be received based on the first control signal and the second control signal control, the first control signal is used to determine the reception of the start frame data, and the second control signal is used to determine the reception of the end frame data. For example, based on the first control signal, a frame of data is collected, and based on the second control signal, the frame data is collected. For example, the first control signal can be an SOP control signal, and the second control signal can be an EOP control signal. The present embodiment can realize automatic recognition of data frame boundaries and continuous storage of addresses by establishing a processing mechanism based on SOP / EOP.

[0099] Step 202: Store the first frame of data into a first storage space.

[0100] Step 203 : In response to reading at least a portion of the first frame data, store the second frame data in a second storage space.

[0101] The second storage space does not overlap with the first storage space. Optionally, the first storage space and the second storage space are contiguous. For example, the next frame of data can be cached where the previous frame of data ended, avoiding the risk of data being overwritten due to a software reset, thereby improving the accuracy and intelligence of data collection.

[0102] Optionally, the second storage space is the free storage space after the data frame is read. By reusing the free space of the read data, the need for additional storage area is reduced, and storage utilization is significantly improved.

[0103] In some embodiments, a first node corresponding to the first frame data and a second node corresponding to the second frame data are determined, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node. For example, each node has its own corresponding storage space, and the frame data of different nodes are stored separately without causing mutual interference. In an embodiment of the present application, the frame data of any of the collected nodes can be stored in the storage space corresponding to the node. This embodiment can automatically complete the concurrent data collection of each node through hardware for multiple nodes of a communication baseband chip.

[0104] In some embodiments, in response to a first node's corresponding cache being full, storage of the first node's frame data is suspended; and / or in response to a second node's corresponding cache being full, storage of the second node's frame data is suspended. For example, when the cache corresponding to any node is full, frame data collection for that node is suspended. This ensures that data in the cache is not contaminated, and storage can resume when free space is available in the cache.

[0105] In some embodiments, the first and second frames of data each include a timestamp. Accordingly, the time interval between the first and second frames is calculated based on the timestamps. The pre-allocated size of the second storage space is then dynamically adjusted based on the time interval. This approach optimizes resource utilization. In low-frame-rate scenarios, the pre-allocated space is automatically reduced to free up resources for other tasks. In high-frame-rate scenarios, the space is dynamically increased to accommodate bursts of data, preventing data loss.

[0106] In some embodiments, the data access frequency of the first frame of data can be obtained; a data retention period can be determined based on the data access frequency; and then, based on the data retention period, resources of at least a portion of the first frame of data that has been read from the first storage space can be released. By determining the data retention period based on the access frequency, the storage space is prevented from being occupied for a long period by data with low access frequency, thereby enabling more efficient use of the storage space.

[0107] The technical solution proposed in the embodiments of the present application relates to the fields of wireless communications and terminal technology, and can specifically be a solution for non-invasive baseband chip data collection, storage, and export, which can be expanded to other fields such as smart electric vehicles.

[0108] Based on the contents of the above embodiments, for ease of understanding, the following examples are given:

[0109] When wireless communication products communicate, facing the unknown world of communication, they need to accumulate large amounts of data to enrich their understanding of the real-world network environment. As an important means of locating problems, the key node data collection solution for communication baseband chips has the advantage of quickly accumulating live network data, improving problem location efficiency, optimizing algorithm performance, and enhancing user experience. It supports locating different problems in different scenarios.

[0110] In some examples, the business modules (such as channel coding and decoding, large-scale MIMO processing) of communication baseband chips (such as 5G baseband, etc.) need to collect TB-level data streams in real time. A solution based on hardware and software platforms and presented by the software platform can be adopted. Among them, the hardware solution faces complex communication link data interaction and needs to collect multi-node business data. An important function of the data acquisition device (Dump, or data acquisition module) is data acquisition. By interacting with DMA (data movement) through pointers, it completes real-time online export of data, can accurately and effectively capture on-site logs, and its core value lies in quickly locating the problem site.

[0111] For example, Figure 4 As shown, it can be an architectural diagram of data collection in a communication baseband chip. For the data of nodes A, B, and C, the data acquisition device collects these data and classifies them into memory. These cached data are quickly moved to the DDR memory through DMA. The tool platform (business maintenance test module) can generate log data corresponding to different nodes based on the data stored in the DDR memory, such as the log data corresponding to nodes A, B, and C (logs 0, 1, and 2), and then locate the problem through these log data. This method can support concurrent data collection from multiple nodes without accessing the debug interface, reducing the complexity of chip integration. The specific workflow may include the following:

[0112] (1) The data interface of the business module (each node in the communication baseband chip) interacts with the data acquisition device through hardware connection, facing complex communication data interaction and supporting multi-node data concurrent acquisition;

[0113] (2) For multi-node data collection, the software can specify the data storage space of each node by configuring the starting address (start_addr) and the ending address (end_addr);

[0114] (3) After the data is packaged, the data acquisition device can interact with the DMA through the pointer and export the data to the DDR memory in real time;

[0115] (4) Based on the test requirements, the platform tool exports the data in the DDR memory to the tool platform for visual maintenance and analysis to assist the business in problem location.

[0116] In some examples, such as Figure 5 As shown, for large-bandwidth, multi-node data collection of communication baseband chip services, an example process can be as follows:

[0117] (1) The software starts the data acquisition (Dump) function of the data acquisition device and initializes the service maintenance module, data acquisition device, DMA data transfer device, etc.

[0118] (2) The data acquisition device relies on SOP and EOP as control signals, where SOP is the control signal to start the acquisition of a frame of data, and EOP is the control signal to end the acquisition of a frame of data. If the received data contains the SOP control signal, the frame of data is acquired. Otherwise, the data transmitted from the upstream is not written into the cache (memory);

[0119] (3) When the data acquisition device reaches the packet length configured by the software (such as the preset packet length), the data acquisition device completes the data packetization;

[0120] (4) After the data is packaged, the data acquisition device pushes the write pointer to the DMA data transfer device through hardware interaction. When the DMA data transfer device determines that the write and read pointers are not equal, it transfers the data and moves the frame data in the buffer of the data acquisition device to the DDR memory.

[0121] (5) When the data acquisition device receives the EOP control signal sent from the upstream, the hardware pushes an interrupt to inform the software that the data acquisition of this frame has ended;

[0122] (6) If there is a second frame of data acquisition, the software needs to shut down the DMA data transfer device, manually clear the read and write pointers of the DMA data transfer device and the read pointer of the data acquisition device, and then enable the DMA data transfer device;

[0123] (7) Repeat steps (2) to (6);

[0124] (8) After collecting the last frame of data, the software turns off the data collection (Dump) function of the data acquisition device.

[0125] For example, the cache (memory) write address interaction during data interaction is as follows Figure 6 As shown, after a packet is assembled, the write address is offset to the next free address. When the EOP control signal is received, the data collection of this frame is completed, and the memory write address (WADDR) is reset to the base address configured by the software. However, when facing complex communication data link interactions, there may be scenarios where multiple frames of data need to be collected, that is, multiple pairs of SOP and EOP data. One optional method is that after each frame of data collection is completed (EOP is the sign of the end of each frame collection), the write memory address is automatically reset by the hardware. Assuming that the data transfer path is now occupied, the data of the first frame is not exported in time, and the SOP control signal of the second frame of data is received, the data starts to be written to the memory from the base address, resulting in the following Figure 6As shown in the result after the second frame is packaged, in the example diagram after the second frame is packaged, the valid data packet of the second frame occupies the storage location of the valid data packet of the first frame, that is, the data of the first frame is at risk of being polluted by the second frame.

[0126] Based on the above example, capturing multiple frames of data requires software intervention, including multiple shutdowns of the DMA data mover and pointer resets. This increases software involvement. This can create a risk of data contamination due to untimely data export. This means that when capturing and storing multiple frames of data, software frequently intervenes to complete these operations: after each data frame transfer, the software must shut down the data mover, manually reset the pointer, and re-enable the module to initiate the next frame of data capture and transfer.

[0127] To further optimize the above example solution, hardware processing logic can be used to automatically collect multi-frame data, reduce software involvement in the process, and reduce system overhead. The hardware also automatically implements continuous storage of multi-frame data to avoid the risk of data not being exported in time and being overwritten by the next frame due to channel back pressure. The ring buffer area that fully utilizes memory can improve storage space utilization.

[0128] In some examples, such as Figure 7 The processing flow shown in FIG. 1 is to propose a new data acquisition device (such as Figure 1 Compared with the above example solution (such as Figures 5 and 6 The example scenario shown here achieves three things:

[0129] (1) Intelligent address management mechanism: Figures 5 and 6 In the example solution shown, after the current frame data acquisition is completed, an interrupt is sent to inform the software. If the next frame data acquisition is required, the software intervenes to shut down the module and reset the pointer. Figure 7 In the scheme shown, when the EOP control signal is received, the address of the memory write will not be reset. If the next frame of data needs to be collected, there is no need for the software to turn off the DMA data moving device switch, reset the pointer, and other steps. The hardware logic automatically handles it, and there is no need for the software to participate in the configuration process. The next frame of data starts from the receipt of the SOP control signal, and the storage address remains in an incremental state instead of resetting the base address. The next frame of data can be directly stored continuously from the current end address. Figure 7 The solution shown only requires that the host computer issues a maintenance test switch when the software starts the data acquisition function, and the software is shut down after the data acquisition is completed. The remaining multi-frame data acquisition process relies on hardware to automatically complete the collection, packaging and export of multi-node data.

[0130] (2) Fully hardware pipeline control: Figures 5 and 6In the example solution shown, software needs to intervene frequently and consider the time of intervention. However, facing the complex data interaction process of the communication baseband chip, it is difficult for the software to determine the time when a certain frame appears, and it increases the complexity of software status queries. There is a risk that the upstream module has already sent the next frame of data during the software intervention process, resulting in the risk of data being overwritten. Figure 7 The solution shown builds a hardware-level data protection system. By establishing a processing mechanism based on SOP / EOP, it realizes automatic identification of data frame boundaries and continuous address storage. After collecting the EOP control signal sent by the upstream module, the address of the memory write is not reset to the base address. The next frame of data continues to be written from the next address after the end of the previous frame, without the risk of overwriting the previous frame. At the same time, it reduces the risk of errors caused by excessive software intervention and significantly improves the real-time performance of the system.

[0131] (3) Distributed storage resource scheduling: Figures 5 and 6 In the example scenario shown, when multi-node data is collected concurrently, software intervention is more frequent. However, during chip operation, the processor needs to undertake various complex and arduous tasks and is not guaranteed to participate in data collection in real time. Figure 7 The solution shown innovatively adopts a space pre-allocation + dynamic wrap-around architecture, and implements the storage space management unit through hardware. The software only needs to allocate storage space for different node data during the initialization process. No software intervention is required during the process. The hardware automatically completes the data collection and wrap-around storage of each concurrent node, thereby improving the utilization of storage space.

[0132] For example, Figure 8 As shown, for multi-frame data write memopry address interaction, Figure 8 It also shows in detail how Figure 6 The difference from the scheme shown is that the valid data packet of the second frame continues to be written from the next storage address where the valid data packet of the first frame ends, and will not overwrite the valid data packet stored in the first frame.

[0133] (1) Figure 6 In the example solution shown, after the first frame of data is written, the memory write address (WADDR) will be reset to the base address configured by the software. Assume that the bus pressure is high and the maintenance test channel is back-pressured by other channels. The first frame of data is not exported in time. If the second frame of data is written at this time, the data of the first frame will be polluted. However, in the case of Figures 7 and 8 In the technical solution, after the first frame of data is collected, the address of the memory write will not be reset by the EOP control signal of the previous frame, and the second frame of data is written to the next address after the end of the previous frame, thereby improving the memory space utilization.

[0134] (2) In the technical solution as Figures 7 and 8 each frame of data is continuously written into the memory address space, if the bus is always occupied, as Figure 8 shown, after a packet of the second frame of data is written, the memory space is full, at this time, the hardware automatically reverses the pressure of the previous module to stop data input, to ensure that the data in the memory is not contaminated, after the bus pressure is released and the data is timely exported, the data is written into the released space in the memory.

[0135] The technical solution in the embodiments of the application is mainly applied to a complex communication baseband chip multi-node and multi-frame data interaction scene, and positioning is accurate and effective to capture the field log, and user experience is improved. After the tool side issues a data collection command, the hardware automatically realizes multi-frame data collection and export, reduces the software participation process, and improves the accuracy and intelligence of data collection.

[0136] Based on the above various embodiment descriptions, the technical solution of the embodiment can have the following advantages:

[0137] (1) The software does not need to frequently intervene, reduces system overhead, and reduces power consumption: the software participates only in the initialization process at startup and the closing process after data collection is completed, and in each frame of data collection process, the software does not need to participate, the hardware automatically realizes collection and transmission of each frame of data, reduces system overhead, reduces the problem risk introduced by excessive software participation, and also saves the power consumption of chip operation, improves the standby time of the chip;

[0138] (2) High storage space utilization: each frame of data is continuously stored in the released area following the address of the previous frame, fully utilizes the ring buffer, and improves the space utilization of the memory;

[0139] (3) Improving the correctness of data: the next frame of data is written from the next address of the previous frame of data storage, and will not contaminate the data of the previous frame, when the previous frame of data is not timely exported, the memory space is full, the scheme will reverse the pressure of the previous stage to pause data writing, to ensure the correctness of the data;

[0140] (4) High data transmission efficiency: the bandwidth of data collection in the scheme can reach several GB / s, supporting long-time and large-data collection, and the collection time can reach s level;

[0141] (5) High debugging efficiency: no software intervention is needed in the data collection process, and the hardware can automatically collect data for reporting in case of sudden problems, improving the efficiency of software positioning problems.

[0142] Further, the embodiment of the application provides a chip, which can be configured to perform the method as Figure 3The data collection method shown.

[0143] Furthermore, an embodiment of the present application provides an electronic device, including: Figure 1 The data acquisition device shown, or Figure 2 The data acquisition system shown, or the chip (the chip includes Figure 1 The data acquisition device shown, or Figure 2 The data acquisition system shown, or configured to perform as Figure 3 data collection method shown).

[0144] like Figure 9 FIG. 1 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application, including:

[0145] at least one processor 301;

[0146] a memory 302 in communication with at least one of the processors 301;

[0147] Input device 303;

[0148] Display device 304.

[0149] The processor 301, the memory 302, the input device 303 and the display device 304 may be connected via a bus or other means. Figure 9 The bus connection is taken as an example.

[0150] The input device 303 can receive user clicks and generate signal inputs related to user settings and function control of the data collection method. The display device 304 can include a display device such as a display screen.

[0151] Optionally, the electronic device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, and the like. The user interface may include a display, an input unit such as a keyboard, and the like. The user interface may also optionally include a USB interface, a card reader interface, and the like. The network interface may optionally include a standard wired interface, a wireless interface (such as a Wi-Fi interface), and the like.

[0152] Those skilled in the art will understand that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.

[0153] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0154] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand and implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments described herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A data collection method, characterized in that: The method comprises: receiving a first frame of data and a second frame of data, where the first frame of data and the second frame of data are consecutive data frames; storing the first frame data in a first storage space; In response to reading at least a portion of the first frame data, the second frame data is stored in a second storage space, where the second storage space does not overlap with the first storage space.

2. The method according to claim 1, characterized in that The first storage space and the second storage space are continuous storage spaces.

3. The method according to claim 1, characterized in that The second storage space is the storage space remaining after the data frame is read.

4. The method according to claim 1, wherein The receiving of the first frame data and the second frame data includes: Receiving the first frame data and the second frame data is controlled based on a first control signal and a second control signal, wherein the first control signal is used to determine the start of receiving the frame data, and the second control signal is used to determine the end of receiving the frame data.

5. The method according to claim 1, wherein The method further comprises: Determine a first node corresponding to the first frame data and a second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

6. The method according to claim 5, characterized in that The method further comprises: In response to the cache space corresponding to the first node being full, suspending storage of the frame data of the first node; and / or, In response to the cache space corresponding to the second node being full, storing the frame data of the second node is suspended.

7. The method according to claim 1, characterized in that The first frame data and the second frame data respectively include a timestamp, and the method includes: Calculate the time interval between the first frame data and the second frame data based on the timestamp; The pre-allocated size of the second storage space is dynamically adjusted according to the time interval.

8. The method according to claim 1, characterized in that The method further comprises: Acquire a data access frequency of the first frame data; Determining the data retention period based on the data access frequency; According to the data retention time, resources of at least a portion of the first frame data that has been read in the first storage space are released.

9. A data acquisition device, characterized in that: include: A receiving unit, configured to receive a first frame of data and a second frame of data, wherein the first frame of data and the second frame of data are consecutive data frames; a storage unit, the storage unit being connected to the receiving unit, and the storage unit being configured to store the first frame data in a first storage space; In response to reading at least a portion of the first frame data, the second frame data is stored in a second storage space, where the second storage space does not overlap with the first storage space.

10. The device according to claim 9, characterized in that The device further comprises: A determination unit, the determination unit is connected to the receiving unit, and the determination unit is used to determine a first node corresponding to the first frame data and a second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

11. The device according to claim 10, characterized in that The storage unit is further configured to suspend storage of the frame data of the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of the frame data of the second node in response to the cache space corresponding to the second node being full.

12. The device according to claim 9, characterized in that The first frame data and the second frame data respectively include a timestamp; The storage unit is further configured to calculate a time interval between the first frame data and the second frame data based on the timestamp; and dynamically adjust a pre-allocated size of the second storage space according to the time interval.

13. The device according to claim 9, characterized in that The storage unit is further used to obtain a data access frequency of the first frame data; determine a data retention period based on the data access frequency; and release resources of at least a portion of the first frame data that has been read in the first storage space according to the data retention period.

14. A data acquisition system, characterized in that: include: A data acquisition device, the data acquisition device is used to receive a first frame of data and a second frame of data from a communication baseband chip, wherein the first frame of data and the second frame of data are continuous data frames; storing the first frame data in a first storage space; a data moving device, the data moving device being connected to the data acquisition device and configured to read at least a portion of the first frame of data into a memory; The data acquisition device is further configured to store the second frame data in a second storage space in response to the data moving device reading at least a portion of the first frame data, wherein the second storage space does not overlap with the first storage space.

15. The system according to claim 14, wherein: The data acquisition device is also used to determine the first node corresponding to the first frame data and the second node corresponding to the second frame data, wherein the first storage space belongs to the storage space corresponding to the first node, and the second storage space belongs to the storage space corresponding to the second node.

16. The system according to claim 15, wherein: The data acquisition device is also used to suspend storage of frame data of the first node in response to the cache space corresponding to the first node being full; and / or suspend storage of frame data of the second node in response to the cache space corresponding to the second node being full.

17. The system according to claim 14, wherein: The first frame data and the second frame data respectively include a timestamp; The data acquisition device is further configured to calculate a time interval between the first frame data and the second frame data based on the timestamp; and dynamically adjust a pre-allocated size of the second storage space according to the time interval.

18. The system according to claim 14, wherein: The data acquisition device is also used to obtain the data access frequency of the first frame data; determine the data retention time based on the data access frequency; and release resources of at least part of the first frame data that has been read in the first storage space according to the data retention time.

19. A chip, characterized in that: The chip is configured to execute the data acquisition method according to any one of claims 1 to 8.

20. A chip, characterized in that: The data acquisition device comprises the data acquisition device according to any one of claims 9 to 13, or the data acquisition system according to any one of claims 14 to 18.

21. An electronic device, characterized in that: The data acquisition device comprises any one of claims 9 to 13, or the data acquisition system according to any one of claims 14 to 18, or the chip according to any one of claims 19 to 20.

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