CMOS intensive model parameter generation method based on flow model
Through the flow model-based method, a Gaussian distribution that can reflect the correlation between parameters is generated, which solves the modeling problem of insufficient transistor intensive model library in EDA software and realizes the efficient design of large-scale integrated circuit simulation.
Patent Information
- Application Number
- CN202510927584.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-10-14
AI Technical Summary
Existing technology makes it difficult to build a comprehensive model library containing statistical information such as fluctuations and aging in EDA software, resulting in the inability to accurately reflect the true characteristics of transistors during circuit simulation. In particular, the problem of model repeated sampling is serious in large-scale integrated circuit design.
A flow model-based approach is used to learn the intrinsic distribution laws of device parameters, construct bidirectional mapping and neural network transformation, generate a Gaussian distribution that can reflect the correlation between parameters, achieve accurate simulation of fluctuations and aging effects, and generate an unlimited number of parameter samples.
It achieves the generation of transistor intensive models that accurately reflect the real circuit characteristics within milliseconds, improves the design efficiency of large-scale integrated circuit simulation, solves the problem of model repeated sampling, and maintains parameter distribution and correlation.
Smart Images
Figure CN120781689A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of integrated circuits, and relates to a generation method of a CMOS intensive model based on a flow model. BACKGROUND
[0002] With the continuous reduction of device size, especially the extreme miniaturization of leading-edge devices such as nanosheet gate-all-around transistors, the influence of statistical fluctuations on transistors is inevitable, and the construction of an intensive model library containing statistical information such as fluctuations and aging in EDA software is the key to realizing correct simulation. However, constructing a model library by directly extracting parameters from experimental or TCAD simulation data will be limited by the amount of data, resulting in limited models, repeated sampling of transistor intensive model samples during circuit simulation, and the inability to reflect the influence of statistical quantities on the circuit, making it difficult to meet the needs of large-scale integrated circuit design. Currently, the industry mainly uses methods based on threshold voltage parameter value distribution or principal component analysis to generate infinite parameter sets, but the former cannot capture the influence of factors other than threshold voltage, and the latter can only maintain a Gaussian distribution, cannot preserve the original parameter distribution and parameter correlation, and lacks fitting of original parameter correlation and tail, and all of them cannot accurately reflect the real circuit characteristics, so a new intensive model generation method that is real-time and efficient, can maintain parameter distribution and correlation, and reflects the influence of statistical quantities is urgently needed. SUMMARY
[0003] The application provides a parameter generation method based on a flow model to solve the problem of insufficient statistical characteristic modeling in the generation of intensive model parameters for nanoscale CMOS devices, learns the internal distribution law of device parameters, accurately simulates physical effects such as fluctuations and aging, and provides real and reliable parameter support for large-scale integrated circuit simulation.
[0004] The application adopts the following technical solution: a generation method of a CMOS intensive model based on a flow model, comprising the following steps: S1: key parameter extraction step The electrical characteristic curve of a transistor produced by TCAD simulation or actual transistor containing fluctuations, aging and other statistical information is taken as a target electrical characteristic curve, and the existing parameter extraction method of the intensive model is used to extract the corresponding intensive model key parameter value of each transistor, and the set of all extracted key parameter values constitutes a basic parameter group used to generate the intensive model in real time; S2: distribution modeling step By utilizing the reversible transformation principle of the flow model, a bidirectional mapping from the parameter space to the latent space is constructed. The values of the basic parameter set generated in step S1 are normalized and transformed, and the parameters are dynamically scaled to eliminate dimensional differences and make different parameters in the same modeling dimension. Through reversible dimension replacement operations (such as randomizing the order of parameters), the spatial independence between parameters is broken, and feature interaction is promoted. The parameters are divided into two groups, and a neural network (such as a multilayer perceptron) is used to analyze one group of parameters to generate a transformation rule (such as a scaling factor and an offset) for the other group of parameters, thereby capturing the nonlinear dependence between parameters (for example, the coordinated change of threshold voltage and parasitic capacitance). Through the superposition of multiple layers of the above transformation, the flow model gradually "stretches" or "distorts" the complex parameter distribution into a simple standard distribution (such as a Gaussian distribution), while recording the details of each transformation step for reverse restoration.
[0005] : Parameter generation step According to the processing of step S2, a random vector is sampled in a simple distribution (such as a Gaussian distribution), and physical effects are converted into mathematical distribution changes by adjusting the sampling range or adding specific mode disturbances (such as simulating the trend of aging bias or simulating random noise of fluctuation). Due to the reversibility of the flow model, the disturbed random vector is transformed back to a new sample in the real parameter space. Since the transformation process preserves the distribution characteristics of the original parameters and the correlation between parameters, the generated parameters can truly reflect the performance changes of the device under the effects of fluctuation and aging; the generated parameters are directly imported into circuit simulation software such as SPICE to replace the traditional finite sample library, enabling real-time parameter calling for large-scale transistor arrays, and making the simulation results reflect the diversity and statistical rules of device parameters in real circuits.
[0006] Preferably, the flow model can learn complex correlations between parameters (such as the negative correlation between threshold voltage increase and mobility decrease) through multiple layers of nonlinear transformation, without assuming Gaussian distribution or linear correlation of parameters as in traditional methods (such as principal component analysis), thus being closer to the physical characteristics of real devices.
[0007] Preferably, in step S2, different disturbance modes can be designed in the latent space to explicitly control the physical effects contained in the generated parameters: Gaussian noise disturbance corresponds to random fluctuation (such as manufacturing process deviation); linear offset disturbance corresponds to systematic aging (such as parameter drift caused by long-term work); multi-modal distribution disturbance corresponds to parameter differences under different working conditions.
[0008] Preferably, in step S3, once the flow model is trained, it can generate an infinite number of parameter samples through simple mathematical transformation (inverse mapping) in real time, avoiding the time-consuming process of relying on a large number of experimental or simulation data to construct a sample library in traditional methods, and significantly improving modeling efficiency.
[0009] Compared with the prior art, the present application has the following advantages: The present application can realize real-time generation of transistor infinite compact model for large-scale integrated circuit simulation, and improve design efficiency. The present application can quickly generate a new parameter set containing statistical information such as fluctuation and aging based on an algorithm, maintain the efficiency of generating a compact model on the basis of accurately reflecting the characteristics of a real circuit, and the generation rate of the model can reach milliseconds. The present application can solve the problem of repeated sampling of a model in the design of a large-scale integrated circuit using EDA software.
[0010] Compared with the prior art, the present application can solve the problem that a real-time generated compact model cannot capture the influence of factors other than threshold voltage on the electrical characteristics of a device, and the real-time generated parameter set can maintain the original parameter distribution and parameter correlation. The model generated by the present application contains statistical information such as fluctuation and aging, and can more realistically reflect the characteristics of a device and the related effects caused by statistical quantities such as fluctuation and aging of a device in a semiconductor manufacturing process in circuit simulation. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 To realize the flowchart of the present application. DETAILED DESCRIPTION
[0012] The present application provides an embodiment: The technical solutions in the embodiments of the present application are clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.
[0013] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and do not define the limiting conditions for the implementation of the present application, and therefore do not have technical substantive significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present application, should fall within the scope of the technical content disclosed by the present application. It should be noted that in the present specification, relationship terms such as first and second are only used to distinguish one entity from another entity, and do not necessarily require or imply any actual relationship or order between the entities.
[0014] S1: key parameter extraction step TCAD simulation or actual transistor containing statistical information of fluctuation, aging and process, etc. The electrical characteristic curve is taken as the target electrical characteristic curve, and the existing parameter extraction method of the intensive model is used to extract the corresponding key parameter value of each transistor. The set of all extracted key parameter values constitutes the basic parameter group used to generate the intensive model in real time subsequently; For nanosheet gate-all-around transistors, 7-dimensional key parameters are selected: PHIG (gate work function difference), U0 (surface potential), CIT (interface trap capacitance), CDSCD (source-drain parasitic capacitance), ETAMOB (mobility modulation parameter), EU (electric field factor), and VSAT (carrier saturation velocity). By loading the industrial standard intensive model (such as BSIM4) through the SPICE simulation software, the parameters are manually adjusted to make the ID-VG and ID-VD curves simulated by the output error less than 5% compared with the TCAD simulation results, and the reference parameter group is determined.
[0015] From 1000 TCAD simulation devices, parameters are extracted to construct the original data set df, and each line is a 7-dimensional parameter vector of a device. The parameters are mapped to a normal distribution and standardized to eliminate dimensional differences.
[0016] In this embodiment, the key parameters include gate work function PHIG, surface potential well parameter CIT, low-field mobility U0, phonon / surface roughness scattering parameter EU, effective field parameter ETAMOB, drain-induced barrier lowering coefficient CDSCD, and carrier saturation velocity VSAT. As shown in Table 1 Table 1 Important parameters of BSIM-CMG model S2: distribution modeling step A parameter joint probability distribution learning method of multi-layer reversible transformation is constructed, which includes a flow model composed of at least 3 reversible transformation levels in series. The model is trained by maximizing the log-likelihood function, so as to learn the joint probability distribution of the basic parameter group in step S1 and maintain the statistical dependence relationship and physical constraint conditions between parameters. Each level contains a data standardization unit for standardizing the input features; a dimension mixing unit for realizing mixing between feature channels through reversible operation; and a conditional transformation unit for dividing the input features into two parts and performing conditional transformation including additive transformation, multiplicative transformation or their combination on one part based on the other part; The dimension mixing unit breaks the spatial independence between parameters by randomly permuting the dimension order, promotes feature mixing, and ensures that the information of each dimension is fully interacted in the subsequent coupling block. The conditional transformation unit adopts a specific split ratio to divide the 7-dimensional parameters into two parts. The parameters of the first part of the dimension are used as input to generate the scale s and offset t of the parameters of the second part of the dimension through two layers of MLP (256 neurons per layer, with GELU activation and LayerNorm), to realize affine transformation y2=z2⊙exp(s)+t, to capture the nonlinear dependence between parameters, and to prevent numerical overflow by limiting the scale parameter range clamp=2.5.
[0017] During training, the self-defined CorrelationLoss loss function combines the basic loss and the correlation penalty term. The former ensures the probability fidelity of reversible transformation and the accuracy of data distribution restoration by minimizing the L2 norm of latent variable z and maximizing the logarithmic Jacobian determinant. The latter enforces the correlation coefficient matrix of the generated parameters to be consistent with the original data with a certain weight, preserving the correlation between parameters. The optimization configuration uses the AdamW optimizer and the cosine annealing learning rate scheduler. The training monitoring ensures the balanced decline of the two types of losses by printing the loss value every 500 cycles, and verifies the distribution consistency of the generated parameters and the original data using the K-S test (e.g., PHIG parameter K-S test p=0.12>0.05, passed the test), ensuring the effective learning of the model on the distribution characteristics of the original data.
[0018] : Parameter generation step The latent vector is sampled from a standard Gaussian distribution, and the latent vector is mapped to the target parameter group through the inverse transformation of the trained flow model. During the generation process, fluctuations, aging, and other statistical quantities are injected by adjusting the distribution parameters of the latent vector, and the generated parameter group is embedded in or associated with the SPICE software. When calling the SPICE software to simulate the circuit, this module generates an unlimited set of transistor compact model parameters for large-scale integrated circuit simulation in real time, realizing large-scale statistical simulation of real circuits.
Claims
1. A method for generating CMOS intensive model parameters based on a flow model, characterized in that: The following steps are involved: S1: Key parameter extraction steps: The electrical characteristic curves generated by TCAD simulations or actual transistors, which include fluctuations, aging, and other statistical information, are used as target electrical characteristic curves. The existing parameter extraction methods for intensive models are used to extract the corresponding key parameter values of the intensive model for each transistor. The set of all extracted key parameter values constitutes the basic parameter set used to subsequently generate the intensive model in real time. S2: Distribution modeling steps: Constructing a method for learning the joint probability distribution of parameters of a multi-layer reversible transformation, the method comprising: establishing a flow model consisting of at least three reversible transformation layers connected in series, and training the model by maximizing a log-likelihood function to enable it to learn the joint probability distribution of the basic parameter group described in step S1 while maintaining the statistical dependencies and physical constraints between the parameters; Each layer includes a data normalization unit that normalizes the input features; a dimension mixing unit that achieves mixing between feature channels through reversible operations; and a conditional transformation unit that divides the input features into two parts and performs an additive transformation, a multiplicative transformation, or a combination thereof on the other part based on one part; S3: Parameter generation step: The joint probability distribution p(X) of the basic parameter group is mapped to a standard Gaussian distribution p(z) through the trained flow model. At this time, the potential vector is sampled from the standard Gaussian distribution z~N(0,1) as the starting point for generating new parameters; During the generation process, statistics such as fluctuations and aging are injected by adjusting the distribution parameters of the potential vector, and the generated parameter group is embedded in SPICE software or associated with the software; when calling SPICE software to simulate the circuit, the module generates an infinite transistor intensive model for large-scale integrated circuit simulation in real time, realizing large-scale statistical simulation of the real circuit.
2. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: Step S1 selects several physical parameters that have a key influence on the electrical characteristics of the device and several fitting parameters used to adjust the simulation results as key parameters; by adjusting the values of the above key parameters, the electrical characteristic curve output by the intensive model can be made to fit the target electrical characteristic curve of the corresponding transistor, thereby realizing the extraction of the selected parameters.
3. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The data normalization unit in step S2 performs normalization according to the mean and variance of the extracted key parameter group in the initial stage of training, so that the mean of the input feature is 0 and the variance is 1. The data normalization unit includes but is not limited to being implemented through an explicit normalization layer (such as activation normalization, batch normalization) or an implicit normalization mechanism (such as weight normalization), thereby improving the fitting accuracy of the flow model to the small sample distribution of CMOS parameters.
4. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The dimensional mixing unit in step S2 achieves parameter dimension mixing through a reversible permutation matrix, wherein the reversible permutation matrix includes a randomly initialized orthogonal matrix or a fixed permutation matrix whose Jacobian determinant has an absolute value of 1, thereby reducing the log-likelihood calculation complexity from O(n²) to O(n).
5. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The conditional transformation unit in step S2 divides the input parameters into two parts, generates scale and offset parameters for the first part of the parameters through a nonlinear sub-network, and performs a conditional transformation including additive transformation, multiplicative transformation or a combination thereof on the second part of the parameters, wherein the nonlinear sub-network is a multilayer perceptron comprising at least two hidden layers and nonlinear activation functions between layers, thereby enhancing the model's ability to express nonlinear dependencies between parameters.
6. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The split ratio of the conditional transformation unit in step S2 is (k:(nk)), where n is the total number of parameter dimensions, k is the number of parameter dimensions of the input nonlinear subnetwork, and the output dimension of the nonlinear subnetwork is 2 (nk), corresponding to the scale parameter and the offset parameter respectively, and the value range of k is 1≤k≤n-1.
7. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: Step S2 balances complexity and efficiency by adjusting the number of neurons, introduces nonlinearity through activation functions, and stabilizes the training process through layer normalization, thereby ensuring that the nonlinear sub-network can efficiently and accurately learn the physical laws or parameter mapping relationships of CMOS devices, thereby generating reliable intensive model parameters.
8. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The method of injecting fluctuation and aging statistics in step S3 includes adding Gaussian noise to the potential vector z, adjusting the variance of the potential distribution, or introducing an offset related to the degree of aging during the inverse transformation process.
9. The method for generating CMOS intensive model parameters based on a flow model according to claim 1, wherein: The intensive model is any intensive model that complies with industrial standards, the simulation software used in the key parameter extraction process is any SPICE software, and the key parameter value extraction method includes but is not limited to any one of BSIM, HiSIM, and PSP model manuals.