MIMO wireless communication channel matrix compression calculation method and device

Abstract

The invention discloses an MIMO wireless communication channel matrix compression calculation method and device, and the method comprises the steps: marking the position of a non-zero element in a channel matrix as 1, marking the position of a zero element as 0, and generating a binary index matrix; performing addressing and aggregation operation on non-zero elements in the channel matrix according to a column priority based on the binary index matrix, and sequentially writing the non-zero elements into a preset continuous storage space in the memory according to the column priority to generate a compression matrix; and sequentially aiming at each calculation unit, firstly determining a corresponding index column according to the binary index matrix, counting non-zero elements in the index column, if the count is greater than 0, performing multiplication and addition operation based on a multiplication and addition operation module, and if the count is equal to 0, writing a 0 value into a partial sum accumulation register as an operation result of the current calculation unit. According to the scheme of the invention, the storage overhead of the MIMO wireless communication channel matrix can be reduced, and the calculation efficiency of the channel matrix can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a MIMO wireless communication channel matrix compression calculation method and device. BACKGROUND

[0002] MIMO (Multiple Input Multiple Output) is a key technology in wireless communication. In a MIMO wireless communication system, a channel matrix is used to describe the wireless channel state between the transmitting end and the receiving end. Due to high antenna deployment density and complex channel environment, the MIMO channel matrix in practice often has high sparsity, i.e., there are a large number of zero elements in the matrix.

[0003] The prior art usually adopts a general sparse matrix compression format (such as CSR, BCSR, etc.) when storing a sparse matrix such as a MIMO wireless communication channel matrix. However, these formats have the problem of large storage overhead when facing the characteristics of uneven sparsity distribution and diverse sparsity patterns of the channel matrix.

[0004] In addition, in the multiplication operation process of the sparse matrix, the prior art usually fails to fully utilize the sparsity characteristics of the matrix, and a large number of zero elements are not effectively skipped in the operation, resulting in serious waste of computing resources.

[0005] Therefore, the prior art urgently needs a MIMO channel matrix processing method that can simultaneously consider sparse matrix compression storage and efficient multiplication and addition operation, in order to reduce storage overhead and improve computing efficiency, and adapt to the dual requirements of resources and performance of large-scale communication systems. SUMMARY

[0006] The present application proposes a MIMO wireless communication channel matrix compression calculation method and device to solve at least one of the technical problems in the background art.

[0007] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a MIMO wireless communication channel matrix compression calculation method is provided, which comprises:

[0008] Marking the non-zero element positions in the MIMO wireless communication channel matrix as 1 and the zero element positions as 0 to generate a binary index matrix, and storing the binary index matrix in a memory;

[0009] Based on the binary index matrix, performing addressing and aggregation operations on the non-zero elements in the channel matrix in column priority order, and writing each non-zero element in the column priority order into a pre-set continuous storage space in the memory to generate a compressed matrix;

[0010] In the calculation, for each calculation unit in turn, first, the corresponding index column is determined according to the binary index matrix, the non-zero elements in the index column are counted, if the count is greater than 0, the corresponding data in the input data and the compressed matrix is selected based on the index column, the selected data is multiplied and added based on the multiplication and addition operation module, and then the operation result is stored in the partial sum accumulation register, if the count is equal to 0, the partial sum accumulation register writes 0 value as the operation result of the current calculation unit, and the calculation unit is logically divided into a group of every N elements according to the column priority order.

[0011] Optionally, if the count is greater than 0, the corresponding data in the input data and the compressed matrix is selected based on the index column, the selected data is multiplied and added based on the multiplication and addition operation module, and then the operation result is stored in the partial sum accumulation register, comprising:

[0012] If the count is less than or equal to M, the selected data is multiplied and added based on the multiplication and addition operation module, and then the operation result is stored in the partial sum accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2, and less than N;

[0013] If the count is greater than M, first, the first M data in the selected data is multiplied and added based on the multiplication and addition operation module, and the operation result is temporarily stored, then the remaining data in the selected data is multiplied and added based on the multiplication and addition operation module, and the sum of the operation result and the temporarily stored operation result is stored in the partial sum accumulation register.

[0014] Optionally, in the processing of complex data calculation, the multiplication and addition operation module adopts a multiplication and addition operation module based on Gauss algorithm.

[0015] Optionally, the counting of the non-zero elements in the index column comprises:

[0016] The index column is sent to a reusable flag controller, and the non-zero elements in the index column are counted by a counter in the reusable flag controller;

[0017] If the count is equal to 0, the partial sum accumulation register writes 0 value as the operation result of the current calculation unit, comprising:

[0018] The count is compared with 0 and M by a comparator in the reusable flag controller, if the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register, so that the partial sum accumulation register writes 0 value as the operation result of the current calculation unit according to the first control signal.

[0019] Optionally, if the count is less than or equal to M, the selected data is multiplied and added based on the multiplication and addition module, and the operation result is stored in the partial sum and accumulation register, including:

[0020] If the count is less than or equal to M, the comparator outputs a second control signal to the multiplication and addition module and the multiplexer, so that the multiplication and addition module selects the corresponding data in the input data and the compressed matrix based on the second control signal according to the index column, and performs multiplication and addition operation, and then sends the operation result to the multiplexer, and the multiplexer stores the operation result in the partial sum and accumulation register according to the second control signal.

[0021] Optionally, if the count is greater than M, the first M data in the selected data is multiplied and added based on the multiplication and addition module, and the operation result is temporarily stored, and then the remaining data in the selected data is multiplied and added based on the multiplication and addition module, and the sum of the operation result of this time and the temporarily stored operation result is stored in the partial sum and accumulation register, including:

[0022] If the count is greater than M, the comparator outputs a third control signal to the multiplication and addition module and the multiplexer, so that the multiplication and addition module selects the corresponding data in the input data and the compressed matrix based on the third control signal according to the index column, and performs multiplication and addition operation on the first M data in the selected data to obtain a first operation result and send it to the multiplexer, and then performs multiplication and addition operation on the remaining data in the selected data to obtain a second operation result and send it to the multiplexer, and the multiplexer sends the first operation result to the register and the second operation result to the summer according to the third control signal, the summer performs summation on the second operation result and the first operation result in the register, and sends the summation result to the partial sum and accumulation register for storage.

[0023] Optionally, the memory is a spin-orbit torque magnetoresistive random access memory.

[0024] In order to achieve the above purpose, according to another aspect of the present application, a MIMO wireless communication channel matrix compression calculation device is provided, which comprises:

[0025] A binary index matrix generation and storage module is configured to mark the position of non-zero elements in the MIMO wireless communication channel matrix as 1 and mark the position of zero elements as 0, generate a binary index matrix, and store the binary index matrix in the memory.

[0026] The matrix compression storage module is configured to address and aggregate non-zero elements in the channel matrix based on the binary index matrix in a column-first order, and sequentially write the non-zero elements into a preset continuous storage space in the memory in the column-first order, to generate a compressed matrix.

[0027] The in-memory computing module is configured to, when performing computation, sequentially for each computing unit, first determine a corresponding index column according to the binary index matrix, count non-zero elements in the index column, if the count is greater than 0, select corresponding data in the input data and the compressed matrix based on the index column, perform multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then store the operation result into a partial sum and accumulation register, if the count is equal to 0, the partial sum and accumulation register writes 0 as the operation result of the current computing unit, and the computing unit is a unit logically divided into groups of N elements in the column-first order.

[0028] Optionally, the in-memory computing module is specifically configured to:

[0029] If the count is less than or equal to M, perform multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then store the operation result into the partial sum and accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2, and less than N;

[0030] If the count is greater than M, first perform multiplication and addition operation on the first M data in the selected data based on the multiplication and addition operation module, temporarily store the operation result, then perform multiplication and addition operation on the remaining data in the selected data based on the multiplication and addition operation module, and store the sum of the operation result and the temporarily stored operation result into the partial sum and accumulation register.

[0031] Optionally, the in-memory computing module comprises a multiplexable flag controller, a multiplication and addition operation module, a multiplexer, a register, and a partial sum and accumulation register; the multiplexable flag controller comprises a counter and a comparator.

[0032] The counter is configured to count the non-zero elements in the index column.

[0033] The comparator is configured to compare the count with 0 and M.

[0034] If the count is equal to 0, the comparator outputs a first control signal to the partial sum and accumulation register, so that the partial sum and accumulation register writes 0 as the operation result of the current computing unit according to the first control signal.

[0035] If the count is less than or equal to M, the comparator outputs a second control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the second control signal, and performs multiply-add operation, and then sends the operation result to the multiplexer, and the multiplexer sends the operation result to the partial sum accumulation register for storage according to the second control signal;

[0036] If the count is greater than M, the comparator outputs a third control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the third control signal, and performs multiply-add operation on the first M data in the selected data to obtain a first operation result and send it to the multiplexer, and then performs multiply-add operation on the remaining data in the selected data to obtain a second operation result and send it to the multiplexer, and the multiplexer sends the first operation result to the register according to the third control signal, and sends the second operation result to the summer, and the summer performs summation on the second operation result and the first operation result in the register, and sends the summation result to the partial sum accumulation register for storage.

[0037] The present application has the following advantages:

[0038] The MIMO wireless communication channel matrix compression calculation method provided by the present application generates and stores a binary index matrix, only identifies and records the non-zero elements in the channel matrix, combines the addressing and aggregation operation of column priority order, and writes the non-zero elements into a continuous storage space in sequence to form a compressed matrix, thereby significantly reducing the data storage of redundant zero elements and effectively reducing the storage overhead of the sparse channel matrix. In the calculation process, the channel matrix is logically divided into a calculation unit of every N elements, and the index matrix is used to count the non-zero elements in each calculation unit. When no non-zero element is detected in the current calculation unit, 0 is directly written as the operation result; when there is a non-zero element, only the corresponding data is subjected to multiply-add operation and written into the partial sum accumulation register, thereby avoiding the invalid processing of zero elements at the calculation level and improving the operation efficiency. Therefore, the present application can reduce the storage resource consumption of the MIMO channel matrix and improve the multiply-add calculation efficiency of the sparse matrix, and is suitable for the demand for efficient data processing in large-scale antenna communication scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings. In the drawings:

[0040] Figure 1 is a flow chart of the MIMO wireless communication channel matrix compression calculation method of the embodiment of the present application;

[0041] Figure 2 is a data storage schematic diagram of the embodiment of the present application;

[0042] Figure 3 is a Gaussian complex multiplication operation schematic diagram of the embodiment of the present application;

[0043] Figure 4 is an in-memory calculation schematic diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0044] In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should be within the scope of protection of the present application.

[0045] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0046] It should be noted that the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device containing a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] Figure 1 is a flowchart of the MIMO wireless communication channel matrix compression calculation method of the embodiment of the present application, as shown in the present application, in one embodiment, the MIMO wireless communication channel matrix compression calculation method of the present application comprises steps S101 to S103. Figure 1

[0049] Step S101, mark the non-zero element position in the MIMO wireless communication channel matrix as 1 and the zero element position as 0 to generate a binary index matrix, and store the binary index matrix in the memory.

[0050] The present application adopts the binary index method to pre-process the channel matrix structure, which can directly extract the distribution of non-zero elements. By marking all non-zero elements as 1 and zero elements as 0, a Boolean matrix is obtained, which simplifies the subsequent non-zero data positioning and aggregation operation. This Boolean index structure can quickly determine whether any position is valid calculation data, thereby improving the processing efficiency of sparse matrices. The index matrix has the same dimension as the original matrix, facilitating one-to-one correspondence and supporting direct positioning. In this way, invalid operations can be significantly reduced, and invalid data paths can be excluded in advance.

[0051] In one embodiment of the present application, during the compression processing of the sparse matrix (referring to the MIMO wireless communication channel matrix), the present application first performs binary index encoding on the sparse matrix: based on the non-zero characteristics of the matrix elements, a Boolean index matrix is constructed, in which the non-zero element coordinate position is marked as logical 1 and the zero value element is marked as logical 0, generating a binary index matrix with the same dimension as the sparse matrix.

[0052] Step S102, based on the binary index matrix, the non-zero elements in the channel matrix are addressed and aggregated in column priority order, and each non-zero element is written into the pre-set continuous storage space in the memory in column priority order to generate a compressed matrix.

[0053] In one embodiment of the present application, the present application adopts a column priority compression strategy during the non-zero element aggregation process, which makes the matrix aggregated in column order, which is suitable for the structural characteristics of the communication channel matrix. In the MIMO system, the channel response is more coherent in the column dimension, and the column priority method is more consistent with the actual organization structure of the data. Through column direction index extraction, non-zero elements can be continuously written into the compressed matrix to construct a high-density data block. The zero element corresponding position is automatically excluded during the writing process, avoiding unnecessary storage space occupation. ​

[0054] In one embodiment of the present application, the present application performs a column-major order-based sparse compression operation, and the specific process is as follows: according to the marking information of the binary index matrix, the non-zero elements are coordinate-addressed and aggregated along the column direction, the continuous non-zero elements are written into the continuous storage space of the compressed matrix according to the column sequence, and at the same time, the redundant storage units occupied by the zero value elements are dynamically removed, and finally the compressed storage structure of the high-density non-zero data block and the corresponding index mapping table is generated.

[0055] In the compression process, the system dynamically skips the zero value elements, and only the effective data is written, which can significantly improve the compression ratio. The continuous storage mode facilitates the improvement of data reading, caching and access efficiency, and the compressed data is more compact, reducing the bandwidth consumption during memory access. Compared with the general sparse matrix format (such as CSR), this strategy is more suitable for this scenario, and can directly cooperate with the index mapping, facilitating subsequent hardware scheduling.

[0056] In one embodiment of the present application, when storing, the memory only stores the binary index matrix and the compressed matrix, as shown in the embodiment of the present application, compared with the prior art, the storage overhead of the sparse matrix is reduced. Figure 2 The present application only stores the compressed matrix and the corresponding binary index matrix, and omits the zero value data and redundant coordinate information in the original matrix, which greatly reduces the storage load compared with the traditional sparse format. This way of the present application simplifies the memory structure on the one hand, and reduces the reading pressure of data in the calculation process on the other hand. It is suitable for communication terminals or base station devices with strict limitations on memory resources and bandwidth.

[0057] In one embodiment of the present application, the memory is a spin-orbit torque magnetoresistive random access memory (SOT-MRAM).

[0058] The present application adopts a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) as the storage medium of the compressed matrix and the binary index matrix. The SOT-MRAM has the characteristics of non-volatility, high write durability, low power consumption, etc., can reduce the data refresh frequency and adapt to the frequent data update demand, and is suitable for the storage characteristics of dynamic sparse matrix in wireless communication. At the same time, the SOT-MRAM supports fast parallel access, facilitates the writing and extraction of continuous data blocks, and can improve the access efficiency of the sparse matrix in the column-major compression mode.

[0059] In addition, the SOT-MRAM has bit-level access capability, can efficiently support the data structure of bit control in the binary index matrix, and further reduces storage redundancy. The low delay and asynchronous access characteristics enable the SOT-MRAM to be directly connected to the multiply-add operation module, improve the collaborative efficiency of data loading and calculation scheduling, and are particularly suitable for the dynamic multiply-add operation process based on sparse sensing proposed in the application, and help to improve the calculation performance and energy efficiency ratio of the overall system.

[0060] In step S103, when calculating, for each calculation unit in turn, the non-zero elements in the index column are counted according to the binary index matrix, if the count is greater than 0, the corresponding data in the input data and the compressed matrix are selected based on the index column, the selected data are subjected to multiply-add operation based on the multiply-add operation module, and then the operation result is stored in the partial sum accumulation register, if the count is equal to 0, the partial sum accumulation register writes 0 as the operation result of the current calculation unit, and the calculation unit is a unit logically divided by the channel matrix according to column priority order, with N elements in each group.

[0061] In the application, the MIMO wireless communication channel matrix is logically divided according to column priority order, and N elements in each column of the matrix are taken as a calculation unit for processing. In the calculation phase, the binary index information corresponding to each calculation unit is read in turn, specifically: from the binary index matrix, an index column composed of N bits corresponding to the calculation unit in the current column is extracted according to column priority order, which is used to indicate whether each position in the unit is a non-zero element. The index column is used to drive the subsequent data selection, counting and multiply-add control process, and is a key input for realizing sparse calculation scheduling.

[0062] In the application, in the calculation phase, the application quickly identifies the non-zero data position corresponding to each calculation unit through the index matrix, without traversing the original matrix to complete data positioning. The number of non-zero elements is quickly obtained through the counter, and it is judged whether to perform multiply-add operation according to the number. Each calculation unit is a logically divided processing block, which is composed of continuous N elements, and can realize parallel scheduling and data block multiplexing under the condition of limited calculation resources.

[0063] If the count is 0, the system directly skips the multiplier calculation process and outputs zero value, avoiding resource waste. If there is a non-zero element, only the corresponding data is subjected to multiply-add operation, and the result is stored in the partial sum register. The judgment mechanism based on sparse sensing in the application can dynamically control whether to activate the calculation logic, effectively reduce power consumption and unnecessary operation, and is particularly suitable for special communication processors or system on chips with limited multiplier resources.

[0064] In one embodiment of the present application, in order to balance the granularity of data division and the resource configuration of the hardware processing unit, the number of elements N contained in each calculation unit is specifically set to 8. This setting facilitates one-to-one correspondence with 8-bit index flag bits, is conducive to realizing bit-by-bit identification and control, simplifies hardware design, and improves the efficiency of index matching and calculation scheduling.

[0065] It can be seen that, by steps S101 to S103, the present application realizes efficient utilization of the sparsity of the MIMO wireless communication channel matrix, extracts the position of the non-zero element by using a binary index method, and combines column priority order for compressed storage, effectively reducing the storage overhead of redundant data. In the calculation process, whether to perform multiplication and addition operation is dynamically judged according to the index information, and only non-zero data is calculated or zero result is directly written, avoiding invalid operation on zero elements, thereby reducing the consumption of storage resources while improving the overall calculation efficiency of the sparse matrix.

[0066] In one embodiment of the present application, when processing complex data calculation, the multiplication and addition operation module adopts a multiplication and addition operation module based on Gaussian algorithm.

[0067] In typical application scenarios such as 5G channel estimation and millimeter wave radar signal processing, the system needs to frequently perform large-scale complex multiplication. Traditional complex multiplication is usually realized by the following calculation formula: if there are two complex numbers A=ar+jai and B=br+jbi, then their product is AB=(arbr-aibi)+j(arbi+aibr), which involves 4 times of real number multiplication and 2 times of addition, and the calculation resource consumption is high, especially in large-scale sparse matrix multiplication process.

[0068] To reduce the operation overhead and improve the calculation efficiency, the present application introduces Gaussian complex multiplication algorithm. Gaussian algorithm reduces the number of multiplication from 4 times to 3 times and increases the number of addition from 2 times to 5 times by formula transformation while keeping the operation correct. Since the area and power consumption of the multiplier are much higher than those of the adder in hardware implementation, this optimization strategy can significantly reduce resource consumption and improve overall calculation performance.

[0069] As shown in FIG. 1, Figure 3 In one embodiment of the present application, the system uses 16-bit fixed-point data for complex calculation. Let the input data be INPUT=IR+jII, and the multiplication factor be DATA=DR+jDI. Gaussian complex multiplication is calculated according to the following steps:

[0070] M1=(IR+II)×(DR+DI);

[0071] M2=IR×DR;

[0072] M3=II×DI;

[0073] OUTR = M2 - M3 (real part output);

[0074] OUTI = M1 - M2 - M3 (imaginary part output);

[0075] By adopting the Gaussian complex multiplication algorithm, the present invention effectively reduces the usage of hardware multiplication resources while ensuring the accuracy of the multiplication results. It is suitable for resource-constrained but computationally intensive communication systems and has significant advantages in improving the energy efficiency of sparse complex matrix multiplication and addition operations.

[0076] like Figure 3 As shown, in one embodiment of the present invention, the multiplication-addition module using the Gaussian algorithm is a structural unit specifically designed for sparse complex multiplication and addition. It integrates three multipliers and several adders for Gaussian complex multiplication, and can complete the calculation process of M1, M2, and M3 in a pipelined manner. Because the Gaussian algorithm reduces the number of multiplications from four to three, the number of multipliers in this module can be reduced, which helps save chip area and reduce power consumption. It is particularly suitable for large-scale complex data parallel processing scenarios.

[0077] In the hardware design, the present invention pairs the multiplication-addition module with a reusable flag controller. The latter determines whether to activate the multiplication-addition module and controls its computational path based on the count of nonzero elements in the index column. If nonzero data is detected in a computational unit, the multiplication-addition module activates the corresponding multiplication and addition device according to the Gaussian algorithm to complete the complex number operation, ultimately outputting the real and imaginary results to the partial sum accumulation register. This structural design not only improves the resource utilization of the multiplication-addition unit, but also enables dynamic scheduling of sparse matrix computation processes and precise management of hardware resources.

[0078] In one embodiment of the present invention, if the count in step S103 is greater than 0, selecting input data and corresponding data in the compressed matrix based on the index column, performing a multiplication and addition operation on the selected data based on a multiplication and addition operation module, and then storing the operation result in a partial sum accumulation register includes:

[0079] If the count is less than or equal to M, performing a multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then storing the operation result in the partial sum accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2 and less than N;

[0080] If the count is greater than M, first, the first M data in the selected data are multiplied and added based on the multiplication and addition operation module, the operation result is temporarily stored, then the remaining data in the selected data are multiplied and added based on the multiplication and addition operation module, and the sum of the operation result of this time and the temporarily stored operation result is stored in the partial sum accumulation register.

[0081] In the application, for the calculation unit with a count result less than or equal to M, multiplication and addition calculation of all non-zero elements can be completed at one time. M multipliers are configured in the multiplication and addition operation module, and M pairs of data can be processed in parallel, avoiding batch operation. This design is beneficial to improve calculation efficiency and reduce timing control complexity. The value range of M is set to be greater than or equal to N / 2 and less than N, which balances the data size of the calculation unit and the availability of hardware resources, and balances the resource utilization rate and the calculation delay.

[0082] In the application, when the number of non-zero elements in the calculation unit exceeds the upper limit M of the multiplication and addition module that can be processed in parallel, the system divides the data into two groups and sequentially completes multiplication and addition operation. The first M data are processed, the intermediate result is temporarily stored, the remaining part is processed in the second time, and then the sum of the first result is calculated and written into the partial sum accumulation register. This processing method avoids linear expansion of the number of multipliers and reduces the chip area overhead. At the same time, by using the intermediate result storage and twice summation strategy, effective support for data exceeding the size under fixed hardware resources is realized, and the flexibility and scalability of the system are enhanced.

[0083] In a preferred embodiment of the application, the number of elements N of the calculation unit is set to 8, and the number of multipliers M configured in the multiplication and addition operation module is set to 4. That is, each calculation unit processes 8 data elements. In theory, if all data are processed in parallel, 8 multipliers and corresponding control logic need to be configured. However, considering that the actual channel matrix has obvious sparseness, most calculation units only contain a small number of non-zero elements, and the number of non-zero elements is usually not more than 4. If the 8-multiplier structure is still used, part of the multipliers will be in an idle state, resulting in resource waste and increasing the chip area and power consumption burden.

[0084] To solve the above problem, the number of multipliers is reduced to 4 in this embodiment, and only 4 non-zero data are processed at one time. For the case that the number of non-zero elements exceeds, two-round calculation method is adopted, and the overall calculation result is completed through the temporary storage and accumulation mechanism. This design significantly improves the utilization efficiency of hardware resources and reduces the physical implementation complexity under the premise of ensuring calculation correctness, which is helpful to deploy large-scale sparse matrix calculation architecture in resource-limited scenarios.

[0085] In an embodiment of the application, the counting of the non-zero elements in the index column in the step S103 comprises:

[0086] The index column is sent to a reusable flag controller, and a counter in the reusable flag controller counts the non-zero elements in the index column.

[0087] In the present application, a reusable flag controller is arranged in the in-memory computing module, which counts the "1"s in each column index.

[0088] In an embodiment of the present application, if the count is equal to 0 in the step S103, the partial sum accumulation register is written with 0 as the operation result of the current computing unit, including:

[0089] The count is compared with 0 and M by a comparator in the reusable flag controller, and if the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register, so that the partial sum accumulation register writes 0 as the operation result of the current computing unit according to the first control signal.

[0090] In an embodiment of the present application, to determine whether to perform the multiplication and addition calculation for each computing unit in the sparse matrix, the system sends the current index column to the reusable flag controller. The reusable flag controller is internally provided with a counter module, which can quickly count the logical "1" bits in the index column to obtain the number of non-zero elements actually existing in the current computing unit. This process adopts a bit-level processing manner, and the counter reads the index bits bit by bit and accumulates the number of "1"s in real time, avoiding the calculation overhead of traversing the complete matrix in the traditional manner.

[0091] After the counting is completed, the result is transmitted to a comparator module in the flag controller. The comparator compares the count value with 0 and a preset upper limit M respectively. If the count result is equal to 0, it means that there is no non-zero data in the current computing unit, which belongs to a zero-computing unit. At this time, the comparator immediately outputs a first control signal to the partial sum accumulation register, triggering the register to automatically write the value 0 as the calculation result corresponding to the current computing unit. This process completely skips the multiplication and addition module and does not need data access and calculation operation.

[0092] This method has two significant advantages: first, it identifies the units that do not need to participate in the calculation in real time through hardware logic, reducing the system-level redundant operation; second, it saves the operation resources and data path overhead, and is particularly suitable for scenarios with high sparsity and large proportion of zero data. The entire process is completed independently by the reusable flag controller and does not depend on external control signals, realizing automation and efficient scheduling.

[0093] In an embodiment of the present application, if the count is less than or equal to M, the selected data is subjected to multiplication and addition operation based on the multiplication and addition operation module, and then the operation result is stored in the partial sum accumulation register, including:

[0094] If the count is less than or equal to M, the comparator outputs a second control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the second control signal, and performs multiply-add operation, and then sends the operation result to the multiplexer, and the multiplexer sends the operation result to the partial sum and accumulation register for storage according to the second control signal.

[0095] In an embodiment of the present application, when the counter in the reusable flag controller determines that the number of non-zero elements in the index column corresponding to a calculation unit is less than or equal to the set number of multipliers M, the comparator will output a second control signal, which is sent to the multiply-add operation module and the multiplexer respectively.

[0096] After receiving the second control signal, the multiply-add operation module starts the operation process. The module extracts corresponding data from the input data and the compressed matrix according to the positions marked as "1" in the index column, and performs multiply-add operation. Since the number of non-zero elements does not exceed the number of multipliers M, the multiply-add operation module can complete parallel processing of all data in one operation period without batch calculation or temporary storage of intermediate results, and the overall operation process is efficient and resource utilization is sufficient.

[0097] After the operation is completed, the result is transmitted to the multiplexer (MUX). The multiplexer selects the data path according to the second control signal, and directly guides the operation result output by the multiply-add module into the partial sum and accumulation register. In this process, there is no need for intermediate register buffering or path switching, which simplifies the data flow structure and reduces the control timing complexity.

[0098] Through the above mechanism, the present application realizes one-time calculation and writing of the calculation unit with fewer non-zero elements, which reduces the operation delay and reduces the power consumption. Compared with the traditional fixed path calculation structure, the present application can more fully adapt to the sparsity characteristics in the channel matrix, while ensuring the calculation correctness, improving the throughput and execution efficiency of the overall system.

[0099] In an embodiment of the present application, if the count is greater than M, the first M data in the selected data are multiplied and added based on the multiply-add operation module, the operation result is temporarily stored, then the remaining data in the selected data are multiplied and added based on the multiply-add operation module, and the sum of the operation result of this time and the temporarily stored operation result is stored in the partial sum and accumulation register, including:

[0100] If the count is greater than M, the comparator outputs a third control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the third control signal, performs multiply-add operation on the first M data in the selected data, obtains a first operation result and sends the first operation result to the multiplexer, then performs multiply-add operation on the remaining data in the selected data, obtains a second operation result and sends the second operation result to the multiplexer, the multiplexer sends the first operation result to the register according to the third control signal, and sends the second operation result to the summer, the summer performs summation on the second operation result and the first operation result in the register, and sends the summation result to the partial sum accumulation register for storage.

[0101] In an embodiment of the present application, when the counter in the reusability flag controller detects that the number of non-zero elements of the current calculation unit is greater than the set number of multipliers M, the comparator will output a third control signal, which is sent to the multiply-add operation module and the multiplexer at the same time.

[0102] After receiving the third control signal, the multiply-add operation module selects corresponding data from the input data and the compressed matrix according to the positions of "1" in the index column, and first performs multiply-add operation on the first M data. The operation is completed in the multiplier array, and a first operation result is output. The first operation result is transmitted to the multiplexer, and then selected according to the third control signal to be introduced into the intermediate register for temporary storage.

[0103] Then, the multiply-add module continues to perform a second round of multiply-add operation on the remaining non-zero elements in the index column, and obtains a second operation result. The result is also sent to the multiplexer, which transfers it to the summer according to the control signal. The summer receives the first operation result in the temporary storage register and the newly generated second operation result at the same time, and performs an addition operation. The final summation result is sent to the partial sum accumulation register as the final calculation output of the current calculation unit.

[0104] The processing mode of the present application allows the system to complete the effective processing of more than M data with only M multipliers, avoiding the waste of hardware caused by the alignment of the number of multipliers with the worst case. Through the batch processing of operation results and the intermediate temporary storage mechanism, the resource utilization rate and the calculation correctness are effectively balanced, which is suitable for channel matrix structures with large changes in actual sparsity, and realizes the dynamic balance between calculation capacity and hardware resources.

[0105] In one embodiment of the present application, the number of elements N of the calculation unit is set to 8, and the number of multipliers M configured in the multiply-add operation module is set to 4. In this embodiment, the multiplexing flag controller counts the "1"s in the index column corresponding to each calculation unit, to determine whether to enter the operation process and which operation path to adopt. When the multiplexing flag controller determines that the number of non-zero elements in a certain index column is less than or equal to 4, the multiply-add operation module completes the multiply-add operation of all non-zero data at one time, and directly writes the accumulated result into the partial sum accumulation register. In this mode, there is no need for intermediate buffering or path switching, the data flow is clear, and the operation efficiency is relatively high. When the count result is greater than 4, i.e., exceeds the maximum parallel calculation capability of the multiply-add operation module, the two-stage processing strategy is adopted in this embodiment. First, the multiply-add operation module completes the multiply-add operation of the first 4 non-zero entries, and temporarily stores the obtained result in a register. Then, the second multiply-add operation is performed on the remaining non-zero element entries, and the result of this operation is added to the value in the register to obtain the final partial sum result, which is written into the partial sum accumulation register. If the multiplexing flag controller determines that the count is zero, i.e., the current calculation unit does not contain any non-zero data, the multiply-add calculation process is directly skipped, and the control signal guides the partial sum accumulation register to write the value "0" as the output result of the calculation unit, thereby avoiding invalid calculation.

[0106] In one embodiment of the present application, when processing complex data calculation, the multiply-add operation module adopts a multiply-add operation module based on Gaussian algorithm.

[0107] In one embodiment of the present application, when processing complex data calculation, the calculation is performed in sequence for each calculation unit, first determining the corresponding index column according to the binary index matrix, counting the non-zero elements in the index column, if the count is greater than 0, selecting the input data and the corresponding data in the compression matrix based on the index column, performing multiply-add operation on the selected data based on the multiply-add operation module, and then storing the operation result in the partial sum accumulation register, if the count is equal to 0, the partial sum accumulation register writes 0 as the operation result of the current calculation unit, specifically including:

[0108] In the calculation, the calculation is performed in sequence for each calculation unit, first determining the corresponding index column according to the binary index matrix, sending the index column into the multiplexing flag controller, and counting the non-zero elements in the index column through the counter in the multiplexing flag controller; comparing the count with 0 and M through the comparator in the multiplexing flag controller:

[0109] If the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register, so that the partial sum accumulation register writes 0 as the operation result of the current calculation unit according to the first control signal, and skips the complex multiplication calculation process of the multiply-add operation module.

[0110] If the count is less than or equal to M, the comparator outputs a second control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding complex data in the input data and the compressed matrix based on the index column according to the second control signal, and performs complex multiply-add operation based on the Gauss algorithm. The specific operation includes:

[0111] M1 = (IR + II) x (DR + DI);

[0112] M2 = IR x DR;

[0113] M3 = II x DI;

[0114] Real part result OUTR = M2 - M3;

[0115] Imaginary part result OUTI = M1 - M2 - M3.

[0116] The complex operation result (OUTR + j·OUTI) output by the multiply-add operation module is sent to the multiplexer, and the multiplexer writes the complex result into the partial sum and accumulation register for storage according to the second control signal.

[0117] If the count is greater than M, the comparator outputs a third control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding complex data in the input data and the compressed matrix based on the index column according to the third control signal, performs complex multiply-add operation based on the Gauss algorithm on the first M data to obtain a first complex operation result (OUT1), and sends it to the multiplexer. Then, a second round of complex multiply-add operation is performed on the remaining data to obtain a second complex operation result (OUT2), which is also sent to the multiplexer.

[0118] The multiplexer sends the first complex operation result OUT1 to the register for temporary storage and the second complex operation result OUT2 to the summer according to the third control signal. The summer performs complex addition operation on OUT2 and OUT1 in the register, and finally writes the summed complex result into the partial sum and accumulation register for storage as the final operation result of the current calculation unit.

[0119] In an embodiment of the present application, the memory adopts a spin-orbit torque magnetoresistive random access memory (SOT-MRAM). Due to the multiple accesses and multiplexing of intermediate results (such as M1, M2, M3, etc.) required by the Gaussian complex multiplication, the fast random access characteristics of the SOT-MRAM can significantly reduce the intermediate value read-write delay. At the same time, its non-volatility and bit-level fine access capability make the loading and writing operations of multiple real / imaginary data more efficient, which helps to improve the data throughput rate of the entire complex multiplication process.

[0120] In addition, the Gaussian algorithm reduces the number of multiplications but increases the number of additions and data scheduling, and the SOT-MRAM supports on-chip tight coupling with the computing module, which can realize the rapid flow of data between the storage and computing units, avoiding the bottleneck caused by frequent memory access. Therefore, applying SOT-MRAM to the complex operation path not only helps to compress the long-term reliable storage of data, but also further optimizes the execution efficiency of the Gaussian algorithm in hardware.

[0121] As can be seen from the above embodiments, the present application provides a sparse matrix compression calculation method based on a SOT-MRAM storage-computing integrated architecture, which solves the core technical problem of storage and computing mismatch in large-scale complex sparse matrix operation. The present application reduces the storage overhead of the sparse matrix by single-bit index compression storage and reusable flag controller technology, eliminates the invalid index resolution and data transfer energy consumption in the traditional architecture; designs a reusable flag controller and a mixed-precision Gaussian algorithm, which reduces the resource occupation of the multiplier by 50% while maintaining the joint sparse characteristics of the real and imaginary parts of the complex operation, and reduces the dynamic switching delay; and finally constructs a storage-computing deep fusion silicon-based hardware system.

[0122] The sparse matrix compression calculation method based on the SOT-MRAM storage-computing integrated architecture provided by the present application reduces the storage overhead by single-bit index dynamic sparse sensing coding technology; uses a mixed-precision Gaussian algorithm and a reusable flag controller to reduce the resource occupation of the multiplier and the overhead of the control logic device while maintaining the joint sparse characteristics of the real and imaginary parts of the complex number; relies on the SOT-MRAM read-write separation and nanosecond-level in-situ computing capability to break through the limitation of the traditional "memory wall", and systematically solves the core bottlenecks of storage redundancy, inefficient computing, and high energy consumption in large model sparse matrix operation, providing a silicon-based hardware foundation for the low-power real-time deployment of AI models with hundreds of millions to tens of billions of parameters.

[0123] Some terms appearing in the above embodiments of the present application will be explained below.

[0124] MRAM: MRAM (Magnetoresistive Random Access Memory) is a non-volatile memory based on the magnetoresistance effect, which stores data by changing the magnetization direction of magnetic materials, with high-speed reading and writing, high durability, and power-off data retention characteristics. Compared with traditional storage technology, its advantages include speed close to DRAM, lifetime far exceeding flash memory, and low power consumption, suitable for embedded systems, automotive electronics, and artificial intelligence fields. With technology iteration, MRAM is expected to become a key storage solution in high-end computing and the Internet of Things.

[0125] SOT-MRAM: SOT-MRAM (Spin-Orbit Torque Magnetoresistive Random Access Memory) is a new type of non-volatile memory technology that uses spin-orbit torque effect to drive magnetization flip, and realizes higher write speed and lower energy consumption by separating read and write paths (current flows through the bottom heavy metal layer to generate transverse spin current), while avoiding the write reliability problem of traditional STT-MRAM. Compared with traditional MRAM, SOT-MRAM has significantly improved in write efficiency (speeded up by more than 10 times), power consumption (reduced by 30%-50%), and durability (>1e16 times). SOT-MRAM is considered as the next generation of high-performance MRAM, suitable for integrated computing and cache.

[0126] MIMO: Multiple Input Multiple Output (MIMO) is a key technology in wireless communication, which deploys multiple sets of antennas at the transmitter and receiver, uses spatial dimensions to transmit data or enhance signal reliability, and significantly improves system capacity and anti-interference ability. Its core principles include spatial multiplexing (simultaneous transmission of multiple signals) and spatial diversity (multi-path anti-attenuation), compared with traditional single antenna (SISO) systems, MIMO can achieve several times speed improvement or coverage expansion in the same bandwidth. The technology is widely used in modern communication standards such as 5G and Wi-Fi 6, supporting high-density connection scenarios such as high-definition video and the Internet of Things.

[0127] In-memory computing (or also known as compute-in-memory, memory computing, etc., English CIM / IMC): In-memory computing is a technology that breaks the bottleneck of the traditional Von Neumann architecture, embeds a computing unit into a storage unit, and directly uses the physical characteristics (such as resistance, current) of the storage device for analog operation to avoid frequent data transfer between the processor and the memory. Its core advantage is to greatly reduce the energy consumption and delay caused by the "memory wall", and it is particularly good at performing matrix multiplication operations in the AI field, and the energy efficiency ratio can reach 10-100 times that of traditional GPU / CPU. Current main applications include edge AI chips, neural network accelerators, etc. Representative technologies include compute-in-memory architectures based on RRAM and MRAM, and are considered as the core direction of the next generation of low-power intelligent computing.

[0128] It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in an order different from that shown here.

[0129] Based on the same inventive concept, the embodiments of the present application also provide a MIMO wireless communication channel matrix compression computing device, as described in the following embodiments. Since the principle of solving problems of the MIMO wireless communication channel matrix compression computing device is similar to that of the MIMO wireless communication channel matrix compression computing method, the embodiments of the MIMO wireless communication channel matrix compression computing device can refer to the embodiments of the MIMO wireless communication channel matrix compression computing method, and the repeated parts will not be described here. The term "unit" or "module" used below can be a combination of software and / or hardware that implements a predetermined function.

[0130] In an embodiment of the present application, the MIMO wireless communication channel matrix compression computing device of the present application comprises:

[0131] A binary index matrix generation and storage module is configured to mark the positions of non-zero elements in the MIMO wireless communication channel matrix as 1 and the positions of zero elements as 0, generate a binary index matrix, and store the binary index matrix in a memory;

[0132] A matrix compression storage module is configured to address and aggregate the non-zero elements in the channel matrix based on the binary index matrix in a column-first order, write each of the non-zero elements in a column-first order into a pre-set continuous storage space in the memory, and generate a compressed matrix;

[0133] The in-memory computing module is configured to, when performing the calculation, sequentially for each calculation unit, first determine a corresponding index column according to the binary index matrix, count non-zero elements in the index column, if the count is greater than 0, select corresponding data in the input data and the compressed matrix based on the index column, perform multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then store the operation result in the partial sum accumulation register, if the count is equal to 0, the partial sum accumulation register writes 0 as the operation result of the current calculation unit, and the calculation unit is a unit logically divided by the channel matrix in a column priority order into groups of every N elements.

[0134] In an embodiment of the present application, the in-memory computing module is specifically configured to:

[0135] If the count is less than or equal to M, perform multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then store the operation result in the partial sum accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2, and less than N;

[0136] If the count is greater than M, first perform multiplication and addition operation on the first M data in the selected data based on the multiplication and addition operation module, temporarily store the operation result, then perform multiplication and addition operation on the remaining data in the selected data based on the multiplication and addition operation module, and store the sum of the operation result of this time and the temporarily stored operation result in the partial sum accumulation register.

[0137] In an embodiment of the present application, the in-memory computing module comprises a reusable flag controller, a multiplication and addition operation module, a multiplexer, a register and a partial sum accumulation register; the reusable flag controller comprises a counter and a comparator;

[0138] The counter is configured to count the non-zero elements in the index column;

[0139] The comparator is configured to compare the count with 0 and M;

[0140] If the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register, so that the partial sum accumulation register writes 0 as the operation result of the current calculation unit according to the first control signal;

[0141] If the count is less than or equal to M, the comparator outputs a second control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the second control signal, and performs multiply-add operation, and then sends the operation result to the multiplexer, and the multiplexer sends the operation result to the partial sum and accumulation register for storage according to the second control signal.

[0142] If the count is greater than M, the comparator outputs a third control signal to the multiply-add operation module and the multiplexer, so that the multiply-add operation module selects corresponding data in the input data and the compressed matrix based on the index column according to the third control signal, and performs multiply-add operation on the first M data in the selected data to obtain a first operation result and send it to the multiplexer, and then performs multiply-add operation on the remaining data in the selected data to obtain a second operation result and send it to the multiplexer, and the multiplexer sends the first operation result to the register according to the third control signal, and sends the second operation result to the summer, and the summer performs summation on the second operation result and the first operation result in the register, and sends the summation result to the partial sum and accumulation register for storage.

[0143] As shown in FIG. 1, Figure 4 The in-memory computing module of the present application includes:

[0144] A reusable flag controller (RFC) internally includes a counter for counting the number of non-zero elements in the index column bit by bit, and a comparator (CMP in the figure) for comparing the number of non-zero elements output by the counter with 0 and M to generate different control signals (counter=0, counter≤4, counter>4).

[0145] A multiply-add operation module (not shown in the figure) is used to perform multiply-add operation on the input data and the compressed matrix data, and the processing result is sent to the multiplexer.

[0146] A multiplexer (MUX) is used to receive the intermediate calculation result output by the multiply-add module, select the path according to the control signal output by the comparator, and decide whether to directly write the result into the partial sum and accumulation register or temporarily store it in the register and then participate in summation.

[0147] A register (Reg) is used to temporarily store the first M multiply-add operation results, especially when the number of non-zero elements is greater than M, the first round of operation results are saved first, and then the second round of results are summed.

[0148] Add: used for summing the first round and the second round multiplication and addition results, and outputting a final partial sum.

[0149] Psum Reg: used for storing the calculation results (partial sums) of each calculation unit or index column, and providing basic data for subsequent overall estimation value aggregation.

[0150] Block Accumulation: used for block-level aggregation of multiple partial sum results, for generating estimation results.

[0151] Estimation Result Buffer: a final result output location, receiving the block-accumulated estimation values, for subsequent processing.

[0152] The three calculation paths of the application are described as follows:

[0153] Path one (counter <= 4):

[0154] If the counter value is less than or equal to M (4 in the figure), the comparator outputs a control signal, and the operation result of the multiplication and addition operation module is directly written into the partial sum accumulation register through the MUX, without intervention of the intermediate register, and the calculation efficiency is the highest.

[0155] Path two (counter > 4):

[0156] If the counter value is greater than M, the first round multiplication and addition operation result is sent to the Reg for temporary storage (label ①), and the second round result is input from the MUX into the adder and added with the temporary storage value in the Reg (label ②), and the sum result is written into the Psum Reg.

[0157] Path three (counter = 0):

[0158] If all the index columns are zero, the counter outputs 0, the comparator outputs a control signal, and the Psum Reg directly writes the value 0, skips the operation logic, and avoids unnecessary power consumption.

[0159] The in-memory calculation module of the application can dynamically select different calculation paths according to the number of non-zero elements in the sparse matrix, reduce operation redundancy while ensuring calculation accuracy. Through integration of the counter, the comparator, the multiplexer, the register and the adder, flexible switching of the data path and efficient processing of the calculation results are realized, the structure is compact, the resource utilization rate is high, and it is particularly suitable for high sparsity application scenarios such as MIMO channel estimation which need to process a large number of complex multiplication and addition operations.

[0160] It is apparent that those skilled in the art should understand that the modules or steps of the present application described above can be realized by using general computing devices, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and optionally, they can be realized by using program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, or they can be respectively manufactured into individual integrated circuit modules, or multiple modules or steps among them can be manufactured into a single integrated circuit module to realize. Thus, the present application is not limited to any specific combination of hardware and software.

[0161] The preferred embodiments of the present application are described above, but the present application is not limited to the above. Various modifications and changes can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A MIMO wireless communication channel matrix compression calculation method, characterized in that: include: Marking non-zero element positions in the MIMO wireless communication channel matrix as 1 and zero element positions as 0 to generate a binary index matrix, and storing the binary index matrix in a memory; performing addressing and aggregation operations on non-zero elements in the channel matrix according to column priority based on the binary index matrix, and writing each non-zero element into a preset continuous storage space in the memory in column priority order to generate a compressed matrix; When performing calculations, for each calculation unit in turn, the corresponding index column is first determined according to the binary index matrix, and the non-zero elements in the index column are counted. If the count is greater than 0, the input data and the corresponding data in the compressed matrix are selected based on the index column, and the selected data are multiplied and added based on the multiplication and addition module. The result of the operation is then stored in the partial sum accumulation register. If the count is equal to 0, the partial sum accumulation register is written with a value of 0 as the operation result of the current calculation unit. The calculation unit is a unit that logically divides the channel matrix into groups of N elements in column priority order.

2. The MIMO wireless communication channel matrix compression calculation method according to claim 1, characterized in that: If the count is greater than 0, selecting input data and corresponding data in the compressed matrix based on the index column, performing a multiplication and addition operation on the selected data based on a multiplication and addition operation module, and then storing the operation result in a partial sum accumulation register, including: If the count is less than or equal to M, performing a multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then storing the operation result in the partial sum accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2 and less than N; If the count is greater than M, the multiplication and addition operation is first performed on the first M data in the selected data based on the multiplication and addition operation module, and the operation result is temporarily stored. Then, the multiplication and addition operation is performed on the remaining data in the selected data based on the multiplication and addition operation module, and the sum of the current operation result and the temporarily stored operation result is stored in the partial sum accumulation register.

3. The MIMO wireless communication channel matrix compression calculation method according to claim 1 or 2, characterized in that: When processing complex data calculations, the multiplication and addition operation module adopts a multiplication and addition operation module based on the Gaussian algorithm.

4. The MIMO wireless communication channel matrix compression calculation method according to claim 2, characterized in that: The counting of non-zero elements in the index column comprises: Sending the index column to a reusable flag controller, and counting non-zero elements in the index column by a counter in the reusable flag controller; If the count is equal to 0, the partial sum accumulation register is written with a value of 0 as the operation result of the current calculation unit, including: The count is compared with 0 and M by the comparator in the multiplexed flag controller. If the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register so that the partial sum accumulation register writes a value of 0 as the operation result of the current calculation unit according to the first control signal.

5. The MIMO wireless communication channel matrix compression calculation method according to claim 4, characterized in that: If the count is less than or equal to M, performing a multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then storing the operation result in the partial sum accumulation register, including: If the count is less than or equal to M, the comparator outputs a second control signal to the multiplication and addition operation module and the multiplexer, so that the multiplication and addition operation module selects the input data and the corresponding data in the compressed matrix based on the index column according to the second control signal, and performs a multiplication and addition operation, and then sends the operation result to the multiplexer. The multiplexer sends the operation result to the partial sum accumulation register for storage according to the second control signal.

6. The MIMO wireless communication channel matrix compression calculation method according to claim 4, characterized in that: If the count is greater than M, first performing a multiplication and addition operation on the first M data in the selected data based on the multiplication and addition operation module, temporarily storing the operation result, then performing a multiplication and addition operation on the remaining data in the selected data based on the multiplication and addition operation module, and storing the sum of the current operation result and the temporarily stored operation result in the partial sum accumulation register, including: If the count is greater than M, the comparator outputs a third control signal to the multiplication and addition operation module and the multiplexer, so that the multiplication and addition operation module selects the input data and the corresponding data in the compressed matrix based on the index column according to the third control signal, performs multiplication and addition operations on the first M data in the selected data to obtain a first operation result and sends it to the multiplexer, then performs multiplication and addition operations on the remaining data in the selected data to obtain a second operation result and sends it to the multiplexer, the multiplexer sends the first operation result to the register according to the third control signal, and sends the second operation result to the summer, the summer sums the second operation result and the first operation result in the register, and sends the sum result to the partial sum accumulation register for storage.

7. The MIMO wireless communication channel matrix compression calculation method according to claim 1, characterized in that: The memory is a spin-orbit torque magnetoresistive random access memory.

8. A MIMO wireless communication channel matrix compression calculation device, characterized in that: include: A binary index matrix generation and storage module is used to mark the non-zero element positions in the MIMO wireless communication channel matrix as 1 and the zero element positions as 0, generate a binary index matrix, and store the binary index matrix in a memory; a matrix compression storage module, configured to perform addressing and aggregation operations on non-zero elements in the channel matrix in column-priority order based on the binary index matrix, and write each non-zero element in sequence in column-priority order into a preset continuous storage space in the memory to generate a compressed matrix; The in-memory calculation module is used to determine the corresponding index column according to the binarized index matrix for each calculation unit in turn when performing calculations, count the non-zero elements in the index column, select input data and corresponding data in the compressed matrix based on the index column if the count is greater than 0, perform multiplication and addition operations on the selected data based on the multiplication and addition operation module, and then store the operation results in the partial sum accumulation register. If the count is equal to 0, the partial sum accumulation register is written with a value of 0 as the operation result of the current calculation unit. The calculation unit is a unit that logically divides the channel matrix into groups of N elements in column priority order.

9. The MIMO wireless communication channel matrix compression calculation device according to claim 8, characterized in that: The in-memory computing module is specifically used to: If the count is less than or equal to M, performing a multiplication and addition operation on the selected data based on the multiplication and addition operation module, and then storing the operation result in the partial sum accumulation register, wherein the number of multipliers in the multiplication and addition operation module is M, M is greater than or equal to N / 2 and less than N; If the count is greater than M, the multiplication and addition operation is first performed on the first M data in the selected data based on the multiplication and addition operation module, and the operation result is temporarily stored. Then, the multiplication and addition operation is performed on the remaining data in the selected data based on the multiplication and addition operation module, and the sum of the current operation result and the temporarily stored operation result is stored in the partial sum accumulation register.

10. The MIMO wireless communication channel matrix compression calculation device according to claim 8, characterized in that: The in-memory calculation module includes: a reusable flag controller, a multiplication and addition operation module, a multiplexer, a register, and a partial sum accumulation register; the reusable flag controller includes: a counter and a comparator; The counter is used to count the non-zero elements in the index column; The comparator is used to compare the count with 0 and M; If the count is equal to 0, the comparator outputs a first control signal to the partial sum accumulation register, so that the partial sum accumulation register writes a value of 0 as the operation result of the current calculation unit according to the first control signal; If the count is less than or equal to M, the comparator outputs a second control signal to the multiplication-addition operation module and the multiplexer, so that the multiplication-addition operation module selects the input data and corresponding data in the compressed matrix based on the index column according to the second control signal, performs a multiplication-addition operation, and then sends the operation result to the multiplexer. The multiplexer sends the operation result to the partial sum accumulation register for storage according to the second control signal; If the count is greater than M, the comparator outputs a third control signal to the multiplication and addition operation module and the multiplexer, so that the multiplication and addition operation module selects the input data and the corresponding data in the compressed matrix based on the index column according to the third control signal, performs multiplication and addition operations on the first M data in the selected data to obtain a first operation result and sends it to the multiplexer, then performs multiplication and addition operations on the remaining data in the selected data to obtain a second operation result and sends it to the multiplexer, the multiplexer sends the first operation result to the register according to the third control signal, and sends the second operation result to the summer, the summer sums the second operation result and the first operation result in the register, and sends the sum result to the partial sum accumulation register for storage.

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