Addressable test circuit based on voltage follower
Through the addressable test circuit based on voltage follower, the problem of test inaccuracy caused by transmission gate voltage drop is solved, and efficient and accurate large-scale transistor performance testing is achieved to support diverse testing needs.
Patent Information
- Application Number
- CN202510899112.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-01
- Publication Date
- 2025-10-17
AI Technical Summary
The input excitation voltage drop problem caused by the output resistance of the transmission gate in traditional addressable test circuits leads to inaccurate test results and is greatly affected by current. Traditional calibration methods have strong limitations and cannot effectively characterize the performance differences between different transistors.
An addressable test circuit based on a voltage follower is adopted to eliminate the influence of the output resistance of the transmission gate through the voltage follower, and a negative feedback structure is formed using an operational amplifier to ensure that the background current of the unit array under test is a constant value, reduce the voltage drop and improve the test accuracy.
It reduces voltage drop in large-scale testing, improves test speed and accuracy, supports simultaneous testing of different types of units under test, reduces leakage interference, and enhances test efficiency.
Smart Images
Figure CN120801970A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor testing, in particular to an addressable test circuit based on a voltage follower. BACKGROUND
[0002] With the continuous shrinking of CMOS technology nodes, the influence of process random fluctuations on device performance is increasingly significant. Due to the influence of factors such as line edge roughness, random doping fluctuations, metal gate granularity, etc., the performance of the same transistor may be significantly different, even leading to circuit function failure, unstable power consumption, etc. A large amount of data is needed to statistically model the random fluctuation phenomenon to ensure that sufficient margin is left during circuit design. In order to accurately characterize these fluctuations and evaluate their impact on performance, the traditional method of testing a transistor with four PADs is too high in time and area cost, and there is an urgent need for a circuit that can test transistors on a large scale and quickly. At present, many works have designed test arrays to efficiently characterize the performance and reliability of transistors. Through address decoding circuit to control the switch circuit, a limited PAD can connect thousands of units to be tested together, and simultaneous measurement can be realized, effectively improving the test efficiency.
[0003] The conventional addressable test circuit directly connects the transmission gate and the unit to be tested, and the equivalent resistance of the transmission gate in conduction will cause a voltage drop of the input excitation. When the current of the unit to be tested is large, the voltage drop of the input excitation will become unacceptable. The Kelvin calibration method can only compensate after measurement, and the range of VD after calibration becomes smaller, and even some transistor characteristics, such as IDSAT, may not be obtained, which brings strong limitations to the test.
[0004] In the case of a determined process, the only way to reduce the voltage drop is to increase the width-length ratio of the transmission gate transistor, and the voltage drop generated is related to the current size and is greatly affected by the current. The improved method is too limited, and the excessive width-length ratio not only increases the area, but also increases the leakage, which produces a large error when measuring the leakage current. Therefore, the voltage drop cannot be adjusted only by increasing the width-length ratio of the transmission gate transistor, and an extra structure needs to be introduced. SUMMARY
[0005] In view of the above defects and deficiencies existing in the prior art, the present application provides an addressable test circuit based on a voltage follower, which aims to eliminate the influence of the output resistance of the transmission gate through the voltage follower, so that the background current of the unit array to be tested is a constant value, and the influence of the background current is excluded when measuring small current, making the result more accurate; dozens of units to be tested can be selected at the same time without increasing the voltage drop, greatly improving the test speed; different performance units to be tested can be connected to realize test diversity.
[0006] To achieve the above object, the application provides an addressable test circuit based on a voltage follower, which comprises:
[0007] An addressing circuit is used for receiving an address signal and decoding according to the address signal.
[0008] A switch circuit array comprises a VD signal switch array and a VG signal switch array; the VD signal switch array selects a corresponding switch unit according to the decoding result, and the selected switch unit couples the VD signal to the drain of a selected DUT in the DUT array through the voltage follower; the VG signal switch array selects a corresponding switch unit according to the decoding result, and the selected switch unit couples the VG signal to the gate of the selected DUT in the DUT array.
[0009] The application is further improved in that the switch unit comprises a transmission gate.
[0010] The application is further improved in that the voltage follower comprises an operational amplifier, the same input end of the operational amplifier serving as the input end of the voltage follower; the output end and the reverse input end of the operational amplifier are connected to form a negative feedback structure and serve as the output end of the voltage follower.
[0011] The application is further improved in that the open loop gain of the operational amplifier is greater than 40 dB.
[0012] The application is further improved in that the DUT in the DUT array comprises a transistor.
[0013] The application is further improved in that the output end of the voltage follower is connected with the drain of the DUT.
[0014] The application is further improved in that the drain current of the unselected DUT is a constant value.
[0015] The application is further improved in that the maximum number of the simultaneously selected DUTs in the switch circuit array is greater than or equal to two.
[0016] The application has the following advantages:
[0017] 1) In the application, the pressure drop of the VD signal in the transmission process can be greatly reduced, and the pressure drop is only affected by the gain of the operational amplifier, and the design of the open loop gain above 40 dB can realize a pressure drop below 1%.
[0018] 2) In the application, the voltage follower makes the drain current of the unselected DUT a constant value, and the background current can be directly measured, and the background current is removed to make the test result more accurate.
[0019] 3) The present application provides a circuit allowing large-scale testing of different types of DUTs, supporting direct comparison of performance between different types of DUTs.
[0020] 4) The present application allows simultaneous testing of tens of DUTs, and the number of simultaneous openings does not affect the VD voltage drop, greatly improving the testing speed BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 A schematic diagram of the voltage follower-based addressable test circuit of the present application;
[0022] Figure 2 A schematic diagram of the voltage follower in the present application. DETAILED DESCRIPTION
[0023] The embodiments of the present application will be described below by way of specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.
[0024] Some exemplary embodiments of the present application are described for illustrative purposes, and it should be understood that the present application can be implemented in other ways not specifically shown in the drawings.
[0025] As shown in Figure 1 The embodiments of the present application provide a voltage follower-based addressable test circuit, which includes an addressing circuit, a switch circuit array, a voltage follower module, and a DUT array. Specifically:
[0026] The addressing circuit is used to receive an address signal and decode according to the address signal.
[0027] The switch circuit array includes a VD signal switch array and a VG signal switch array; the VD signal switch array selects a corresponding switch unit according to the decoding result, and the selected switch unit couples the VD signal to the drain of the selected DUT (DUT) in the DUT array through the voltage follower; the VG signal switch array selects a corresponding switch unit according to the decoding result, and the selected switch unit couples the VG signal to the gate of the selected DUT in the DUT array. The switch unit is a transmission gate.
[0028] In some embodiments, the VD signal and the VG signal are generated by a dedicated signal generation circuit. The switch circuit array, the voltage follower module, and the DUT array are integrated on the same chip. The output end of each DUT is connected to the signal output end VS.
[0029] As shown in Figure 2 , the voltage follower includes an operational amplifier, an in-phase input end of the operational amplifier serving as an input end of the voltage follower; an output end of the operational amplifier and a reverse input end being connected to form a negative feedback structure and serving as an output end of the voltage follower. The output end of the voltage follower is connected with a drain of the DUT.
[0030] The structure has the following advantages: the output voltage V out is substantially equal to the input voltage V in , the output impedance is very small, and the input impedance is very large. Taking the open-loop gain of the operational amplifier as A, it can be obtained from the following formula that ΔV is irrelevant to the DUT current, and the voltage is more stable. It is ensured that although there is a larger current in the path, a voltage drop is basically not generated. Since the input resistance is very large, the transmission gate connected at the input end of the voltage follower will not generate a voltage drop, so it can be ensured that regardless of how large the current of the DUT is, the transmission signal will not generate a relatively obvious voltage drop.
[0031]
[0032] In some embodiments, the open-loop gain A of the operational amplifier is greater than 40 dB, so that the voltage drop of the VD signal at the voltage follower is less than 1%.
[0033] Since the drain of each DUT is connected with the corresponding voltage follower, the drain voltage of each DUT is determined by the corresponding voltage follower. When not selected, the use of the voltage follower makes the drain current of the unselected DUT a constant value, so that the leakage current test is more accurate. In an ideal case, the drain voltage of the unselected DUT should be zero, and after the voltage follower is used, due to the existence of the offset voltage, the actual drain voltage of the DUT is always the offset voltage of the voltage follower, which is a stable and measurable signal, so there is a stable drain current for the unselected DUT, and the drain interference can be accurately measured.
[0034] In some embodiments, Figure 1 , the total bit width of the row address and the column address is N, and the addressing circuit can realize connection of 2 N DUT tests. In other embodiments, the addressing circuit can realize more complex addressing functions, for example, the number of simultaneously selected DUTs is greater than or equal to 2, so as to realize simultaneous testing of multiple DUTs (for example, simultaneously selecting a row and a column in the DUT array).
[0035] In some embodiments, the DUT is a transistor; the transistor includes a source S, a gate G, and a drain D; the source of each DUT is connected to an output (VS) of the array of units under test; the array of units under test is configured with one or more outputs; when there are multiple outputs. The same array of units under test can be composed of different types and sizes of DUTs. Due to different current characteristics, different DUTs exhibit a large difference in voltage drop. By the method of increasing the input voltage of the tester in the prior art, some DUTs may be broken down, and the actual drain voltage of some DUTs may not reach their working voltage. Therefore, in the case of testing multiple different types of DUTs at the same time, the traditional connection method is no longer applicable. The addressable test circuit with voltage follower structure in the embodiment is used, and the VD voltage drop is not affected by the current of the DUT under test, so when different DUTs are arranged in the same array, the voltage drop is basically consistent.
[0036] By selecting multiple DUTs at the same time, the test efficiency can be effectively improved. In order to reduce the leakage interference of DUTs that are not selected, two-stage transmission gates are usually used to avoid the situation that the leakage of DUTs in the same row but different columns or in the same column but different rows is too large. For example, when testing a 32x32 DUT array, 32 second-stage transmission gates are connected to the same first-stage transmission gate. However, when applying long-term stress to the DUT, applying stress one by one results in too long test time, thereby generating a solution for simultaneously opening multiple DUTs. However, when multiple DUTs are opened at the same time, the first-stage transmission gate will generate a larger voltage drop, thereby increasing the influence of the voltage drop of the transmission gate itself. By using the voltage follower structure connection, the VD voltage drop is not affected by the number of simultaneously opened DUTs, and many DUTs can be opened at the same time for testing, thereby achieving more efficient use.
[0037] By using the voltage follower, the voltage drop caused by the transmission gate in the switch circuit can be greatly reduced. The problems in the Kelvin calibration method, such as complex test transfer characteristic curve, small voltage measurable range, different performance units under test voltage drop, and test ability affected by the number of parallel DUTs, can be effectively solved. Therefore, the point to be protected is to introduce the voltage follower structure to reduce the voltage drop of the transmission gate when large-scale testing is performed using the addressing method.
[0038] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. An addressable test circuit based on a voltage follower, characterized in that: include: An addressing circuit, used for receiving an address signal and performing decoding according to the address signal; The switch circuit array includes a VD signal switch array and a VG signal switch array; the VD signal switch array selects the corresponding switch unit according to the decoding result, and the selected switch unit couples the VD signal to the drain of the selected unit under test in the unit under test array through a voltage follower; the VG signal switch array selects the corresponding switch unit according to the decoding result, and the selected switch unit couples the VG signal to the gate of the selected unit under test in the unit under test array.
2. The addressable test circuit based on a voltage follower according to claim 1, characterized in that: The switch unit includes a transmission gate.
3. The addressable test circuit based on a voltage follower according to claim 1, characterized in that: The voltage follower includes an operational amplifier, the non-inverting input terminal of the operational amplifier serves as the input terminal of the voltage follower; the output terminal of the operational amplifier is connected to its inverting input terminal to form a negative feedback structure and serves as the output terminal of the voltage follower.
4. The addressable test circuit based on a voltage follower according to claim 3, characterized in that: The open-loop gain of the operational amplifier is greater than 40 dB.
5. The addressable test circuit based on a voltage follower according to claim 1, characterized in that: The cells under test in the cell under test array include transistors.
6. The addressable test circuit based on a voltage follower according to claim 5, characterized in that: The output end of the voltage follower is connected to the drain of the unit to be tested.
7. The addressable test circuit based on a voltage follower according to claim 5, characterized in that: The leakage current of the unselected units to be tested is a constant value.
8. The addressable test circuit based on a voltage follower according to claim 1, characterized in that: The maximum number of units to be tested that are simultaneously selected by the switch circuit array is greater than or equal to two.