Control method for under-voltage tripping and voltage detection closing for low-voltage switch

Abstract

The invention discloses a control method for under-voltage tripping and voltage detection closing for a low-voltage switch, and relates to the technical field of power distribution automation. The problems of function separation, low detection precision, poor anti-interference capability and inconvenient maintenance in the prior art are solved. The method comprises the following steps: S1, acquiring a high-precision digital voltage through a voltage transformer, a voltage division network, an isolation amplifier and a 24-bit delta sigma ADC; s2, interference is suppressed by combining temperature compensation, FIR filtering, median filtering and an oversampling integration algorithm; s3, comparing the real-time voltage with a tripping / closing threshold value which can be configured online in parallel; s4 / S5, triggering a zero-crossing short pulse to drive opening / closing based on the threshold value and the time delay; s6, performing parallel fault monitoring, shielding misoperation and uploading fault data; according to the invention, the detection precision, the anti-interference capability and the operation and maintenance efficiency of the system are obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power distribution automation, and more particularly to a control method for under-voltage tripping and voltage detection closing of low-voltage switch. BACKGROUND

[0002] As the core component for realizing circuit over-current protection, opening / closing control and fault isolation in power distribution system, low-voltage switch is widely used in industrial, commercial and residential power distribution networks. A typical low-voltage switch usually consists of a split excitation release, a thermal release, a magnetic release, and a closing / opening coil. When a short circuit or overload occurs in the power distribution network, the split excitation release or the thermal release quickly cuts off the circuit to protect the line and equipment; when the line voltage returns to normal, the load needs to be reconnected by manual or automatic reclosing to restore power supply.

[0003] In existing automatic reclosing devices, one type of time-delay reclosing method controls the preset delay time after opening by a timer, and automatically issues a closing command when the delay time arrives. This method is simple to implement, but cannot make intelligent judgments according to the actual voltage recovery of the power grid, and is prone to blind closing when the voltage is not stable and the fault has not been cleared, resulting in multiple closing failures or triggering secondary faults. There is also a voltage closed-loop reclosing method that continuously monitors the bus voltage after opening, and issues a closing command when the detected voltage reaches a preset recovery threshold and lasts for a certain time. This method can avoid blind reclosing, but existing implementations mostly rely on analog circuits or simple logic of single-chip microcomputers, and have problems such as weak anti-interference ability, high misoperation rate, and insufficient parameter flexibility.

[0004] In addition, for under-voltage tripping protection, the traditional method is mostly completed by a thermal release or an electronic under-voltage release. On the one hand, the response speed of the thermal release to under-voltage is affected by the thermal time constant, and the response speed is slow; on the other hand, although the electronic under-voltage release improves the response performance, most of them only provide simple threshold detection and time-delay tripping functions, and cannot consider the reclosing judgment after tripping.

[0005] In summary, the existing technology mainly has the following deficiencies in implementing automatic tripping and closing control: Firstly, the tripping protection and reclosing functions are separated, and there is no unified logic control platform, making it difficult to realize the cooperative judgment of fault and voltage state; secondly, the voltage detection precision and anti-electromagnetic interference ability are weak, and are easily affected by transient surges and harmonic interference, leading to mis-tripping or delayed closing; at the same time, the existing system parameter configuration mostly relies on on-site switch quantity dial or knob, and the parameter configuration and maintenance mode is single, making it difficult to realize remote online debugging and batch configuration; in addition, there is also a lack of log recording and communication function, making it difficult to feedback the device state and fault information to the upper monitoring system in a timely manner, which is not conducive to the intelligent operation and maintenance of the power distribution network. SUMMARY

[0006] In view of the deficiencies of the prior art, the application discloses a control method for under-voltage tripping and voltage detection closing of a low-voltage switch, and aims at solving the problems in the background art.

[0007] In order to achieve the above technical effects, the application adopts the following technical solutions: A control method for under-voltage tripping and voltage detection closing of a low-voltage switch comprises the following steps: Step S1, the bus phase voltage and line voltage signals are introduced into a monitoring unit through a voltage transformer and a voltage dividing network arranged on the system main bus side; the monitoring unit uses an isolation amplifier to perform signal isolation and amplitude amplification on the analog voltage, and then uses a 24-bit delta-sigma analog-to-digital converter to sample and obtain a digital voltage value; Step S2, the environmental temperature is collected in real time by a temperature sensor, the digital voltage value is subjected to temperature drift compensation transformation based on the temperature value, and the grid transient disturbance is suppressed by using a finite impulse response filter, a sliding window median filter and an oversampling integration algorithm to obtain a real-time voltage value; Step S3, the real-time voltage value is compared in parallel with an under-voltage tripping threshold value and a voltage detection closing threshold value which are set in advance through a parameter configuration interface by using an embedded digital signal processing algorithm; Step S4, when the voltage value continuously falls below the preset under-voltage tripping threshold value and the duration exceeds the preset under-voltage tripping delay time, a synchronous zero-crossing short pulse is triggered by a microcontroller and sent to a tripping drive interface to drive the low-voltage switch tripping coil to act; Step S5, when the voltage value recovers to continuously be higher than the preset voltage detection closing threshold value after tripping and the duration exceeds the preset voltage detection closing delay time, a synchronous zero-crossing short pulse is triggered by a microcontroller and sent to a closing drive interface to drive the low-voltage switch closing coil to act; Step S6, during the tripping or closing process, the fault monitoring module detects abnormal events including overcurrent, under-phase, overvoltage and drive failure in real time, and if an abnormality is detected, the subsequent tripping and closing command is shielded and the fault data is uploaded to the upper monitoring system.

[0008] Based on the above technical solutions, the application has the following positive and beneficial effects: 1, steps S1-S3 output the same version of real-time voltage value after temperature compensation and multi-stage collaborative filtering of the original voltage signal, so that the under-voltage criterion and the closing criterion are compared in parallel on the basis of the same state quantity, thereby logically naturally connecting the fault detection and voltage recovery judgment processes, and avoiding the reclosing error or delay caused by the failure to accurately record the grid state after tripping.

[0009] 2. The temperature drift compensation and programmable filtering algorithm used in this solution directly suppresses transient surges and harmonic distortions in the power grid. Combined with dynamic delay triggering and zero-point synchronization mechanisms, the filtered voltage error is minimized, so that each tripping or closing action is based on the real fault state or steady-state recovery state. Compared with simulation or simple logic methods that are susceptible to interference, the action decision is more accurate and reliable, significantly reducing the risk of false tripping or delay.

[0010] 3. The parameter configuration interface allows any network or bus configuration command to be inserted at the front end of step S3, breaking the field dependence of traditional DIP switch or knob adjustment. This enables tripping threshold, closing threshold, and delay parameters to be remotely issued and batch synchronized to multiple devices, thereby offloading repetitive work from field maintenance personnel and improving the system's deployment efficiency and operational flexibility.

[0011] 4. This solution immediately blocks subsequent commands and actively uploads logs whenever an action is triggered or an anomaly is detected, forming a closed-loop action-monitoring-feedback link. This ensures that the upper-level monitoring system can synchronously grasp the entire process of device operation and fault evolution, providing reliable decision-making data support for online diagnosis and intelligent operation and maintenance of the power distribution network. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the circuit for implementing the present invention; Figure 2 This is a diagram illustrating the working principle of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] In one embodiment, such as Figure 1The circuit principle diagram shows that the entire control device relies on the close coupling of the low-voltage switch loop and the control loop to realize the functions of under-voltage tripping and voltage detection closing. The voltage of each phase bus is first collected by the voltage transformer installed on the main bus side, and then output through the secondary side. A voltage dividing network composed of high resistance and low temperature drift thin film resistor further reduces the typical hundred volt level secondary voltage to the acceptable several volt range of the analog front end. The voltage signal after voltage division is amplified and isolated by an isolation amplifier with high voltage resistance. The isolation device uses an ISO124 type integrated isolation module with thousands of volts of common mode suppression capability to ensure reliable protection for the microelectronic devices in the rear stage when overvoltage or lightning surge occurs on the bus side. The differential analog voltage output by the isolation amplifier is connected in series to the analog input terminal of the programmable gain amplifier PGA and the high-resolution delta-sigma ADC, respectively. The PGA uses a model such as PGA114, which receives gain switching commands from the STM32H743 master MCU through the SPI bus, to achieve dynamic switching of 1 to 16 gain ranges. The ADC uses a 24-bit delta-sigma structure device such as ADS1278, which supports multi-rate switching from 8 kHz to 64 kHz through its internal programmable sampling rate module. The sampling rate is also dynamically adjusted by the MCU through SPI in real time to balance signal bandwidth and processing load.

[0015] The digitized sampling data is automatically written to the MCU internal FIFO buffer through the DMA channel, and the host core triggers the interrupt service routine with a period of 1 ms for temperature compensation and filtering processing. The ambient temperature is measured in real time by the TMP117 digital temperature sensor integrated on the control board and input to the MCU through the I2C bus. The MCU performs CRC check on the read temperature value to ensure data integrity, and then calls the pre-stored segmented polynomial interpolation algorithm module in the interrupt context. Based on the temperature-voltage drift curve obtained through laboratory calibration, the module maps the current temperature to the corresponding correction coefficient segment and calculates the correction coefficient through a quadratic polynomial. The original digital voltage value is multiplied by the coefficient to generate temperature-compensated voltage data. The compensation process is completed using the floating point operation unit built into the STM32H743 to ensure high precision calculation.

[0016] The compensated voltage data directly enters the programmable finite impulse response filter, which can be adjusted online on site through Modbus RTU or local LCD + knob interface. The filter order and cutoff frequency shield the power grid spike pulse and high frequency harmonic. The filtered signal is then processed by the sliding window median filter algorithm to remove residual pulse noise, and then the high frequency sampling points are averaged by N-point averaging in an oversampling integration manner to further smooth the output and improve the signal-to-noise ratio. The filtering and integration process is completely completed by the host core or DMA, ensuring real-time performance.

[0017] In the same interrupt cycle, the MCU core compares the filtered real-time voltage with the under-voltage trip threshold and the over-voltage close threshold saved in the registers. The threshold and corresponding delay parameters can be sent to multiple devices by the host computer through Modbus broadcast, CAN multicast or local panel interface in batches, and saved in non-volatile Flash. After receiving the new threshold or delay setting, the MCU updates the register parameters in real time, and the changes take effect without restarting.

[0018] When the filtered voltage value is continuously lower than the under-voltage trip threshold and the cumulative time exceeds the set delay, the MCU determines that the "under-voltage" condition is met. At this time, the opto-isolator controlled by the GPIO pin drives the UCC27211 isolation gate drive chip to send a 20ms short pulse to the opening relay coil. Before sending the drive pulse, the MCU needs to wait for the current zero-crossing interrupt signal from the ACS712 current sensor and the LM311 comparator output, and delay 100 to 500us after capturing the zero-crossing moment to realize zero-crossing triggering, so as to reduce coil arc and mechanical wear. The position state of the opening coil is fed back by the on-board Hall proximity sensor, and after photoelectric isolation, it enters the MCU GPIO port to confirm the execution result of the opening command.

[0019] After the opening is completed, the MCU continues to monitor the real-time voltage in each interrupt cycle, and when it is continuously higher than the over-voltage close threshold and the cumulative duration exceeds the close delay, the close condition is met. The MCU waits for the current zero-crossing signal again, and sends a close drive pulse to the close relay coil after capturing zero to realize automatic reclosing. After closing, the MCU reads the auxiliary switch state feedback to confirm whether the closing is successful or failed, and triggers the fault handling process when a failure is detected.

[0020] The overcurrent, open-phase and voltage surge contents are responsible for the fault monitoring subsystem running in parallel with the MCU. The overcurrent detection unit uses DMA to send the current sensor output sampling data into the FFT analysis module, which extracts the fundamental and 3-11 harmonic amplitudes in real time and generates dynamic overcurrent thresholds through sliding window accumulation statistics; the open-phase detection unit compares the three-phase voltage amplitude differences and combines double-layer threshold logic to determine the continuous open-phase state; the voltage surge detection unit calculates AV / At based on the filtered voltage data of multiple consecutive cycles, and when the transient rate exceeds the preset threshold and accumulates to the trigger number, the voltage surge fault flag is set. Each fault subunit merges into the highest priority fault code through internal priority arbitration logic, and the MCU immediately shields all subsequent jump and close commands when determining the fault and calls the Flash write subroutine to package the fault code, fault type and timestamp into the ring Flash area. If the main communication link is available, the communication submodule sends the Modbus function code with CRC and ACK mechanism to the upper monitoring system through RS 485, otherwise relies on the power-off write protection logic triggered by the power monitoring module to ensure atomic storage of logs in the flash memory, and after the power is restored, the Flash ring area is read in the startup routine. The log marked as "reported" is sent in order until all are confirmed and the storage area is cleared.

[0021] It should be noted that in the present embodiment, the electrical connection of each hardware module strictly follows the industrial standard design, the bus coupler is connected to the DIN rail dedicated voltage input terminal, the isolation amplifier and the PGA are arranged in the analog signal area, the AD converter is provided with a ground isolation partition to suppress digital backflow, and the MCU and the communication interface and the drive interface are all made of double metal connectors to ensure vibration resistance and EMC performance. The entire control device is installed in the secondary control cabinet through the standard 35mm DIN rail, isolated from the primary main circuit through a high-voltage insulating sleeve, and meets the national low-voltage power distribution safety specifications.

[0022] In another embodiment, a control method for low-voltage switch under-voltage tripping and pressure detection closing, as shown in Figure 2 Step S1, the bus phase voltage and line voltage signals are introduced into the monitoring unit through the voltage transformer and the voltage dividing network arranged on the system main bus side, the monitoring unit uses an isolation amplifier to perform signal isolation and amplitude amplification on the analog voltage, and then uses a 24-bit delta-sigma analog-to-digital converter to sample and obtain digitalized voltage values; in step S1, a programmable gain amplifier is further configured in front of the 24-bit delta-sigma analog-to-digital converter, the programmable gain amplifier is used to automatically switch the gain multiple according to the measurement voltage level, to ensure that the digitalized voltage values with the best signal-to-noise ratio are obtained under different voltage ranges, and at the same time, the ADC sampling rate can be dynamically adjusted within the range of 8 kHz to 64 kHz.

[0023] The programmable gain amplifier works in combination with a 24-bit delta-sigma analog-to-digital converter, and the working logic thereof comprises: The MCU receives an analog voltage output by the isolation amplifier, generates an initial digitized voltage sample through the 24-bit delta-sigma ADC, and internally calculates the peak-to-peak value and the root mean square value of the sample through a sliding window, thereby quantifying the current voltage amplitude interval; When the calculation result exceeds the preset dead zone band, the MCU sends a gain gear switching instruction to the programmable gain amplifier through SPI according to the amplitude interval and the multi-gear gain mapping table, and simultaneously performs sampling rate adjustment in the range of 8 kHz to 64 kHz based on the real-time spectral energy distribution analysis; After the sampling rate and gain switching are completed, the calibration pulse is injected through the analog-to-digital converter, and the digital calibration unit performs zero offset and gain correction on the new gear output, thereby eliminating switching distortion; The amplitude out-of-limit determination result is applied to a second-order sliding average suppression, and the sampling rate and gain switching are allowed when a preset number of continuous periods are exceeded.

[0024] In the present embodiment, it should be noted that the "programmable gain amplifier" in the present application is different from the traditional fixed gain operational amplifier, which is internally integrated with a multi-gear hardware gain switch and has an interface for communication with a microcontroller, and can seamlessly switch between different gain gears according to external instructions; the "delta-sigma analog-to-digital converter" means a high-resolution ADC that uses oversampling and sigma-delta modulation principles, and the output thereof is obtained through a digital filter to obtain a high-precision digital value; the "dead zone band" in the present application refers to the amplitude interval boundary for suppressing noise triggering, and only when the sampling peak-to-peak value exceeds the interval can the gain or sampling rate switching operation be triggered, thereby preventing frequent adjustment caused by weak signal fluctuations; "spectrum energy-oriented sampling rate adjustment" refers to dynamically selecting the most reasonable ADC sampling rate based on the frequency component energy distribution obtained by performing a short-time Fourier transform on the sampling data, so as to balance the bandwidth requirement and the calculation load. The specific determination can be made by the user according to the actual situation, and no limitation is made in this regard.

[0025] In practical applications, the voltage collection process needs to be closely combined with the actual working scene of the bus. In this embodiment, YN BW50 or similar type oil-immersed voltage transformers are arranged on each phase bus, and the 100V voltage output on the secondary side is reduced to the 0-3.3V interval through the S1, S2 and S3 voltage dividing resistor network. The voltage dividing resistor needs to use a low temperature drift thin film resistor with a temperature coefficient of not higher than 50ppm / ℃ to avoid distortion of the voltage dividing ratio caused by a large change in the ambient temperature. The obtained analog quantity is differentially input through the pins AIN0 / AIN1 to access the ISO124 type isolation amplifier. The isolator not only provides DC isolation, but also has a 10x or 20x voltage amplification function to expand the small voltage swing to the same order of magnitude as the sampling range of the subsequent ADC. The common mode rejection ratio of the isolation amplifier needs to reach at least 80dB to suppress the common mode interference on the bus side, while ensuring that the input resistance is above 10kΩ to avoid affecting the voltage dividing network.

[0026] After the output of the isolation amplifier, the signal enters the AD8234 or PGA114 type programmable gain amplifier front end. When the MCU (such as the STM32H7 series large core) is powered on and initialized, the PGA is sent a configuration command through the SPI interface to clear the internal registers and set the initial gain to 1x. At this stage, after receiving the “GAIN=1x” instruction, the PGA switches the internal switch to directly send the input signal to the subsequent ADC. At the same time, the ΔΣ ADC (such as ADS1278) sets the initial sampling rate to 16kHz in its internal configuration register. After the ADC is started after power-on, it reports its status word to the MCU, which verifies the parameter writing success through CRC check and handshake signal reply. Thereafter, the ADC starts continuous sampling at a rate of 16kHz, and outputs 24-bit digital samples processed by an oversampling digital filter.

[0027] In order to realize the quantization of the voltage amplitude interval and the trigger condition judgment of the gain / sampling rate automatic adjustment, the MCU receives the ADC output through the DMA channel to move the data to the internal operation buffer, and executes the sliding window algorithm in turn. Specifically, in a fixed length sample sequence, the processor calculates the difference between the maximum value and the minimum value of the signal in this segment in turn, and combines it with the root mean square value of the sample in this segment to form a quantitative description of the signal amplitude interval. In this process, all samples are treated as unsigned numbers and do not need to be sign-extended, so the operation speed can be greatly optimized to ensure that the processor can complete the calculation without blocking under the real-time sampling rate.

[0028] When the signal amplitude quantization result falls into the predefined stable interval, the processor directly submits the sample to the next stage of temperature compensation and filtering process; but when the quantization result exceeds the boundary of the stable interval, that is, outside the so-called "dead zone", it indicates that the gain or sampling rate setting of the current analog front end is no longer suitable for the current signal strength, which may cause signal overload or insufficient signal-to-noise ratio. At this time, the processor consults the internal storage gain and sampling rate mapping table according to the amplitude interval after quantization. The mapping table is prepared in advance during device design, covering several intervals from the minimum to the maximum possible signal amplitude, and specifying the corresponding gain and sampling rate for each amplitude interval. In this mapping process, the correspondence between amplitude and gain, sampling rate is determined according to experimental data and system reliability requirements to ensure the best signal-to-noise ratio in various working situations.

[0029] Subsequently, the processor issues gain level switching instructions to the programmable gain amplifier and simultaneously issues new sampling rate settings to the analog-to-digital converter. The two operations are completed through the same serial peripheral to ensure that both switching occurs at the same time, avoiding temporary distortion caused by mismatched gain and sampling rate. After switching is completed, the amplifier and ADC both report the current working state to the processor through the status register. The processor receives and verifies the data before proceeding to the next step.

[0030] In order to eliminate the slight distortion caused by the switching process, the analog-to-digital converter will trigger a calibration pulse function after switching. At this time, the ADC will automatically generate a fixed known amplitude test pulse and feedback to the processor in the form of digital samples at the output end. The processor compares the sample with the expected reference value to calculate the zero point offset and gain error. Next, before starting to record new real-time sampling data, the processor will correct all subsequent sampling values in real time according to the error correction algorithm to minimize the error. In this way, even slight deviations caused by hardware characteristics during dynamic switching can be eliminated in time, ensuring continuous high precision of the data.

[0031] The entire gain and sampling rate adjustment logic is executed in the MCU in an event-driven manner. The above sliding window calculation, dead zone determination and second-order sliding average smoothing are completed in the timing interrupt routine; while the SPI write command, state word handshake and calibration pulse injection are executed as the main loop task outside the interrupt, when the MCU is not occupied by high priority interrupts. Through this software and hardware cooperative mode, without a dedicated DSP, high-precision and high-real-time front-end sampling self-adaptation can be completed on the Cortex M7 architecture.

[0032] It should be noted that the "automatic switching of sampling rate" in the present application is essentially different from the simple setting of a fixed high sampling rate in the prior art. The former dynamically selects the most reasonable sampling rate according to the spectral energy distribution, so as to reduce the processing load when there are less high-frequency useless noise components, and to increase the sampling rate when there are more harmonics or fast transients, so as to balance the operation resources and signal integrity.

[0033] After the above-mentioned gain and sampling rate adaptation is completed, the MCU further processes the final digitized voltage value according to the temperature compensation and filtering algorithm in step S2, and then enters the threshold comparison and trip decision process of step S3. In the overall control method, step S1 provides a voltage acquisition reference with high reliability, high precision and adaptive characteristics, ensuring that the subsequent judgment of the bus under-voltage trip and the voltage detection closing logic is based on the real and undistorted voltage state. It is precisely because of this accurate digital voltage acquisition capability that the data transmitted by the same channel in step S3 meets the real-time requirement and can resist power grid interference, so as to realize accurate parallel comparison of the trip threshold and the closing threshold, and to couple the fault and voltage recovery judgment into a unified logic platform, so as to effectively solve the problem of separation of trip protection and reclosing function and decision islandization in the traditional scheme.

[0034] In step S2, the environmental temperature is collected in real time by a temperature sensor, the digitalized voltage value is compensated and transformed based on the temperature value, and the finite impulse response filter, the sliding window median filter and the oversampling integration algorithm are used to suppress the power grid transient interference, so as to obtain the real-time voltage value. Specifically, in step S2, the FIR filter uses programmable filter coefficients to modify the filter order and cutoff frequency online; the sliding window median filter algorithm realizes double suppression of power grid sharp pulse and harmonic components through adjustable window width and data accumulation times. In step S2, the principle of compensating and transforming the digitalized voltage value based on the temperature value is as follows: the MCU periodically reads the digital temperature sensor output through the I2C interface, and after CRC verification, the temperature value is input into a multi-order polynomial temperature compensation model. The multi-order polynomial temperature compensation model calculates the real-time gain correction coefficient according to the pre-calibrated temperature and voltage drift curve by using the piecewise linear interpolation algorithm. If the correction coefficient exceeds the upper and lower limits, a two-order least square fitting subroutine is triggered to regenerate the calibration curve and update the coefficient table. Then, the original digitized voltage value obtained in step S1 is multiplied by the correction coefficient to generate the temperature-compensated voltage data, and the compensated voltage data is written into the ring FIFO buffer and synchronously triggers the input of the subsequent FIR filter.

[0035] It should be noted that the "periodic reading" in the present application is distinguished from fixed frequency sampling, which can match the temperature transient scene with dynamic rhythm adjustment capability, avoiding compensation failure caused by sampling lag. Temperature data is strictly screened by CRC check during transmission. CRC-8 polynomial is used for redundant check of data packet. If the check fails, the current data packet is discarded and the retransmission mechanism is triggered to ensure the reliability of data from the communication layer.

[0036] The temperature value is input into a multi-order polynomial temperature compensation model, which is the core engine for temperature drift correction. Its operation relies on the pre-calibrated temperature-voltage drift curve. At the implementation level, the model divides the wide temperature range of -40°C to 85°C into linear intervals of every 5°C, and calculates the real-time gain correction coefficient K through piecewise linear interpolation algorithm. Specifically, when the current temperature T is detected to be in the calibration interval, the coefficient K is obtained by linear interpolation of the end values K(T_k) and K(T_{k+1}): K(T) = K(T_k) + [K(T_{k+1}) - K(T_k)] × (T - T_k) / (T_{k+1} - T_k). This calculation process is efficiently executed in the MCU through table lookup method, and the pre-calibrated coefficient table is stored in the non-volatile memory. It is worth noting that when the correction coefficient K exceeds the preset safety boundary (typical threshold 0.85~1.15) or the temperature jump amplitude exceeds the historical mean ±10°C, the system will trigger a second-order least squares fitting subroutine for dynamic recalibration. The subroutine collects the latest 20 groups of temperature-drift data points, constructs the Vandermonde matrix Φ and solves the normal equation Φ^TΦa = Φ^Tb, updates the polynomial coefficient vector a, and finally generates a new calibration curve and refreshes the coefficient table. This mechanism enables the system to maintain compensation accuracy when encountering sensor abnormalities or extreme temperature changes. For example, when the temperature suddenly rises by 50°C due to air conditioning failure in a workshop, the system completes coefficient table reconstruction within 3ms, avoiding misoperation caused by compensation failure.

[0037] Temperature-compensated voltage data is written to a 256-bit circular FIFO buffer. The buffer stores data in 32-bit floating-point format, and the write pointer W_ptr advances according to the modulo operation rule: W_ptr = (W_ptr + 1) % 256. When the write pointer crosses a quarter boundary of the buffer (e.g., from 63 to 64), a hardware interrupt signal synchronously triggers the subsequent FIR filter to start data processing. It should be noted that the "window width" in this application differs from the fixed-window algorithm. Its adjustable characteristic is reflected in the automatic expansion of the window width to 64 points to enhance suppression capability when the harmonic distortion rate exceeds 5%, while reverting to the default 32-point value under steady-state conditions to reduce computational load. The innovation of the FIR filter lies in its support for online programming of filter coefficients. The coefficient vector b is dynamically generated through the Hamming window function. An example of the pseudocode for online updating of FIR coefficients is shown below: { for (int n=0; n <N; n++) {float hamm = 0.54 - 0.46*cos(2*PI*n / (N-1)); / / Hamming window float sinc = (n == N / 2) ? 2*fc / fs : sin(2*PI*fc*(nN / 2) / fs) / (PI*(nN / 2)); b[n] = hamm * sinc;} } The filter order can be dynamically adjusted between 16 and 128, with a cutoff frequency covering the range of 10Hz to 1kHz. When grid frequency fluctuations are detected, the system optimizes the filtering characteristics by modifying the cutoff frequency f_c in real time. For example, when encountering a frequency dip caused by motor start-up and shutdown, the cutoff frequency is automatically lowered to 40Hz to filter out low-frequency oscillation components. Simultaneously, a sliding window median filtering algorithm serves as a second level of protection. Its window width can be configured from 16 to 256 points, and the number of data accumulations m is adaptively selected between 4 and 16. This algorithm suppresses interference in two stages: first, the data within the window is sorted and the median is taken to eliminate single spikes; then, the arithmetic mean of the m consecutive median outputs is calculated to smooth harmonic disturbances. Experimental results show that this dual suppression mechanism reduces voltage fluctuations from ±12% to ±1.5% under a 6kV / μs grid transient impact, significantly improving the reliability of threshold determination.

[0038] The output of the entire signal processing chain is directly related to the core control logic of the low-voltage switch. In the under-voltage tripping scenario, the voltage sequence output by the FIR is sent to the tripping decision module. If the voltage of the continuous 5 sampling points is lower than 0.85 times the rated value (the specific threshold value can be configured according to the field working condition), the tripping mechanism is triggered. The key role of temperature compensation in this link is to eliminate the measurement deviation caused by the wide temperature range. For example, in a low-temperature environment of-20°C, the uncorrected op-amp offset voltage may cause a positive deviation of 2.3%, which is easy to cause premature tripping, while the error is suppressed within ±0.5% after compensation. In the closing scenario with voltage detection, the value of the anti-interference algorithm is particularly prominent: when there is intermittent arc harmonic in the power grid, the traditional RC filter may cause the closing signal to lag 100ms due to group delay, while the adjustable window width median filter in this scheme can control the delay within 10ms, while ensuring that the closing voltage detection error is less than 1% under 1kHz harmonic interference. It is worth noting that the reconstruction period of the least squares fitting subroutine, the adjustment step of the FIR order and other parameters can be determined by the field processing capacity, and this application does not make hard constraints.

[0039] Step S3, the real-time voltage value is compared with the under-voltage tripping threshold and the closing threshold with voltage detection set in advance through the parameter configuration interface by the embedded digital signal processing algorithm; in the implementation, a double-path independent comparator is deployed at the hardware level to process the under-voltage tripping and closing criterion with voltage detection respectively. The under-voltage tripping channel is set to a default threshold of 0.85 times the rated voltage (the specific value can be configured to 0.70-0.95pu), when the real-time voltage is lower than the threshold, the delay timer is started immediately. It should be noted that the "tripping delay time" in this application is different from the fixed delay, which supports hierarchical setting in the range of 200ms to 5s (such as 500ms for heavy load power grid and 250ms for sensitive load), and a moving average filter algorithm is introduced during the delay period to suppress voltage jitter: V_avg = Σ(ω_i * V_i) (i=1~5), the weight ω=[0.1,0.15,0.25,0.25,0.25] only when the average voltage of the continuous 5 sampling points is lower than the threshold (the continuous point number can be configured to 3-15 times), and the cumulative delay reaches the set value, the tripping command is output. The closing channel with voltage detection adopts a double-constraint strategy-the real-time voltage needs to be higher than the default closing threshold of 0.90pu (adjustable range 0.85-1.05pu), and at the same time, the voltage change rate limit `|dV / dt| <0.2 pu / ms` (the slope threshold can be set to 0.1-1.0pu / ms) is met. For example, in a certain standby power switching scenario, the voltage rises to 0.92pu but there is a 0.3pu / ms overshoot, at this time the slope constraint will block the closing command until the fluctuation is flat. The local interaction of the parameter configuration interface is realized through the knob encoder, physical button and LCD display screen.

[0040] As a typical implementation: User short-presses the knob to activate menu navigation in standby interface, and long-presses the knob to enter the first-level menu after rotating the knob to switch to the "Parameter Setting" item and confirming. The LCD displays the parameter item and the current value in two rows (such as the first row "UV_Thd:" and the second row "0.85pu"), and the value characters are highlighted in white and flicker when the target parameter (such as "Trip_Delay") is switched to by rotating the knob and the knob is long-pressed for 2 seconds to enter the editing mode. The user rotates the knob to adjust the value by 0.01pu or 10ms steps (the step size can be adjusted), and the MCU immediately performs three verifications after confirmation: range check (dangerous setting of trip threshold > 0.95pu is refused), reasonableness check (closing delay must be less than trip delay), and storage operation (new value is written to FRAM addresses 0x2000-0x2003). The LCD displays the comparison between the new and old parameters (such as "0.85pu→0.82pu") for 3 seconds at the moment of saving, and the visual feedback enhances the traceability of the operation. If no operation is detected for 10 seconds during the modification process, the system automatically exits the editing mode and restores the original value. The core of the on-site bus batch delivery mechanism lies in segmented transmission and cluster management.

[0041] When the host computer sends a multicast command frame (function code 0x10, group address 0x0F represents the 15th device group) through the Modbus RTU protocol, the switch device on the bus first parses the multicast address in the frame header. It should be noted that the "multicast address" in this application is different from the unicast address, the high 8 bits of which identify the device group number (0x00~0xFF supports 256 groups), and the low 8 bits mark the segment number (0x01~0x20 corresponds to 32 4KB frames). The device only receives data when the group number matches, effectively reducing network load. Each frame of data is attached with a CRC-16 check code, using the shift algorithm of polynomial 0x8005: the segmented data that passes the check is temporarily stored in the RAM buffer, and after the last frame flag (0xFFFF) arrives, a global CRC check is performed. After success, the MCU saves the current running parameter snapshot to the backup area (address 0x3000-0x30FF), and then writes the new parameters atomically to the FRAM main memory area through hardware write protection lock. If the check fails (such as the last frame CRC error bit 0x01), discard the buffer data and return an error code 0xEE+error type word to the bus, and the host computer can resend the specific frame accordingly. In a certain substation renovation case, the operation and maintenance personnel used this mechanism to batch upgrade the closing threshold of 30 switches from 0.90pu to 0.93pu, and the configuration file was transmitted in 8 frames, with a total time consumption of only 420ms (traditional point-to-point configuration requires >6 seconds). The safety fault-tolerant architecture runs throughout the parameter update process. Before writing to FRAM, the system creates a double parameter mirror in the backup area (address mirror interval 512 bytes), and any single-point storage failure can be recovered through cross-checking. The parameter takes effect instantly, triggering an interrupt service routine, and switching the register pointer to the new parameter area at the beginning of the next sampling period. In extreme cases (such as power interruption during writing), the power-on self-test program identifies damaged data blocks by comparing the checksums of the main and backup areas, and automatically rolls back to the last valid parameters. At the same time, the local interaction and bus configuration settings are mutually exclusive - when the knob is in the parameter editing state, the bus receiving module suspends responding to multicast commands to avoid concurrent modification conflicts. These mechanisms ensure that when the bus communication is interrupted due to lightning in a certain chemical plant, the switch device can still perform trip protection according to the threshold parameters stored locally, and the post-diagnosis shows that the parameter error rate is 0. The deep coupling with the core control behavior is reflected in two typical scenarios: 1. Under-voltage trip execution chain: when the grid voltage drops to 0.78pu due to line short circuit, the hardware comparator in step S3 detects the under-voltage state within 8us. After the delay counter starts, although the voltage rises to 0.87pu at 180ms (still lower than the set value of 0.82pu), the moving average algorithm (taking the weighted value of the last 5 points 0.81pu) still determines that the state is continuous. After 250ms delay arrives, the trip signal is driven through optical coupling isolation to drive the split coil, and the whole chain delay control from voltage anomaly to mechanical tripping is controlled within 260ms±5ms, meeting the GB 14048.2 standard.

[0042] 2. Detection of closing brake cooperation: After the standby generator is started, the voltage rises from 0 to 0.94pu, and step S3 detects that the voltage exceeds the threshold value (0.90pu) and starts a 100ms delay. During this period, the voltage fluctuates to 0.89pu due to load switching, but because the duration is less than 2ms and the slope does not exceed the limit, the closing command is still output as scheduled. The actuator is locked for 500ms (lock time configurable) after receiving the command to prevent misoperation caused by closing inrush current. The adjustable range of each parameter and the adaptive logic are as follows: The trip threshold is dynamically adjusted according to the type of power supply: the main power grid is set to 0.85pu by default, and the photovoltaic microgrid is set to 0.82pu to cope with higher volatility. The moving average weight can be switched: the steady-state load uses equal weight [0.2, 0.2, 0.2, 0.2, 0.2], and the impact load uses front-heavy and rear-light [0.3, 0.25, 0.2, 0.15, 0.10]. The multicast address allocation strategy supports geographical zoning (such as A zone device group 0x10) or functional grouping (such as critical load group 0xA0).

[0043] It should be emphasized that the icon design of the LCD menu, the pulse number / turn of the knob encoder (20PPR or 40PPR), and the absolute address mapping of the FRAM storage area can be determined according to the hardware platform resources, and do not affect the implementation of the core mechanism. In large intelligent power distribution rooms, this module improves the parameter deployment efficiency by 15 times, and the protection correct action rate under fault conditions reaches 99.98%. Its distributed configuration architecture has become a standardized design paradigm for low-voltage intelligent switches.

[0044] Step S4, when the voltage value is continuously lower than the preset under-voltage trip threshold and the duration exceeds the preset under-voltage trip delay time, the microcontroller triggers a synchronous zero-crossing short pulse and sends it to the opening drive interface to drive the low-voltage switch opening coil to act; Step S5, when the voltage value recovers to continuously above the preset detection of closing brake threshold and the duration exceeds the preset detection of closing brake delay time after opening, the microcontroller triggers a synchronous zero-crossing short pulse and sends it to the closing drive interface to drive the low-voltage switch closing coil to act; Specifically, when step S3 determines that the under-voltage condition is continuously met (the voltage is continuously lower than the set threshold and the duration exceeds the trip delay), the microcontroller starts the opening sequence; when the voltage recovers to above the closing threshold and stabilizes for more than the closing delay after opening, the closing process is triggered. The key point is to use the grid current zero-crossing detector as a synchronous reference to generate a 100-500μs delay narrow pulse to drive the opening and closing coils, so that the mechanism action avoids the current peak stress area, significantly reducing electromagnetic impact and contact ablation. The execution condition of under-voltage trip (S4) needs to meet both the voltage criterion and the time criterion: The real-time voltage value is continuously lower than the preset threshold (typical value 0.85 times rated voltage, adjustable range 0.70-0.95 pu) after mobile weighted average filtering (for example, 5-point weight [0.1, 0.15, 0.25, 0.25, 0.25]), and the state is continuously maintained for more than the trip delay (default 200 ms, can be set to 50 ms-5 s). It should be noted that the "continuous lower" in the present application is different from single sampling determination, which uses a historical state latching mechanism - if the voltage temporarily rises above the threshold during the delay period but the duration is less than 2 ms (can be set to 0.5-5 ms), the delay counter continues to accumulate without being cleared.

[0045] The trigger logic of the pressure closing (S5) needs to meet three constraints: the opening operation has been completed (the system state machine is in the "open" bit); the real-time voltage is continuously higher than the closing threshold (default 0.90 pu, can be set to 0.85-1.05 pu) after slope constraint filtering (|dV / dt| < 0.2 pu / ms); the voltage stable state duration exceeds the closing delay (default 100 ms, can be set to 50 ms-3 s). The core parameters of the synchronous zero-crossing short pulse include: the zero-crossing point detection accuracy depends on the current transformer (CT) secondary side signal conditioning circuit, which uses a high-speed comparator (such as LM393) to convert the sinusoidal current into a square wave, the rising edge marks the zero-crossing point, and the hardware delay is controlled to be ≤10 μs; the pulse trigger window is 100-500 μs adjustable time window (default 300 μs), which avoids the arc reignition period (0-80 μs) after current zero-crossing and the mechanical response delay zone (>600 μs); the pulse width is strictly limited to 150-250 μs (default 200 μs), which ensures that the coil obtains sufficient driving energy (typical value 5A x 200 μs = 1 mJ) but avoids continuous energization leading to overheating.

[0046] The under-voltage tripping execution flow (S4) starts with the microcontroller receiving the trip command in step S3: first, the current zero-crossing detector output is monitored by the TIM timer input capture channel to capture the rising edge of the square wave, and the zero-crossing time T0 is recorded; second, the pulse sending time T1 = T0 + Δt is calculated according to the preset Δt value (which can be modified online). It should be noted that the "delay trigger" in this application is different from the fixed phase angle control, and its dynamic adjustment capability is reflected in that when the coil temperature sensor detects a low temperature of -20°C, Δt is automatically increased from 300 μs to 500 μs to compensate for mechanical hysteresis; finally, a 200 μs high-level pulse is output at T1 to start the PWM channel, which drives the IGBT module (such as IRG4PH50U) through optical coupling isolation (TLP785), so that the tripping coil operates in the low electromagnetic stress interval after the current zero-crossing. The fault recording of a certain chemical plant shows that when the tripping is triggered 300 μs after the current zero-crossing, the current is only 3.2 A (2.7% of the peak current of 120 A) at the moment of contact separation, and the arc energy is reduced by 76% compared with traditional random tripping.

[0047] The under-voltage tripping execution flow (S4) starts with the microcontroller receiving the trip command in step S3: first, the current zero-crossing detector output is monitored by the TIM timer input capture channel to capture the rising edge of the square wave, and the zero-crossing time T0 is recorded; second, the pulse sending time T1 = T0 + Δt is calculated according to the preset Δt value (which can be modified online). It should be noted that the "delay trigger" in this application is different from the fixed phase angle control, and its dynamic adjustment capability is reflected in that when the coil temperature sensor detects a low temperature of -20°C, Δt is automatically increased from 300 μs to 500 μs to compensate for mechanical hysteresis; finally, a 200 μs high-level pulse is output at T1 to start the PWM channel, which drives the IGBT module (such as IRG4PH50U) through optical coupling isolation (TLP785), so that the tripping coil operates in the low electromagnetic stress interval after the current zero-crossing. The fault recording of a certain chemical plant shows that when the tripping is triggered 300 μs after the current zero-crossing, the current is only 3.2 A (2.7% of the peak current of 120 A) at the moment of contact separation, and the arc energy is reduced by 76% compared with traditional random tripping. ```c if ((adc_buf[i-1] > 2048 && adc_buf[i] <= 2048) || (adc_buf[i-1] < 2048 && adc_buf[i] >= 2048)) { t_zero = t_sample - (adc_buf[i-1] * T_s) / (adc_buf[i-1] - adc_buf[i]);} ``` When the hardware detector fails, the system automatically switches to software mode, and the precision is degraded from ±5 μs to ±100 μs, which can still maintain basic operation. The electromagnetic optimization of pulse timing is based on the equation of mechanism dynamics: Where: m is the mass of the core (typically 80 g), K is the electromagnetic force coefficient (0.05 N / A2), F_s is the spring counterforce (40 N). When the drive current I = 5 A, the theoretical movement time ≈8 ms. Triggering 300 μs after zero crossing can make the core start moving in the low electromagnetic force interval of the current, and the actual measured mechanism impact force is reduced from 1200 N to 450 N. It should be noted that the "synchronous zero-crossing short pulse" in the present application is different from the ordinary level signal, which is strictly limited in the 100-500 μs window after the zero crossing point and the pulse width is ≤250 μs, realizing the timing matching of electromagnetic force and mechanical movement.

[0048] The cooperation with the protection logic is reflected in the double protection mechanism: the coil health monitoring module samples the current waveform at 1 kHz during the closing and opening process, and if the current rise time > 50 μs (indicating contact oxidation) or the peak current < 4 A (coil turn-to-turn short circuit), the warning code E23 is triggered and recorded to the non-volatile memory; the reclosing lock function automatically disables the closing instruction after two consecutive closing failures (such as due to permanent short circuit), and the local knob needs to be reset or the bus command needs to be unlocked.

[0049] The extreme working condition response covers high harmonic and low temperature scenarios: in a certain frequency converter load distribution cabinet (THD = 18%), the zero-crossing detector generates false zero-crossing points due to 5th harmonic interference, and the system automatically enables 128-point FFT fundamental extraction to lock the zero-crossing signal at 50 Hz fundamental, with an error < 15 μs; in a high-cold area (-35 °C) substation, the increased viscosity of mechanical lubricating grease prolongs the mechanism action time to 38 ms, and after the temperature control module detects the low temperature, it automatically adjusts Δt to 500 μs and increases the pulse width to 250 μs, ensuring reliable opening. If the meter trips and the light is on during implementation, first check for overload or short circuit faults (such as measuring load impedance), then operate the closing button to the "I" position through the insulated handle, and gradually restore the load to avoid secondary tripping.

[0050] The parameter adaptive strategy dynamically adjusts according to the working conditions: when the coil temperature > 85 °C, Δt is reduced by 50 μs to compensate for the resistance increase; when THD > 10%, FFT fundamental extraction is enabled to suppress harmonic interference; when the voltage fluctuation rate > 5%, the closing slope threshold is reduced to 0.1 pu / ms to improve the stringent conditions. The specific filter weight coefficients (such as front-heavy and rear-light [0.3, 0.25, 0.2, 0.15, 0.10]) can be determined according to the load impact characteristics, and the present application does not make rigid constraints. It should be noted that the "pressure detection closing" in the present application is different from the traditional reclosing, which requires the voltage to recover stably and have a slope constraint to avoid surge current impact leading to protection misoperation. In actual engineering, the zero-crossing detection hardware can use a Rogowski coil instead of a traditional CT; the number of fault records stored in the FRAM (such as E01-E99) can be allocated according to the storage space.

[0051] Step S4-S5, the contact electric life is improved from 10,000 times to 30,000 times at the zero-crossing trigger makes the breaking arc energy ≤50mJ (national standard GB / T 14048.1 requires ≤300mJ), the measured 30MHz frequency band radiation interference is reduced to 42dBμV (traditional scheme 55dBμV), and the CISPR 11 Class A certification is passed; the synchronous control precision reaches ±5μs, the zero sequence circulating current of multiple parallel inverters is reduced by 90%. The design has been applied to the intelligent universal circuit breaker (model NA1-6300).

[0052] Step S6, during the breaking or closing process, the abnormal events including overcurrent, under-phase, overvoltage and driving failure are detected in real time by the fault monitoring module, if the abnormality is detected, the subsequent jump and close command is shielded, and the fault data is uploaded to the upper monitoring system.

[0053] Specifically, the overcurrent detection unit uses fast Fourier transform (FFT) to analyze the current waveform in real time, applies Hanning window function based on 256-point sampling window (sampling rate 4kHz) to suppress spectrum leakage, and calculates the amplitude of fundamental and harmonic components. It should be noted that the "overcurrent threshold" in the present application is different from the fixed threshold, and its dynamic model integrates the load baseline, harmonic increment and temperature drift: `I_threshold = 0.8 * I_base + 0.15 * ΔI_h3 + 0.05 * T_coeff` Where I_base is the historical sliding average current (window width 20 cycles), ΔI_h3 is the 3rd harmonic increment (sensitive indication of motor winding fault), and T_coeff is the temperature compensation coefficient from step S2. When the current amplitude of 3 consecutive cycles exceeds the threshold or the 5 / 7th harmonic increases by more than 40%, the overcurrent flag (alarm code 0x01) is triggered.

[0054] The phase loss detection unit synchronously acquires three-phase voltages (sampling rate 2kHz, resolution 12bit), calculating 40 moving effective values ​​per cycle. It should be noted that the "phase loss state" in this application differs from a single-phase power outage. It identifies asymmetrical faults such as open circuits and poor contact through dual criteria of amplitude difference and phase offset: if the amplitude difference exceeds 15% of the rated phase voltage (configurable from 10% to 25%) or the phase cosine value is less than 0.8 (corresponding to ±36° deviation), and persists for more than 200ms, a phase loss flag (alarm code 0x02) is triggered. In specific implementation, the system first sorts the three-phase voltages and takes the median V_median. If a phase satisfies `|V_x - V_median| > 0.15 * V_median`, the phase difference cosine value is calculated using a cross-correlation algorithm. In a cable phase loss case, the voltage of phase A drops to 70V (standard 230V), and the phase difference between phases B and C expands to 130°. The system locks the fault within 210ms. The voltage surge detection unit employs a composite sliding window algorithm (32 points @ 2kHz) combined with an improved CUSUM model. It should be noted that the "voltage surge rate" in this application differs from ordinary differential calculations; it uses Gaussian weighting to suppress noise interference. ```python gauss_weights = [exp(-(i-15.5)2 / 50) for i in range(32)]# σ=5 Gaussian window weighted_diff = sum(w * (V_t[i] - V_t[i-1]) for i,w in enumerate(gauss_weights)) if abs(weighted_diff) > 0.5: Threshold 0.5V / ms can be set to 0.2-1.0 trigger_fault() ``` When the voltage surge exceeds the limit for two consecutive calculation cycles, the voltage surge flag (alarm code 0x04) is triggered. During the lightning strike test, a 6kV / 1.2μs surge caused the C-phase voltage to rise to 480V within 5ms (surge rate 1.2V / ms), and the detection unit responded within 15μs.

[0055] The fault flag is processed by a hardware priority arbiter: overcurrent (0x01) is the highest level, immediately shielding all operations; open-phase (0x02) is the middle level, only shielding closing and allowing tripping; voltage mutation (0x04) is the lowest level, only recording and not shielding. The arbiter uses FPGA logic gates to make nanosecond-level decisions, outputs the fault code to the "operation prohibition" register, and cuts off the driving signal path in hardware. After the fault is locked, the host computer needs to send a 0x55AA reset command to release it. In actual debugging, the window size (such as 16-64 points) and phase tolerance (0.7-0.9) can be adjusted according to the noise level on site. The power-off data protection relies on the built-in Flash of STM32F4 to build a ring-shaped log area (starting address 0x080E0000). When the power voltage drops to 4.7V, the standby capacitor maintains power supply for 50ms, and the system performs sector erase (200ms) and then writes compressed logs: timestamp (Unix seconds), arbitration fault code, 12-bit sampling values of three-phase voltage and current. This module is deeply linked with the tripping and closing control. If overcurrent occurs during undervoltage tripping execution (S4), the opening pulse is immediately blocked to actuate the fuse; if open-phase occurs during the on-load closing (S5) stage, the closing command is shielded, and the LCD displays "open-phase lockout". The specific Flash address mapping can be modified according to the MCU model (such as 0x0807F000 for STM32F1), and the Gaussian weight coefficient σ (3-10) also does not affect the core mechanism, reflecting the dual breakthroughs of fault immunity and data resilience.

[0056] Although the specific embodiments of the present application are described above, those skilled in the art should understand that these specific embodiments are only illustrative, and those skilled in the art can make various omissions, substitutions and changes to the details of the above method and system without departing from the principles and essence of the present application. For example, combining the above method steps, performing substantially the same function in substantially the same manner to achieve substantially the same result according to the same method is within the scope of the present application. Therefore, the scope of the present application is only limited by the appended claims.

Claims

1. A control method for undervoltage tripping and voltage-detected closing of a low-voltage switch; characterized in that: The method includes the following steps: Step S1: The phase voltage and line voltage signals of the bus are introduced into the monitoring unit through the voltage transformer and voltage divider network set on the main bus side of the system. The monitoring unit uses an isolation amplifier to isolate the analog voltage signal and amplify the amplitude, and then uses a 24-bit Δ-Σ analog-to-digital converter to sample and obtain the digital voltage value. Step S2: The ambient temperature is collected in real time by a temperature sensor. The digital voltage value is transformed by temperature drift compensation based on the temperature value. Finite impulse response filtering, sliding window median filtering and oversampling integration algorithm are used to suppress transient interference from the power grid and obtain the real-time voltage value. Step S3: The real-time voltage value is compared in parallel with the undervoltage trip threshold and the voltage detection closing threshold pre-set through the parameter configuration interface using an embedded digital signal processing algorithm. Step S4: When the voltage value is continuously lower than the preset undervoltage trip threshold and the duration exceeds the preset undervoltage trip delay time, the microcontroller triggers a synchronous zero-crossing short pulse, which is sent to the trip drive interface to drive the low-voltage switch trip coil to operate. Step S5: When the voltage value recovers to a level continuously higher than the preset voltage detection closing threshold after the circuit breaker is opened and the duration exceeds the preset voltage detection closing delay time, the microcontroller triggers a synchronous zero-crossing short pulse, which is sent to the closing drive interface to drive the low-voltage switch closing coil to operate. Step S6: During the tripping or closing process, the fault monitoring module performs real-time detection of abnormal events, including overcurrent, phase loss, overvoltage, and drive failure. If an abnormality is detected, subsequent tripping or closing commands are blocked and the fault data is uploaded to the upper-level monitoring system.

2. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In step S1, the 24-bit Δ-Σ analog-to-digital converter is further configured with a programmable gain amplifier at its front end. The programmable gain amplifier is used to automatically switch the gain factor according to the measured voltage level to ensure that the digital voltage value with the best signal-to-noise ratio is obtained under different voltage ranges. At the same time, the ADC sampling rate can be dynamically adjusted in the range of 8 kHz to 64 kHz.

3. The control method for undervoltage tripping and voltage-detected closing of a low-voltage switch according to claim 2, characterized in that: The joint operating logic of the programmable gain amplifier and the 24-bit Δ-Σ analog-to-digital converter includes: The MCU receives the analog voltage output from the isolation amplifier, generates an initial digital voltage sample through a 24-bit ΔΣ ADC, and internally calculates the peak, peak value and root mean square value of the sample through a sliding window to quantize the current voltage amplitude range. When the calculation result exceeds the preset dead band, the MCU sends a gain level switching command to the programmable gain amplifier via SPI according to the amplitude range and the multi-level gain mapping table, and simultaneously uses real-time spectrum energy distribution analysis to adjust the sampling rate in the range of 8kHz to 64kHz with spectrum energy guidance. After the sampling rate and gain are switched, a calibration pulse is injected through the analog-to-digital converter, and the digital calibration unit performs zero bias and gain correction on the new range output to eliminate switching distortion. The second-order moving average suppression is applied to the amplitude over-limit judgment result, and the sampling rate and gain switching are allowed when the amplitude exceeds a preset number of consecutive cycles.

4. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In step S2, the FIR filter uses programmable filter coefficients to modify the filter order and cutoff frequency online; the sliding window median filtering algorithm achieves dual suppression of power grid spike pulses and harmonic components through adjustable window width and data accumulation count.

5. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In step S2, the principle of temperature drift compensation transformation of digital voltage value based on temperature value is as follows: The MCU periodically reads the output of digital temperature sensor through I²C interface and performs CRC verification. Then, it inputs the temperature value into multi-order polynomial temperature compensation model. The multi-order polynomial temperature compensation model calculates the real-time gain correction coefficient according to the pre-calibrated temperature and voltage drift curves using a piecewise linear interpolation algorithm. If the correction coefficient exceeds the upper and lower limits, the second-order least squares fitting subroutine is triggered to regenerate the calibration curve and update the coefficient table. Then, the original digital voltage value obtained in step S1 is multiplied by the correction coefficient to generate temperature-compensated voltage data. The compensated voltage data is written into the ring FIFO buffer and the input of the subsequent FIR filter is triggered synchronously.

6. The control method for undervoltage tripping and voltage-detected closing of a low-voltage switch according to claim 1, characterized in that: In step S3, the reference parameters for undervoltage tripping threshold, voltage detection closing threshold, tripping delay time, and closing delay time are set online through a parameter configuration interface. The parameter configuration interface allows interaction via local LCD display, rotary knobs, and fieldbus, and supports batch distribution of configuration files to multiple devices through a batch distribution mechanism. The working principle of step S3 includes: Periodically scan the input events of the knob and drive the LCD to display the menu hierarchy. When the user selects a parameter by rotating the knob and presses to confirm, the threshold and delay parameters are updated to the register in real time, and the comparison between the old and new parameters is displayed on the screen in real time. The MCU's communication module automatically registers with the fieldbus network upon startup and periodically listens for Modbus RTU / CAN broadcast frames. When it receives a parameter transmission frame with a predefined function code, it parses the device group address, configuration file content, and CRC check value within the frame. The configuration file is transmitted in the form of segmented frames. Each frame header contains a multicast address and a segment sequence number. After the device passes the verification, it writes the segmented data into a temporary buffer. After receiving all segments and completing the overall CRC check, the data is written into the non-volatile memory in batches. At the same time, a parameter activation interrupt is triggered, and the threshold and delay registers used in step S3 are updated. Before writing, the MCU saves a snapshot of the current parameters; if writing or verification fails, the snapshot is automatically restored and the error code is sent back via LCD or fieldbus. After configuration, the MCU deploys the new parameters in the next sampling cycle and broadcasts the parameter status to the host system via the fieldbus.

7. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In steps S5 and S4, the synchronous zero-crossing short pulse is triggered by the microcontroller and the grid current zero-crossing detector. The grid current zero-crossing detector monitors the current waveform in real time. When the current zero-crossing point is detected, a drive pulse is sent within a delay range of 100 microseconds to 500 microseconds to reduce mechanical and electromagnetic shocks during switching.

8. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In step S6, the fault monitoring module includes an overcurrent detection unit, a phase loss detection unit, and a voltage surge detection unit. The overcurrent detection unit analyzes the amplitude change of the current waveform based on fast Fourier transform and calculates the overcurrent threshold in real time. The phase loss detection unit determines the phase loss state by comparing the differences in the three-phase voltage amplitudes. The voltage surge detection unit detects the voltage surge rate using a sliding window algorithm and triggers a fault state when the threshold is exceeded. The overcurrent detection unit, phase loss detection unit, and voltage surge detection unit each map the fault flag to different levels of alarm codes, output the highest-level fault code through a priority arbitrator, and trigger shielding logic to invalidate subsequent trip and close commands.

9. The control method for undervoltage tripping and voltage detection closing of a low-voltage switch according to claim 1, characterized in that: In step S6, the unuploaded logs are automatically saved to the built-in Flash memory in the event of a power outage, and are automatically uploaded after power is restored.

Images