Regulator circuit, low dropout regulator and method for increasing ripple suppression of power supply

Abstract

The invention relates to a regulator circuit, a low dropout regulator and a method for increasing power supply ripple suppression. A regulator circuit includes a first stage, a second stage, and a boost circuit. The first stage includes a reference input and a feedback input configured to receive feedback from an output of the regulator circuit. The second stage is coupled to the first stage. The second stage includes an output transistor configured to drive the output of the regulator circuit. The boost circuit includes a first transistor configured to generate a bias current based on an output current of the output transistor. The boost circuit also includes a current-to-voltage converter configured to generate a bias voltage based on the bias current, and a capacitive element coupled between the current-to-voltage converter and a node of the first stage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to power supply ripple rejection in voltage regulators, and in particular, to an adaptive system for enhancing power supply ripple rejection in low-dropout voltage regulators. BACKGROUND

[0002] A voltage regulator circuit is a circuit for converting a regulated or unregulated input voltage to a regulated output voltage that can be used to power an electronic device. A low-dropout (“LDO”) regulator (or LDO regulator) is a type of linear voltage regulator circuit that can provide a regulated output voltage even when there is only a small difference between the input voltage and the desired output voltage. An LDO regulator can utilize an open-drain topology at the output of the LDO in which an output transistor is driven into saturation, thereby minimizing the voltage drop across the output transistor in the case where the desired output voltage is close to the input voltage.

[0003] One performance parameter of voltage regulator circuits, including LDO regulators, is power supply ripple rejection (“PSRR”), also known as power supply rejection ratio. The PSRR of a voltage regulator circuit describes the ability of the voltage regulator circuit to suppress the effects of noise or other variations on the input voltage supply of the voltage regulator circuit on the regulated output voltage of the voltage regulator circuit. The inventors of the present disclosure have recognized that known techniques for improving PSRR can use large bias currents. Accordingly, the inventors of the present disclosure have discovered that it can be difficult to improve PSRR without adversely affecting quiescent current consumption. Embodiments of the present disclosure can address one or more of these challenges. SUMMARY

[0004] According to a first aspect, there is provided a regulator circuit comprising: a first stage, a second stage, and a boost circuit. The first stage comprises a reference input and a feedback input configured to receive feedback from an output of the regulator circuit. The second stage is coupled to the first stage, the second stage comprising an output transistor configured to drive the output of the regulator circuit. The boost circuit comprises: a first transistor configured to generate a bias current based on an output current of the output transistor; a current-to-voltage converter configured to generate a bias voltage based on the bias current; and a capacitive element coupled between the current-to-voltage converter and a node of the first stage.

[0005] According to a second aspect, there is provided a low dropout regulator comprising: a first amplifier stage, a second amplifier stage, and a boost circuit. The first amplifier stage is configured to be powered by a first voltage supply, the first amplifier stage comprising: a reference input and a feedback input configured to receive feedback from an output of the low dropout regulator. The second amplifier stage is configured to be powered by a second voltage supply, the second amplifier stage comprising: a second stage input coupled to a first stage output, and an output transistor configured to drive the output of the low dropout regulator. The boost circuit is configured to be powered by the second voltage supply, the boost circuit comprising: a first transistor configured to mirror an output current of the output transistor to generate a bias current, a current to voltage converter configured to generate a bias voltage based on the bias current, and a capacitive element coupled between the current to voltage converter and a node of the first amplifier stage.

[0006] According to a third aspect, there is provided a method for increasing power supply ripple rejection, the method comprising: providing a regulated output voltage at an output of a regulator circuit; generating a bias current based on an output current of the regulator circuit; converting the bias current to a bias voltage at a bias voltage node; and capacitively coupling the bias voltage node to an amplifier stage of the regulator circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] A more complete understanding of embodiments of the application can be obtained by reference to the following description taken in connection with the accompanying drawings, wherein like reference numerals indicate like features.

[0008] Figure 1 A schematic diagram of an LDO regulator is shown in accordance with example embodiments of the present disclosure.

[0009] Figure 2 A plot of operating voltages within an LDO regulator is shown in accordance with example embodiments of the present disclosure.

[0010] Figure 3A A plot of improved PSRR of an LDO regulator is shown in accordance with example embodiments of the present disclosure.

[0011] Figure 3B A plot of improved PSRR of an LDO regulator is shown in accordance with example embodiments of the present disclosure.

[0012] Figure 4 A plot of bias voltage and bias current of a PSRR boost circuit as a function of output current of an LDO regulator is shown in accordance with example embodiments of the present disclosure.

[0013] Figure 5 A plot of the capacitance of a varactor diode as a function of the bias voltage applied across the varactor diode is shown in accordance with example embodiments of the present disclosure.

[0014] Figure 6 A method for enhancing power supply ripple rejection of a regulator circuit is shown in accordance with example embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description, the drawings, and the claims.

[0016] Figure 1 A schematic diagram of an LDO regulator 100 is shown in accordance with example embodiments of the present disclosure. The LDO regulator 100 can include a first stage 110, a second stage 120, an output terminal 130, a compensation circuit 135, and a PSRR boost circuit 150. The LDO regulator 100 can receive a reference voltage V REF , a first voltage supply VDD, and a second voltage supply VCC. The LDO regulator 100 can provide a regulated output voltage V REF at the output terminal 130 based on the reference voltage V OUT and feedback from the output terminal 130. The LDO regulator 100 can be configured to provide the regulated output voltage V OUT to an electronic device, such as a load 140. An output current I OUT provided by the LDO regulator 100 can depend on an amount of current drawn by the load 140. The amount of current drawn by the load 140 can vary depending on operating characteristics of the electronic circuit forming the load 140. For example, when the electronic circuit forming the load 140 is in a standby or non-operational mode, the load current can be 0 mA. Conversely, when the electronic circuit forming the load 140 is operating, the load 140 can draw a load current higher than 0 mA, such as 5 mA, 1 mA, 10 mA, 100 mA, 1 A, or more.

[0017] The first stage 110 can be implemented in any suitable manner in accordance with the operations described in the present disclosure. In some embodiments, the first stage 110 can include a reference input terminal 101, a feedback input terminal 102, transistors 111-114, and a current source 116. As Figure 1As shown in FIG, the components of the first stage 110 can be configured as a first amplifier stage. Transistors 111 and 112 can be P-channel metal oxide semiconductor field effect transistors ("P-channel MOSFETs" or "PMOS" transistors). PMOS transistors 111 and 112 can be configured as a differential pair, wherein their respective source terminals are coupled together to commonly receive a bias current from a current source 116. Current source 116 can be coupled to a first voltage supply VDD and can generate a bias current for the first stage 110. The gate of transistor 111 can be coupled to a reference input 101 to receive a reference voltage V REF The gate of transistor 112 can be coupled to feedback input 102 to receive a feedback voltage from the output of LDO regulator 100. Thus, the differential pair formed by transistors 111 and 112 can provide a reference voltage V at reference input 101. REF Any voltage difference between the feedback voltage and the feedback voltage at the feedback input 102 is compared and amplified.

[0018] like Figure 1 As shown, transistors 113 and 114 can be N-channel metal oxide semiconductor field effect transistors ("N-channel MOSFETs" or "NMOS" transistors). The drain of NMOS transistor 113 can be coupled to the drain of PMOS transistor 111, and the drain of NMOS transistor 114 can be coupled to the drain of PMOS transistor 112. In addition, the gate of NMOS transistor 113 and the gate of NMOS transistor 114 can be coupled to the drain of NMOS transistor 113 at node A, so that NMOS transistor 114 mirrors the current of NMOS transistor 113. Therefore, the components of first stage 110, including current source 116, PMOS transistors 111 and 112, and NMOS transistors 113 and 114, can collectively form a first amplifier stage having a first stage output at node 119.

[0019] The second stage 120 may be implemented in any suitable manner according to the operations described in this disclosure. In some embodiments, the second stage 120 may include an NMOS transistor 121, an NMOS transistor 122, a PMOS transistor 123, and a PMOS transistor 124. Figure 1 As shown in FIG, the components of the second stage 120 can be configured as a second amplifier stage, wherein the PMOS transistor 124 is configured as an output transistor having an open drain output terminal that drives the output terminal 130 of the LDO regulator 100. The second stage 120 may include a second stage input terminal that can be coupled to the first stage output terminal of the first stage 110. For example, Figure 1As shown in FIG, the gate of NMOS transistor 121 may be coupled to the first stage output at node 119, and the source of NMOS transistor 121 may be coupled to ground GND. NMOS transistor 121 may thus generate a drive current based on the transconductance of NMOS transistor 121 and the gate-to-source voltage applied across node 119 and ground GND.

[0020] NMOS transistor 122 may be coupled to reside in the path of the drive current generated by NMOS transistor 121. Figure 1 As shown in FIG, NMOS transistor 122 may have a gate coupled to VDD and a source coupled to the drain of NMOS transistor 121. Thus, NMOS transistor 122 may maintain a bias voltage at the drain of NMOS transistor 121 at a level equal to VDD minus the gate-to-source voltage of NMOS transistor 122. VDD may be a low voltage supply at, for example, 1.8V, 3.3V, 5.0V, or any other voltage suitable for low-voltage complementary metal oxide semiconductor ("CMOS") circuits. In some embodiments, VCC may be any of the following: a low voltage supply substantially equal to or greater than VDD; a medium voltage supply, such as 24V or up to 40V; or a high voltage supply greater than 40V, such as 50V, 60V, 70V, or higher. In embodiments where VDD and VCC have the same voltage value, VDD and VCC may be implemented by a single voltage supply. VDD and VCC may be supplied by one or more voltage regulators located upstream of LDO regulator 100. These upstream voltage regulators may be implemented with on-chip circuitry along with the components of the LDO regulator 100 , or may be implemented with off-chip circuitry separate from the chip on which the components of the LDO regulator 100 may be implemented.

[0021] The PMOS transistor 123 and the PMOS transistor 124 may be configured to mirror the driving current generated by the NMOS transistor 121 and passing through the NMOS transistor 122 to convert the output current I OUT is provided to the load 140. The respective sources of the PMOS transistor 123 and the PMOS transistor 124 can be coupled to the second voltage supply VCC. The gates of the PMOS transistors 123 and 124 can be coupled together and further coupled to the drain of the PMOS transistor 123. The drain of the PMOS transistor 123 can also be coupled to the drain of the NMOS transistor 122. Therefore, the drive current generated by the NMOS transistor 121 can pass through the PMOS transistor 123 and can be mirrored by the PMOS transistor 124 to convert the output current I OUTto the load 140. The PMOS transistor 123 and the PMOS transistor 124 can be designed in a ratio in size such that the drive current consumed by the second stage 120 from the second voltage supply VCC is proportional to the output current I OUT to the load 140. For the purposes of this disclosure, the size of an individual NMOS transistor or PMOS transistor can refer to the width-to-length ratio of the transistor's conduction channel, and the size ratio between different transistors can refer to the width-to-length ratio of one transistor relative to the width-to-length ratio of another transistor. The ratio of the size of the PMOS transistor 123 to the PMOS transistor 124 can be, for example, 1 : 10, 1 : 100, 1 : 1000, or less, to scale proportionally according to the same ratio to produce the output current I OUT drawn by the load 140. When the output current I OUT drawn by the load 140 is zero, the bias current consumed by the second stage 120 can likewise be zero, despite any nominal semiconductor leakage current.

[0022] The second stage 120 can also include an output capacitor 125 and feedback resistors 126 and 127. The output capacitor 125 can store charge at the output terminal 130 of the LDO regulator 100. When the LDO regulator 100 responds to changes in the demand for the output current I OUT drawn by the load 140, the output capacitor 125 can help maintain the regulated output voltage V OUT at the desired output voltage level.

[0023] The feedback resistors 126 and 127 can be coupled in series to form a resistor divider between the output terminal 130 and ground GND. The feedback resistors 126 and 127 can be designed to have large resistance values, for example, in the range of kilo-ohms, mega-ohms, or higher, such that the current drawn and consumed by the feedback resistors 126 and 127 from the PMOS transistor 124 is small relative to the output current I OUT drawn by the load 140. An intermediate node between the resistor 126 and the resistor 127 can be coupled to the feedback input 102 of the first stage 110. The feedback resistors 126 and 127 can thus provide feedback to the first stage 110 representative of the output voltage V OUT Based on this feedback, the first stage 110 and the second stage 120 can collectively regulate the output voltage V OUT to a level proportional to the reference voltage V REF .

[0024] In some implementations, the output capacitor 125, as well as the feedback resistors 126 and 127, can be implemented as on-chip components, as off-chip components, or as a combination of on-chip and off-chip components. Figure 11 and 2. In other embodiments, the output capacitor 125, feedback resistors 126 and 127, or any combination thereof, may be implemented separately from the second stage 120. For example, in some embodiments, the transistors 121 to 124 of the second stage 120 may be implemented as on-chip circuitry along with the components of the first stage 110 and the PSRR boost circuit 150, while the output capacitor 125 and feedback resistors 126 and 127 may be implemented separately with off-chip components. Additionally, the feedback of the LDO regulator 100 may be provided by a circuit such as Figure 1 The feedback resistors 126 and 127 shown in FIG are implemented as feedback resistors, or by a resistor suitable for representing the output voltage V OUT The feedback signal is provided to the feedback input 102 for any other feedback network implementation.

[0025] LDO regulator 100 may also include compensation circuit 135. Compensation circuit 135 may be configured to compensate for the frequency response of LDO regulator 100 and thereby ensure the stability of LDO regulator 100. In some embodiments, compensation circuit 135 may be implemented by a capacitor coupled between ground and the output of the first stage at node 119. In other embodiments, compensation circuit 135 may be located at any suitable location within LDO regulator 100 and may include any suitable arrangement of components (such as capacitors and resistors) for ensuring the stability of the regulation loop. In some embodiments, compensation circuit 135 may be implemented using on-chip circuitry along with components of first stage 110, second stage 120, and PSRR boost circuit 150. In other embodiments, the compensation circuit may be implemented using off-chip components separate from first stage 110, second stage 120, or PSRR boost circuit 150.

[0026] like Figure 1 As shown, the LDO regulator 100 may also include a PSRR boost circuit 150. The PSRR boost circuit 150 may be implemented in any suitable manner according to the operations described in the present disclosure. In some embodiments, the PSRR boost circuit 150 may include transistors 153, 152, 151 and a capacitive element 160. Transistor 153 may be a PMOS transistor that matches PMOS transistors 123 and 124. The source of PMOS transistor 153 may be coupled to VCC, and the gate of PMOS transistor 153 may be coupled to the gates of PMOS transistors 123 and 124. PMOS transistor 153 may thus mirror the drive current with PMOS transistor 124 to generate an output current I OUT In a similar manner, the driving current through the PMOS transistor 123 is mirrored to generate the bias current I biaspsrr The bias current I generated by the PMOS transistor 153 for the PSRR boost circuit 150 biaspsrrIt can be compared with the output current I OUT In this disclosure, I biaspsrr The description of may refer to the DC component of the current generated by the PMOS transistor 124 unless both the DC component and the AC ripple of the current generated by the PMOS transistor 124 are described. Because the PMOS transistor 153 mirrors the drive current with the PMOS transistor 124 to generate the output current I OUT A similar approach is used to generate the driving current I biaspsrr Therefore, the PMOS transistor 153 can also be referred to as a transistor based on the output current I OUT Produce I biaspsrr , or more specifically, is referred to as the output current I OUT In some embodiments, the sizes of the PMOS transistor 153 and the PMOS transistor 124 can be designed in a ratio such that the bias current I consumed by the PSRR boost circuit 150 is biaspsrr Relative to the output current I OUT The ratio of the size of the PMOS transistor 153 to the size of the PMOS transistor 124 may be, for example, 1:10, 1:100, 1:1000, or less to provide a smaller size than that of the PMOS transistor 153. OUT Scaling the bias current I biaspsrr .

[0027] like Figure 1 As shown in the figure, the bias current I biaspsrr The bias current I can be received by the drain of the NMOS transistor 151 at the node B of the PSRR boost circuit 150 through the NMOS transistor 152. The NMOS transistor 151 can be configured as a diode-connected transistor, wherein the gate of the NMOS transistor 151 is coupled to the drain of the NMOS transistor 151 and the source of the NMOS transistor 151 is coupled to the ground GND. The NMOS transistor 151 can thus function as a current-to-voltage converter based on the bias current I received by the NMOS transistor 151. biaspsrr A bias voltage is generated at node B.

[0028] Capacitive element 160 may be coupled, for example, between node B of PSRR boost circuit 150 and node A of first stage 110. Capacitive element 160 may include diode 161 coupled in series with capacitor 162. Diode 161 may be arranged such that its cathode points toward node B of PSRR boost circuit 150. For example, Figure 1, diode 161 may have an anode coupled to node A of first stage 110, while capacitor 162 is coupled in series between the cathode of diode 161 and node B of PSRR boost circuit 150. In other examples, diode 161 may have a cathode coupled to node B of PSRR boost circuit 150, while capacitor 162 is coupled in series between the anode of diode 161 and node A of first stage 110. In other embodiments, capacitive element 160 may include any suitable number of instances of diode 161 and capacitor 162 arranged in series or in parallel to provide suitable capacitive coupling between node B of PSRR boost circuit 150 and node A of first stage 110.

[0029] The first stage 110 and the PSRR boost circuit 150 can be configured so that the diode 161 remains in the reverse biased operating region or the zero biased operating region. For example, the DC operating point of the node B depends on the size of the NMOS transistor 151 and the output current I OUT Bias current I for mirroring biaspsrr The size of the NMOS transistor 151 and the I biaspsrr with I OUT The ratio of may be configured such that the DC operating voltage at node B remains close to or higher than the DC operating voltage at node A of first stage 110 , thereby keeping diode 161 in a zero bias or reverse bias operating region.

[0030] Figure 2 An exemplary graph showing the corresponding DC operating voltages of node A and node B within the LDO regulator 100 according to an exemplary embodiment of the present disclosure is shown. Graph 201 shows the DC operating voltages of node A and node B as the output current I OUT The DC operating voltage (“V A ”). The graph 202 shows the output current I OUT The DC operating voltage (“V B ").like Figure 2 As shown in FIG, the DC operating voltage of node A can be kept constant regardless of the output current I OUT On the other hand, as the output current I OUT As the capacitive element 160 increases, the DC operating voltage of the node B of the PSRR boost circuit 150 may increase from a voltage close to the voltage of the node A at a nominal output current (such as 1 μA) to a voltage greater than the voltage of the node A. Thus, the relative voltages of the node of the first stage 110 with the capacitive element 160 coupled therebetween and the node of the PSRR boost circuit 150 maintain the diode 161 in a zero bias or reverse bias operating region.

[0031] Because diode 161 is held in a reverse-biased or zero-biased operating region, diode 161 can act as a space-charge region (depletion / barrier) capacitor. The capacitance C 160 may be expressed as:

[0032] C 160 = (C 161 *C 162 ) / (C 161 +C 162 )

[0033] where C 161 is the capacitance of diode 161 and C 162 is the capacitance of capacitor 162.

[0034] Referring again to Figure 1 , PSRR boost circuit 150 can improve the PSRR of LDO regulator 100. PSRR boost circuit 150 provides compensation for unwanted variations in output current I OUT and output voltage V OUT caused by high-frequency AC ripple on VCC. As explained in detail below, PSRR boost circuit 150 can be configured to generate and inject compensation into the regulation loop of LDO regulator 100 that is opposite in phase to the effect that high-frequency AC ripple on VCC would otherwise have on output current I OUT and output voltage V OUT of LDO regulator 100.

[0035] As described above with reference to Figure 1 , PMOS transistor 153 of PSRR boost circuit 150 can be configured to generate a bias current I OUT that is proportional to output current I biaspsrr . In terms of high-frequency AC ripple on VCC adding a high-frequency ripple component to I OUT , the high-frequency AC ripple on VCC can similarly add a high-frequency AC ripple component to I biaspsrr that is proportional in amplitude to the DC component of I biaspsrr . As described above, NMOS transistor 151 can be configured as a diode-connected transistor and coupled to receive I biaspsrr . NMOS transistor 151 can thus act as a current-to-voltage converter that generates a voltage at node B based on I biaspsrr . Accordingly, the high-frequency AC ripple from VCC can be injected into I biaspsrrThe bias voltage at node B is translated to the first stage 110. The capacitive element 160 can capacitively couple node B of the PSRR boost circuit 150 to node A of the first stage 110. The capacitive element 160 can thus inject at least a portion of the high-frequency AC ripple present on node B of the PSRR boost circuit 150 into node A of the first stage 110.

[0036] The polarity of node A of the first stage 110 can be opposite to the polarity of the output of the LDO regulator 100. For example, in the LDO regulator 100, the signal path from node A of the first stage 110 to the output 130 traverses three inversions, including across the NMOS transistor 114, the NMOS transistor 121, and the PMOS transistor 124. Thus, the high-frequency AC ripple originating from VCC and that can be injected into node A of the first stage 110 as a compensation signal can tend to cancel and compensate for the high-frequency AC ripple from VCC on the output current I OUT and the output voltage V OUT has the effect of.

[0037] Referring back to Figure 1 , the diode 161 and the capacitor 162 can be sized such that their capacitances do not substantially affect the gain or phase margin of the LDO regulator 100 at unity gain. The diode 161 can be sized such that its nominal zero-bias capacitance can be, for example, 4 pF, 2 pF, 1 pF, or less. Similarly, the capacitor 162 can be sized such that its capacitance can be, for example, 4 pF, 2 pF, 1 pF, or less. The PSRR boost circuit 150 can thus improve the PSRR of a regulator circuit, such as the LDO regulator 100, without adversely affecting the operating bandwidth or stability of the regulator circuit.

[0038] Figure 3A and Figure 3B A plot showing improved PSRR of an example LDO regulator according to an example embodiment of the disclosure is shown. The PSRR boost circuit 150 can improve the PSRR in a range of frequencies above the unity-gain bandwidth of the LDO regulator. Figure 3A The PSRR of an example LDO regulator having a unity-gain bandwidth of about 3 kHz at an output current I OUT of 5 μΑ is shown. Plot 301 shows the PSRR of an example LDO regulator with the PSRR boost circuit 150, and plot 302 shows the PSRR of an example LDO regulator without the PSRR boost circuit 150. As shown in Figure 3A at an output current I OUT of 5 μΑ, the PSRR boost circuit 150 can improve the PSRR of frequencies ranging approximately from 4 kHz to 40 kHz. Figure 3BThe output current I OUT The PSRR of an example LDO regulator with a unity gain bandwidth of about 60 kHz at an output current I OUT The PSRR of an example LDO regulator with a unity gain bandwidth of about 60 kHz at an output current I Figure 3B The PSRR of an example LDO regulator with a unity gain bandwidth of about 60 kHz at an output current I OUT The PSRR of an example LDO regulator with a unity gain bandwidth of about 60 kHz at an output current I Figure 3A The PSRR of an example LDO regulator with a unity gain bandwidth of about 60 kHz at an output current I 3B As shown collectively, the PSRR improvement techniques disclosed herein provide an adaptive system whereby the PSRR improvement provided by the PSRR boost circuit 150 can vary with both the frequency and the output current I OUT of the regulator.

[0039] Embodiments of the PSRR boost circuit 150 are described above as operating with an LDO regulator 100 that includes a first stage 110 and a second stage 120. In other embodiments, the PSRR boost circuit 150 can also be implemented to improve the PSRR of other types of regulator circuits or other types of LDO regulators. For example, the PSRR boost circuit 150 can be implemented to improve the PSRR of a regulator circuit that utilizes any number and any type of amplifier stage suitable for providing a regulated output voltage at an output of the regulator circuit. In some embodiments, the PSRR boost circuit 150 can generate a compensation signal based on a high frequency ripple at VCC and inject the compensation signal into a node within the regulator circuit that is opposite in polarity to the output of the regulator circuit.

[0040] The features of the PSRR boost circuit 150 can allow the maximum bias current I biaspsrr clamped at a maximum value. The maximum current consumed by the PSRR boost circuit 150 from VCC can therefore be advantageously limited.

[0041] Referring back to Figure 1 , the PMOS transistor 153 of the PSRR boost circuit 150 mirrors the drive current generated by the NMOS transistor 121 in a similar manner to the PMOS transistor 124. The PMOS transistor 153 therefore generates a bias current I biaspsrr for the PSRR boost circuit 150 that can be proportional to the output current I OUT In some embodiments, the NMOS transistor 152 can operate as a clamp or clamp transistor that limits the maximum bias current I biaspsrr For example, as Ibiaspsrr with I OUT As increases in proportion, the voltage at node B increases. Figure 1 As shown in , node B is coupled to the source of NMOS transistor 152. The voltage at node B can therefore be limited to a maximum of VDD minus the gate-to-source voltage of NMOS transistor 152.

[0042] Figure 4 shows the output current I according to an example embodiment of the present disclosure. OUT The bias voltage at the node B and the bias current I of the PSRR boost circuit 150 change accordingly. biaspsrr Graph 401 shows VDD set to an example voltage of 1.8V. Graph 402 shows the voltage at node B of the PSRR boost circuit 150, as shown in FIG. Figure 1 As shown in FIG, the node B is coupled to the source of the NMOS transistor 152. A graph 403 shows the bias current I of the PSRR boost circuit 150. biaspsrr I biaspsrr Can be compared with the output current I OUT increases proportionally until the output current I OUT Reaching threshold I THOUT Until. THOUT In this case, the voltage at node B can be clamped to a maximum value equal to VDD minus the gate-to-source voltage of NMOS transistor 152. OUT Higher than I THOUT When the bias current I biaspsrr can also be clamped to a constant or nearly constant value.

[0043] When the output current I OUT Less than I THOUT When the bias current I biaspsrr It can be expressed as:

[0044] I biaspsrr =I OUT / N

[0045] Where N is the ratio of the size of the PMOS transistor 124 in the second stage 120 to the size of the PMOS transistor 153 in the PSRR boost circuit 150. OUT Greater than I THOUT When the bias current I biaspsrr It can be expressed as:

[0046] I biaspsrr =(VDD–Vgs 152 )*gm 151

[0047] where Vgs 152 is the gate-to-source voltage of NMOS transistor 152, and gm 151 is the transconductance of NMOS transistor 151.

[0048] The bias current I biaspsrr may be set using a number of design parameters at which the output current threshold I THOUT is clamped. For example, the ratio of the size of PMOS transistor 124 in the second stage 120 to the size of PMOS transistor 153 in the PSRR boost circuit 150 determines the ratio of I biaspsrr to the output current I OUT . As another example, the VDD voltage applied to the gate of NMOS transistor 152 can be increased or decreased to increase or decrease the voltage level at which node B is clamped, and thus the current level of the bias current I biaspsrr . Although Figure 1 the gate of NMOS transistor 152 is shown as being coupled to VDD, the gate of NMOS transistor 152 can also be coupled to any other voltage source suitable for setting the bias voltage at which NMOS transistor 152 clamps node B, and thus the voltage of the bias current I biaspsrr . As a further example, the size of NMOS transistor 152 can be selected to determine the gate-to-source voltage of NMOS transistor 152 at a given current, and the size of NMOS transistor 151 can be selected to determine the transconductance (gm 151 ) of NMOS transistor 151.

[0049] In some implementations, the PSRR boost circuit 150 can improve the PSRR of a regulator, such as the LDO regulator 100, while also preventing low and high peaks during large transients, such as a large step in the VCC voltage or a large change in the output current I OUT drawn by the load 140.

[0050] For example, as described above with reference to Figure 2 , the PSRR boost circuit 150 can be configured such that the diode 161 is held in a reverse-biased or zero-biased region of operation. In such operating conditions, the diode 161 can act as a varactor or varicap, whose capacitance can vary with the bias voltage across the diode 161.

[0051] Figure 5 A plot showing the capacitance of a varicap as a function of the bias voltage applied across the varicap, such as the diode 161, is shown in accordance with example implementations of the disclosure. The plot 501 shows that the capacitance of an example implementation of the diode 161 decreases from, for example, about 1.8 pF to about 1.0 pF as the bias voltage from the cathode to the anode of the diode 161 is increased from 0 V to 3 V.

[0052] Because the capacitance of diode 161 decreases as the bias voltage from the cathode to the anode of diode 161 increases, capacitive element 160 provides a weaker capacitive coupling between node B of PSRR boost circuit 150 and node A of first stage 110 as the bias voltage at node B increases relative to the bias voltage at node A. Thus, the amount of compensation provided by PSRR boost circuit 150 in response to large transient steps, such as large steps in the VCC voltage provided to LDO regulator 100 or large steps in the output current I OUT drawn by load 140, can be limited. When LDO regulator 100 experiences a transient step in the VCC voltage of, for example, 5 V, 10 V, 20 V, or more, PSRR boost circuit 150 can improve the PSRR of LDO regulator 100 accordingly without overcompensating. When LDO regulator 100 experiences a transient step in the output current I OUT drawn by load 140 of, for example, 10 mA, 100 mA, or more, PSRR boost circuit 150 can likewise improve the PSRR of LDO regulator 100 without overcompensating.

[0053] Figure 6 Operations of an example method 600 for enhancing power supply ripple rejection of a regulator circuit according to example implementations of the disclosure are shown. Method 600 can be performed by any suitable mechanism, such as first stage 110, second stage 120, and PSRR boost circuit 150 of LDO regulator 100, or any suitable combination thereof. Method 600 can be performed with fewer or more steps than shown in Figure 6 . Moreover, steps of method 600 can be omitted, repeated, performed in parallel, performed in a different order than shown in Figure 6 , or recursively performed. One or more steps of method 600, although shown in order, can be performed at the same time or in a reordered manner.

[0054] At step 602, a regulated output voltage can be provided at an output of a regulator circuit. For example, LDO regulator 100 can provide regulated output voltage V OUT at output 130.

[0055] At step 604, a bias current can be generated based on an output current of the regulator circuit. For example, PSRR boost circuit 150 can include PMOS transistor 153, which can generate bias current I OUT proportional to output current I biaspsrr . In some implementations, PMOS transistor 153 can mirror the drive current of PMOS transistor 124 to provide output current I OUTThe driving current through the PMOS transistor 123 is mirrored in the same manner. The PMOS transistor 153 can therefore also be referred to as mirroring the output current I OUT Mirroring.

[0056] At step 606, the bias current may be converted to a bias voltage at the bias voltage node. For example, the NMOS transistor 151 of the PSRR boost circuit 150 may be configured to receive the bias current I biaspsrr The NMOS transistor 151 can be configured as a diode-connected MOSFET with its drain coupled to its gate. The NMOS transistor 151 can thus function as a current-to-voltage converter based on the bias current I biaspsrr Instead, a bias voltage is generated at a bias voltage node such as node B of the PSRR boost circuit 150 .

[0057] At step 608, the bias voltage node may be capacitively coupled to an amplifier stage of the regulator circuit. Figure 1 As shown, capacitive element 160 may capacitively couple node B of PSRR boost circuit 150 to node A of first stage 110 .

[0058] At step 610, the capacitive coupling may be varied based on the bias voltage. Figure 2 As shown in FIG, node A and node B may be biased so that the diode 161 of the capacitive element 160 outputs a current I OUT The diode 161 can thus be used as a varactor diode whose capacitance varies based on the bias voltage applied across the diode 161, as shown in FIG. Figure 5 As shown in . With the output current I OUT As θ changes, the bias voltage at node B may also change, thereby causing the capacitance of diode 161 and the total capacitance of capacitive element 160 to change.

[0059] At step 612, the maximum value of the bias current may be clamped. For example, the PMOS transistor 153 may be configured to mirror the PMOS transistor 123 with the PMOS transistor 124 to generate the output current I OUT In the same way, the PMOS transistor 123 is mirrored to generate the bias current I biaspsrr Therefore, the output current I of the LDO regulator 100 can be OUT To generate the bias current I of the PSRR boost circuit 150 biaspsrr In addition, the NMOS transistor 152 may be placed between the PMOS transistor 153 and the node B of the PSRR boost circuit 150. biaspsrrin the path of the NMOS transistor 152. The gate of the NMOS transistor 152 can be coupled to VDD. The voltage at node B can thus be limited to VDD minus the maximum gate-to-source voltage of the NMOS transistor 152. Thus, the bias current I biaspsrr may increase in proportion to the output current I OUT until the output current I OUT reaches a threshold I THOUT . Above I THOUT , the voltage at node B can be clamped to equal VDD minus the maximum gate-to-source voltage of the NMOS transistor 152. When the output current I OUT is above I THOUT , the bias current I biaspsrr of the PSRR boost circuit 150 can thus likewise be clamped to a maximum value.

[0060] Although examples have been described above, modifications and changes can be suggestively made by those skilled in the art without departing from the spirit and scope of those examples. The descriptions of various implementations have been illustrated to explain the principles of the application. Based on the disclosure given above, numerous variations and modifications will become obvious to those skilled in the art. The appended claims are intended to cover all such variations and modifications.

Claims

1. A regulator circuit, comprising: First stage, second stage and boost circuit, The first stage includes a reference input and a feedback input, the feedback input being configured to receive feedback from an output of the regulator circuit; the second stage coupled to the first stage, the second stage comprising an output transistor configured to drive the output of the regulator circuit; The boost circuit includes: a first transistor, a current-to-voltage converter, and a capacitive element. The first transistor is configured to generate a bias current based on an output current of the output transistor; The current-to-voltage converter is configured to generate a bias voltage based on the bias current; The capacitive element is coupled between the current-to-voltage converter and a node of the first stage.

2. The regulator circuit of claim 1, wherein the capacitive element comprises a varactor diode.

3. The regulator circuit of claim 2, wherein the capacitive element further comprises a capacitor coupled in series with the varactor diode. 4 . The regulator circuit according to claim 1 , wherein the boost circuit comprises a clamp circuit configured to limit a maximum value of the bias current.

5. The regulator circuit of claim 1 , wherein: The first stage is configured to be powered by a first voltage supply; and The second stage and the boost circuit are configured to be powered by a second voltage supply. 6 . The regulator circuit of claim 1 , wherein the output transistor of the second stage is coupled to provide an open-drain output to the output terminal of the regulator circuit. 7 . The regulator circuit of claim 1 , wherein the current-to-voltage converter of the boost circuit comprises a diode-connected transistor.

8. A low pressure dropout regulator, comprising: a first amplifier stage, a second amplifier stage and a voltage boost circuit, The first amplifier stage is configured to be powered by a first voltage supply, the first amplifier stage comprising: a reference input and a feedback input, the feedback input configured to receive feedback from an output of the low dropout regulator; The second amplifier stage is configured to be powered by a second voltage supply, the second amplifier stage comprising: a second stage input terminal and an output transistor, The second stage input terminal is coupled to the first stage output terminal; The output transistor is configured to drive the output terminal of the low dropout regulator; The boost circuit is configured to be powered by the second voltage supply, the boost circuit comprising: a first transistor, a current-to-voltage converter, and a capacitive element, The first transistor is configured to mirror an output current of the output transistor to generate a bias current; The current-to-voltage converter is configured to generate a bias voltage based on the bias current; The capacitive element is coupled between the current-to-voltage converter and a node of the first amplifier stage.

9. The low dropout regulator of claim 8, wherein the capacitive element comprises a varactor diode.

10. The low dropout regulator of claim 9, wherein the capacitive element further comprises a capacitor coupled in series with the varactor diode. 11 . The low dropout regulator according to claim 8 , wherein the boost circuit comprises a clamp circuit configured to limit a maximum value of the bias current. 12 . The low dropout regulator of claim 8 , wherein the second voltage provided by the second voltage supply is equal to or greater than the first voltage provided by the first voltage supply.

13. The low dropout regulator of claim 8, wherein the output transistor of the second amplifier stage is coupled to provide an open drain output to the output terminal of the low dropout regulator.

14. The low voltage dropout regulator of claim 8, wherein the current-to-voltage converter of the boost circuit comprises a diode-connected transistor.

15. A method for increasing power supply ripple rejection, the method comprising: providing a regulated output voltage at an output of the regulator circuit; generating a bias current based on an output current of the regulator circuit; converting the bias current into a bias voltage at a bias voltage node; as well as The bias voltage node is capacitively coupled to an amplifier stage of the regulator circuit.

16. The method of claim 15, further comprising varying the capacitive coupling based on the bias voltage.

17. The method of claim 15, further comprising clamping the bias current to a maximum value.

18. The method of claim 15, wherein clamping the bias current comprises limiting the bias voltage based on at least a voltage level of a first voltage supply and a gate-to-source voltage of a clamping transistor.

19. The method of claim 15, wherein generating the bias current comprises mirroring the output current of the regulator circuit.

20. The method of claim 15, wherein converting the bias current to the bias voltage at a bias voltage node comprises receiving the bias current at a diode-connected metal oxide semiconductor field effect transistor.

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