High-side power transistor drive circuit and method for a 4:1 switched capacitor voltage converter

Abstract

The application discloses a high-side power tube driving circuit and method applied to a 4:1 switched capacitor voltage converter. The internal node voltage of the switched capacitor voltage converter with an input-output voltage conversion ratio of 4:1 is utilized to change in the switching action process, three bootstrap capacitors and two power sources VIN and REGN are used to drive four high-side power tubes in the voltage converter by controlling the switching sequence, and the source following structure is avoided, so that the chip cost area can be saved, the power consumption is reduced, and the chip conversion efficiency is improved on the basis of ensuring high reliability.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of switched capacitor voltage converters, and relates to a high-side power tube driving circuit and method applied to a 4:1 switched capacitor voltage converter. BACKGROUND

[0002] The switched capacitor architecture voltage converter is a typical inductiveless converter, which combines a capacitor and a certain number of power switches to realize the charging and discharging of the capacitor through the control of the power switches. Due to its small size, integration, high power density and other advantages, it is widely used in high-efficiency voltage conversion and charging applications.

[0003] For a switched capacitor voltage converter with a conversion ratio of 4:1, the topology generally consists of three capacitors and eight power switches, and the driving control mode and power supply of the power tubes need to be carefully designed and considered, so as to minimize the design difficulty and chip cost while ensuring the reliability of the chip. SUMMARY

[0004] To solve the problems in the prior art, the application provides a high-side power tube driving circuit and method applied to a 4:1 switched capacitor voltage converter, which uses three bootstrap capacitors and two power supplies (VIN and REGN) to drive four high-side power tubes by reasonably controlling the switching timing, and avoids using a source following structure, thereby saving chip cost area, reducing power consumption, and improving chip conversion efficiency on the basis of ensuring high reliability.

[0005] To achieve the above-mentioned target, the application adopts the following technical solutions:

[0006] The high-side power tube driving circuit applied to the 4:1 switched capacitor voltage converter comprises power tubes Q1-Q8 and flying capacitors Cfly1-Cfly3.

[0007] Among them, Q5-Q8 are connected in series as a high-side power tube module; Q1 and Q4 are connected in series, and Q2 and Q3 are connected in parallel after being connected in series as a low-side power tube module; the high-side power tube module and the low-side power tube module are connected in series, and the series connection node is the VOUT node; and the connection nodes between Q8 and Q7, Q7 and Q6, Q6 and Q5, Q1 and Q4, and Q2 and Q3 are nodes CT3, CT2, CT1, CB2, and CB1, respectively; Cfly1 is connected between nodes CT1 and CB1, Cfly2 is connected between nodes CT2 and CB2, and Cfly3 is connected between nodes CT3 and CB1.

[0008] The driving circuit comprises a first driving unit, a second driving unit, and a third driving unit.

[0009] Wherein, the first driving unit is connected with Q8 and Q7, and the periodic variation of the CT3 node voltage and the bootstrap capacitor C BST1 , and the power supply VIN realizes the promotion of the BST1 node voltage, and the BST1 node voltage is used for driving Q8 and Q7 in the high-side power tube module.

[0010] The second driving unit is connected with Q6, and the periodic variation of the CT1 node voltage and the bootstrap capacitor C BST2 , and the power supply REGN realizes the promotion of the CDRVH node voltage, and the CDRVH node voltage is used for driving Q5 in the high-side power tube module and providing the driving voltage Vcom for the second driving unit.

[0011] The third driving unit is connected with Q5, and the periodic variation of the CDRVL node voltage and the bootstrap capacitor C DRV , and the power supply REGN realizes the promotion of the CDRVH node voltage, and the CDRVH node voltage is used for driving Q5 in the high-side power tube module and providing the driving voltage Vcom for the second driving unit.

[0012] The application further comprises the following preferred schemes:

[0013] Preferably, the power tubes Q1-Q8 are all NMOS tubes, and the source and the drain are connected.

[0014] The source of Q8 is further connected with the drain of Q7, the source of Q7 is further connected with the drain of Q6, and the source of Q6 is further connected with the drain of Q5.

[0015] The source of Q4 is further connected with the drain of Q3, and the source of Q2 is further connected with the drain of Q1.

[0016] The source of Q4 and the source of Q3 are both grounded and connected with the negative electrode of the output power supply, and the drain of Q1 and Q2 are both connected with the source of Q5 and the positive electrode of the output power supply, and the positive electrode output voltage is voltage Vout.

[0017] Preferably, during normal periodic operation, Q1, Q3, Q5 and Q7 are switched at the same time, Q2, Q4, Q6 and Q8 are switched at the same time, and the time sequence of Q1, Q3, Q5 and Q7 and Q2, Q4, Q6 and Q8 is opposite.

[0018] During the system operation, the pressure difference between the upper and lower plates of Cfly1 capacitor is always VOUT, the pressure difference between the upper and lower plates of Cfly2 capacitor is always 2VOUT, and the pressure difference between the upper and lower plates of Cfly3 capacitor is always 3VOUT.

[0019] Preferably, the first driving unit comprises switches S1 and S2, a bootstrap capacitor C BST1 , a power supply VIN, a bootstrap capacitor C BST1 and a storage capacitor C Hold1 .

[0020] wherein one end of S1 is connected to the drain of Q8, the other end of S1 is connected to the upper plate of C BST1 , the lower plate of C BST1 is connected to the node CT3;

[0021] the connection point of S1 and the upper plate of C BST1 is the node BST1;

[0022] the node voltage of BST1 is the positive power rail of the buffer of Q8, the negative power rail of the buffer of Q8 is connected to the node CT3, the input of the buffer is controlled by the system timing, and the output is connected to the gate of Q8;

[0023] the node voltage of BST1 also provides the positive power rail for the buffer of Q7 through S2, the negative power rail of the buffer of Q7 is connected to the node CT2, the input of the buffer is controlled by the system timing, the output is connected to the gate of Q7, and a storage capacitor C Hold1 is connected between the positive and negative power rails of the buffer.

[0024] Preferably, the gate of Q7 is also connected to the negative electrode of clamping diode ZD1, and the positive electrode of ZD1 is connected to the node CT2.

[0025] Preferably, the second driving unit comprises diode D2 and bootstrap capacitor C BST1 .

[0026] wherein the positive electrode of diode D2 is connected to the driving voltage Vcom, the negative electrode is connected to the upper plate of bootstrap capacitor C BST1 , and the connection point is BST2, and the lower plate of bootstrap capacitor C BST1 is connected to the node CT1;

[0027] the node voltage of BST2 also provides the positive power rail for the buffer of Q6, the negative power rail of the buffer of Q6 is connected to the node CT1, the input of the buffer is controlled by the system timing, and the output is connected to the gate of Q6.

[0028] Preferably, the third driving unit comprises switches S3, S4, S5, diode D1, bootstrap capacitor C DRV , and power supply REGN.

[0029] wherein one end of S3 is connected to the node voltage Vout of the series connection of the high-side power tube module and the low-side power tube module, the other end is connected to one end of S4, and the connection point is the node CDRVL, the other end of S4 is connected to the ground;

[0030] the node CDRVL is connected to the lower plate of C DRV , and the upper plate of C DRVThe upper plate of the capacitor is connected with the negative electrode of D1, and the connection point is CDRVH node, and the positive electrode of D1 is connected with power supply REGN;

[0031] The CDRVH node voltage provides the positive power supply rail for the buffer of Q5 through S5, and the connection point of S5 and the positive power supply rail of the buffer of Q5 is Vcom node, the negative power supply rail of Q5 is connected with VOUT node, and the input end of the buffer is controlled by system timing, and the output end is connected with the gate of Q5.

[0032] The application of the high-side power tube driving method applied to the 4:1 switch capacitor voltage converter comprises:

[0033] The BST1 node voltage is raised through the periodic change of the CT3 node voltage, and then Q8 and Q7 are driven;

[0034] The BST2 node voltage is raised through the periodic change of the CT1 node voltage, and then Q6 is driven;

[0035] The CDRVH node voltage is raised through the periodic change of the CDRVL node voltage controlled by the switch, and the CDRVH node voltage drives Q5.

[0036] Preferably, for the power tube Q8:

[0037] When Q8 and the same timing Q2, Q4 and Q6 power tubes are turned off and the opposite timing Q1, Q3, Q5 and Q7 power tubes are turned on, the CT3 node voltage is 3VOUT, at this time, the control switch S1 is closed, VIN charges C BST1 fly3, and the BST1 node voltage is equal to VIN, that is, 4VOUT, and the voltage difference between the upper plate and the lower plate of the C BST1 fly3 is VOUT;

[0038] When Q8 is turned on, VIN charges Cfly3, and the CT3 node voltage is equal to VIN, that is, 4VOUT, at this time, the switch S1 is opened, and the BST1 node voltage is self-boosted to 5VOUT by the C BST1 fly3, so that BST1 is selected as the power supply of the gate drive of Q8, and the voltage difference between the BST1 node and the CT3 node of the power supply rail of the driving circuit during the turn-on or turn-off of Q8 is always 1VOUT;

[0039] For the power tube Q7:

[0040] When Q7 and Q1, Q3, Q5 of the same time sequence are turned on, Q2, Q4, Q6, Q8 are turned off, at this time, the voltage of the CT2 node is charged to 3VOUT by CT3, the voltage of BST1 is 4VOUT, at this time, the control switch S2 is closed, the voltage of the Q7 driving circuit power supply rail BST1 to the CT2 node is 4VOUT to 3VOUT, the voltage difference is VOUT, which ensures the normal work of the Q7 driving circuit;

[0041] When Q7 is turned off, Q8 is turned on, at this time, the voltage of the CT2 node is 2VOUT, the voltage of BST1 is known to be 5VOUT, at this time, the control switch S2 is opened to cut off the BST1 voltage, the power supply state of the Q7 driving circuit is maintained by the charge stored in the capacitor C Hold1 on the capacitor C DRV , and ZD1 ensures that the gate-source voltage of Q7 does not exceed the device withstand voltage.

[0042] Preferably, for the power tube Q5:

[0043] The control switches S3 and S4 are periodically opened to make the voltage of the CDRVL node jump between 0 and VOUT;

[0044] REGN charges the capacitor C DRV when S4 is closed, and the voltage of the CDRVH node is boosted to the sum of VOUT and REGN when S3 is closed, and D1 prevents the reverse flow from the CDRVH node to the REGN node;

[0045] The voltage of the Vcom node is maintained at the high voltage of CDRVH by the control switch S5, that is, the voltage value of the sum of VOUT and REGN;

[0046] The voltage of the Vcom node makes the voltage difference between the Vcom node and the VOUT node of the driving circuit power supply rail of Q5 always be one REGN voltage;

[0047] For the power tube Q6:

[0048] When Q6 is turned off, the voltage of the CT1 node is VOUT, the Vcom node charges the capacitor C BST2 through the diode D2, and the voltage of the BST2 node is charged to Vcom, that is, the sum of VOUT and REGN, and the voltage across the capacitor C BST2 is REGN;

[0049] When Q6 is turned on, the voltage of the CT2 node is charged to 2VOUT by the voltage of the CT1 node, at this time, the voltage of BST2 is boosted to the sum of 2VOUT and REGN;

[0050] Thus, the BST2 node voltage makes the driving circuit power rail of the Q6 transistor always have a voltage difference between the BST2 node and the CT1 node of REGN voltage, and meanwhile, the D2 is used to prevent the reverse flow to the Vcom node when the BST2 node voltage is the sum of 2VOUT and REGN.

[0051] The present application has the advantages that, compared with the prior art:

[0052] 1. The present application proposes a driving circuit for a switch capacitor converter architecture with a conversion ratio of 4:1, which utilizes the node state of the 4:1 switch capacitor architecture itself and only utilizes two power supplies (VIN and REGN) and three bootstrap capacitors to drive four power transistors by reasonably controlling the switch timing.

[0053] 2. The driving architecture proposed by the present application does not use a source following structure, which can effectively improve the chip conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a high-side power transistor driving schematic applied to a 4:1 switch capacitor voltage converter;

[0055] Figure 2 is the specific driving timing and key node voltage of the high-side power transistor of the present application;

[0056] Figure 3 is the gate node potential and timing of the four high-side power transistors Q5, Q6, Q7 and Q8 finally obtained by the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. The embodiments described in the present application are only a part of the embodiments of the present application, but not all the embodiments. Based on the spirit of the present application, other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0058] As Figure 1As shown, the embodiment 1 of the present application provides a high-side power tube driving circuit applied to a 4:1 switched capacitor voltage converter, which utilizes the changes of the internal node voltage of the switched capacitor voltage converter with an input-output voltage conversion ratio of 4:1 in the switching process, uses three bootstrap capacitors and the power supply VIN and REGN to drive four high-side power tubes in the voltage converter by controlling the switching timing, in the preferred but non-limiting embodiment of the present application, the switched capacitor converter topology with an input-output voltage conversion ratio of 4:1 includes eight power tubes Q1-Q8 and three flying capacitors Cfly1-Cfly3, and in the normal cycle operation, four power tubes Q1, Q3, Q5 and Q7 are switched simultaneously, four power tubes Q2, Q4, Q6 and Q8 are switched simultaneously, and the timing of the two groups of Q1, Q3, Q5 and Q7 and Q2, Q4, Q6 and Q8 is opposite.

[0059] During the system operation, the voltage difference between the upper and lower plates of the Cfly1 capacitor is always VOUT, the voltage difference between the upper and lower plates of the Cfly2 capacitor is always 2VOUT, and the voltage difference between the upper and lower plates of the Cfly3 capacitor is always 3VOUT.

[0060] Among them, NMOS tubes Q5-Q8 are high-side power tubes, and the driving circuit designed for the four tubes uses three bootstrap capacitors C BST1 , BST2 and C DRV .

[0061] Among them, the BST1 node and the CT3 node are respectively connected to the upper and lower plates of the C BST1 capacitor, the BST2 node and the CT1 node are respectively connected to the upper and lower plates of the C BST2 capacitor, and the CDRVH node and the CDRVL node are respectively connected to the upper and lower plates of the C DRV capacitor.

[0062] BST1 and BST2 respectively realize the voltage boosting through the periodic changes of the internal nodes CT3 and CT1, and CDRVH realizes the voltage boosting through the periodic changes of the CDRVL node voltage designed artificially.

[0063] Further preferably, the power tubes Q1-Q8 are all NMOS tubes, and the source and the drain thereof are connected;

[0064] The source of Q8 is further connected to the drain of Q7, the source of Q7 is further connected to the drain of Q6, and the source of Q6 is further connected to the drain of Q5;

[0065] The source of Q1 is further connected to the drain of Q4, and the source of Q2 is further connected to the drain of Q3.

[0066] The source of Q4 and the source of Q3 are connected to ground and connected to the output negative power supply, and the drain of Q1 and Q2 are connected to the source of Q5 and the output positive power supply, and the output voltage of the positive power supply is voltage Vout.

[0067] In normal cycle operation, Q1, Q3, Q5 and Q7 are switched at the same time, Q2, Q4, Q6 and Q8 are switched at the same time, and the timing of Q1, Q3, Q5 and Q7 is opposite to that of Q2, Q4, Q6 and Q8.

[0068] During system operation, the voltage difference between the upper plate and the lower plate of Cfly1 capacitor is always VOUT, the voltage difference between the upper plate and the lower plate of Cfly2 capacitor is always 2VOUT, and the voltage difference between the upper plate and the lower plate of Cfly3 capacitor is always 3VOUT.

[0069] Further preferably, the driving circuit comprises a first driving unit, a second driving unit and a third driving unit;

[0070] The first driving unit is connected with Q8 and Q7, and the voltage of CT3 node is periodically changed to raise the voltage of BST1 node through bootstrap capacitor C BST1 and power supply VIN, and the voltage of BST1 node is used to drive Q8 and Q7 in the high-side power tube module.

[0071] The first driving unit comprises switches S1 and S2, bootstrap capacitor C BST1 , power supply VIN, bootstrap capacitor C BST1 and storage capacitor C Hold1 .

[0072] One end of S1 is connected with the drain of Q8 and the other end of S1 is connected with the upper plate of C BST1 , and the lower plate of C BST1 is connected to node CT1.

[0073] The connection point of S1 and the upper plate of C BST1 is node BST1.

[0074] The node voltage of BST1 is the positive power supply rail of the buffer of Q8, the negative power supply rail of the buffer of Q8 is connected to CT3 node, the input of the buffer is controlled by system timing, and the output is connected to the gate of Q8.

[0075] The node voltage of BST1 also provides the positive power supply rail for the buffer of Q7 through S2, the negative power supply rail of the buffer of Q7 is connected to CT2 node, the input of the buffer is controlled by system timing, and the output is connected to the gate of Q7, and storage capacitor C Hold1 is connected between the positive and negative power supply rails of the buffer.

[0076] The gate of Q7 is also connected to the negative pole of a clamping diode ZD1, and the positive pole of ZD1 is connected to the CT2 node.

[0077] The second driving unit is connected to Q6, and based on a driving voltage Vcom, the periodic variation of the voltage of the CT1 node and the bootstrap capacitor C BST2 achieves the boosting of the voltage of the BST2 node, which is used to drive Q6 in the high-side power tube module;

[0078] The second driving unit comprises a diode D2 and a bootstrap capacitor C BST1 ;

[0079] The positive pole of D2 is connected to the driving voltage Vcom, and the negative pole is connected to the upper plate of the bootstrap capacitor C BST1 , and the connection point is BST2, and the lower plate of the bootstrap capacitor C BST1 is connected to the CT1 node.

[0080] The voltage of the BST2 node also provides a positive power rail for the buffer of Q6, and the negative power rail of the buffer of Q6 is connected to the CT1 node, the input end of the buffer is controlled by the system timing, and the output end is connected to the gate of Q6.

[0081] The third driving unit is connected to Q5, and the periodic variation of the voltage of the CDRVL node controlled by the switch and the bootstrap capacitor C DRV , and the power supply REGN achieve the boosting of the voltage of the CDRVH node, which is used to drive Q5 in the high-side power tube module and provide the driving voltage Vcom for the second driving unit.

[0082] The third driving unit comprises switches S3, S4, S5, a diode D1, a bootstrap capacitor C DRV , and a power supply REGN.

[0083] One end of S3 is connected to the voltage Vout of the series connection of the high-side power tube module and the low-side power tube module, the other end is connected to one end of S4, and the connection point is the CDRVL node, and the other end of S4 is grounded.

[0084] The CDRVL node is connected to the lower plate of C DRV , and the upper plate of C DRV is connected to the negative pole of D1, and the connection point is the CDRVH node, and the positive pole of D1 is connected to the power supply REGN.

[0085] The voltage of the CDRVH node provides a positive power rail for the buffer of Q5 through S5, and the connection point of S5 and the positive power rail of the buffer of Q5 is the Vcom node, the negative power rail of the buffer of Q5 is connected to the VOUT node, the input end of the buffer is controlled by the system timing, and the output end is connected to the gate of Q5.

[0086] The application relates to a high-side power tube driving method for a 4:1 switch capacitor voltage converter based on the above driving circuit.

[0087] The BST1 node voltage is raised through periodic variation of the CT3 node voltage, thereby driving Q8 and Q7;

[0088] The BST2 node voltage is raised through periodic variation of the CT1 node voltage, thereby driving Q6;

[0089] The CDRVL node voltage is raised through periodic variation of the switch-controlled CDRVL node voltage, and the CDRVL node voltage drives Q5.

[0090] The specific driving process is as follows:

[0091] For the power tube Q8:

[0092] When Q8 and Q2, Q4 and Q6 of the same time sequence are turned off and Q1, Q3, Q5 and Q7 of the opposite time sequence are turned on, the CT3 node voltage is 3VOUT, at this time, the system controls the switch S1 to be closed, and VIN charges the capacitor C BST1 The capacitor charges, and the BST1 node voltage is equal to VIN, that is, 4VOUT, the voltage difference between the upper and lower plates of the capacitor C BST1 is VOUT;

[0093] When Q8 is turned on, VIN charges the capacitor Cfly3, and the CT3 node voltage is equal to VIN, that is, 4VOUT, at this time, the switch S1 is opened, and the BST1 node voltage is self-boosted to 5VOUT by the capacitor C BST1 Therefore, BST1 is selected as the power supply of the Q8 gate driving circuit, so that the voltage difference of the power supply rail (BST1 to CT3) of the driving circuit during the on or off period of Q8 is always 1VOUT.

[0094] For the power tube Q7:

[0095] BST1 is used as the power supply of the Q7 driving circuit.

[0096] When Q7 and Q1, Q3 and Q5 of the same time sequence are turned on, Q2, Q4, Q6 and Q8 are turned off, at this time, the CT2 node voltage is charged to 3VOUT by CT3, and the BST1 voltage is 4VOUT, at this time, the system controls the switch S2 to be closed, the voltage of the Q7 driving circuit power supply rail (BST1 to CT2) is 4VOUT to 3VOUT, and the voltage difference is 1VOUT, which can ensure the normal work of the Q7 driving circuit;

[0097] When Q7 is off, Q8 is on, at this time, the voltage of CT2 node is 2VOUT, the voltage of BST1 is known as 5VOUT, at this time, the control switch S2 is off to cut off the voltage of BST1, the power supply state of Q7 driving circuit is maintained by the charge stored on the capacitor C Hold1 on the capacitor C DRV with the voltage of BST1 (4VOUT) in the stage of Q7 on and Q8 off. At the same time, the clamping diode ZD1 is used to ensure that the voltage of Q7 gate-source does not exceed the voltage withstanding value of the device.

[0098] For the power tube Q5:

[0099] The control switches S3 and S4 are periodically turned off to make the voltage of CDRVL node jump between 0 and VOUT.

[0100] REGN is the internal LDO output voltage of the chip, which charges the capacitor C DRV when S4 is closed, and boosts the voltage of CDRVH to VOUT+REGN when S3 is closed.

[0101] Among them, the diode D1 is used to prevent the reverse flow from the node of CDRVH to the node of REGN.

[0102] The voltage of Vcom node can be kept as the high voltage of CDRVH by the system controlled switch S5, that is, the voltage value of VOUT+REGN. The power supply of Vcom node voltage can meet the driving circuit power rail (Vcom to VOUT) voltage difference of Q5 tube which is always one REGN voltage.

[0103] For the power tube Q6:

[0104] Its driving circuit is powered by BST2.

[0105] When Q6 is off, the voltage of CT1 node is VOUT, and the voltage of Vcom node charges the capacitor C BST2 through the diode D2, and the voltage of BST2 node is charged to Vcom (VOUT+REGN), and the voltage across the capacitor C BST2 is REGN.

[0106] When Q6 is on, the voltage of CT2 node is charged to 2VOUT by the voltage of CT1 node, at this time, the voltage of BST2 is boosted to 2VOUT+REGN.

[0107] The power supply of BST2 can meet the driving circuit power rail (BST2 to CT1) voltage difference of Q6 tube which is always REGN voltage.

[0108] Among them, the diode D2 has the same effect as D1, which is used to prevent the reverse flow from the node of BST2 to the node of Vcom when the voltage is 2VOUT+REGN.

[0109] Based on the above description, the drive timing and the key node voltage of the high-side power tube of the present application are as shown in Figure 2 .

[0110] The final obtained gate node potential and timing of Q5, Q6, Q7 and Q8 are as shown in Figure 3 .

[0111] Combining Figure 2 and Figure 3 , it can be seen that when Q8 and Q7 are turned on, the voltage difference VGS between the gate and the source is VOUT, and when Q8 and Q7 are turned off, the gate node voltage is the same as the source node voltage.

[0112] When Q6 and Q5 are turned on, the voltage difference VGS between the gate and the source is REGN, and when Q6 and Q5 are turned off, the gate node voltage is the same as the source node voltage.

[0113] The beneficial effects of the present application are that, compared with the prior art:

[0114] 1. The present application proposes a drive circuit for a switch capacitor converter architecture with a conversion ratio of 4:1, which utilizes the node state of the 4:1 switch capacitor architecture itself and only utilizes two power supplies (VIN and REGN) and three bootstrap capacitors to drive four power tubes through reasonable control of the switch timing.

[0115] 2. The drive architecture proposed by the present application does not use a source following structure, which can effectively improve the chip conversion efficiency.

[0116] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application and not to limit it, although the present application has been described in detail with reference to the above examples, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered within the protection scope of the claims of the present application.

Claims

1. A high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter, wherein the 4:1 switched capacitor converter includes power transistors Q1 to Q8 and flying capacitors Cfly1 to Cfly3; in, Q5 to Q8 are connected in series to form a high-side power transistor module; Q1 and Q4 are connected in series, and Q2 and Q3 are connected in series and then in parallel to form a low-side power transistor module; the high-side power transistor module and the low-side power transistor module are connected in series, with the series node being the VOUT node; and the connection nodes between Q8 and Q7, Q7 and Q6, Q6 and Q5, Q1 and Q4, and Q2 and Q3 are nodes CT3, CT2, CT1, CB2, and CB1, respectively; Cfly1 is connected between nodes CT1 and CB1, Cfly2 is connected between nodes CT2 and CB2, and Cfly3 is connected between nodes CT3 and CB1, characterized in that: The driving circuit includes a first driving unit, a second driving unit, and a third driving unit; The first driving unit is connected to Q8 and Q7, and operates through the periodic variation of the voltage at node CT3 and the bootstrap capacitor C. BST1 The power supply VIN is used to boost the voltage at node BST1, which is then used to drive Q8 and Q7 in the high-side power transistor module. The second drive unit is connected to Q6 and, based on the drive voltage Vcom, utilizes the periodic variation of the voltage at node CT1 and the bootstrap capacitor C. BST2 To achieve the boost of the BST2 node voltage, the BST2 node voltage is used to drive Q6 in the high-side power transistor module; The third drive unit is connected to Q5, and controls the periodic variation of the CDRVL node voltage and the bootstrap capacitor C through a switch. DRV The power supply REGN boosts the CDRVH node voltage, which is used to drive Q5 in the high-side power transistor module and provides the drive voltage Vcom for the second drive unit.

2. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 1, characterized in that: The power transistors Q1 to Q8 are all NMOS transistors, and their source and drain are connected. The source of Q8 is also connected to the drain of Q7, the source of Q7 is also connected to the drain of Q6, and the source of Q6 is also connected to the drain of Q5. The source of Q1 is also connected to the drain of Q4, and the source of Q2 is also connected to the drain of Q3. The sources of Q4 and Q3 are both grounded and connected to the negative terminal of the output power supply. The drains of Q1 and Q2 are both connected to the source of Q5 and the positive terminal of the output power supply. The output voltage of the positive terminal is voltage Vout.

3. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 2, characterized in that: During normal operation, power transistors Q1, Q3, Q5, and Q7 switch on and off simultaneously, as do power transistors Q2, Q4, Q6, and Q8. The timing sequence of Q1, Q3, Q5, and Q7 is reversed compared to that of Q2, Q4, Q6, and Q8. During system operation, the voltage difference between the upper and lower plates of capacitor Cfly1 is always VOUT, the voltage difference between the upper and lower plates of capacitor Cfly2 is always 2VOUT, and the voltage difference between the upper and lower plates of capacitor Cfly3 is always 3VOUT.

4. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 3, characterized in that: The first driving unit includes switches S1 and S2, and a bootstrap capacitor C. BST1 Power supply VIN, bootstrap capacitor C BST1 and storage capacitor C Hold1 ; One end of S1 is connected to the drain of Q8 via the power supply VIN, and the other end of S1 is connected to C. BST1 The upper electrode plate, C BST1 The lower electrode plate is connected to node CT3; S1 and C BST1 The connection point of the upper electrode plate is node BST1; The node voltage of BST1 is the positive power rail of the Q8 buffer, and the negative power rail of the Q8 buffer is connected to the CT3 node. The input of the buffer is controlled by the system timing, and the output is connected to the gate of Q8. The node voltage of BST1 also provides a positive power rail for the Q7 buffer via S2. The negative power rail of the Q7 buffer is connected to the CT2 node. The input of this buffer is controlled by system timing, and its output is connected to the gate of Q7. A storage capacitor C is connected between the positive and negative power rails of this buffer. Hold1 .

5. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 4, characterized in that: The gate of Q7 is also connected to the negative terminal of clamping diode ZD1, and the positive terminal of ZD1 is connected to node CT2.

6. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 4, characterized in that: The second driving unit includes a diode D2 and a bootstrap capacitor C. BST1 ; In this circuit, the positive terminal of diode D2 is connected to the driving voltage Vcom, and the negative terminal is connected to the bootstrap capacitor C. BST1 The upper plate, with connection point BST2, and bootstrap capacitor C BST1 The lower electrode plate is connected to node CT1; The BST2 node voltage also provides a positive power rail for the Q6 buffer. The negative power rail of the Q6 buffer is connected to the CT1 node. The input of the buffer is controlled by the system timing, and the output is connected to the gate of Q6.

7. The high-side power transistor drive circuit for a 4:1 switched capacitor voltage converter according to claim 6, characterized in that: The third driving unit includes switches S3, S4, and S5, diode D1, and bootstrap capacitor C. DRV Power supply REGN; Among them, one end of S3 is connected to the series node voltage Vout of the high-side power transistor module and the low-side power transistor module, and the other end is connected to one end of S4, and the connection point is the CDRVL node. The other end of S4 is grounded. CDRVL node connection C DRV The lower electrode plate, C DRV The upper plate of D1 is connected to the negative terminal of D1, and the connection point is the CDRVH node. The positive terminal of D1 is connected to the power supply REGN. The CDRVH node voltage provides a positive power rail for the Q5 buffer through S5, and the connection point between S5 and the positive power rail of the Q5 buffer is the Vcom node. The negative power rail of the Q5 buffer is connected to the VOUT node. The input of the buffer is controlled by the system timing, and the output is connected to the gate of Q5.

8. A method for driving the high-side power transistor of a 4:1 switched capacitor voltage converter based on the driving circuit described in claim 7, characterized in that: The voltage of the BST1 node is increased by the periodic variation of the CT3 node voltage, thereby driving Q8 and Q7. The voltage of the BST2 node is increased by the periodic variation of the CT1 node voltage, thereby driving Q6; The CDRVH node voltage is boosted by periodic variations in the CDRVL node voltage controlled by a switch, and the CDRVH node voltage drives Q5.

9. The high-side power transistor driving method for a 4:1 switched capacitor voltage converter according to claim 8, characterized in that: For power transistor Q8: When power transistors Q8 and Q2, Q4, and Q6 (with the same timing) are off, while power transistors Q1, Q3, Q5, and Q7 (with the opposite timing) are on, the voltage at node CT3 is 3VOUT. At this time, control switch S1 closes, and VIN supplies power to C. BST1 Charging, the voltage at node BST1 equals VIN and 4VOUT, C BST1 The voltage difference between the upper and lower plates of the capacitor is VOUT; When Q8 is turned on, VIN charges Cfly3, and the voltage at node CT3 equals VIN, i.e., 4VOUT. At this time, switch S1 is open, and the voltage at node BST1 is charged by C. BST1 The capacitor bootstraps to 5VOUT, thereby selecting BST1 as the power supply for the Q8 gate drive, ensuring that the voltage difference between the power supply rail BST1 node and CT3 node of the drive circuit is always 1VOUT during the Q8 turn-on or turn-off period. For power transistor Q7: When Q7 and its sequentially connected transistors Q1, Q3, and Q5 are turned on, Q2, Q4, Q6, and Q8 are turned off. At this time, the voltage at node CT2 is charged to 3VOUT by CT3, and the voltage at BST1 is 4VOUT. At this time, control switch S2 is closed, and the voltage from power rail BST1 to node CT2 of the Q7 drive circuit is from 4VOUT to 3VOUT, with a voltage difference of VOUT, ensuring the normal operation of the Q7 drive circuit. When Q7 is off, Q8 is on. At this time, the voltage at node CT2 is 2VOUT, and the voltage at BST1 is known to be 5VOUT. Control switch S2 then opens, cutting off the BST1 voltage. The power supply state of the Q7 drive circuit is determined by the BST1 voltage during the Q7 on / off phase (4VOUT), stored in capacitor C. Hold1 The charge on the device is maintained, while ZD1 ensures that the gate-source voltage of Q7 does not exceed the device's withstand voltage.

10. The method for driving the high-side power transistor in a 4:1 switched capacitor voltage converter according to claim 8, characterized in that: For power transistor Q5: Control switches S3 and S4 are periodically opened and closed, causing the voltage at the CDRVL node to fluctuate between 0 and VOUT; REGN affects capacitor C when S4 is closed. DRV During charging, when S3 is closed, the voltage of the CDRVH node is bootstrapped to the sum of VOUT and REGN, while D1 prevents backflow from the CDRVH node to the REGN node. The voltage at the Vcom node is maintained at a high level of CDRVH by controlling switch S5, which is the sum of the voltage values ​​of VOUT and REGN. The voltage difference between the Vcom node and the VOUT node of the power rail of the Q5 transistor drive circuit is always equal to one REGN voltage by utilizing the Vcom node voltage. For power transistor Q6: When Q6 is off, the voltage at node CT1 is VOUT, and the voltage at node Vcom is supplied to capacitor C through diode D2. BST2 During charging, the BST2 node voltage is charged to Vcom, which is the sum of VOUT and REGN, and the capacitor C... BST2 The voltage across the terminals is REGN; When Q6 is turned on, the voltage at node CT2 is charged to 2VOUT by the voltage at node CT1. At this time, the voltage at BST2 is bootstrapping to the sum of 2VOUT and REGN. Therefore, the voltage at node BST2 ensures that the voltage difference between node BST2 and node CT1 of the power rail of the Q6 transistor's drive circuit is always the REGN voltage. At the same time, D2 is used to prevent backflow to node Vcom when the voltage at node BST2 is the sum of 2VOUT and REGN.

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