Chip, power supply state control method and equipment

Abstract

The embodiment of the invention provides a chip, a power state control method and equipment. The chip comprises a plurality of control units, a plurality of sensing units and a plurality of power domains, wherein each control unit is connected with at least one sensing unit, and the sensing units connected with the same control unit are connected with at least one function module in the same power domain. The sensing unit can be used for determining the power supply state required by the function module according to the state indication information of the function module, and sending a power supply state jump request to the control unit. And the control unit can be used for determining a target power state required by the corresponding power domain according to the power state jump request of each sensing unit, and sending a target control request to the PMIC to trigger the PMIC to control the power state of the power domain. Through the chip, independent control of each power domain can be realized under the condition that the response speed and the power consumption overhead are not influenced, the control granularity is finer, and the control precision is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular, to a chip, a power state control method and equipment. BACKGROUND

[0002] A multi-core processor includes multiple power domains, and power states of different power domains can be controlled respectively during running of the multi-core processor. However, the current power state control scheme for the power domains has problems such as large power consumption overhead, slow response speed, and coarse control granularity. SUMMARY

[0003] Therefore, embodiments of the present application provide a chip, a power state control method and equipment to at least partially solve the above problems.

[0004] According to a first aspect of embodiments of the present application, a chip is provided, including: multiple control units, multiple sensing units and multiple power domains; wherein each control unit is connected with at least one sensing unit, and the sensing units connected with the same control unit are all connected with at least one functional module in the same power domain. The sensing unit is configured to determine a required power state of the connected functional module according to state indication information of the connected functional module. In addition, the sensing unit is further configured to send a power state jump request to the connected control unit according to the required power state of the connected functional module. The control unit is configured to determine a target power state required by the power domain corresponding to each sensing unit connected according to the power state jump request sent by each sensing unit connected. In addition, the control unit is further configured to send a target control request to an off-chip power management chip PMIC according to the target power state required by the power domain corresponding to each sensing unit connected, and the target control request is used for the off-chip power management chip to control the power state of the power domain.

[0005] According to a second aspect of embodiments of the present application, a power state control method is provided, applied to the chip as described in the first aspect, and the method includes: determining, by the sensing unit, a required power state of the currently connected functional module according to state indication information of the currently connected functional module; In addition, the sensing unit is further configured to send a power state jump request to the connected control unit according to the required power state of the connected functional module. determining, by the control unit, a target power state required by the power domain corresponding to each sensing unit connected according to the power state jump request sent by each sensing unit connected. and sending, by the control unit, a target control request to an off-chip power management chip PMIC according to a target power state required by each power domain corresponding to the connected perception unit, the target control request being used for the off-chip power management chip to control the power state of the power domain.

[0006] According to a third aspect of the embodiments of the present application, an electronic device is provided, and the electronic device comprises the chip according to the first aspect, and the chip is used to execute the method according to the second aspect.

[0007] According to a fourth aspect of the embodiments of the present application, a computer storage medium is provided, and the computer storage medium stores a computer program, and the computer program is executed by a processor to implement the method according to the second aspect.

[0008] Through the technical solutions of the embodiments of the present application, the load conditions of different power domains can be automatically perceived based on a hardware manner, and the power state switching can be automatically initiated based on the hardware manner, without the need to query or configure a register through a software manner, so that the system response time is shortened. Moreover, the above solutions can realize independent control of each power domain without excessively affecting the response speed and power consumption overhead, so that the control granularity is more fine, and the control precision is improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0010] Figure 1 A structural schematic diagram of a power domain in a multi-core processor is provided for the embodiments of the present application. Figure 2 A structural schematic diagram of a chip is provided for the embodiments of the present application. Figure 3 A structural schematic diagram of a perception unit is provided for the embodiments of the present application. Figure 4 Another structural schematic diagram of a chip is provided for the embodiments of the present application. Figure 5 A flowchart of a power state control method is provided for the embodiments of the present application. Figure 6 A structural schematic diagram of an electronic device is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0011] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the technical solutions of the embodiments of the present application. It will be apparent, however, to one of ordinary skill, that embodiments of the present application can be practiced without these specific details. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure the embodiments of the present application.

[0012] The term used in the embodiments of the present application is merely for the purpose of describing particular embodiments and is not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are intended to include both singular and plural forms, unless the context clearly indicates otherwise.

[0013] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0014] It should also be noted that the terms "first", "second", "third" in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0015] In addition, the term "and / or" in the embodiments of the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects have an "or" relationship.

[0016] In order to facilitate the understanding of the technical solutions of the embodiments of the present application, the related technologies of the embodiments of the present application are described as follows. The following related technologies can be combined with the technical solutions of the embodiments of the present application in any way, and all belong to the protection scope of the embodiments of the present application.

[0017] The chip based on the multi-core processor includes a plurality of processing units, each processing unit can include an independent processor and a plurality of specific function execution modules. The chip based on the multi-core processor can include a plurality of power domains, Figure 1 An example of dividing the power domain of the multi-core processor is given, such as Figure 1As shown in the figure, a multi-core processor may include multiple independent power domains, such as power domain 1, power domain 2, power domain 3, and an always-on power domain. The power states of each power domain are independent of each other, thereby reducing the power consumption of the multi-core processor and improving the performance of the multi-core processor.

[0018] During the operation of a multi-core processor, the performance and load of each functional module in the multi-core processor (including the processor in any processing unit and each functional execution module) can be monitored, and based on the performance and load of each functional module, the power status of each power domain in the multi-core processor can be dynamically adjusted to achieve dynamic power consumption control of each power domain, thereby adapting to the power supply requirements of different functional modules in the multi-core processor.

[0019] A common technical solution is to query the operating status of each functional module through software to achieve power state control for different power domains. However, this solution requires frequent software queries and register configuration, which consumes a lot of power and has a slow response speed. In addition, because software-based power state control and power-down operations require a long software configuration time and slow response speed, it can usually only control multiple power domains uniformly, resulting in coarse control granularity.

[0020] In order to solve the above problems, this application is proposed.

[0021] In an embodiment of the present application, a chip based on a multi-core processor, which may be a system-on-chip (SoC), is provided. The chip is capable of responding to load changes in each functional module within each power domain through hardware, thereby dynamically changing the power state of each power domain within the chip and achieving independent control of each power domain. The method provided in an embodiment of the present application avoids the power consumption overhead caused by redundant software query register configuration and solves the problems of slow response speed and coarse control granularity of power state control in power domains in related technologies.

[0022] The chip provided in the embodiment of the present application and the functional implementation of the chip are described in detail below in conjunction with the relevant drawings.

[0023] Figure 2 This is a schematic diagram of the structure of the chip provided in this application. Figure 2 As shown, the chip provided in the embodiment of the present application may include multiple control units, multiple sensing units, and multiple power domains. Each control unit is connected to at least one sensing unit, and the at least one sensing unit connected to each control unit is respectively connected to at least one functional module in the same power domain. It should be noted that the functional module connected to the sensing unit can be the processor itself or a specific function execution module.

[0024] A chip based on the structure as shown in Figure 2 The perception unit can be configured to receive the state indication information sent by each function module currently connected, and determine the power state required by each function module currently connected according to the received state indication information. In one possible implementation, the number of function modules connected to each perception unit is one, and then one perception unit can acquire the state indication information sent by a specific function module to determine the power state required by the function module. In another possible implementation, the number of function modules connected to each perception unit is multiple, and then one perception unit can simultaneously acquire the state indication information of multiple function modules and determine the power state required by each function module.

[0025] The state indication information can include work state indication information and load state indication information. The work state indication information can be used to describe the work state of the corresponding function module, and can include, for example, idle state indication information and active state indication information. The idle state indication information can be used to indicate that the function module enters an idle state, and the active state indication information can be used to indicate that the function module enters an active state. The load state indication information can be used to describe the load condition of the corresponding function module, and can include, for example, at least one instruction retirement count information, such as a floating-point instruction retirement counter or a memory access instruction retirement counter. The more instruction retirements, the more instructions executed by the function module in a specific period, and the greater the load of the function module in the specific period.

[0026] Based on the above state indication information, on the one hand, the perception unit can be configured to predict the work state of the function module currently connected according to the work state indication information of the function module currently connected. Specifically, the perception unit can determine the idle state duration of the function module currently connected according to the idle state indication information and the active state indication information output by the function module currently connected. For example, the perception unit can determine the idle state duration according to the interval between the received idle state indication information and the subsequent adjacent active state indication information. Then, the perception unit can predict the work state of the function module currently connected according to the idle state duration of the function module currently connected. For example, the longer the idle state duration of the function module currently connected, the more likely the work state of the function module in the next period is idle. The shorter the idle state duration of the function module currently connected, the more likely the work state of the function module in the next period is active.

[0027] In another aspect, the perception unit can be configured to predict the load state of the currently connected function module according to the load state indication information of the currently connected function module. Specifically, the perception unit can determine the load index of the currently connected function module according to at least one instruction retirement count information output by the currently connected function module according to a target algorithm. Illustratively, the perception unit can perform linear weighting calculation on each instruction retirement count information to obtain a weighted value of each count result, which can be used as the load index. Further, the perception unit can predict the load state of the currently connected function module according to the load index of the currently connected function module. Illustratively, the obtained load index can be compared with a preset threshold value. When the load index is greater than the set threshold value, it is predicted that the load level of the function module in the next period is high, otherwise, when the load index is less than the set threshold value, it is predicted that the load level of the function module in the next period is low.

[0028] Further, the perception unit can determine the power state required by the currently connected function module according to the predicted working state and load state of the function module, and send a power state jump request to the connected control unit according to the power state.

[0029] Specifically, in the embodiments of the present application, a plurality of power states can be defined in advance for the current power domain. Illustratively, the plurality of power states can include normal working voltage level, clock off, memory sleep (Memory Sleep), memory power-off (Memory Power-Off), power switch (Power Switch) off, off-chip power management chip (Power Management IC, PMIC) off, etc. Among them, the power switch (Power Switch) off refers to cutting off the power supply of a specific function module in the power domain through the on-chip power switch, which belongs to the chip internal power management. The PMIC off refers to turning off the power supply of a certain specific power domain as a whole through the external PMIC, which belongs to the system-level power management and needs the cooperation of the chip and the external PMIC.

[0030] The different working states and load states of the functional module can correspond to different power states in advance. Then, the sensing unit can determine the matching power state according to the predicted working state and load state, that is, the power state required by the functional module in the next period. For example, when it is determined based on the foregoing method that the load index is less than the set threshold and the duration of the idle state exceeds the set threshold, it is predicted that the load level of the functional module in the next period is low and the working state is the idle state. Then, according to the preset mapping relationship between different working states and load states and different power states, the current matching power state is determined as: low working voltage gear, clock off, memory sleep, power off, including memory power off, power switch off and off-chip power management chip off. Thus, the low-power state is entered. Further, the sensing unit can generate a corresponding power state jump request and send it to the control unit, so that the control unit executes the subsequent process according to the power state jump request and finally realizes the switching of the power state of the functional module.

[0031] Figure 3 A structural diagram of a sensing unit provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the sensing unit can include a first sensing unit, a second sensing unit and an output unit. The first sensing unit can be a working state estimation module, which can be used to realize the functions of predicting the working state of the functional module according to the working state indication information of the functional module. The second sensing unit can be a load state estimation module, which can be used to realize the functions of predicting the load state according to the load state indication information of the functional module. The output unit can be used to realize the functions of determining the power state required by the functional module according to the working state and the load state, and sending a power state jump request to the control unit according to the power state. Figure 3

[0032] Further, as shown in FIG. 2, the sensing unit can further include a wake-up module, which can be used to wake up the corresponding functional module in response to receiving an interrupt wake-up signal. The interrupt wake-up signal can come from a related functional module inside the chip, or from a related functional module outside the chip. When it comes from a related functional module outside the chip, the external module can send an interrupt wake-up signal to the wake-up module in the sensing unit based on an external interface. Figure 3 Based on the chip with the structure shown in FIG. 2, further, the control unit can be used to determine the target power state required by the power domain corresponding to each sensing unit connected according to the power state jump request sent by each sensing unit connected.

[0033] Figure 2

[0034] ​​​In the embodiments of the present application, the perception units connected to each control unit are connected to the functional modules in the same power domain. Then, for any control unit, the target power state required by the corresponding power domain can be determined according to the power states indicated by the power state jump requests received from each perception unit. For example, the control unit can determine the power states required by the functional modules connected to each perception unit according to the power state jump requests sent by each perception unit, and then, according to a preset arbitration principle, arbitrate the power states required by each functional module to determine the target power state required by the power domain in which each functional module is located. The preset arbitration principle may, for example, be to take the power state with lower power consumption from the power states required by each functional module as the target power state. Alternatively, other possible arbitration principles may also be followed, such as taking the power state that makes the chip performance best as the target power state, and the embodiments of the present application do not limit this.

[0035] In addition, the control unit is also configured to send a target control request to the PMIC according to the target power state required by the power domain corresponding to each connected perception unit, and the target control request is used to control the power state of the power domain by the PMIC.

[0036] Specifically, the control unit can be configured to generate a target control signal according to the target power state required by the power domain corresponding to each connected perception unit, and the target control signal can be a control signal inside the chip, for example, can include a power signal, a clock signal, and a reset signal, etc. In addition, the control unit can also be configured to generate a target control request according to the target control signal and send the target control request to the PMIC. The target control request can be an instruction that the PMIC can understand, and the target control request can be used to instruct the PMIC to perform a corresponding power state control operation on the power domain to switch the power state of the power domain to the target power state.

[0037] In another possible implementation of the embodiment of the present application, the control unit may include a first control unit and a second control unit. The first control unit may be a power state control unit, which may be used to implement the above-mentioned related functions of determining the target power state required by the corresponding power domain based on the power state jump request sent by each connected sensing unit, and may also be used to implement the above-mentioned related functions of generating the target control signal according to the target power state required by the corresponding power domain. The second control unit may be a PMIC control unit, which may be used to implement the above-mentioned related functions of generating the target control request according to the target control signal and sending the target control request to the PMIC. In response to the target control signal sent by the first control unit, the second control unit may automatically trigger the sending of the target control request to the PMIC in accordance with the format of the PMIC protocol without software intervention, so that the PMIC controls the power state of the power domain.

[0038] The chip provided in the embodiments of the present application can automatically sense the load conditions of different power domains and automatically initiate power state switching based on hardware, without requiring software to query or configure registers. This shortens system response time. Furthermore, the above solution enables independent control of each power domain without excessively affecting response speed and power consumption, resulting in finer control granularity and improved control accuracy.

[0039] Figure 4 Another structural diagram of the chip provided in the embodiment of the present application. Figure 4 As shown, the chip may include multiple power domains, and the multiple power domains may include a normally-on power domain. The normally-on power domain refers to a power domain that always remains powered on. The normally-on power domain may include a PMIC control unit, a power state control unit, and a sensing unit provided in the embodiment of the present application. Among them, each power state control unit may be connected to a PMIC control unit, and the PMIC control unit may be connected to an external PMIC. In addition, each power state control unit may also have multiple sensing units, and each sensing unit connected to each power control unit may be connected to different functional modules under the same power domain.

[0040] Understandably, Figure 4 In the chip with the structure shown, the sensing unit corresponds to the functional unit one-to-one, and the power state control unit corresponds to the power domain one-to-one. Figure 4 In the chip with the structure shown, the sensing chip can dynamically monitor the load status of the power domain at the granularity of the functional module, which is more flexible. In addition, the power status control unit can trigger independent control of the power status of each power domain at the granularity of the power domain, which has a smaller control granularity.

[0041] Based onFigure 4 In the chip shown in the structure, in the embodiment of the present application, each sensing unit can be used to obtain the state indication information of the specific function module connected, and determine the power state required by each function module in the subsequent period according to the obtained state indication information. Then, according to the required power state, the power state jump request can be sent to the power state control unit. The specific function implementation mode can refer to the foregoing embodiment, which will not be described here.

[0042] Then, for any power state control unit, the power state required by each function module can be determined according to the power state jump request sent by each sensing unit, and then the power state required by each function module can be arbitrated according to the preset arbitration principle, and the target power state required by the corresponding power domain is determined from each predefined power state. In the embodiment of the present application, the power state supported by the power state control unit can be configured by software, for example, the power state control unit can be configured to support all power states, or the power state control unit can be configured to support part of the power states. Then, the power state control unit can send a PMIC power control request to the PMIC control unit according to the target power state obtained by arbitration, so as to trigger the PMIC control unit to send a PMIC control command to the PMIC. The PMIC control command can be used to trigger the PMIC to control the power state of the power domain, so that the corresponding power domain switches to the target power state. The specific function implementation mode can refer to the description of the foregoing embodiment, which will not be described here.

[0043] The external PMIC independent of the chip can be used to control the power state of the whole power domain, on the basis of which, in the embodiment of the present application, the power state of each function unit can also be independently controlled by the power switch (Power Switch) in each power domain. For example, after the power state control unit receives the power state jump request sent by any sensing unit, the power state of the corresponding function unit can be controlled by the power switch (Power Switch) in the corresponding power domain. In this way, smaller granularity power state control can be achieved.

[0044] In another implementation, the chip can also have other structures. For example, the power state control unit and the sensing unit can be connected in a one-to-one manner, i.e., one power state control unit can be connected to one sensing unit. Meanwhile, the sensing unit and the functional unit can be connected in a one-to-many manner, i.e., one sensing unit can be connected to all functional modules in the same power domain. In this way, the state indication information of the functional modules in the same power domain can be sent to the same sensing unit, and the sensing unit can determine the required power state of each functional unit and send the power state jump request corresponding to each functional unit to the power control unit. Through this implementation, the chip structure can be simplified, and the load state of different functional units in the power domain can be monitored through fewer sensing units.

[0045] In another embodiment, a power state control method is also provided, which can be applied to the chip described in the above embodiments. Figure 5 A flowchart of the power state control method provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the power state control method provided by the embodiments of the present application includes the following steps. Figure 5 In step 101, the sensing unit determines the required power state of the currently connected functional module according to the state indication information of the currently connected functional module.

[0046] In step 102, the sensing unit sends a power state jump request to the connected control unit according to the required power state of the currently connected functional module.

[0047] In step 103, the control unit determines the target power state required by the power domain corresponding to each sensing unit according to the power state jump request sent by each connected sensing unit.

[0048] In step 104, the control unit sends a target control request to the PMIC according to the target power state required by the power domain corresponding to each connected sensing unit, and the target control request is used for the PMIC to control the power state of the power domain.

[0049] In one possible implementation, the control unit includes a first control unit and a second control unit. The method includes: determining, by the first control unit, the target power state required by the power domain corresponding to each sensing unit according to the power state jump request sent by each connected sensing unit; generating, according to the target power state required by the power domain corresponding to each connected sensing unit, a target control signal, the target control signal including a power signal, a clock signal and a reset signal; and generating, by the second control unit, a target control request according to the target control signal and sending the target control request to the off-chip power management chip. ​

[0050] In a possible implementation manner, the target power state required by the power domain corresponding to each sensing unit is determined by the first control unit according to the power state jump request sent by each connected sensing unit, including: the power state required by the functional module connected to each sensing unit is determined by the first control unit according to the power state jump request sent by each connected sensing unit; and the power state required by the functional module connected to each sensing unit is arbitrated according to a preset arbitration principle to obtain the target power state required by the power domain corresponding to each sensing unit.

[0051] In a possible implementation manner, the state indication information includes working state indication information and load state indication information; the sensing unit includes a first sensing unit, a second sensing unit and an output unit; and the method includes: the working state of the currently connected functional module is predicted by the first sensing unit according to the working state indication information of the currently connected functional module; the load state of the currently connected functional module is predicted by the second sensing unit according to the load state indication information of the currently connected functional module; and the power state required by the currently connected functional module is determined by the output unit according to the working state and the load state of the currently connected functional module, and the power state jump request is sent to the connected control unit according to the power state required by the currently connected functional module.

[0052] In a possible implementation manner, the working state indication information includes idle state indication information and active state indication information; and the load state indication information includes at least one instruction retirement count information.

[0053] In a possible implementation manner, the working state of the currently connected functional module is predicted by the first sensing unit according to the working state indication information of the currently connected functional module, including: the idle state duration of the currently connected functional module is determined by the first sensing unit according to the idle state indication information and the active state indication information output by the currently connected functional module; and the working state of the currently connected functional module is predicted according to the idle state duration of the currently connected functional module.

[0054] In a possible implementation manner, the load state of the currently connected functional module is predicted by the second sensing unit according to the load state indication information of the currently connected functional module, including: the load index of the currently connected functional module is determined by the second sensing unit according to the at least one instruction retirement count information output by the currently connected functional module by using a target algorithm; the target algorithm includes a linear weighting algorithm; and the load state of the currently connected functional module is predicted according to the load index of the currently connected functional module.

[0055] In a possible implementation, the perception unit further includes a wake-up module; and the method further includes: in response to receiving the interrupt wake-up signal, the wake-up module wakes up the corresponding functional module.

[0056] Since the details of the power state control method have been described in the foregoing chip embodiment part in combination with the structural schematic diagram, the specific process can be referred to the description in the foregoing chip embodiment part, and will not be described here again.

[0057] By the power state control method provided in the embodiments of the present application, the load conditions of different power domains can be automatically perceived in a hardware manner, and the power state switching can be automatically initiated in a hardware manner, without the need of querying or configuring a register in a software manner, so that the system response time is shortened. Moreover, the foregoing scheme can realize independent control of each power domain without excessively affecting the response speed and power consumption overhead, so that the control granularity is more fine, and the control precision is improved.

[0058] Figure 6 A structural schematic diagram of an electronic device according to an embodiment of the present application is shown, the electronic device can be configured with the chip provided in the embodiments of the present application, and the chip can be used to execute the power state control method provided in the embodiments of the present application. The specific implementation of the electronic device is not limited in the embodiments of the present application.

[0059] As shown in Figure 6 , the electronic device can include a processor 502, a communications interface 504, a memory 506, and a communications bus 508.

[0060] The processor 502, the communications interface 504, and the memory 506 can complete mutual communication through the communications bus 508. The communications interface 504 is configured to communicate with other electronic devices or servers. The processor 502 is configured to execute the program 510, and specifically can execute the related steps in the foregoing power state control method embodiments.

[0061] Specifically, the program 510 can include program code, and the program code includes computer operation instructions.

[0062] The processor 502 can be a processor CPU, or an application specific integrated circuit ASIC, or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device can be the same type of processors, such as one or more CPUs; or can be different types of processors, such as one or more CPUs and one or more ASICs.

[0063] a memory 506 for storing a program 510. The memory 506 can include a high-speed RAM memory and can also include a non-volatile memory, such as at least one disk memory.

[0064] The program 510 can be specifically configured to enable the processor 502 to perform the following operations: in an optional embodiment, the program 510 is also configured to enable the processor 502 to perform the specific implementation of each step in the program 510. The specific implementation of each step in the program 510 can be referred to the corresponding description in the above-mentioned power state control method embodiments and the corresponding description in the system, which will not be described herein. It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, the specific working process of the above-mentioned devices and modules can be referred to the corresponding process description in the above-mentioned method embodiments, which will not be described herein.

[0065] The embodiments of the present application also provide a computer program product, which includes computer instructions for instructing a computing device to perform the operations corresponding to the power state control method in any of the above-mentioned method embodiments. It should be noted that, according to the implementation needs, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or part of the operations of the components / steps can be combined into a new component / step, so as to achieve the purpose of the embodiments of the present application.

[0066] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned method according to the embodiments of the present application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium such as a CDROM, RAM, floppy disk, hard disk or magneto-optical disk, or be implemented by downloading the computer code from a network and storing it in a local recording medium, so that the method described herein can be processed by such software on a recording medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware such as an ASIC or FPGA. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component (for example, RAM, ROM, flash memory, etc.) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor or hardware, the power state control method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the power state control method shown herein, the execution of the code will convert the general-purpose computer into a special-purpose computer for executing the power state control method shown herein.

[0067] Those skilled in the art can appreciate that the units and method steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0068] It should be noted that in the present application, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus including a series of elements includes not only those elements, but also other elements not explicitly listed, or other elements inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus including the element.

[0069] In addition, it should be noted that the user-related information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to sample data for training models, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0070] The above sequence numbers of the embodiments of the present application are only for description, not representing the advantages and disadvantages of the embodiments.

[0071] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0072] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0073] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0074] The above embodiments are only used for describing the present application, and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, all equivalent technical solutions belong to the scope of the present application, and the patent protection scope of the present application should be defined by the claims.

Claims

1. A chip, characterized in that: include: Multiple control units, multiple sensing units, and multiple power domains; wherein each of the control units is connected to at least one sensing unit, and the sensing units connected to the same control unit are all connected to at least one functional module in the same power domain; The sensing unit is configured to determine the power state required by the connected functional module based on the state indication information of the connected functional module; the state indication information includes working state indication information and load state indication information; Furthermore, the sensing unit is further configured to send a power state jump request to the connected control unit according to the power state required by the connected functional module; The control unit is configured to determine the target power state required by the power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit; In addition, the control unit is also used to send a target control request to the off-chip power management chip PMIC according to the target power state required by the power domain corresponding to each connected sensing unit, and the target control request is used by the off-chip power management chip to control the power state of the power domain.

2. The chip according to claim 1, characterized in that The control unit includes a first control unit and a second control unit; The first control unit is specifically configured to determine the target power state required by the power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit; and, generating a target control signal according to the target power state required by the power domain corresponding to each connected sensing unit, wherein the target control signal includes a power signal, a clock signal, and a reset signal; The second control unit is specifically configured to generate a target control request according to the target control signal, and send the target control request to the off-chip power management chip.

3. The chip according to claim 2, characterized in that The first control unit is specifically configured to: Determining the power state required by the functional modules connected to each sensing unit according to the power state jump request sent by each connected sensing unit; According to a preset arbitration principle, the power states required by the functional modules connected to the respective sensing units are arbitrated to obtain the target power states required by the power domains corresponding to the respective sensing units.

4. The chip according to claim 1, characterized in that The sensing unit includes a first sensing unit, a second sensing unit and an output unit; The first sensing unit is configured to predict the working state of the connected functional module based on the working state indication information of the connected functional module; The second sensing unit is configured to predict the load state of the connected functional module based on the load state indication information of the connected functional module; The output unit is used to determine the power state required by the connected functional module based on the working state and the load state of the connected functional module, and send a power state jump request to the connected control unit based on the power state required by the connected functional module.

5. The chip according to claim 4, characterized in that The working state indication information includes idle state indication information and active state indication information; the load state indication information includes at least one instruction retirement count information.

6. The chip according to claim 5, characterized in that The first sensing unit is specifically configured to: Determining a duration of the idle state of the connected functional module based on the idle state indication information and the active state indication information output by the connected functional module; The working state of the connected functional module is predicted according to the duration of the idle state of the connected functional module.

7. The chip according to claim 5, characterized in that The second sensing unit is specifically configured to: Determining a load index of the connected functional module using a target algorithm based on at least one instruction retirement count information output by the connected functional module; the target algorithm includes a linear weighted algorithm; According to the load index of the connected functional module, the load status of the connected functional module is predicted.

8. The chip according to claim 4, characterized in that The sensing unit further includes a wake-up module; the wake-up module is configured to wake up the corresponding functional module in response to receiving an interrupt wake-up signal.

9. A power state control method, characterized in that: Applied to the chip according to any one of claims 1 to 8; the method comprising: The sensing unit determines the power state required by the connected functional module according to the state indication information of the connected functional module; And, the sensing unit sends a power state jump request to the connected control unit according to the power state required by the connected functional module; The control unit determines the target power state required by the power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit; Furthermore, the control unit sends a target control request to the off-chip power management chip PMIC according to the target power state required by the power domain corresponding to each connected sensing unit, and the target control request is used by the off-chip power management chip to control the power state of the power domain.

10. An electronic device, characterized in that: The method comprises the chip according to any one of claims 1 to 8, wherein the chip is configured to execute the method according to claim 9.

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