Error reporting methods and electronic devices for processor platforms

Abstract

This application discloses a method and electronic device for error reporting on a processor platform, relating to the field of computer hardware technology. The method includes acquiring multiple error identifiers of the processor platform, which characterize the types of faults encountered by the platform. Based on historical data and real-time operating parameters, a predictive model is constructed. This model improves the predictive maintenance capabilities of the processor platform. Then, based on the error identifiers and the predictive model, the types of faults that the processor platform may experience in the future are determined. Therefore, this method solves the technical problem in related technologies where it is difficult to provide early warnings of potential faults in processor platforms. It achieves the technical effect of timely detection of impending faults in the processor platform, allowing for timely handling based on the prediction results, and avoiding the loss of opportunities to take preventative measures before faults occur.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to an error reporting method and electronic device for a processor platform. Background Technology

[0002] In modern data centers and high-performance computing environments, system reliability, availability, and maintainability (RAS) are crucial for ensuring business continuity and reducing operational costs. Currently, in server platforms, the BIOS (Basic Input / Output System), as the core component for hardware initialization and management, primarily relies on standard interfaces such as APEI (ACPIP Platform Error Interface) for recording and reporting error information. However, existing BIOS RAS mechanisms mainly focus on recording and reporting errors that have already occurred, with limited capabilities for in-depth analysis of historical error data and prediction of potential faults, easily missing opportunities to take preventative measures before faults occur. Summary of the Invention

[0003] This application provides a method and electronic device for error reporting on a processor platform, in order to at least solve the technical problem in the related art that processor platforms have difficulty in providing early warning of potential faults.

[0004] This application provides an error reporting method for a processor platform, comprising: acquiring multiple error identifiers of the processor platform, the error identifiers being used to characterize the fault types of the processor platform; constructing a prediction model based on historical data and real-time operating parameters, the historical data and real-time operating parameters including at least: error logs of the processor platform's basic input / output system, hardware operating parameters, and environmental monitoring data; determining the fault types that the processor platform will generate in the future based on the multiple error identifiers and the prediction model; and reporting the fault types to the processor platform and issuing an early warning.

[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the error reporting method of any of the processor platforms described above when executing the computer program.

[0006] This application's error reporting method acquires multiple error identifiers from the processor platform, encompassing the types and characteristics of errors on the platform, providing foundational data for subsequent error analysis and prediction. Based on historical data and real-time operating parameters, a predictive model is constructed. This model enhances the predictive maintenance capabilities of the processor platform. Furthermore, by using the error identifiers and the predictive model, the types of faults that the processor platform may experience in the future are determined. Therefore, this addresses the technical problem in related technologies where processor platforms struggle to provide early warnings of potential faults. It enables timely detection of impending faults on the processor platform, allowing for prompt handling based on prediction results and preventing missed opportunities to take preventative measures before faults occur. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A hardware structure block diagram of a mobile terminal for an error reporting method for a processor platform provided in an embodiment of this application is shown.

[0009] Figure 2 A flowchart illustrating an error reporting method for a processor platform provided in an embodiment of this application;

[0010] Figure 3 This is a flowchart illustrating another error reporting method for a processor platform provided in an embodiment of this application.

[0011] The above figures include the following reference numerals:

[0012] 102. Processor; 104. Memory; 106. Transmission device; 108. Input / output device. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The specific application environment architecture or specific hardware architecture on which the error reporting method of the processor platform depends is described here.

[0017] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device for an error reporting method on a processor platform according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a central processing unit (CPU), microprocessor (MCU), or programmable logic device (FPGA), etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0018] The error reporting method in this application is primarily used in environments with strict requirements for Reliability, Availability, and Serviceability (RAS), such as data center servers, high-performance computing systems, and embedded computing platforms. Specifically, its application environment architecture is as follows:

[0019] Distributed computing architecture: In large-scale server clusters, this method can coordinate the BIOS and BMC on multiple nodes to achieve cross-node fault detection and reporting, thereby improving the stability and operational efficiency of the entire cluster.

[0020] Virtualization environment: The method is applicable to virtualized data centers, can penetrate the virtualization layer, and can monitor and warn of errors in physical hardware in real time, ensuring the continuous operation of virtual machines and services.

[0021] The technical solution of this application is specifically designed for the following hardware architectures:

[0022] The BMC, integrated with the VGA controller, is crucial for efficient data exchange, acting as a hardware management controller. The BMC's VGA controller provides dedicated video memory, allowing the BIOS to directly access and write error data, significantly reducing data transfer latency.

[0023] TLS and AES-256 Encryption Hardware: To ensure data security and compliance, this method relies on hardware that supports TLS (Transport Layer Security) and AES-256 (Advanced Encryption Standard) encryption. TLS ensures data encryption during network transmission, while AES-256 is used for encryption of data stored at rest, together forming a double line of defense for data protection.

[0024] AGESA (Generic Packaged Software Architecture) microcode compatible hardware: The hardware should support the AGESA microcode for the platform server, which is a core component for processor low-level initialization and configuration. AGESA provides a software foundation tightly integrated with the processor's error detection and reporting mechanisms.

[0025] Hardware Interface Configuration: In this application, the BMC in the platform server integrates a VGA controller and has an independent video memory address space. Through the Hardware Abstraction Layer (HAL) configuration of the BIOS, the video memory address of the BMC is mapped to the system memory address space, enabling the BIOS to access it directly.

[0026] The following are some of the technical terms involved:

[0027] Reliability, Availability, and Serviceability (RAS) describes a system's ability to maintain normal operation during runtime. These three concepts form the foundational criteria for evaluating and designing high-performance, mission-critical systems. RAS emphasizes a system's ability to operate without failure for a predetermined time (reliability), its ability to continue operating or recover quickly in the event of a failure (availability), and its ability to be maintained and upgraded without requiring system shutdown (maintainability). For data center, cloud computing environments, and enterprise applications, RAS is crucial for ensuring business continuity and data integrity. Through comprehensive optimization of hardware design, firmware functionality, management software, and service strategies, RAS aims to maximize system uptime, minimize the impact of failures, support rapid repair and upgrades, and reduce unplanned and unplanned system downtime.

[0028] The Basic Input / Output System (BIOS) is the low-level firmware that runs when a computer starts up. It is responsible for tasks such as hardware self-testing, initializing peripheral devices, and loading the operating system bootloader. The BIOS acts as a bridge between the computer hardware and the operating system, ensuring that hardware devices can be correctly recognized and used by the operating system. During the boot process, the BIOS checks hardware configurations and sets system parameters, which is crucial for ensuring stable computer operation and efficient startup.

[0029] The Baseboard Management Controller (BMC) is a management chip independent of the main processor, responsible for remote monitoring and system management. It's a microprocessor embedded on the server motherboard, operating independently of the main CPU, primarily used for remote monitoring and managing system operating status. The BMC collects information through various sensors and hardware interfaces, such as temperature, voltage, and fan speed, and also supports remote server control via network. The BMC is a core component of a server's Reliability, Availability, and Serviceability (RAS) capabilities. It can monitor system health in real time, performing functions such as remote power on / off, fault warnings, and logging, thereby improving system availability and maintainability and reducing the monitoring burden on administrators.

[0030] The Machine Check Architecture (MCA) mechanism is a key machine check architecture in the processor used to detect and report hardware errors. It is primarily used to identify and log hardware failures that occur during runtime. The design goal of MCA is to collect as much detailed error information as possible when a hardware failure occurs, so that the operating system or BIOS can take appropriate corrective actions or perform fault analysis, thereby improving system reliability, availability, and maintainability (RAS).

[0031] The Boot Error Record Table (BERT) is a table in the BIOS used to record error information that occurs during the boot process. It's a data structure within the BIOS specifically designed to record errors that occur during system startup. It acts as a system log, especially during system initialization, capturing many hardware or firmware-level errors. The BERT table helps system administrators and engineers quickly diagnose problems during startup, providing early indications of hardware failures, facilitating maintenance and debugging. It typically contains information such as error code, error type, the time the error occurred, and the location of the error, making it extremely important for troubleshooting.

[0032] Transport Layer Security (TLS) is used to provide data encryption and authentication in network communications.

[0033] The embodiments of this application provide an error reporting method for a processor platform, and the method is described in detail in conjunction with the execution flow of the error reporting method for the processor platform.

[0034] According to the error reporting method for a processor platform provided in this application, such as Figure 2 As shown, it includes:

[0035] Step S1: Obtain multiple error identifiers of the processor platform. The error identifiers are used to characterize the fault type of the processor platform.

[0036] Specifically, during the operation of the processor platform, error identifiers from the MCA mechanism are continuously monitored and collected. These error identifiers not only contain the error type but also, through the MCA record register, detailed information such as the occurrence time, CPU number, memory channel number, and error address, providing foundational data for subsequent error classification and fault prediction. Error identifiers are derived from the acquired hardware error information and its type. Hardware error information includes, but is not limited to, memory errors, CPU errors, and bus errors. Error information at processor platform startup can be obtained through BERT table records. Real-time and comprehensive error identifier collection allows for timely understanding of the processor platform's health status, providing detailed data support for subsequent intelligent analysis and early warning. This improves the processor platform's response speed and the accuracy of fault detection.

[0037] Step S2: Construct a predictive model based on historical data and real-time operating parameters. The historical data and real-time operating parameters include at least: error logs of the processor platform's basic input / output system, hardware operating parameters, and environmental monitoring data.

[0038] Specifically, when building the predictive model, the error logs recorded by the BIOS are first analyzed in depth. These error logs include, but are not limited to, BERT table records and MCA error logs. Features such as error type, frequency, and impact range are extracted from the error logs. Simultaneously, hardware operating parameters are continuously monitored and provided, including but not limited to real-time operating parameters such as CPU temperature, memory voltage, and fan speed, as well as environmental monitoring data such as temperature, humidity, and power status in the data center. This multi-source data is integrated and input into the machine learning model. After training, the model can identify potential fault modes and early warning signals. The predictive model, combining historical data and real-time parameters, can accurately predict potential future hardware failures based on the current hardware status and operating environment, for example, issuing warnings 36 / 72 hours in advance. This reduces the risk of unplanned downtime and improves the availability and operational efficiency of the processor platform.

[0039] Step S3: Based on multiple error identifiers and prediction models, determine the types of faults that the processor platform will experience in the future.

[0040] Specifically, when a new hardware error occurs, a new error identifier is detected. This error identifier data is input into a pre-trained predictive model. The model analyzes this data to identify potential failure modes and outputs a prediction of the failure type for a future period (e.g., the next week), including the specific type of failure and its estimated probability of occurrence. Furthermore, some hardware operating parameters of the current processor platform can also be input into the predictive model. This allows for a comprehensive evaluation based on the current operating status of the processor platform and the predicted failures, leading to more accurate maintenance measures. By combining real-time error data with the predictive model, maintenance strategies can be dynamically adjusted, prioritizing high-risk failures, reducing failure response time, and improving the targeting and efficiency of maintenance.

[0041] Step S4: Report the fault type to the processor platform and issue a warning.

[0042] Specifically, once the predictive model identifies potential future fault types, the BIOS immediately reports this fault type information to the BMC via an optimized data exchange mechanism (based on efficient transmission of VGA controller video memory). The BMC then forwards the warning information to the server management system or notifies maintenance personnel to take preventative measures, such as automatic reboot repair or memory chip isolation.

[0043] The aforementioned error reporting method for the processor platform acquires multiple error identifiers, which encompass the types and characteristics of errors, providing foundational data for subsequent error analysis and prediction. Based on historical data and real-time operating parameters, a predictive model is constructed. This model enhances the predictive maintenance capabilities of the processor platform. Furthermore, by analyzing the error identifiers and the predictive model, the types of faults that the processor platform may experience in the near future are determined. Therefore, this approach addresses the technical challenge of providing early warnings of potential faults in related technologies. It enables timely detection of impending faults and allows for prompt intervention based on predictions, preventing missed opportunities to take preventative measures before faults occur.

[0044] In some optional implementations, the method further includes: initializing the basic input / output system; obtaining read permissions for the video memory space, and obtaining the address and capacity of the video memory space based on the read permissions; and partitioning a buffer with a preset capacity in the video memory space. By completing the video memory space configuration during the BIOS initialization phase, the efficiency of error data reporting is improved, the data interaction time between the BIOS and the BMC is reduced from the traditional 300ms to below 50ms, a reduction of 83%, and the system startup time is shortened by an average of 15%, reducing unnecessary latency.

[0045] First, the address mapping is obtained. During the BIOS initialization phase, the VGA controller information of the BMC is read through the PCI configuration space to obtain its video memory base address and size.

[0046] Configure permission settings, configure the processor platform memory-mapped register (MMR), and grant the BIOS read and write permissions to this video memory region;

[0047] Buffer allocation is performed, and a fixed-size circular buffer (e.g., 16KB) is partitioned within the BMC video memory to store erroneous data. The buffer structure is as follows:

[0048] typedef struct {

[0049] uint32_t head; / / Write pointer

[0050] uint32_t tail; / / Read pointer

[0051] uint8_t data

[16384] ; / / Data storage area

[0052] uint8_t flags; / / Status flags

[0053] BiosBmcSharedBuffer.

[0054] The PCI (Peripheral Component Interconnect) standard is a high-speed bus standard for connecting computer hardware. Originally developed by Intel, it aimed to provide faster data transfer speeds and better performance than the previous ISA bus. The advent of the PCI bus greatly promoted the standardization and compatibility of computer hardware, allowing peripherals from different manufacturers (such as graphics cards, sound cards, and network cards) to communicate with the computer motherboard through a unified interface. Each PCI device has a configuration space, a memory area used to store and retrieve the device's configuration information. The configuration space contains information such as the device's identifier, function, and status registers, which are crucial for the operating system or BIOS to initialize and configure hardware devices. During computer startup, the BIOS or operating system identifies and configures PCI devices by accessing the PCI configuration space. For example, reading the BMC's VGA controller information and obtaining its video memory base address and size are achieved by accessing specific registers in the PCI configuration space. Access to the PCI configuration space is typically accomplished through PCI configuration registers, which allow the host to read and write the PCI device's configuration information. The access process involves writing the device's bus number, device number, function number, and register offset address into the PCI Configuration Address Register, and then obtaining configuration data by reading the PCI Configuration Data Register, or updating the device status by writing new configuration values ​​into it.

[0055] In some optional implementations, obtaining multiple error identifiers of the processor platform includes: obtaining multiple error messages of the processor platform; and constructing an error structure based on the multiple error messages and a preset order.

[0056] Specifically, error detection is performed first. The processor's MCA mechanism detects a hardware error and notifies the BIOS via an interrupt. Then, data is packaged. The BIOS reads the error information from the MCA register and constructs the read error information into an error structure according to a certain preset order. The error structure is as follows:

[0057] typedef struct {

[0058] uint8_t error_type; / / MCA error type

[0059] uint8_t severity; / / Severity level

[0060] uint32_t cpu_id; / / CPU ID

[0061] uint32_t bank_id; / / Memory channel number

[0062] uint64_t error_address; / / Error address

[0063] uint32_t mca_record

[16] ; / / MCA record register value

[0064] uint64_t timestamp; / / Timestamp

[0065] uint32_t crc32; / / CRC checksum

[0066] } McaIrqData.

[0067] Upon detecting new error messages in the Basic Input / Output System (BMC), the error messages are transformed into error identifiers based on the error structure and preset format. By constructing structured error identifiers, data interaction between the BIOS and BMC is simplified, the complexity of data transmission is reduced, and the reliability and integrity of transmission are ensured. This reduces the real-time error reporting time from an average of 10 seconds to less than 1 second, an improvement of 90%.

[0068] In some optional implementations, the error information is transformed into an error identifier based on the error structure, including:

[0069] Obtain the write pointer to the processor platform's buffer; only after obtaining the write pointer can information be stored in the data storage area.

[0070] The error structure is written to the data storage area of ​​the buffer according to the write pointer, and the error data checksum CRC in the data storage area is updated according to the error structure. The data storage area is used to temporarily store the error structure; the VGA video memory space of the BMC is used as a temporary information storage intermediary between the BIOS and the BMC. Specifically, after the BIOS detects a hardware error (such as MCA error, memory error, etc.), it packages the error data according to a preset structure format, calculates the CRC checksum, and then writes it to a designated area of ​​the VGA video memory of the BMC. When it is needed to read it later, the video memory can be accessed in parallel through a dedicated hardware interface to obtain the error data, replacing the traditional IPMI serial communication method, which improves the data interaction efficiency. The single interaction time between the BIOS and the BMC is reduced from 300ms of traditional IPMI to less than 50ms, a reduction of about 83%. Due to the reduction of the interaction latency between the BIOS and the BMC, the platform boot time is shortened by an average of 15%, from 45 seconds to 38 seconds. To ensure compatibility, the platform also retains IPMI communication as a backup plan, automatically switching to IPMI mode when the video memory interaction is abnormal.

[0071] According to a preset cycle, multiple ready flags in the buffer are retrieved, and it is determined whether the ready flag is the target ready flag (READY_FLAG=1). If the ready flag is the target ready flag, the updated error data checksum in the data storage area is read. Based on the updated error data checksum, it is determined whether the data in the error structure is normal. The above CRC is the unique checksum of the error data packet. When the BIOS sends the data packet to the BMC, it will also send the CRC checksum. The BMC uses this as the verification credential to ensure that the data has not been corrupted.

[0072] If the data in the error structure is confirmed to be normal, the normal error structure is parsed according to a preset format to obtain the error identifier. The preset format is the structure of the error structure. By setting a ready flag and verifying CRC, the reliability of error reporting is significantly enhanced. Even under high load conditions, the system's fault detection accuracy can be maintained at over 90%, improving the overall stability of the system.

[0073] The aforementioned MCA mechanism monitors various potential hardware failure points at the processor core level, including but not limited to the memory system (such as the memory controller, data path, and cache), I / O subsystem, system bus, power management unit, and clock unit. When an error is detected, the MCA triggers an interrupt (Machine Check Interrupt, or MCI) and stores the error information in a set of dedicated registers called Machine Check Registers (MCR).

[0074] The MCA mechanism can report various types of errors, which are divided into two main categories: Uncorrectable Error (UCE) and Correctable Error (CE).

[0075] Uncorrectable error (UCE): This type of error usually means that the hardware component is permanently damaged and the system needs to respond immediately, such as shutting down the affected CPU core or restarting the entire system.

[0076] Correctable Errors (CE): In contrast, CE errors are usually transient and can be corrected by the hardware's own error correction capabilities, such as ECC memory error correction. Nevertheless, frequent CE errors may indicate an impending UCE error in the hardware. The error information in this application can be either of the above two error types. Targeted processing is performed based on the detected error type.

[0077] In some alternative implementations, the method further includes:

[0078] After receiving the error flag, output the acknowledgment flag (ACK_FLAG=1) to the basic input / output system.

[0079] When the basic input / output system receives an acknowledgment flag, the ready flag and confirmed flag in the processor platform's buffer are cleared.

[0080] Specifically, based on the error structure, the BIOS (BMC) parses the error data and remaps it to its internal buffer memory to obtain an error identifier. An acknowledgment flag is then output to the Basic Input / Output System (BIOS). Furthermore, the fault type is determined based on the error identifier and a prediction model, and the data is reported. By introducing the acknowledgment flag, bidirectional communication and confirmation between the BIOS and BIOS are achieved. The timely clearing mechanism of the flag avoids redundant data storage, improves buffer utilization, and reduces the possibility of data conflicts.

[0081] In some optional implementations, the method further includes: before outputting an acknowledgment flag to the basic input / output system, if the ready flag is a target ready flag, acquiring the acknowledgment flag according to a preset period, determining whether the acknowledgment flag is a target preset flag, and if the acknowledgment flag is a target preset flag, clearing the ready flag and the confirm flag in the processor platform's buffer.

[0082] Specifically, after the BIOS writes the ready flag, it polls for the acknowledgment flag. Once the acknowledgment flag is obtained, both the ready and acknowledgment flags are cleared to release buffer space and prepare for new error data, indicating that the interaction is complete. This ensures dynamic use of the buffer and fast platform response, reduces unnecessary waiting time, and improves the platform's real-time performance.

[0083] In some alternative implementations, the method further includes:

[0084] The process involves acquiring historical error logs, cleaning and extracting features from the data to obtain the target historical error log. The extracted features include at least: error type and frequency of occurrence. Historical error logs include, but are not limited to, BERT table records and MCA error logs. The extracted features may also include the scope of impact, such as single-DIMM failures or cross-CPU node failures.

[0085] A machine learning model is trained based on the target's historical error logs and error categories to obtain an error classification model; the machine learning model includes, but is not limited to, algorithms such as random forest or LSTM.

[0086] Error identifiers are classified according to an error classification model.

[0087] Specifically, when a new error occurs (when an error is detected, the control MCA mechanism generates an interrupt notification to the BIOS), the error data is input into the trained model, which outputs the error category. Through deep analysis of historical data and machine learning-driven model training, newly emerging errors can be automatically and accurately classified, improving the accuracy and efficiency of error identification. Intelligent error classification reduces the time administrators spend locating critical issues by 60%, from an average of 30 minutes to 12 minutes.

[0088] In some alternative implementations, the method further includes:

[0089] Based on the target characteristics of multiple error identifiers, the priority of multiple error identifiers is determined. The target characteristics include: the scope of impact of the error identifier and the load status of the processor platform.

[0090] The system dynamically adjusts error priorities based on factors such as the scope of the error's impact (e.g., single-DIMM failure or cross-CPU node failure) and the platform's current load status (e.g., CPU utilization, memory utilization). For example, if the platform load is high, even minor hardware errors can quickly escalate into serious failures. In this case, the model automatically prioritizes such errors to ensure timely response. By dynamically adjusting error priorities, errors that may significantly impact overall performance can be addressed first, improving the timeliness of fault response and the level of system stability maintenance. Especially under high-load scenarios, this mechanism can effectively prevent system crashes caused by underestimating initial errors, further enhancing the platform's availability and reliability. For instance, when the system CPU utilization reaches 85%, minor errors (such as single-DIMM correctable errors) will be elevated to high priority, thereby preventing potential escalation and ensuring stable system operation under high-pressure environments.

[0091] In some optional implementations, a predictive model is constructed based on historical data and real-time operating parameters, including:

[0092] Acquire historical data and real-time operating parameters, including basic input / output system error logs, hardware operating parameters, processor platform microcode data, and environmental monitoring data. BIOS error logs include, but are not limited to: BERT table records, MCA error logs, and memory self-test results; hardware operating parameters include, but are not limited to: real-time data such as CPU temperature, memory voltage, and fan speed; AGESA microcode data includes, but is not limited to: processor low-level error information, such as cache errors and bus errors; and environmental monitoring data includes, but is not limited to: data center temperature, humidity, and power status.

[0093] A predictive model is obtained by training a machine learning model based on historical data and real-time operating parameters. The machine learning model includes at least one of the following: random forest or long short-term memory network. The predictive model obtained by the above method has an accuracy rate of over 90% in predicting memory failures and can issue warnings 72 hours in advance. Preventive maintenance measures can be taken in a timely manner based on the prediction results of the predictive model, reducing unplanned downtime by 50% and MTTR (Mean Time To Repair) from 4 hours to 2.4 hours. The intelligent error classification of the predictive model reduces the time for administrators to locate critical issues by 60%, from an average of 30 minutes to 12 minutes.

[0094] The processor platform described in this application supports AGESA 1.2.0 and above microcode in terms of hardware; in terms of software, it supports memory interaction interfaces with mainstream BMC firmware (such as AST2500 and iKVM), while retaining IPMI 2.0 compatibility mode. Regarding data security, TLS encrypted transmission and AES-256 storage encryption are used to ensure the confidentiality of error data, and blockchain evidence storage guarantees the immutability of the data. In terms of compliance support, it meets compliance requirements such as ISO 27001 and PCI-DSS, and the auditability of error reports reaches enterprise-level standards. Regarding audit trails, blockchain evidence storage allows for the traceability of the entire process of error report generation, transmission, and storage, meeting compliance audit requirements.

[0095] To optimize error reporting, a multi-level error reporting strategy is introduced. When the BIOS detects a hardware error, it first performs a preliminary analysis to determine whether it needs to be immediately reported to the BMC, or whether it can be handled at the BIOS level first, based on the severity and scope of the error. For example, for minor, correctable errors, the BIOS can attempt to repair them locally, such as through mechanisms like PPR (Power-on Program Package Repair); while for serious, uncorrectable errors, the BIOS will immediately trigger the reporting process to ensure that the BMC and the upper-level management platform can respond promptly.

[0096] Users can customize the triggering conditions and strategies for error alerts based on their business needs and platform operating environment. Through the BIOS and BMC management interfaces, users can set specific error types and parameter thresholds (such as CPU temperature exceeding 80°C, memory error frequency exceeding 10 times / hour, etc.). When the platform detects errors meeting these conditions, it will automatically initiate the alert process and take corresponding preventative measures. A user interface is provided for customizable settings, enhancing system configurability and user interaction, allowing even non-professionals to easily manage the system's RAS features.

[0097] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the error reporting method for the processor platform of this application will be described in detail below with reference to specific embodiments.

[0098] Example

[0099] like Figure 3 As shown, the BIOS controls the detection of hardware errors on the platform, generates error data from the detected error information and packages it, calculates a new CRC checksum, obtains multiple error messages from the processor platform, and constructs an error structure based on the multiple error messages and a preset order.

[0100] The BIOS writes the error structure to the VGA video memory and sets the buffer's ready flag. When the ready flag is set to 1, the MBC monitors the ready flag, reads video memory data, and verifies the CRC checksum. After successful verification, the error data is processed (the error structure is parsed to obtain the error identifier): The processor platform's buffer write pointer is obtained; the error structure is written to the buffer's data storage area according to the write pointer, and the error data checksum in the data storage area is updated based on the error structure. The data storage area is used to temporarily store the error structure. Multiple ready flags in the buffer are obtained at preset intervals, and it is determined whether each ready flag is the target ready flag. If the ready flag is the target ready flag, the updated error data checksum in the data storage area is read. Based on the updated error data checksum, it is determined whether the data in the error structure is normal. If the data in the error structure is normal, the normal error structure is parsed according to a preset format to obtain the error identifier. After obtaining the error identifier, the confirmation flag is set to 1.

[0101] During the process of obtaining error flags, the confirmation flag is polled to see if it is 1. If the confirmation flag is 1 and the ready flag is 1, the ready flag (to 0) and the confirmation flag (to 0) are cleared. If the ready flag is 1, the confirmation flag is obtained according to a preset period, and it is determined whether the confirmation flag is the target preset flag. If the confirmation flag is the target preset flag, the ready flag and confirmation flag in the processor platform's buffer are cleared.

[0102] Simultaneously, based on the obtained error identifiers and prediction models, the types of faults that the processor platform may experience in the future are determined; the fault types are reported to the processor platform and warnings are issued.

[0103] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0104] Embodiments of this application also provide an error reporting device for a processor platform. The device includes: an acquisition module for acquiring multiple error identifiers of the processor platform, the error identifiers being information characterizing the fault type of the processor platform; a construction module for constructing a prediction model based on historical data and real-time operating parameters, the historical data and real-time operating parameters including at least: error logs of the processor platform's basic input / output system, hardware operating parameters, and environmental monitoring data; a determination module for determining the fault type that the processor platform will experience within a future period based on the multiple error identifiers and the prediction model; and a reporting module for reporting the fault type to the processor platform and issuing an early warning.

[0105] For a description of the features in the embodiment corresponding to the error reporting device of the processor platform, please refer to the relevant description of the embodiment corresponding to the error reporting method of the processor platform, which will not be repeated here.

[0106] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the error reporting method embodiments of any of the processor platforms described above.

[0107] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the error reporting method for any of the processor platforms described above when it is run.

[0108] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0109] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the error reporting method embodiments of any of the processor platforms described above.

[0110] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the error reporting method embodiments of any of the processor platforms described above.

[0111] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0112] The foregoing has provided a detailed description of an error reporting method and electronic device for a processor platform provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An error reporting method for a processor platform, characterized in that, include: The method involves: acquiring multiple error identifiers from a processor platform, where the error identifiers characterize the fault type of the processor platform; the processor platform's basic input / output system includes video memory space, which includes a buffer; acquiring multiple error messages from the processor platform; constructing an error structure based on the multiple error messages and a preset order; when a new error message is detected in the basic input / output system, converting the error message into an error identifier based on the error structure and a preset format; acquiring a write pointer to the buffer of the processor platform, which involves: writing the error structure to the data storage area of ​​the buffer according to the write pointer, and updating the error data checksum in the data storage area according to the error structure, where the data storage area is used to temporarily store the error structure; acquiring multiple ready flags in the buffer at a preset period, determining whether the ready flag is a target ready flag, and if the ready flag is the target ready flag, reading the updated error data checksum in the data storage area; Based on the updated error data verification value, determine whether the data in the error structure is normal; if the data in the error structure is normal, parse the normal error structure according to the preset format to obtain the error identifier; Historical error logs are obtained, and the data in the historical error logs is cleaned and features are extracted to obtain target historical error logs. The extracted features include at least: error type, scope of impact, and frequency of occurrence. A machine learning model is trained based on the target historical error logs and error categories to obtain an error classification model. The error identifiers are classified based on the error classification model. Based on historical data and real-time operating parameters, a predictive model is constructed. The historical data and real-time operating parameters include at least the error logs of the processor platform's basic input / output system, hardware operating parameters, and environmental monitoring data. Based on the multiple error identifiers and the prediction model, determine the types of faults that the processor platform will experience in the future; The fault type will be reported to the processor platform and an early warning will be issued.

2. The error reporting method according to claim 1, characterized in that, The acquisition of multiple error identifiers from the processor platform includes: Obtain multiple error messages from the processor platform; Based on the multiple error messages and a preset order, an error structure is constructed; If a new error message is detected in the input of the basic input / output system, the error message is converted into an error identifier according to the error structure and preset format.

3. The error reporting method according to claim 2, characterized in that, The method further includes: The basic input / output system is initialized. Obtain read permission for the video memory space, and obtain the address and capacity of the video memory space based on the read permission; A buffer with a preset capacity is partitioned within the video memory space.

4. The error reporting method according to claim 1, characterized in that, The method further includes: After receiving the error flag, an acknowledgment flag is output to the basic input / output system; When the basic input / output system receives the acknowledgment flag, the ready flag and confirmed flag in the processor platform's buffer are cleared.

5. The error reporting method according to claim 4, characterized in that, The method further includes: Before outputting an acknowledgment flag to the basic input / output system, if the ready flag is the target ready flag, the acknowledgment flag is acquired according to a preset period, and it is determined whether the acknowledgment flag is the target preset flag. If the acknowledgment flag is the target preset flag, the ready flag and the confirm flag in the buffer of the processor platform are cleared.

6. The error reporting method according to claim 1, characterized in that, The method further includes: The priority of the error identifiers is determined based on the target characteristics of the error identifiers, wherein the target characteristics include the scope of influence of the error identifiers and the load status of the processor platform.

7. The error reporting method according to claim 1, characterized in that, The process of constructing a prediction model based on historical data and real-time operating parameters includes: The historical data and the real-time operating parameters are acquired, including the error log of the basic input / output system, the hardware operating parameters, the microcode data of the processor platform, and the environmental monitoring data. The machine learning model is trained based on the historical data and the real-time operating parameters to obtain the prediction model, wherein the machine learning model includes at least one of the following: random forest or long short-term memory network.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the error reporting method of the processor platform as described in any one of claims 1 to 7 when executing the computer program.

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