Hybrid memory index management method and device, equipment and medium

Abstract

The invention relates to the technical field of database management, and discloses a hybrid memory index management method and device, equipment and a medium. Receiving an access request, providing a target index node from the cache when the access request is hit, and reading the target index node from the nonvolatile storage medium when the access request is not hit; writing branch nodes into a high-bandwidth memory cache according to node types, writing leaf nodes into a dynamic random access memory cache, and registering information; when the cache of the high-bandwidth memory meets a first trigger condition, migrating the branch node to the cache of the dynamic random access memory and updating information; and when the cache of the dynamic random access memory meets a second trigger condition, migrating the branch node to the high-bandwidth memory cache, replacing the node and updating the information. According to the method, the node residence position is dynamically adjusted by distinguishing the node types and combining the cache performance, and the index node mapping table is synchronously updated, so that the index request processing performance and the storage resource utilization efficiency are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of database management, and in particular to a hybrid memory index management method, device, equipment and medium. BACKGROUND

[0002] As a kind of data processing software system, database management system undertakes the function of loading data from persistent medium (such as disk, cloud storage service) to CPU pipeline context and carrying out computing processing. Since the core of database system is data analysis and processing, its demand for computer hardware resources mainly focuses on IO capability. However, in modern computer architecture, the IO capability of CPU accessing data has been a system bottleneck for a long time, especially in the typical data analysis scene of database management system. IO bottleneck limits the processing efficiency of system in high concurrency and large data environment, seriously affecting the overall performance of database.

[0003] Taking BTREE index search as an example, as the most common, highest frequency and supporting high concurrency access basic operation in database, its performance is limited particularly significantly. The structure of BTREE index determines that there is significant hierarchical difference in node access: from the root node, the access frequency of nodes presents the characteristics of decreasing from top to bottom layer by layer. Especially the root node and upper branch nodes, the access frequency is much higher than that of lower nodes and leaf nodes, and these high-frequency access nodes constitute obvious IO access hotspots. In the environment of large data and multi-thread concurrency, these hotspot nodes become the main source of database IO bottleneck, leading to the decrease of system overall throughput, the increase of access delay, and seriously restricting the performance improvement of database management system.

[0004] In the traditional hardware environment, the general memory architecture usually takes DRAM as the main storage medium. Although DRAM has relatively large capacity, its access bandwidth and delay are difficult to meet the performance requirements in the high concurrency hotspot access scene. Therefore, the industry gradually introduces high bandwidth memory (HBM) components. HBM has higher access bandwidth and lower delay than traditional DRAM, but the capacity is relatively small, which is difficult to meet the cache demand of all data pages. In the prior art, how to cooperatively schedule and manage between HBM and DRAM cannot provide an efficient index node cache optimization mechanism for the high-frequency access characteristics of BTREE branch nodes in the database management system. Lack of precise cache allocation and dynamic adjustment strategy for hotspot branch nodes leads to insufficient utilization of HBM resources or inability to improve the access delay of hotspot branch nodes in DRAM, which is particularly evident in large-scale data environment, further aggravating the performance bottleneck of database system. SUMMARY

[0005] The main purpose of the present application is to provide a hybrid memory index management method, device, equipment and storage medium, aiming at solving the technical problem that the prior art cannot dynamically allocate hybrid memory resources according to index node types, resulting in that branch nodes with high frequency access are limited by standard memory performance bottlenecks, causing data processing delay and throughput decline.

[0006] To achieve the above purpose, the present application provides a hybrid memory index management method, comprising: establishing an index node mapping table for recording the residence information of each index node in the storage resource; receiving an access request for a target index node, retrieving the residence information of the target index node in the index node mapping table, and providing the target index node from the corresponding cache when hit; when the index node mapping table does not contain the residence information of the target index node, reading the target index node from the non-volatile storage medium; when the target index node is a branch node, writing the target index node as a branch node into a high-bandwidth memory cache; when the target index node is a leaf node, writing the target index node as a leaf node into a dynamic random access memory cache; and registering the residence information of the target index node in the index node mapping table; when the high-bandwidth memory cache meets a first trigger condition, performing migration of the branch node to the dynamic random access memory cache, and updating the corresponding residence information in the index node mapping table; when the dynamic random access memory cache meets a second trigger condition, performing migration of the branch node to the high-bandwidth memory cache and corresponding node replacement, and updating the corresponding residence information in the index node mapping table.

[0007] Further, to achieve the above purpose, the present application provides a hybrid memory index management device, comprising: a mapping table management module for establishing an index node mapping table for recording the residence information of each index node in the storage resource; a cache access module for receiving an access request for a target index node, retrieving the residence information of the target index node in the index node mapping table, and providing the target index node from the corresponding cache when hit; a persistent reading module for reading the target index node from the non-volatile storage medium when the index node mapping table does not contain the residence information of the target index node; The cache write module is configured to write the target index node as a branch node into a high bandwidth memory cache when the target index node is a branch node, and write the target index node as a leaf node into a dynamic random access memory cache when the target index node is a leaf node, and register the residence information of the target index node in the index node mapping table. The high bandwidth memory cache migration module is configured to perform migration of the branch node to the dynamic random access memory cache when the high bandwidth memory cache meets a first trigger condition, and update the corresponding residence information in the index node mapping table. The dynamic random access memory cache migration module is configured to perform migration of the branch node to the high bandwidth memory cache and corresponding node replacement when the dynamic random access memory cache meets a second trigger condition, and update the corresponding residence information in the index node mapping table.

[0008] Further, to achieve the above object, the present application also provides a computer device, which comprises a memory, a processor, and a hybrid memory index management program stored in the memory and executable on the processor, and the hybrid memory index management program is used to implement the steps of the hybrid memory index management method.

[0009] Further, to achieve the above object, the present application also provides a computer readable storage medium, which stores a hybrid memory index management program, and the hybrid memory index management program is used to implement the steps of the hybrid memory index management method when executed by a processor.

[0010] Beneficial effects: The application relates to the technical field of database management, and discloses a hybrid memory index management method, device, equipment and medium, which comprises the following steps: establishing an index node mapping table for recording the residence information of each index node in a storage resource; receiving an access request for a target index node, providing the target index node from a corresponding cache when a hit occurs; reading the target index node from a nonvolatile storage medium when a miss occurs; writing branch nodes into a high-bandwidth memory cache and writing leaf nodes into a dynamic random access memory cache according to the type of the target index node and registering the residence information; migrating the branch nodes to the dynamic random access memory cache and updating the residence information when the high-bandwidth memory cache meets a first trigger condition; migrating the branch nodes to the high-bandwidth memory cache, performing corresponding node replacement and updating the residence information when the dynamic random access memory cache meets a second trigger condition. The application distinguishes the cache storage positions based on the index node type and access characteristics, combines the capacity and performance characteristics of the high-bandwidth memory cache and the dynamic random access memory cache, dynamically adjusts the residence positions of the branch nodes, keeps the synchronous update of the index node mapping table, realizes the rapid access of hot data of the branch nodes and the reasonable distribution of cold and hot data, and improves the performance and storage resource utilization efficiency of the database system when processing high-concurrency index requests. BRIEF DESCRIPTION OF DRAWINGS

[0011] The application will be further described below in combination with the drawings and embodiments, and the drawings show: Figure 1 An application environment schematic diagram of the hybrid memory index management method in an embodiment of the application; Figure 2 A flowchart of the hybrid memory index management method in an embodiment of the application; Figure 3 A functional module schematic diagram of the hybrid memory index management device in a preferred embodiment of the application; Figure 4 A structure schematic diagram of the computer equipment in an embodiment of the application; Figure 5 Another structure schematic diagram of the computer equipment in an embodiment of the application. DETAILED DESCRIPTION

[0012] It should be understood that the specific embodiments described herein are merely intended to explain the application, and are not intended to limit the application.

[0013] The hybrid memory index management method provided by the embodiments of the application can be applied to, for example, Figure 1In an application environment of the present application, a client communicates with a server through a network. The server can establish an index node mapping table for recording the residence information of each index node in the storage resource through the client; receive an access request for a target index node, provide the target index node from the corresponding cache when hit, read the target index node from the non-volatile storage medium when missed; write the branch node into the high-bandwidth memory cache according to the type of the target index node, write the leaf node into the dynamic random access memory cache and register the residence information; when the high-bandwidth memory cache meets the first trigger condition, migrate the branch node to the dynamic random access memory cache and update the residence information; when the dynamic random access memory cache meets the second trigger condition, migrate the branch node to the high-bandwidth memory cache and perform the corresponding node replacement and update the residence information. The present application distinguishes the cache storage location based on the index node type and access characteristics, combines the capacity and performance characteristics of the high-bandwidth memory cache and the dynamic random access memory cache, dynamically adjusts the residence location of the branch node and keeps the synchronous update of the index node mapping table, realizes the fast access of the branch node hotspot data and the reasonable distribution of the hot and cold data, and improves the performance and storage resource utilization efficiency of the database system when processing high-concurrency index requests. The client can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices. The server can be implemented by an independent server or a server cluster composed of multiple servers. The present application will be described in detail through specific embodiments.

[0014] Please refer to Figure 2 , Figure 2 The flowchart of an embodiment of the hybrid memory index management method provided by the present application is shown. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0015] As Figure 2 shown, the hybrid memory index management method provided by the present application includes the following steps: S10, establishing an index node mapping table for recording the residence information of each index node in the storage resource; In this embodiment, in order to record the residence information of each index node in the storage resource, an efficient data structure needs to be constructed to manage the residence information of the index node. The "index node" here refers to a unit used to organize data in the index structure, usually corresponding to a data page, with a fixed format and storage requirements. In order to support large-scale concurrent retrieval access, the residence information needs to have the ability of fast query, dynamic update and conflict processing. For this purpose, a hash table is used as a mapping structure to organize data through the mapping relationship between the unique identifier and the corresponding position of the bucket array. The unique identifier is usually generated by the physical address, logical number or globally unique ID of the node. The bucket array is a block of continuous space allocated in memory, with the initial state set by initialization operation. Each bucket can independently store multiple residence information entries. The residence information entry contains cache location identifier, memory address offset and last access timestamp. The cache location identifier is used to distinguish between high-bandwidth memory cache and dynamic random access memory cache, the memory address offset is used to quickly locate specific data within the cache unit, and the last access timestamp is used for subsequent access order management. The conflict chain table is used to solve the case where different index nodes are mapped to the same bucket position, and the residence information entries corresponding to the same bucket are stored in the conflict chain table in order. The capacity of the bucket array, the organization form of the conflict chain table and the selection of the hash function can all be parameter adjusted based on different requirements to improve the overall retrieval and update efficiency. In this way, the state of each index node in the cache resource can be efficiently recorded and maintained in memory, providing a foundation for subsequent access requests.

[0016] The capacity of the bucket array can be dynamically configured in different production environments, for example, in a high-concurrency database system, a larger capacity can be allocated to accommodate more entries, and the length threshold of the conflict chain table can be adjusted to reduce the performance degradation caused by conflicts. Different hash functions can be selected based on different hardware architectures, such as using performance-optimized hash functions such as MurmurHash in hardware that supports SIMD instructions to improve hash calculation efficiency. The memory distribution of the bucket array can also be optimized through memory alignment to reduce the delay of cross-cache line access. In terms of the organization form of the residence information entry, multi-level indexing can be supported to record more metadata such as access frequency, heat level, etc., to improve the availability and fine-grained management level of the residence information. For distributed database environments, part of the index node mapping table content can be stored in multiple nodes in a distributed manner, combined with a distributed consistency protocol to ensure global consistency and fault tolerance.

[0017] Example description: In a routing cache acceleration system for a telecommunication network, in order to improve the lookup efficiency of routing table entries, the system establishes an index node mapping table in memory for recording the residence information of each routing index node in storage resources. In specific implementation, a hash mapping mechanism is adopted, taking the unique identifier of each routing index node as the key value, to quickly locate the bucket position in the mapping table, and record the residence information such as cache location identifier, memory address offset and access time in the corresponding bucket position. This structure supports fast access and update in a multi-thread high-concurrency environment, ensures that the routing index node can be accurately located and scheduled among different cache resources (such as cache or main memory), thereby reducing the delay of large-scale routing table retrieval in communication services, and meeting the strict requirements of communication networks for low-latency data processing.

[0018] By adopting a hash table and combining a collision chain table and multi-dimensional residence information, the present embodiment can efficiently support the management needs of index nodes among different types of caches, realize fast recording and querying of index node cache location, address and access state, improve the response speed of data retrieval and update, and improve the utilization efficiency of cache resources.

[0019] S20, receiving an access request for a target index node, retrieving the residence information of the target index node in the index node mapping table, and providing the target index node from the corresponding cache when a hit is made; In the embodiment, an access request for a target index node is received, i.e. an externally submitted request message containing an access target is obtained during system runtime, which can come from different communication interfaces or API calls, and is an interaction entrance of the system and external data access logic. The access request includes a structured data unit containing a unique identifier of the target index node, which is a logical reference of the target index node, such as a predefined key value or number in the index tree, which can ensure unique correspondence in the global data set, and is often encoded by the primary key or routing information in the database. Retrieving the residence information of the target index node is a quick query operation on the unique identifier contained in the access request, and the query range is limited in the index node mapping table, which adopts a hash table data structure and has the ability to locate the corresponding storage location with constant time complexity, and the conflict chain table is used to ensure correct resolution in the case of hash conflict. Hit means that the corresponding storage entry containing the cache location identifier and the physical location offset of the data in the cache is successfully found in the query process. The corresponding cache means the cache category determined according to the cache location identifier, including high-bandwidth memory cache or dynamic random access memory cache with different performance characteristics. Providing the target index node means reading the data of the node from the determined storage location of the cache category and returning it to the requester, which ensures that the delay of data read operation is minimized. In specific implementation, the access request message can be parsed, the target index node unique identifier can be extracted, the hash function can be used to process the unique identifier to locate the bucket position of the index node mapping table, and the conflict chain table can be scanned in sequence to verify whether it matches. After successful matching, the cache location identifier and memory offset are extracted and the corresponding cache unit is accessed to read the node data from the location and return it. This logical design ensures that the query processing path of the cache system is efficient and reliable, and meets the strict requirements of delay control in a multi-threaded concurrent environment.

[0020] Different data structures or index strategies can be used to manage unique identifiers, such as using a multi-field combined key to construct a unique identifier, or adjusting the hash function in different deployment environments to adapt to the distribution characteristics of different size data sets. The maximum length of the conflict chain table can also be set, and when the length of the chain table exceeds the threshold, rehashing or zipper + tree structure can be used to reduce the performance loss caused by conflicts. The cache location identifier can reserve an extension field to support future cache media, such as adding non-volatile memory cache types without modifying the access logic. A zero-copy data path can be used in the process of accessing cache data to reduce copying overhead through kernel space and user space shared memory mapping, further improving access performance. For different hardware configuration environments, the cache access priority can be dynamically adjusted according to the cache hit rate, and the low-delay high-bandwidth memory cache resources are preferentially used to ensure the balance of overall access performance under different load pressures.

[0021] Example: In the data routing management module of the communication network device, the system frequently receives query requests for routing index nodes, maintains the residence information of each routing index node in the cache using a mapping table, and when a request arrives, quickly matches the mapping table record by analyzing the destination node identifier in the data packet and directly obtains the node data response request from the cache resource, avoiding the delay caused by accessing persistent storage, thereby ensuring the real-time and fast availability of the network routing table.

[0022] This embodiment realizes efficient acquisition of the target index node by analyzing the access request and quickly retrieving the unique identifier of the target index node, combined with the selection and positioning of the cache unit based on the cache location identifier, reducing the high delay problem caused by traditional full table scanning or disk random access, and improving the response speed of the system in large-scale data concurrent access scenarios.

[0023] S30, when the index node mapping table does not contain the residence information of the target index node, reading the target index node from a non-volatile storage medium; In this embodiment, when an access request is received and no residence information matching the unique identifier of the target index node is found in the index node mapping table, the target index node data needs to be obtained by accessing the non-volatile storage medium. The index node mapping table is a directory structure for cache hit judgment, and its miss triggers subsequent storage access operations. The non-volatile storage medium usually includes a disk array, a solid state disk, or a distributed storage cluster, which is used to permanently save index node data.

[0024] To realize reading data from a non-volatile storage medium, the system first sends a read command to the persistent storage interface. The command needs to contain positioning information sufficient to uniquely locate the physical position of the target index node in the storage medium, which can be a direct mapping address of the node unique identifier, or a page number, block number, or object key. The storage interface initiates a read request based on the positioning information to analyze the physical storage location, and the target index node data returned by the read request is loaded into the memory buffer as the original data block.

[0025] Since the index node data saved in the storage medium may be stored in a compressed encoding or specific format, the data loaded into the buffer is first subjected to integrity verification. Integrity verification can be achieved through a cyclic redundancy check to ensure that the data has not been damaged during medium reading and transmission. After verification, the original data block is decoded to restore the decoded data to the target index node that can be directly accessed, and it is temporarily stored in the loading buffer for subsequent cache update or direct data service.

[0026] The physical location positioning can be completed through different storage interfaces, for example, using the LBA addressing mode of the SATA protocol, the namespace plus logical block addressing of the NVMe protocol, or determining the physical location based on the storage bucket and object key through the object storage API. The allocation of the data buffer can be page-aligned, and the page size can be adjusted to 4 KB, 8 KB, or 16 KB to adapt to the read-write characteristics of the backend device. The integrity check can use different levels of check algorithms, for example, CRC-32, CRC-64, or SHA-256, to balance between performance and data security according to the scene requirements. The pre-reading mechanism can be used as an optimization means to pre-fetch adjacent nodes while reading the data of a node, thereby reducing the delay of subsequent access, and is particularly suitable for sequential scanning or hotspot index area.

[0027] Example description: In a database storage system, when a client requests an index node data that is not in the cache, the system parses the physical offset position of the node in the NVMe SSD according to the unique identifier of the node, then reads the data page from the physical position through the storage interface, and loads the data page into the memory buffer. CRC-32 check is performed immediately after loading to ensure data integrity, and decoding is performed on the data after the check is passed to obtain the index node data that can be directly accessed, and then the data is used to respond to the client request and can update the cache to improve the efficiency of subsequent access.

[0028] The present embodiment can ensure that the target index node data is reliably read and correctly decoded in a high-concurrency and high-randomness access scenario by falling back to access the non-volatile storage medium when the mapping table is not hit, thereby improving data availability, reducing access delay, and enhancing the stability of the system as a whole.

[0029] S40, when the target index node is a branch node, writing the target index node as a branch node into the high-bandwidth memory cache; when the target index node is a leaf node, writing the target index node as a leaf node into the dynamic random access memory cache; and registering the residence information of the target index node in the index node mapping table; In this embodiment, when processing the target inode data, it is first necessary to distinguish its type, that is, to determine whether the target inode is a branch node. The branch node is an intermediate node in the B-tree structure used to guide the search path, and usually has a higher access frequency. The leaf node is a node in the B-tree that stores actual data, and has a relatively low access frequency. Type distinction can be completed by checking the type flag field in the inode metadata. Based on the type determination result, the branch node data is written to the high bandwidth memory cache, that is, HBM (High Bandwidth Memory), which has the characteristics of high bandwidth, low delay, but limited capacity, and is suitable for storing high access frequency data. At this time, sufficient continuous HBM storage space should be allocated, and the data of the target inode is copied to the HBM cache in blocks, and the block size can be 4KB, 8KB or 16KB, to adapt to the storage format of the node data page. For the leaf node, write to the dynamic random access memory cache, that is, the DRAM cache. The DRAM has a relatively large capacity but a relatively high delay, and is suitable for being used as a cache area for low access frequency data. The leaf node data should also be allocated continuous memory space before data copying. After completing the cache writing, the residence information of the target inode in the inode mapping table also needs to be registered. The residence information registration includes the cache location identifier, that is, it is clear that the target node is currently stored in the high bandwidth memory cache or the dynamic random access memory cache, and the memory address offset of the node data in the cache unit. The registration information will be used as the basis for subsequent access request fast hit.

[0030] Memory space allocation can be optimized in different ways, for example, a 4KB page-aligned fixed buffer is reserved in HBM for branch nodes, and dynamic allocation is used in DRAM for leaf nodes to adapt to the actual data size. Type determination can be completed by setting the type identification bit of the metadata field. This field can use one byte and clearly identify the branch node or leaf node through the value domain, which is convenient for program reading and parsing. The data copying operation can use the DMA (Direct Memory Access) engine to reduce the participation of the CPU and improve the data carrying efficiency. In the process of registering the residence information, a hash function can be selected to optimize the mapping table index positioning, reduce the conflict rate, and record the latest access timestamp for each residence information entry to support the subsequent cache eviction strategy. Pre-allocated memory pool can also be used to reduce the fragmentation and overhead caused by runtime memory allocation.

[0031] Example description: In the field of communication, for example in the user context index management scenario of mobile core network, the system needs to frequently retrieve the context record corresponding to the user identifier. After receiving the user identifier request, the user identifier is first parsed as the unique identifier of the target index node. If the parsing result shows that the node is a branch node, the system will load its data page directly into the high-bandwidth memory cache, and register its cache location and memory address offset. For the leaf node determined after the identifier parsing, the system loads it into the dynamic random access memory cache and registers its storage location and address information in the mapping table. In this way, high-concurrency context retrieval requests can quickly hit between different cache levels, improving the response speed and retrieval performance of the mobile core network to the user context, and adapting to the strict requirements of high concurrency and low latency in communication services.

[0032] The embodiment can effectively improve the index node access performance, reduce the data migration delay between storage levels, maximize the memory usage efficiency under the condition of limited cache capacity, and ensure that high-throughput index query capability can still be provided under the conditions of large data volume and high concurrency by caching the branch node with high-frequency access to the high-bandwidth memory cache and caching the leaf node with low-frequency access to the dynamic random access memory cache.

[0033] S50, when the high-bandwidth memory cache meets the first trigger condition, performing the migration of the branch node to the dynamic random access memory cache, and updating the corresponding residence information in the index node mapping table; In the embodiment, the current available space of the high-bandwidth memory cache is monitored to dynamically perceive the state of the remaining resources in the cache and ensure that adjustment measures are taken in time when the resources approach saturation. The current available space can be obtained by periodically calculating the difference between the used capacity and the total capacity of the high-bandwidth memory cache, which is derived from the commonly used memory usage monitoring method of modern memory management modules. The first trigger condition is used to define that the migration operation of the branch node is triggered when the available space of the high-bandwidth memory cache is lower than a certain preset threshold, which can be set by system initialization parameter configuration, for example, the threshold is set to 20% or less of the total capacity of the high-bandwidth memory. After determining that the trigger condition is met, the least used branch node needs to be determined from the least used linked list of the high-bandwidth memory cache first, and the linked list is updated by maintaining the access frequency or access timestamp, and the tail of the linked list represents the least recently used node. In the migration process, the linked list tail node is accessed first and the associated branch node cache space is extracted, and then the data content of the cache space is transferred to the dynamic random access memory cache through a memory copy operation to ensure data consistency. Subsequently, a new linked list node is inserted at the head of the least used linked list of the dynamic random access memory cache to manage the migrated branch node cache space and maintain the access sequence correctly in the new cache environment. After the migration is completed, the resident information entry in the index node mapping table needs to be updated, the cache location identifier of the original branch node is modified to the dynamic random access memory cache, and the new memory address offset of the node is updated. In the entire operation, the migration operation not only involves physical copying of data, but also requires maintaining the integrity of the linked list structure and index relationship to ensure the accuracy and efficiency of subsequent access.

[0034] The efficient copy operation of data from the high-bandwidth memory cache to the dynamic random access memory cache can be realized by configuring the hardware-supported DMA engine, and the migration efficiency can be improved by parallelizing the multi-threaded memory copy task. In the threshold setting of the trigger condition, it can be flexibly adjusted according to the capacity characteristics of different hardware platforms, for example, in a high-bandwidth memory cache with small capacity, the threshold can be set to 10% of the total capacity to ensure timely release of cache resources, while in a platform with large capacity, the threshold can be set to 30% to reduce the performance overhead caused by frequent migration. In the maintenance of the linked list node, a double-linked list can be used to quickly access the tail node and insert a new node at the head, and a more fine-grained cache eviction policy can be implemented by increasing the node access counter.

[0035] Example description: In the field of communication, the protocol stack processing module of a cellular base station needs to maintain a large amount of dynamically updated protocol control block index data. As the concurrent data volume increases, the high-bandwidth memory cache space in the base station may gradually become tight. The system can monitor the available space of the high-bandwidth memory cache, and when the space is lower than a preset threshold, select the least accessed protocol control block index node to migrate it from the high-bandwidth memory cache to the dynamic random access memory cache, and update the node location and memory offset in the mapping table. This process can reduce the performance degradation caused by insufficient cache resources, ensure that the protocol stack can still respond to index data queries efficiently when a large number of users are concurrently accessing, and meet the business needs of low latency and high concurrency in the field of communication.

[0036] The embodiment described above can timely migrate the least used branch node to the dynamic random access memory cache when the available space of the high-bandwidth memory cache is insufficient, not only ensuring the space utilization rate of the high-bandwidth memory cache, but also maintaining accurate management of the migrated node by updating the index node mapping table, thereby reducing the risk of cache overflow and improving the overall access efficiency of the system.

[0037] S60, when the dynamic random access memory cache satisfies a second trigger condition, performing migration of the branch node to the high-bandwidth memory cache and corresponding node replacement, and updating the corresponding residence information in the index node mapping table.

[0038] In the embodiment, the second trigger condition is satisfied when the access frequency or hot degree of the branch node in the dynamic random access memory cache reaches a pre-set threshold, for example, the access count exceeds a limited number within a statistical window, at which time it is indicated that the branch node becomes a hot node and its access performance needs to be improved. The condition is determined by periodically counting the access count of the branch node, which can be collected by means of access records or access timestamps. After determining that the condition is satisfied, the data content of the hot branch node cache space is first copied to the high-bandwidth memory cache to take advantage of the low-latency and high-bandwidth of the high-bandwidth memory cache to improve the access efficiency. To facilitate the management of the newly migrated hot branch node, a new linked list node is inserted at the tail position of the least used linked list of the high-bandwidth memory cache, so that it is marked as the latest migrated node to participate in subsequent cache management strategies. At the same time, the tail position of the least used linked list of the high-bandwidth memory cache is accessed to select a cold data node to be replaced. After obtaining the replacement node, its associated cache space is extracted and the data content is copied back to the dynamic random access memory cache to complete the node replacement. Subsequently, a new linked list node is inserted at the head position of the least used linked list of the dynamic random access memory cache to maintain the cache management state of the cold node. During the entire process, the resident information entries in the index node mapping table also need to be updated synchronously, and the cache location identifier and memory address offset of the hot node and the replaced node are updated respectively to ensure the accuracy of subsequent query positioning. The various links are closely logically associated, and the monitoring, data copying, linked list maintenance and index updating form a complete cache management closed loop to ensure efficient management of hot nodes in the cache and optimization of the high-bandwidth memory cache space.

[0039] The second trigger condition can be adjusted according to the access mode on different hardware platforms, for example, in a hot centralized service, a lower access count threshold can be set to accelerate the migration of hot nodes, and in a dispersed service, the threshold can be increased to reduce unnecessary migration overhead. An asynchronous migration mechanism can be used, i.e. the migration of hot nodes and the migration of replacement nodes can be performed in parallel through independent threads to reduce latency. For linked list maintenance, a double-linked list or a circular linked list can be selected to improve the access and modification efficiency of the linked list nodes. For servers with different memory capacity configurations, the cache management strategy can also be dynamically adjusted, for example, under high-capacity high-bandwidth memory configuration, multiple hot nodes can be migrated simultaneously to improve the hot data carrying capacity of the cache. By maintaining multi-dimensional statistical information of the cache nodes, for example, by combining access frequency and access time interval to optimize the replacement algorithm, the accuracy of cold and hot node identification can be improved.

[0040] Example description: in high-performance gateway devices in the field of communication, the cache management module needs to frequently and concurrently access a large number of branch node data, such as protocol routing table or data session state index. In order to improve the access performance of hot routing table entries, when it is monitored that the access frequency of a certain routing table branch node in the dynamic random access memory cache continuously exceeds the threshold value, that is, the migration is triggered, the hot routing table branch node is copied to the high-bandwidth memory cache, and a new linked list node is inserted at the tail of the least frequently used linked list of the high-bandwidth memory cache. At the same time, the tail node of the least frequently used linked list of the high-bandwidth memory cache is selected as the node to be replaced, and the data thereof is migrated to the dynamic random access memory cache, and a new linked list node is inserted at the head of the least frequently used linked list of the cache. Through the synchronous update of the mapping table, the communication gateway can quickly respond to the high-concurrency query demand for the hot routing table node, significantly reduce the query delay and improve the network service throughput.

[0041] The embodiment dynamically detects the hot branch node in the dynamic random access memory cache and timely migrates it to the high-bandwidth memory cache, while performing the cold node replacement operation, so as to reasonably utilize the cache resources. After updating the index node mapping table, the consistency and accuracy of the cache node access path are ensured, so that the access performance of the hot data is significantly improved, the access delay is reduced, and the dynamic adaptability of the cache structure is optimized in the multi-thread concurrent access environment.

[0042] The application relates to the technical field of database management, and discloses a hybrid memory index management method and device, equipment and a medium, which comprises the following steps: establishing an index node mapping table for recording the residence information of each index node in a storage resource; receiving an access request for a target index node, providing the target index node from the corresponding cache when a hit occurs; reading the target index node from a non-volatile storage medium when a miss occurs; writing branch nodes into a high-bandwidth memory cache and writing leaf nodes into a dynamic random access memory cache according to the type of the target index node and registering the residence information; migrating the branch nodes to the dynamic random access memory cache and updating the residence information when the high-bandwidth memory cache meets a first trigger condition; migrating the branch nodes to the high-bandwidth memory cache, performing corresponding node replacement, and updating the residence information when the dynamic random access memory cache meets a second trigger condition. The application distinguishes the cache storage positions based on the type and access characteristics of the index nodes, dynamically adjusts the residence positions of the branch nodes, and keeps the synchronous update of the index node mapping table, so that the fast access of hot branch node data and the reasonable distribution of hot and cold data are realized, and the performance and storage resource utilization efficiency of the database system in processing high-concurrency index requests are improved.

[0043] In one embodiment, the above step S10 comprises: S101, creating an index node mapping table by using a hash table data structure; S102, allocating continuous memory space for the inode mapping table and initializing the bucket array; S103, when a new inode is added, extracting the unique identifier of the inode to generate a key value; S104, processing the key value using a hash function to determine the bucket position of the inode in the inode mapping table; S105, storing the residence information entry containing the cache location identifier, memory address offset and last access timestamp in the bucket position; S106, when a bucket position conflict of the inode mapping table is detected, using a linked list method to append a conflict entry in the inode mapping table; S107, when the inode cache location is changed, updating the residence information of the corresponding entry in the inode mapping table.

[0044] In this embodiment, when creating an inode mapping table for recording the residence information of each inode in the storage resource, a hash table is first used as the data structure. The hash table is a mapping data structure that maps keys to values, with the characteristic of quickly accessing values through keys, and is suitable for storing and managing a large amount of inode residence information to meet the high-performance retrieval requirement. By allocating continuous memory space for the mapping table and initializing the bucket array, it can be ensured that each bucket in the bucket array is cleared or set to a null pointer, ready to accept subsequent storage. The allocation of continuous memory space improves the locality and traversal efficiency of memory access. When a new inode is added, the unique identifier of the inode needs to be extracted, which can come from the logical position of the node in the index structure, the globally unique ID or other distinguishable identifier. This identifier is used as a key value for subsequent hash calculation. By using a hash function on the key value, the key value can be mapped to the index position in the bucket array, so as to determine the bucket position of the inode residence information in the mapping table. The hash function can be a mature algorithm such as modulo operation, multiplication hash or CRC32, which needs to balance between performance and conflict rate.

[0045] When the bucket position is determined, a residence information entry is stored at the position, the entry including a cache position identifier indicating a storage position of current index node data in a high bandwidth memory cache or a dynamic random access memory cache, a memory address offset recording a physical or virtual offset address of the data in a corresponding cache unit, and a last access timestamp supporting subsequent cache replacement or access pattern analysis. In the operation process, when a hash conflict is detected, i.e., different key values are mapped to the same bucket position, the conflict is solved by a linked list method, i.e., a linked list is maintained at the conflict bucket position, and the conflict entries are hung in the linked list. The linked list method can support an arbitrary number of conflict entries without rehashing, thereby maintaining the integrity and scalability of the structure. The maximum length of the conflict linked list can be limited at each bucket position, for example, set to not more than 8, to balance the space overhead and performance.

[0046] When the cache position of a subsequent index node changes, e.g., migrates from a high bandwidth memory cache to a dynamic random access memory cache, the residence information entry of the index node needs to be relocated based on the unique identifier of the index node. After successful relocation, the cache position identifier and the memory address offset fields in the entry are updated to ensure that the information in the mapping table is consistent and synchronized with the real cache state. Data consistency needs to be ensured in the case of high concurrency access, e.g., by using read-write locks or atomic update mechanisms, to ensure that the mapping table state can still be correctly maintained in a concurrent read-write environment.

[0047] The embodiment realizes efficient index node positioning, conflict management and dynamic updating by using a hash table to store and maintain the residence information of index nodes, supports fast retrieval and modification of the residence position of index nodes in a high concurrency access scenario, reduces access delay and improves cache access hit rate, and meets the requirements for performance and accuracy when multiple threads access a database index structure.

[0048] In one embodiment, the above step S20 includes: S201, parsing an access request message to obtain a unique identifier of a target index node; S202, using a hash function to process the unique identifier of the target index node to determine a target bucket position of the target index node in the index node mapping table; S203, sequentially retrieving whether there is a target residence information entry matching the unique identifier of the target index node in a conflict linked list at the target bucket position; S204, when the retrieval hits, extracting a target cache position identifier and a memory address offset from the target residence information entry; S205, according to the target cache position identifier, selecting a high bandwidth memory cache unit or a dynamic random access memory cache unit as a target cache unit; S206, locating target inode data in the target cache unit using the memory address offset and reading the target inode data as an access response.

[0049] In the present embodiment, the process of receiving an access request for a target inode and retrieving its residence information in the inode mapping table involves request parsing, unique identifier determination, hash retrieval path calculation, collision list traversal, residence information extraction, cache path selection and data positioning. First, the access request message carries information used to uniquely identify the target inode, which can be derived from the 64-bit global ID assigned to each node internally, the encoding based on the business primary key or the encoding string of the physical storage path. The parsing of the request message can be completed by field mapping and verification through structured protocols (such as Protocol Buffers, gRPC data structure), ensuring the consistency and reliability of the parsing results.

[0050] After the unique identifier is parsed, it is input into a hash function to map to the bucket position of the inode mapping table. The choice of hash function directly affects the collision probability and performance. Hash algorithms suitable for large-scale data scenarios such as CityHash or MetroHash can provide better distribution. The calculated bucket position is used as an index to enter the bucket array of the inode mapping table. After array positioning, the collision list maintained at the bucket position is sequentially traversed. The residence information entries saved in the list nodes contain a unique identifier field, which is used to compare the unique identifier of the current access request with the entry identifier one by one. The collision list requires a traversal termination condition (such as NULL pointer judgment at the end of the list) during sequential retrieval, and can use hardware acceleration instruction sets (such as SIMD parallel comparison instructions) to optimize the comparison performance, especially when the length of the list node is small, which significantly reduces the CPU instruction path length.

[0051] Once the search hits, the cache location identifier and memory address offset recorded in the residence information entry are extracted. The cache location identifier is used to distinguish whether the inode is currently located in the high-bandwidth memory cache or the dynamic random access memory cache, and its design can use enumeration values to simplify the processing logic. The memory address offset is used as a direct index offset value for accessing the cache unit, which is used to accurately locate the address of the target inode data stored in the cache unit. At this time, through the cache access path selection logic, the corresponding cache space is quickly switched according to the cache location identifier. The implementation of the access path can be based on an abstract cache access interface (such as a unified cache access API layer) to mask the differences between cache types, so that both high-bandwidth memory cache and dynamic random access memory cache can be called through a unified interface.

[0052] When the target cache unit is determined, data positioning and reading are performed in combination with the extracted memory address offset, and data access can adopt a direct memory addressing mode to reduce the instruction path length. Atomicity and consistency of cache access need to be ensured during data access, for example, through read-write locks or lock-free concurrent access techniques, to ensure the correctness and consistency of the returned data in a multi-thread concurrent access scenario. After data extraction is completed, an access response is constructed, the positioned and extracted index node data is encapsulated into the response data structure, and the calling party is returned in a standard format. The entire process strictly depends on the efficient positioning of the index node mapping table and the cache path switching capability, and improves the data access performance and stability after search hits.

[0053] The embodiment efficiently completes the parsing of the unique identifier and the fast hash positioning by using the cached residence information in the index node mapping table when receiving the access request, ensures correct hits of the target index node in combination with conflict list traversal, and can immediately access the high-bandwidth memory cache or dynamic random access memory cache based on the cache location identifier and the memory address offset to extract data after a hit. This processing flow greatly reduces the delay of the data access path, reduces the dependence on access to persistent media, effectively supports fast data retrieval of index nodes in a high-concurrency and high-access-density environment, enables systems such as databases that require high-performance index access to still maintain low-latency and high-throughput data access characteristics under limited resources, and thus enhances the scalability and resource utilization efficiency of the overall data processing system.

[0054] In one embodiment, the above step S30 includes: S301, when no target residence information entry matching the unique identifier of the target index node is retrieved in the conflict list table at the target bucket position of the index node mapping table, a read command containing target index node positioning information is sent to a persistent storage interface; S302, the physical storage position of the target index node is located in the non-volatile storage medium according to the target index node positioning information through the persistent storage interface; S303, the target index node original data is read from the physical storage position; S304, the target index node original data is loaded into a data decoding buffer, and a cyclic redundancy check operation is performed on the target index node original data in the data decoding buffer; S305, when the cyclic redundancy check passes, a decoding operation is performed on the target index node original data, and the decoded target index node data is temporarily stored in a loading buffer.

[0055] In this embodiment, when the target inode resides information is not contained in the inode mapping table, the target inode data is retrieved from the non-volatile storage medium through the persistent path. This process flow first includes traversing the target bucket location conflict list in the inode mapping table for retrieval. The conflict list is a linear chain structure designed to solve the storage conflict when different key values in the hash table are mapped to the same bucket location, and the unique identifier and residence information entry are saved in the chain list node. When no matching unique identifier is found during the sequential retrieval process, it is determined that there is no corresponding target inode residence information in the inode mapping table.

[0056] On this basis, the access path is transferred to the persistent storage interface, which can be an NVMe controller, a SAS adapter, a cloud storage API, or other hardware or software interfaces that directly access non-volatile storage media. The target inode positioning information includes a unique identifier or its mapped physical storage path or offset. The read command is encapsulated and issued through the persistent storage interface to perform access operations on the non-volatile storage medium. The non-volatile storage medium includes but is not limited to SSD, HDD, solid state array, NAND Flash array, and can support sequential or random block access.

[0057] After the interface receives the read command, the corresponding physical block address is retrieved through the positioning information, and the readout operation on the physical storage location is completed to obtain the original data of the target inode. The original data is loaded into the data decoding buffer in the system memory after being read out, and the buffer is used for data integrity verification and subsequent decoding operations. Data integrity is verified by cyclic redundancy check (CRC). CRC is a polynomial check value of a data block, which is used to detect bit-level errors generated during storage or transmission. The algorithm source can adopt standard forms such as CRC-32, CRC-64, etc. to adapt to different data block sizes and error detection strength requirements.

[0058] When the CRC check passes, the data decoding operation is started, and the data decoding is determined according to the encoding storage format, for example, when the data block storage uses compression encoding, it needs to be decompressed and decoded, and when it uses redundancy encoding, it needs to be decoded for data error correction. The decoding algorithm can select algorithms such as Zstandard, LZ4, Reed-Solomon, etc. The decoded inode data is loaded into the loading buffer, which is a short-term cache area in memory, and can be used for subsequent decoding data to be directly written into the cache management unit or to be scheduled by the cache replacement strategy. The entire operation flow strictly follows the order to ensure that the data is safely, completely and efficiently loaded from the physical medium to the memory buffer, providing reliable input for the next step of data use.

[0059] The embodiment can make the system accurately and efficiently deal with the cache miss scenario, reduce the data access path delay, ensure the correctness and integrity of the index node data, and enhance the robustness of the data access path and the stability of the system as a whole.

[0060] In one embodiment, the step S40 comprises: S401, determining the metadata type mark of the target index node; S402, when the metadata type mark is a branch node, allocating a continuous memory space in the high-bandwidth memory cache as a branch node cache space; S403, copying the data of the target index node to the branch node cache space, and creating a first linked list node associated with the branch node cache space; S404, inserting the first linked list node into the head position of the least used linked list of the high-bandwidth memory cache; S405, when the metadata type mark is a leaf node, allocating a continuous memory space in the dynamic random access memory cache as a leaf node cache space; S406, copying the data of the target index node to the leaf node cache space, and creating a second linked list node associated with the leaf node cache space; S407, inserting the second linked list node into the head position of the least used linked list of the dynamic random access memory cache; S408, creating a new residence information entry in the index node mapping table to record the cache location identifier and memory address offset of the target index node.

[0061] In the embodiment, when the target index node is loaded into the cache, it is necessary to first parse the metadata type mark according to its data content or metadata field. The metadata type mark is a classification attribute recording the function or position of the node, which is used to indicate the role of the node in the tree structure, such as a branch node or a leaf node. The value of the metadata type mark can be derived from a predefined field in the index node metadata header, which can be represented by an enumeration value or a bit flag. The parsing process is based on fixed offset memory reading or structure field unpacking.

[0062] When the analysis result indicates that the target inode is a branch node, the operation logic enters the write path of the high-bandwidth memory cache space. In the high-bandwidth memory cache, the system allocates a continuous memory space according to page alignment, and the continuous memory space is a physically continuous page frame provided by a memory allocator interface (such as mmap, hugetlbfs, or NUMA-aware allocation) of a physical memory management unit, for guaranteeing high bandwidth and low latency of inode data access. The size of the branch node cache space is usually dynamically determined according to the original page size of the target inode data, for example, 4 KB or 8 KB. Subsequently, the data of the target inode is written into the branch node cache space through a memory copy operation, and the memory copy is in the form of memcpy or DMA transmission to ensure data consistency.

[0063] After the write is completed, in order to manage the position of the branch node cache space in the cache system and support subsequent cache replacement strategies, a linked list node needs to be created as a descriptor, and the linked list node internally maintains a pointer to the branch node cache space. The creation of the linked list node can be achieved by allocating an object from a linked list node object pool, and the linked list node object usually has a fixed size and contains fields such as a data pointer field, a predecessor pointer, and a successor pointer. The first linked list node after creation is inserted into the head position of the least frequently used linked list of the high-bandwidth memory cache, and the head position represents the most frequently used position. The insertion operation is completed by updating the predecessor and successor pointer relationship of the head pointer of the linked list and the new node, and after the insertion, the node immediately becomes a priority for high-bandwidth memory cache access.

[0064] If the analysis metadata type tag result indicates that the target inode is a leaf node, the write operation enters the dynamic random access memory cache path. A continuous memory space is allocated in the dynamic random access memory cache as a leaf node cache space, and the difference between the dynamic random access memory cache and the high-bandwidth memory cache mainly lies in access latency and capacity. The memory allocation can be achieved by a page granularity memory area provided by a regular malloc or slab allocator, and the allocated space also needs to meet the page size requirement of the target inode data. After copying the target inode data to the leaf node cache space, a linked list node is created as a descriptor, and the linked list node internally points to the leaf node cache space. The linked list node is inserted into the head position of the least frequently used linked list of the dynamic random access memory cache after allocation. The insertion logic is similar, and the node is placed as the most frequently accessed position of the leaf node cache by modifying the head pointer of the linked list.

[0065] Regardless of the type of target inode, after the cache write and the linked list management are completed, the residence information of the target inode needs to be registered in the inode mapping table. The inode mapping table is organized in the form of a hash table, and the residence information entry includes a cache location identifier and a memory address offset. The cache location identifier is used to indicate the cache area where the inode currently resides, and the memory address offset is used to accurately locate the physical address of the node data in the cache. The registration of the new residence information entry calculates the bucket position of the unique identifier of the target inode through a hash function, and inserts the residence information entry in the conflict linked list at the bucket position. The insertion position can be the head of the linked list or the tail of the linked list, and the specific strategy is optimized according to the retrieval efficiency. After the registration is completed, subsequent access to the target inode can be directly based on the inode mapping table to perform cache hit query, thereby reducing access delay.

[0066] The embodiment accurately identifies the category of the target inode by first parsing the metadata type marker, uses high-bandwidth memory cache and dynamic random access memory cache as storage spaces for different types of nodes respectively, and cooperates with the linked list node management mechanism corresponding to the branch node cache space and the leaf node cache space respectively, to realize efficient classified storage and ordered management of the cache space, quickly determine the access priority during access, accurately register the residence position and physical memory offset of the target inode in the inode mapping table, support fast retrieval and consistent update of the cache layer, thereby improving cache hit rate, reducing cross-layer access delay, optimizing concurrent throughput capacity of the access path, and taking into account the space utilization and access performance of different types of nodes.

[0067] In one embodiment, the above step S50 includes: S501, monitoring the current available space of the high-bandwidth memory cache; S502, when the current available space is lower than a preset space threshold, determining a tail position of the least recently used linked list of the high-bandwidth memory cache; S503, obtaining a tail linked list node at the tail position; S504, extracting an associated to-be-migrated branch node cache space from the tail linked list node; S505, copying data in the to-be-migrated branch node cache space to the dynamic random access memory cache; S506, creating a new linked list node containing a data copy pointer of the to-be-migrated branch node cache space; S507, inserting the new linked list node into a head position of the least recently used linked list of the dynamic random access memory cache; S508, removing the tail linked list node from the least recently used linked list of the high-bandwidth memory cache; S509, updating the resident information entry corresponding to the branch node cache space to be migrated in the index node mapping table to modify the cache location identifier to dynamic random access memory cache and update the memory address offset.

[0068] In the embodiment, the current available space of the high-bandwidth memory cache is monitored by continuously sampling and counting the number or capacity of used memory blocks and unused memory blocks in the cache module. This monitoring can be achieved by maintaining an atomic counter when the cache is allocated and released to obtain accurate real-time available capacity. The value of the counter is updated once after each branch node cache space allocation or release. The condition that the available space is lower than the preset space threshold is determined by comparing the current available space counter value with the threshold parameter. The threshold parameter can be set based on the percentage of the cache capacity or the absolute byte number, for example, when the available space is less than 5% of the total capacity, the migration is triggered.

[0069] Determining the tail position of the least frequently used list of the high-bandwidth memory cache requires direct access to the data structure of the list. The least frequently used list is implemented as a doubly linked list, where the tail pointer always points to the list node with the longest usage time. By using the tail pointer, the tail position can be quickly located, avoiding traversal of the entire list and improving efficiency. Obtaining the tail list node at the tail position means directly reading the node object pointed to by the tail pointer. The node object contains a pointer to the cache space.

[0070] Extracting the associated branch node cache space to be migrated from the tail list node means reading the cache space pointer field in the list node to parse the memory address interval pointed to. This memory address interval stores the entire data content of the branch node to be migrated. Copying the data in the branch node cache space to be migrated to the dynamic random access memory cache is achieved through a memory copy operation. The target is a pre-allocated continuous memory region in the dynamic random access memory cache, ensuring that the data content does not change after migration and the addresses are continuous. Memory copying can be achieved through high-performance memory copy instruction sets (such as AVX acceleration) or DMA channels to improve copying efficiency.

[0071] The purpose of creating a new list node containing a data copy pointer of the branch node cache space to be migrated is to manage the data copy in the dynamic random access memory cache through a list. The new list node object is allocated by a memory pool or a special object allocator, which maintains a pointer to the data copy and the predecessor and successor pointers of the doubly linked list. The new list node is inserted into the head position of the least frequently used list of the dynamic random access memory cache, which represents the most recently accessed node to ensure that the migrated branch node can be quickly hit in subsequent access. The insertion operation is completed by modifying the list head pointer and updating the pointer pointing relationship between the list nodes.

[0072] Removing the tail list node from the least used list of the high bandwidth memory cache is a cleaning operation on the cache management structure of the high bandwidth memory cache after the migration operation is completed. The process is achieved by modifying the successor pointer of the predecessor node of the tail to NULL, and updating the tail pointer of the list to point to the predecessor node, while releasing the memory resources occupied by the original tail list node object.

[0073] Updating the resident information entry corresponding to the cache space of the branch node to be migrated in the index node mapping table means modifying the cache location identification field of the node from the high bandwidth memory cache to the dynamic random access memory cache, and updating the memory address offset field according to the memory address of the data copy in the dynamic random access memory cache. This update needs to reposition the bucket position of the branch node to be migrated in the index node mapping table through a hash function, and retrieve the entry matching the unique identifier of the branch node to be migrated in the conflict list at the bucket position. After updating the cache location identification and memory address offset of the resident information entry, it is ensured that the subsequent query can accurately obtain the new resident location and physical address of the node.

[0074] The embodiment can actively initiate a migration operation when the cache is close to saturation by monitoring the available space state of the high bandwidth memory cache in real time, accurately select the least used list tail node as the migration object, and realize the migration of the low access frequency branch node from the high bandwidth memory cache to the dynamic random access memory cache. During the migration process, data duplication and list node reconstruction are used to maintain data integrity and cache consistency. After the migration is completed, the resident information is updated in the index node mapping table, so that subsequent queries can accurately access the data without sensing the migration details, improve the dynamic adaptation ability of the cache system to hot and cold data, reduce the pressure on the high bandwidth memory cache, and effectively improve the overall cache hit rate and access performance.

[0075] In one embodiment, the above step S60 includes: S601, monitoring the access count of the branch node in the dynamic random access memory cache; S602, when the access count exceeds the pre-designed threshold, marking the corresponding branch node cache space as a hot node to be migrated; S603, locating the list node of the hot node to be migrated in the least used list of the dynamic random access memory cache; S604, copying the data in the cache space of the hot node to be migrated to the high bandwidth memory cache; S605, creating a new list node containing a data copy pointer of the cache space of the hot node to be migrated; S606, inserting the new list node into the tail position of the least used list of the high bandwidth memory cache; S607, access a tail position of the high-bandwidth memory cache least recently used list, and obtain a to-be-replaced list node located at the tail position; S608, extract an associated to-be-replaced branch node cache space from the to-be-replaced list node; S609, copy data in the to-be-replaced branch node cache space to a dynamic random access memory cache; S610, create another new list node containing a data copy pointer of the to-be-replaced branch node cache space; S611, insert the another new list node into a head position of a dynamic random access memory cache least recently used list; S612, update a residence information entry of the to-be-migrated hot node in the index node mapping table to modify a cache position identifier to the high-bandwidth memory cache and update a memory address offset; S613, update a residence information entry of the to-be-replaced branch node in the index node mapping table to modify a cache position identifier to the dynamic random access memory cache and update a memory address offset.

[0076] In the embodiment, monitoring the access count of the branch node in the dynamic random access memory cache is completed by binding an independent access counter to each branch node cache space in the cache unit. The counter is updated by an atomic increment instruction or a transactional counting unit, and can keep correct access frequency records when multiple threads are concurrently accessed. The access count exceeding the preset threshold is determined by comparing the access frequency threshold of the dynamic random access memory cache with the real-time access count. The threshold can be adjusted according to the business scenario, such as the percentile of the average access distribution or the historical statistical distribution dynamic optimization.

[0077] The to-be-migrated hot node is marked by setting a specific flag bit for the corresponding branch node cache space or adding a flag field in the cache metadata structure. The flag field is used for subsequent positioning of the node in the list and as an identification of the migration object. The list node of the to-be-migrated hot node is positioned by traversing the list nodes in the dynamic random access memory cache least recently used list and comparing the cache space pointers with the hot node cache space pointers. After positioning, the pointer of the list node is directly held.

[0078] The data in the cache space of the hot node to be migrated is copied to the high-bandwidth memory cache by a memory copy function or a DMA channel to copy data from the dynamic random access memory cache specified address range to the pre-allocated continuous memory area of the high-bandwidth memory cache. The new linked list node containing the data copy pointer of the cache space of the hot node to be migrated is created by allocating a node structure through the linked list node memory allocator, and recording the memory address of the data copy and the associated context meta information in the pointer field thereof. The new linked list node is inserted into the tail position of the least used linked list of the high-bandwidth memory cache by pointing the predecessor pointer of the new node to the current tail node, pointing the successor pointer of the tail node to the new node, and updating the linked list tail pointer, so that the node becomes the end of the linked list, indicating that it has just migrated in and needs to stay for a long time.

[0079] The tail position of the least used linked list of the high-bandwidth memory cache is accessed and the hot node to be replaced linked list node located at the position is obtained by directly accessing the linked list tail pointer to obtain the memory reference of the node entity. The cache space of the branch node to be replaced is extracted by reading the value of the cache space pointer field in the hot node to be replaced linked list node, and locking the target region of the dynamic random access memory cache corresponding to the cache space. The data is copied to the dynamic random access memory cache by writing the data into the new continuous memory space allocated in the dynamic random access memory cache through memory copy, to ensure that the replaced data is completely moved in.

[0080] Another new linked list node containing the data copy pointer of the cache space of the branch node to be replaced is created by generating a linked list node through the memory object allocator and filling the cache space pointer field thereof with the memory address of the data copy in the dynamic random access memory cache. The other new linked list node is inserted into the head position of the least used linked list of the dynamic random access memory cache by pointing the successor pointer of the new node to the current linked list head node, pointing the predecessor pointer of the linked list head node to the new node, and updating the linked list head pointer, so that the replaced node has the highest priority immediately after migration.

[0081] Updating the residence information entry of the hot node to be migrated in the index node mapping table means locating the bucket position of the hot node to be migrated in the index node mapping table according to its unique identifier through a hash function, searching and updating the cache location identifier of the corresponding entry in the conflict linked list at the bucket position to the high-bandwidth memory cache, and updating the memory address offset to the physical address of the data copy of the node in the high-bandwidth memory cache. Updating the residence information entry of the branch node to be replaced means locating the storage position of the replaced node in the index node mapping table in the same way, and updating the cache location identifier to the dynamic random access memory cache and the memory address offset to the physical address offset of the new storage position thereof.

[0082] Example Description: In a communication network management platform, for fast index access of configuration data and state data between 5G base stations, the system needs to manage the operation information of a large number of distributed communication nodes, which is organized in a multi-level tree structure and stored in the backend database of the system using a B-tree index-based data structure. Due to the high concurrent access characteristics of base station state data, especially the frequent reading of upper-level network topology configuration nodes and less access to leaf nodes, a cache management mechanism for high-performance communication data processing is needed to speed up the access of these index nodes.

[0083] First, the system establishes a special index node mapping table using a hash table data structure, allocates continuous memory space and initializes the bucket array. This mapping table associates each communication network index node with its cache residency status, calculates the specific bucket position in the bucket array through a hash function on the node's unique identifier, and saves the residency information in the bucket position, including cache location identifier, memory address offset, and last access timestamp. When the bucket position conflicts, the system appends conflict entries through a linked list to ensure that node information can be quickly retrieved even under high load conditions.

[0084] When the communication system receives an access request for a target communication index node, it first parses the request data packet and extracts the node's unique identifier. The hash function is used to quickly locate the target bucket, and the corresponding residency information is retrieved in the conflict linked list in the bucket position. After hitting, the cache location identifier and memory address offset are extracted from the residency information. If the cache location identifier indicates that the data resides in the high-bandwidth memory cache, the high-bandwidth memory cache is directly accessed to obtain the node data as the access response; if it indicates that the data resides in the dynamic random access memory cache, the dynamic random access memory cache is directly accessed to obtain the data, ensuring low-latency processing of 5G network node data requests.

[0085] If the index node mapping table does not contain the residency information of the target communication index node, the system will read the target index node data from the underlying non-volatile storage medium. This process locates the target node's address on the physical medium through the persistent storage interface, reads the original data to the data decoding buffer, performs cyclic redundancy check to verify data integrity, completes data decoding and temporary storage in the loading buffer after verification.

[0086] After successfully loading the data, the system determines the node type according to the index node metadata type tag. If the node is a branch node, it is written to the high-bandwidth memory cache, a continuous memory space is allocated to store the node data, a corresponding linked list node is created and inserted into the head position of the least frequently used linked list of the high-bandwidth memory cache, so that it immediately has the priority of being accessed. If the node is a leaf node, it is written to the dynamic random access memory cache, and the same cache space allocation, linked list node creation and insertion operations are performed, and its residence information is registered in the index node mapping table, recording the cache location identifier and address offset, which facilitates subsequent fast retrieval.

[0087] During system operation, the high-bandwidth memory cache space is limited, and the system continuously monitors the available space of the high-bandwidth memory cache. When the available space is below a set threshold, branch node migration is triggered, the tail linked list node of the least frequently used linked list is taken as the migration object, its associated branch node cache space data is extracted and copied to the dynamic random access memory cache, a new linked list node corresponding to the data copy is created and inserted into the head position of the least frequently used linked list of the dynamic random access memory cache, the original tail linked list node is removed from the high-bandwidth memory cache linked list, and the cache location identifier and memory address offset of the node are updated in the index node mapping table to ensure consistency between the cache state and the mapping table.

[0088] In addition, for the dynamic random access memory cache, when the access count of a certain branch node exceeds a preset threshold, the system identifies the node as a hot node and triggers the hot node migration process. The system locates the position of the hot node in the least frequently used linked list of the dynamic random access memory cache, copies the hot node cache space data to the high-bandwidth memory cache, and creates and inserts a new linked list node at the tail position of the least frequently used linked list of the high-bandwidth memory cache. In order to maintain the balance of cache capacity, the system obtains a cold node from the tail of the least frequently used linked list of the high-bandwidth memory cache as a replacement object, extracts the cold node cache space data and copies it to the dynamic random access memory cache, creates another new linked list node and inserts it into the head position of the least frequently used linked list of the dynamic random access memory cache. Finally, the residence information of the hot node and the cold node in the index node mapping table is updated, and their cache locations are marked as the high-bandwidth memory cache or the dynamic random access memory cache, respectively, and the memory address offset is updated.

[0089] The embodiment can accurately identify the hot branch node by fine monitoring of the branch node access count in the dynamic random access memory cache, and timely migrate the hot node to the high bandwidth memory cache when the access frequency exceeds the set threshold. In the migration process, the tail node of the linked list is selected as the replacement object to move the cold data from the high bandwidth memory cache to the dynamic random access memory cache, forming a dynamic balance adjustment of cold and hot data. Through data replication, linked list node reconstruction and index node mapping table updating, the data consistency and state traceability of the entire system are maintained. In the subsequent access process, the cache can be accurately hit without sensing the migration details, effectively improving the utilization rate of the high bandwidth memory cache space, avoiding storing long-term unaccessed data in the cache, enhancing the ability of the cache structure to adapt to multi-thread high concurrency and high frequency access, and improving the running efficiency and response speed of the overall database system or data processing system.

[0090] In an embodiment, a hybrid memory index management device is provided, which corresponds to the hybrid memory index management method in the above embodiments. Referring to Figure 3 , Figure 3 The figure is a function module schematic diagram of a preferred embodiment of the hybrid memory index management device of the present application. The mapping table management module 10, the cache access module 20, the persistent read module 30, the cache write module 40, the high bandwidth memory cache migration module 50 and the dynamic random access memory cache migration module 60. The detailed description of each function module is as follows: The mapping table management module 10 is used to establish an index node mapping table for recording the residence information of each index node in the storage resource; The cache access module 20 is used to receive an access request for a target index node, retrieve the residence information of the target index node in the index node mapping table, and provide the target index node from the corresponding cache when hit; The persistent read module 30 is used to read the target index node from the non-volatile storage medium when the index node mapping table does not contain the residence information of the target index node; The cache write module 40 is used to write the target index node as a branch node into the high bandwidth memory cache when the target index node is a branch node, and write the target index node as a leaf node into the dynamic random access memory cache when the target index node is a leaf node; and register the residence information of the target index node in the index node mapping table; The high bandwidth memory cache migration module 50 is used to execute the migration of the branch node to the dynamic random access memory cache when the high bandwidth memory cache satisfies the first trigger condition, and update the corresponding residence information in the index node mapping table; The DRAM cache migration module 60 is configured to execute migration of the branch node to the HBM cache and corresponding node replacement when the DRAM cache satisfies a second trigger condition, and update corresponding residency information in the index node mapping table.

[0091] In one embodiment, the mapping table management module 10 is specifically configured to: Create an index node mapping table using a hash table data structure; Allocate continuous memory space for the index node mapping table and initialize the bucket array; When a new index node is added, a unique identifier of the index node is extracted to generate a key value; Processing the key value using a hash function to determine a bucket position of the index node in an index node mapping table; storing a resident information entry including a cache location identifier, a memory address offset, and a last access timestamp at the bucket location; When a bucket position conflict in the index node mapping table is detected, a linked list method is used to add a conflicting entry to the index node mapping table; When the index node cache location changes, the residency information of the corresponding entry in the index node mapping table is updated.

[0092] In one embodiment, the cache access module 20 is specifically configured to: Parse the access request message to obtain the unique identifier of the target index node; Processing the unique identifier of the target index node using a hash function to determine the target bucket position of the target index node in the index node mapping table; Sequentially searching the conflict linked list of the target bucket position to determine whether there is a target resident information entry that matches the unique identifier of the target index node; When a search hits, extracting a target cache location identifier and a memory address offset from the target residency information entry; According to the target cache location identifier, selecting a high bandwidth memory cache unit or a dynamic random access memory cache unit as a target cache unit; The target index node data is located in the target cache unit using the memory address offset and the target index node data is read as an access response.

[0093] In one embodiment, the persistent read module 30 is specifically configured to: When a target resident information entry matching the unique identifier of the target index node is not retrieved in the conflict linked list of the target bucket position of the index node mapping table, sending a read command containing the target index node location information to the persistent storage interface; locating a physical storage location of the target inode in the non-volatile storage medium according to the target inode locating information through the persistent storage interface; reading target inode original data from the physical storage location; loading the target inode original data into a data decoding buffer and performing a cyclic redundancy check operation on the target inode original data in the data decoding buffer; when the cyclic redundancy check passes, performing a decoding operation on the target inode original data and temporarily storing the decoded target inode data in a loading buffer.

[0094] In an embodiment, the cache writing module 40 is specifically configured to: determining a metadata type mark of the target inode; when the metadata type mark is a branch node, allocating a continuous memory space in the high-bandwidth memory cache as a branch node cache space; copying data of the target inode to the branch node cache space and creating a first linked list node associated with the branch node cache space; inserting the first linked list node into a head position of a least recently used linked list of the high-bandwidth memory cache; when the metadata type mark is a leaf node, allocating a continuous memory space in the dynamic random access memory cache as a leaf node cache space; copying data of the target inode to the leaf node cache space and creating a second linked list node associated with the leaf node cache space; inserting the second linked list node into a head position of a least recently used linked list of the dynamic random access memory cache; creating a new residence information entry in the inode mapping table to record a cache location identifier and a memory address offset of the target inode.

[0095] In an embodiment, the high-bandwidth memory cache migration module 50 is specifically configured to: monitoring a current available space of the high-bandwidth memory cache; when the current available space is lower than a preset space threshold, determining a tail position of a least recently used linked list of the high-bandwidth memory cache; obtaining a tail linked list node at the tail position; extracting an associated to-be-migrated branch node cache space from the tail linked list node; copying data in the to-be-migrated branch node cache space to the dynamic random access memory cache; creating a new linked list node containing a data copy pointer of the to-be-migrated branch node cache space; inserting the new list node into a head position of the dynamic random access memory cache least recently used list; removing the tail list node from the high bandwidth memory cache least recently used list; updating a resident information entry corresponding to the to-be-migrated branch node cache space in the index node mapping table to modify a cache location identifier to a dynamic random access memory cache and update a memory address offset.

[0096] In an embodiment, the dynamic random access memory cache migration module 60 is specifically configured to: monitoring access counts of branch nodes in the dynamic random access memory cache; when the access count exceeds a pre-designed threshold, marking a corresponding branch node cache space as a to-be-migrated hot node; locating a list node of the to-be-migrated hot node in a dynamic random access memory cache least recently used list; copying data in the to-be-migrated hot node cache space to a high bandwidth memory cache; creating a new list node containing a data copy pointer of the to-be-migrated hot node cache space; inserting the new list node into a tail position of the high bandwidth memory cache least recently used list; accessing the tail position of the high bandwidth memory cache least recently used list and obtaining a to-be-replaced list node located at the tail position; extracting an associated to-be-replaced branch node cache space from the to-be-replaced list node; copying data in the to-be-replaced branch node cache space to the dynamic random access memory cache; creating another new list node containing a data copy pointer of the to-be-replaced branch node cache space; inserting the another new list node into a head position of the dynamic random access memory cache least recently used list; updating a resident information entry of the to-be-migrated hot node in the index node mapping table to modify a cache location identifier to a high bandwidth memory cache and update a memory address offset; updating a resident information entry of the to-be-replaced branch node in the index node mapping table to modify a cache location identifier to a dynamic random access memory cache and update a memory address offset.

[0097] In an embodiment, a computer device is provided, which can be a server, and an internal structure diagram of the computer device can be as shown in Figure 4As shown in the figure. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide determination and control capability. The memory of the computer device includes non-volatile and / or volatile storage medium, internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with the external client through the network connection. The computer program is executed by the processor to realize the function or step of the server side of the hybrid memory index management method.

[0098] In one embodiment, a computer device is provided, which can be a client, and its internal structure diagram can be as shown in the figure. Figure 5 As shown in the figure. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide determination and control capability. The memory of the computer device includes non-volatile storage medium, internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with the external server through the network connection. The computer program is executed by the processor to realize the function or step of the client side of the hybrid memory index management method.

[0099] In one embodiment, a computer device is provided, including a memory, a processor and a computer program stored on the memory and executable on the processor, and the processor executes the computer program to realize the following steps: Establishing an index node mapping table for recording the residence information of each index node in the storage resource; Receiving an access request for a target index node, searching the residence information of the target index node in the index node mapping table, and providing the target index node from the corresponding cache when hit; When the index node mapping table does not contain the residence information of the target index node, reading the target index node from the non-volatile storage medium; When the target index node is a branch node, writing the target index node as a branch node into the high bandwidth memory cache; when the target index node is a leaf node, writing the target index node as a leaf node into the dynamic random access memory cache; and registering the residence information of the target index node in the index node mapping table; When the high bandwidth memory cache meets the first trigger condition, performing the migration of the branch node to the dynamic random access memory cache, and updating the corresponding residence information in the index node mapping table; when the high bandwidth memory cache meets a second trigger condition, performing migration of the branch node to the dynamic random access memory cache and corresponding node replacement, and updating corresponding residence information in the index node mapping table.

[0100] In one embodiment, a computer readable storage medium is provided, having stored thereon a computer program, which when executed by a processor implements the following steps: establishing an index node mapping table for recording residence information of each index node in a storage resource; receiving an access request for a target index node, retrieving residence information of the target index node in the index node mapping table, and providing the target index node from a corresponding cache when a hit is made; when the index node mapping table does not contain residence information of the target index node, reading the target index node from a non-volatile storage medium; when the target index node is a branch node, writing the target index node as a branch node to a high bandwidth memory cache; when the target index node is a leaf node, writing the target index node as a leaf node to a dynamic random access memory cache; and registering residence information of the target index node in the index node mapping table; when the high bandwidth memory cache meets a first trigger condition, performing migration of the branch node to the dynamic random access memory cache, and updating corresponding residence information in the index node mapping table; when the dynamic random access memory cache meets a second trigger condition, performing migration of the branch node to the high bandwidth memory cache and corresponding node replacement, and updating corresponding residence information in the index node mapping table.

[0101] It should be noted that the functions or steps that the computer readable storage medium or the computer device can implement described above can correspond to the related descriptions of the server side and the client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0102] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0103] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of functional units and modules is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0104] It should be noted that the above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A hybrid memory index management method, characterized in that: The following steps are involved: Establishing an index node mapping table for recording the residency information of each index node in the storage resource; receiving an access request for a target index node, retrieving the residency information of the target index node from the index node mapping table, and providing the target index node from a corresponding cache when a hit is found; When the index node mapping table does not include the residency information of the target index node, reading the target index node from a non-volatile storage medium; When the target index node is a branch node, writing the target index node as a branch node into a high-bandwidth memory cache; When the target index node is a leaf node, writing the target index node as a leaf node into a dynamic random access memory cache; and registering the residency information of the target index node in the index node mapping table; When the high bandwidth memory cache satisfies a first trigger condition, executing migration of the branch node to the dynamic random access memory cache, and updating corresponding residency information in the index node mapping table; When the dynamic random access memory cache satisfies a second trigger condition, the branch node is migrated to the high bandwidth memory cache and the corresponding node is replaced, and corresponding residency information is updated in the index node mapping table.

2. The hybrid memory index management method according to claim 1, wherein: Establish an index node mapping table for recording the residency information of each index node in the storage resource, including: Create an index node mapping table using a hash table data structure; Allocate continuous memory space for the index node mapping table and initialize the bucket array; When a new index node is added, a unique identifier of the index node is extracted to generate a key value; Processing the key value using a hash function to determine a bucket position of the index node in an index node mapping table; storing a resident information entry including a cache location identifier, a memory address offset, and a last access timestamp at the bucket location; When a bucket position conflict in the index node mapping table is detected, a linked list method is used to add a conflicting entry to the index node mapping table; When the index node cache location changes, the residency information of the corresponding entry in the index node mapping table is updated.

3. The hybrid memory index management method according to claim 1, wherein: Receiving an access request for a target index node, retrieving residency information of the target index node from the index node mapping table, and providing the target index node from a corresponding cache when a hit is found, comprising: Parse the access request message to obtain the unique identifier of the target index node; Processing the unique identifier of the target index node using a hash function to determine the target bucket position of the target index node in the index node mapping table; Sequentially searching the conflict linked list of the target bucket position to determine whether there is a target resident information entry that matches the unique identifier of the target index node; When a search hits, extracting a target cache location identifier and a memory address offset from the target residency information entry; According to the target cache location identifier, selecting a high bandwidth memory cache unit or a dynamic random access memory cache unit as a target cache unit; The target index node data is located in the target cache unit using the memory address offset and the target index node data is read as an access response.

4. The hybrid memory index management method according to claim 1, wherein: When the index node mapping table does not include the residency information of the target index node, reading the target index node from a non-volatile storage medium includes: When a target resident information entry matching the unique identifier of the target index node is not retrieved in the conflict linked list of the target bucket position of the index node mapping table, sending a read command containing the target index node location information to the persistent storage interface; Locating the physical storage location of the target index node in a non-volatile storage medium according to the target index node location information through the persistent storage interface; Read the target index node original data from the physical storage location; Loading the target index node original data into a data decoding buffer, and performing a cyclic redundancy check operation on the target index node original data in the data decoding buffer; When the cyclic redundancy check passes, a decoding operation is performed on the target index node original data, and the decoded target index node data is temporarily stored in a loading buffer.

5. The hybrid memory index management method according to claim 1, wherein: When the target index node is a branch node, the target index node is written into a high-bandwidth memory cache as a branch node; when the target index node is a leaf node, the target index node is written into a dynamic random access memory cache as a leaf node; Registering the residency information of the target index node in the index node mapping table includes: Determine the metadata type tag of the target index node; When the metadata type is marked as a branch node, allocating continuous memory space in the high-bandwidth memory cache as a branch node cache space; Copying the data of the target index node to the branch node cache space, and creating a first linked list node associated with the branch node cache space; Inserting the first linked list node into the head position of the least used linked list of the high bandwidth memory cache; When the metadata type is marked as a leaf node, a continuous memory space is allocated in the dynamic random access memory cache as a leaf node cache space; Copying the data of the target index node to the leaf node cache space, and creating a second linked list node associated with the leaf node cache space; Inserting the second linked list node into the head position of the least used linked list of the dynamic random access memory cache; A new resident information entry is created in the index node mapping table to record the cache location identifier and memory address offset of the target index node.

6. The hybrid memory index management method according to claim 1, wherein: When the high bandwidth memory cache satisfies a first trigger condition, executing migration of the branch node to the dynamic random access memory cache and updating corresponding residency information in the index node mapping table, including: monitoring current available space of the high-bandwidth memory cache; When the current available space is lower than a preset space threshold, determining the tail position of the high-bandwidth memory cache least-used linked list; Obtaining the tail linked list node located at the tail position of the table; Extracting the associated branch node cache space to be migrated from the tail linked list node; Copying the data in the cache space of the branch node to be migrated to the dynamic random access memory cache; Creating a new linked list node containing a data copy pointer of the cache space of the branch node to be migrated; Inserting the new linked list node into the head position of the least used linked list of the dynamic random access memory cache; Remove the tail linked list node from the high bandwidth memory cache least used linked list; The resident information entry corresponding to the cache space of the to-be-migrated branch node is updated in the index node mapping table to modify the cache location identifier to dynamic random access memory cache, and update the memory address offset.

7. The hybrid memory index management method according to claim 1, wherein: When the dynamic random access memory cache satisfies the second trigger condition, executing migration of the branch node to the high bandwidth memory cache and corresponding node replacement, and updating corresponding residency information in the index node mapping table, including: monitoring access counts of branch nodes in the dynamic random access memory cache; When the access count exceeds a preset count threshold, the corresponding branch node cache space is marked as a hot node to be migrated; Locate the linked list node of the hotspot node to be migrated in the least used linked list of the dynamic random access memory cache; Copy the data in the cache space of the hotspot node to be migrated to the high-bandwidth memory cache; Creating a new linked list node containing a data copy pointer of the cache space of the hotspot node to be migrated; Inserting the new linked list node into the tail position of the least used linked list of the high bandwidth memory cache; Accessing the tail position of the least used linked list of the high bandwidth memory cache and obtaining the linked list node to be replaced located at the tail position; Extracting the associated to-be-replaced branch node cache space from the to-be-replaced linked list node; Copying the data in the cache space of the branch node to be replaced to the dynamic random access memory cache; Creating another new linked list node containing a data copy pointer of the branch node cache space to be replaced; Inserting the other new linked list node into the head position of the least used linked list of the dynamic random access memory cache; Updating the resident information entry of the hot node to be migrated in the index node mapping table to modify the cache location identifier to a high-bandwidth memory cache and update the memory address offset; The resident information entry of the to-be-replaced branch node is updated in the index node mapping table to modify the cache location identifier to dynamic random access memory cache and update the memory address offset.

8. A hybrid memory index management device, characterized in that: The hybrid memory index management device includes: A mapping table management module, used to establish an index node mapping table for recording the resident information of each index node in the storage resource; a cache access module, configured to receive an access request for a target index node, retrieve the residency information of the target index node from the index node mapping table, and provide the target index node from a corresponding cache when a hit is found; a persistent reading module, configured to read the target index node from a non-volatile storage medium when the index node mapping table does not contain the resident information of the target index node; a cache write module, configured to write the target index node as a branch node into a high-bandwidth memory cache when the target index node is a branch node; and to write the target index node as a leaf node into a dynamic random access memory cache when the target index node is a leaf node; and to register the residency information of the target index node in the index node mapping table; a high-bandwidth memory cache migration module, configured to execute migration of the branch node to the dynamic random access memory cache and update corresponding residency information in the index node mapping table when the high-bandwidth memory cache satisfies a first trigger condition; The dynamic random access memory cache migration module is used to execute the migration of the branch node to the high bandwidth memory cache and the corresponding node replacement when the dynamic random access memory cache meets the second trigger condition, and update the corresponding residency information in the index node mapping table.

9. A computer device, characterized in that: The computer device includes a memory, a processor, and a hybrid memory index management program stored in the memory and capable of running on the processor. When the hybrid memory index management program is executed by the processor, the steps of the hybrid memory index management method as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that A hybrid memory index management program is stored on the storage medium, and when the hybrid memory index management program is executed by the processor, the steps of the hybrid memory index management method according to any one of claims 1 to 7 are implemented.

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