Quantum circuit processing method and device based on binary decision diagram counting

Abstract

The invention relates to a quantum circuit processing method and device based on binary decision diagram counting. The method comprises the steps that a quantum circuit recorded in a quantum circuit file is converted into a corresponding initial power sum formula; based on a task type of a to-be-processed task for the quantum circuit, processing the power sum formula to obtain a target power sum formula; and constructing a corresponding multi-terminal binary decision diagram based on the target power sum expression, and processing the multi-terminal binary decision diagram to obtain a processing result of the to-be-processed task.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of digital integrated circuits, in particular to a quantum circuit processing method and device based on binary decision diagram counting. BACKGROUND

[0002] Quantum circuit analysis is an important research field in quantum computing, which can assist in the design of quantum algorithms, verify the function of quantum circuits, and has a wide range of applications in quantum compilation and quantum computing system structure research.

[0003] In related technologies, quantum circuits are analyzed based on state vectors or tensor networks, but in the case of large quantum circuit scale, the efficiency is often low, and even the analysis task cannot be completed due to excessive storage and computing resource requirements. SUMMARY

[0004] To overcome the problems in the related art, the embodiments of the present disclosure provide a quantum circuit processing method and device based on binary decision diagram counting to solve the defects in the related art.

[0005] According to a first aspect of an embodiment of the present disclosure, a quantum circuit processing method based on binary decision diagram counting is provided, the method comprising:

[0006] Converting a quantum circuit recorded in a quantum circuit file into a corresponding initial power sum formula;

[0007] Based on the task type of the to-be-processed task of the quantum circuit, processing the power sum formula to obtain a target power sum formula;

[0008] Based on the target power sum formula, constructing a corresponding multi-terminal binary decision diagram, and processing the multi-terminal binary decision diagram to obtain a processing result of the to-be-processed task.

[0009] In one possible embodiment of the present disclosure, the conversion of the quantum circuit recorded in the quantum circuit file into the corresponding initial power sum formula comprises:

[0010] Based on a pre-configured set of quantum gates, configuring variables for each circuit in the quantum circuit recorded in the quantum circuit file;

[0011] For each quantum gate in the quantum circuit, based on the variables on the input line and the variables on the output line of the quantum gate, generating a power expression of the quantum gate;

[0012] Based on the power expression of each quantum gate in the quantum circuit and the circuit between the quantum gates, constructing an initial power sum formula for representing the quantum circuit.

[0013] In a possible embodiment of the present disclosure, the quantum circuit comprises a plurality of quantum bits, and each quantum bit has at least one quantum gate;

[0014] The variable is configured for each line in the quantum circuit recorded in the quantum circuit file based on the pre-configured set of quantum gates, comprising:

[0015] A variable is configured for each quantum bit;

[0016] For each quantum gate on each quantum bit, a variable is configured for the input line and the output line of the quantum gate based on the attribute of the quantum gate, wherein the attribute of the quantum gate is used to represent the relationship between the input variable and the output variable of the quantum gate.

[0017] In a possible embodiment of the present disclosure, the variable is configured for the input line and the output line of the quantum gate based on the attribute of the quantum gate, comprising:

[0018] If the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are the same, the variable on the input line of the quantum gate is configured as the variable on the output line of the quantum gate.

[0019] If the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are different, a new variable different from the variable on the input line of the quantum gate is configured on the output line of the quantum gate.

[0020] In a possible embodiment of the present disclosure, the power sum formula is processed based on the task type of the to-be-processed task of the quantum circuit to obtain a target power sum formula, comprising:

[0021] If the task type is amplitude calculation, the input variable of the initial power sum formula is assigned a value of 0, the output variable of the initial power sum formula is assigned a preset amplitude, and the internal variables of the initial power sum formula are summed to obtain a target power sum formula.

[0022] In a possible embodiment of the present disclosure, the method further comprises:

[0023] If the initial power sum formula represents that the input variable and the output variable are the same and the assignment is contradictory, the processing result of the to-be-processed task is set to 0.

[0024] In a possible embodiment of the present disclosure, the power sum formula is processed based on the task type of the to-be-processed task of the quantum circuit to obtain a target power sum formula, comprising:

[0025] If the task type is measurement result sampling, an expression for characterizing the target measurement result is determined based on the target measurement result and the initial sum-of-powers formula, and the expression is determined as the target sum-of-powers formula.

[0026] In a possible embodiment of the present disclosure, the processing of the sum-of-powers formula based on the task type of the task to be processed for the quantum circuit to obtain a target sum-of-powers formula comprises:

[0027] If the task type is equivalence detection, an expression for characterizing a preset operation result of unitary matrices of two quantum circuits to be detected is determined based on the initial sum-of-powers formula of the two quantum circuits, and the expression is determined as the target sum-of-powers formula, where the preset operation result of the unitary matrices of the two quantum circuits is used to characterize whether the two quantum circuits have equivalence.

[0028] In a possible embodiment of the present disclosure, the preset operation result of the unitary matrices of the two quantum circuits comprises the following:

[0029] a trace of an inner product of a conjugate transpose of a unitary matrix of one of the two quantum circuits and a unitary matrix of the other quantum circuit.

[0030] In a possible embodiment of the present disclosure, the constructing of the corresponding multiterm binary decision diagram based on the target sum-of-powers formula comprises:

[0031] dividing a plurality of summation terms of a multivariate linear polynomial in the target sum-of-powers formula into a plurality of groups, and constructing a multiterm binary decision diagram based on summation terms in each group, respectively;

[0032] constructing the multiterm binary decision diagram corresponding to the target sum-of-powers formula based on the multiterm binary decision diagrams of the groups.

[0033] In a possible embodiment of the present disclosure, the constructing of the corresponding multiterm binary decision diagram based on the target sum-of-powers formula comprises:

[0034] determining an order of variables in the target sum-of-powers formula in the multiterm binary decision diagram based on at least one of the following: an order of the quantum bits involved, an order of the quantum gates connected, and a sorting result of the preset tool on the variables;

[0035] constructing the multiterm binary decision diagram corresponding to the target sum-of-powers formula based on the order of the variables in the target sum-of-powers formula in the multiterm binary decision diagram.

[0036] In a possible embodiment of the present disclosure, the processing of the multiterm binary decision diagram to obtain a processing result of the task to be processed comprises:

[0037] The multi-terminal binary decision diagram is counted to obtain a processing result of the to-be-processed task.

[0038] According to a second aspect of the embodiments of the present disclosure, a quantum circuit processing device based on binary decision diagram counting is provided, and the device comprises:

[0039] A conversion module is configured to convert a quantum circuit recorded in a quantum circuit file into a corresponding initial power sum formula.

[0040] A processing module is configured to process the power sum formula based on a task type of a to-be-processed task of the quantum circuit to obtain a target power sum formula.

[0041] A construction module is configured to construct a corresponding multi-terminal binary decision diagram based on the target power sum formula, and process the multi-terminal binary decision diagram to obtain a processing result of the to-be-processed task.

[0042] In a possible embodiment of the present disclosure, the conversion module is configured to:

[0043] configure a variable for each line in the quantum circuit recorded in the quantum circuit file based on a preconfigured quantum gate set;

[0044] generate a power expression of each quantum gate in the quantum circuit based on the variable on an input line and the variable on an output line of the quantum gate;

[0045] construct an initial power sum formula for representing the quantum circuit based on the power expression of each quantum gate in the quantum circuit and the lines between the quantum gates.

[0046] In a possible embodiment of the present disclosure, the quantum circuit comprises a plurality of quantum bits, and each quantum bit has at least one quantum gate thereon;

[0047] When the conversion module is configured to configure a variable for each line in the quantum circuit recorded in the quantum circuit file based on a preconfigured quantum gate set, the conversion module is configured to:

[0048] configure one variable for each quantum bit;

[0049] for each quantum gate on each quantum bit, configure a variable for an input line and an output line of the quantum gate based on an attribute of the quantum gate, wherein the attribute of the quantum gate is used to represent a relationship between an input variable and an output variable of the quantum gate.

[0050] In a possible embodiment of the present disclosure, when the conversion module is configured to configure a variable for an input line and an output line of the quantum gate based on the attribute of the quantum gate, the conversion module is configured to:

[0051] if the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are the same, configuring the variable on the input line of the quantum gate as the variable on the output line of the quantum gate;

[0052] if the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are different, configuring a new variable on the output line of the quantum gate, which is different from the variable on the input line of the quantum gate.

[0053] In a possible embodiment of the present disclosure, the processing module is configured to:

[0054] if the task type is amplitude calculation, assigning the input variable of the initial power sum formula as 0, assigning the output variable of the initial power sum formula as a preset amplitude, and summing the internal variables of the initial power sum formula to obtain the target power sum formula.

[0055] In a possible embodiment of the present disclosure, the processing module is further configured to:

[0056] if the initial power sum formula represents that the input variable and the output variable are the same and the assignment is contradictory, setting the processing result of the task to be processed as 0.

[0057] In a possible embodiment of the present disclosure, the processing module is configured to:

[0058] if the task type is measurement result sampling, determining an expression for representing a target measurement result based on the target measurement result and the initial power sum formula, and determining the expression as the target power sum formula.

[0059] In a possible embodiment of the present disclosure, the processing module is configured to:

[0060] if the task type is equivalence detection, determining an expression for representing a preset operation result of unitary matrices of two quantum circuits to be detected based on the initial power sum formula of the two quantum circuits, and determining the expression as the target power sum formula, wherein the preset operation result of the unitary matrices of the two quantum circuits is used to represent whether the two quantum circuits have equivalence.

[0061] In a possible embodiment of the present disclosure, the preset operation result of the unitary matrices of the two quantum circuits comprises:

[0062] a trace of an inner product of a conjugate transpose of a unitary matrix of one quantum circuit and a unitary matrix of another quantum circuit in the two quantum circuits.

[0063] In a possible embodiment of the present disclosure, the construction module is configured to, when constructing a corresponding multi-terminal binary decision diagram based on the target power sum formula, be configured to:

[0064] divide the plurality of summation terms of the multi-linear polynomial in the target power-sum formula into a plurality of groups, and construct a multi-terminal binary decision diagram based on summation terms in each group, respectively;

[0065] construct a multi-terminal binary decision diagram corresponding to the target power-sum formula based on the multi-terminal binary decision diagrams of each group.

[0066] In a possible embodiment of the present disclosure, the constructing module is configured to, when constructing the multi-terminal binary decision diagram corresponding to the target power-sum formula based on the target power-sum formula, be configured to:

[0067] determine the order of variables in the target power-sum formula in the multi-terminal binary decision diagram based on at least one of the following: the order of the involved qubits, the order of the connected quantum gates, and the sorting result of the variables by a preset tool;

[0068] construct the multi-terminal binary decision diagram corresponding to the target power-sum formula based on the order of variables in the target power-sum formula in the multi-terminal binary decision diagram.

[0069] In a possible embodiment of the present disclosure, the constructing module is configured to, when processing the multi-terminal binary decision diagram to obtain the processing result of the to-be-processed task, be configured to:

[0070] perform a counting operation on the multi-terminal binary decision diagram to obtain the processing result of the to-be-processed task.

[0071] According to a third aspect of embodiments of the present disclosure, a computer program product is provided, including computer programs / instructions, which, when executed by a processor, implement the steps of the method of the first aspect.

[0072] According to a fourth aspect of embodiments of the present disclosure, an electronic device is provided, including a memory and a processor, the memory is configured to store computer instructions executable on the processor, and the processor is configured to implement the method of the first aspect when executing the computer instructions.

[0073] According to a fifth aspect of embodiments of the present disclosure, a computer-readable storage medium is provided, which stores a computer program, and the program, when executed by a processor, implements the method of the first aspect.

[0074] The technical solutions provided by the embodiments of the present disclosure can include the following beneficial effects:

[0075] The quantum circuit processing method provided by the embodiment of the present disclosure first converts the quantum circuit recorded in the quantum circuit file into a corresponding initial power sum formula; next, based on the task type of the task to be processed for the quantum circuit, the power sum formula is processed to obtain a target power sum formula; finally, a corresponding multi-terminal binary decision diagram is constructed based on the target power sum formula, and the multi-terminal binary decision diagram is processed to obtain the processing result of the task to be processed. This method identifies the quantum circuit by converting it into a power sum form, and processes the initial power sum formula based on the task type of the task to be processed so that the task to be processed has an equivalent effect on the initial power sum formula. Finally, the task to be processed is completed through the multi-terminal binary decision diagram corresponding to the target power sum formula to obtain the processing result. This method completes the analysis task of the quantum circuit through the multi-terminal binary decision diagram corresponding to the power sum formula, which not only improves efficiency but also reduces the demand for storage resources and computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0077] Figure 1 is a flow chart of a quantum circuit processing method based on binary decision diagram counting according to an exemplary embodiment of the present disclosure;

[0078] Figure 2 is a schematic diagram of a quantum circuit according to an exemplary embodiment of the present disclosure;

[0079] Figure 3 is a schematic diagram of a CNOT gate according to an exemplary embodiment of the present disclosure;

[0080] Figure 4 is a schematic diagram of a decision diagram according to an exemplary embodiment of the present disclosure;

[0081] Figure 5 is a logic diagram of a quantum circuit processing method based on binary decision diagram counting according to an exemplary embodiment of the present disclosure;

[0082] Figure 6 1 is a schematic structural diagram of a quantum circuit processing device based on binary decision diagram counting according to an exemplary embodiment of the present disclosure;

[0083] Figure 7 It is a structural block diagram of an electronic device shown in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description herein relates to the drawings, in which the same numbers represent the same or similar elements, unless otherwise represented. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0085] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0086] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a temporal or chronological order. Rather, these terms are used solely to distinguish one from another only. For example, a first information can be termed a second information, and similarly, a second information can also be termed a first information, without departing from the scope of the present disclosure. Depending on the context, the word "if' as used herein can be interpreted to mean "when" or "in response to determining" or "in response to a determination".

[0087] First, some concepts in this specification are explained.

[0088] Quantum Computation: A way of computing that takes advantage of the superposition and entanglement of quantum states to perform analysis tasks quickly.

[0089] Qubit: A form of quantum information.

[0090] Quantum Operation: A way of manipulating qubits to process the quantum information they carry, including quantum gates, qubit state preparation, quantum measurement, etc.

[0091] Quantum Gate: A class of quantum operations that can be represented as a unitary transformation between qubit states. Common quantum gates include Pauli I, X, Y, Z gates, Hadamard gate (H), controlled Pauli X gate (CNOT), swap gate (SWAP), etc.

[0092] Clifford gate: A special class of quantum gates that, under conjugation, map tensor products of Pauli I, X, Y, Z gates to tensor products of Pauli gates. That is, let P be a tensor product of Pauli gates, and V be a Clifford gate. Then is also a tensor product of Pauli gates.

[0093] Quantum circuit: A model that describes the process of quantum computation, which describes how quantum operations are performed on qubits.

[0094] Quantum measurement: A process used to obtain a classical description of the state of a qubit.

[0095] Quantum gate set: A set of quantum gates. It is often necessary to specify the set of quantum gates used in a quantum computation in advance.

[0096] Binary decision diagram (BDD): A directed acyclic graph used to represent Boolean functions, where each internal node corresponds to a Boolean variable, and the outgoing edges of a node represent the values of the variable (0 or 1). Terminal nodes represent the values of the function.

[0097] Multi-terminal binary decision diagram (MTBDD): A binary decision diagram that allows terminal nodes to take multiple possible values, often used to represent functions of integer or real values.

[0098] Tensor: A multi-dimensional array representation of data, which can be used to describe the state of qubits, quantum gates, and their interactions.

[0099] Tensor network: A network formed by connecting tensors in a specific way. Operations such as tensor contraction, tensor decomposition, index rearrangement, and connection can be performed on a tensor network.

[0100] Sum-of-powers (SOP): A representation of a quantum circuit. It is usually in the form of where R is a real number, ω is a complex number with a modulus of 1 determined by the quantum circuit, f is a multilinear polynomial, and x and y are variables in f. For a quantum circuit represented using a specific set of quantum gates, the corresponding SOP form can be obtained efficiently. SOP can be transformed by variable summation, variable assignment, and other operations.

[0101] Quantum Circuit Analysis: analyzing a given quantum circuit to obtain the properties of interest of the quantum circuit, including quantum circuit simulation, equivalence checking, circuit synthesis and optimization, etc.

[0102] Quantum Circuit Simulation: a quantum circuit analysis method to simulate the execution process of a quantum circuit on a classical computing device. For example, calculating the probability of measuring a specific result after the execution of a quantum circuit, and sampling a measurement output result of a quantum circuit.

[0103] Quantum Circuit Equivalence Checking: a quantum circuit analysis method to determine whether two quantum circuits are equivalent.

[0104] Based on the above technical problems mentioned in the background art, in a first aspect, at least one embodiment of the present disclosure provides a quantum circuit processing method based on binary decision diagram counting, which is used to perform a to-be-processed task on a quantum circuit, such as amplitude calculation, measurement result sampling, equivalence checking, etc., and can complete the to-be-processed task in a more efficient and lower resource occupation manner (i.e., occupying less storage resources and less computing resources).

[0105] Please refer to the accompanying drawings Figure 1 which exemplarily shows a flowchart of the method, including steps S101 to S103.

[0106] In step S101, the quantum circuit recorded in the quantum circuit file is converted into the corresponding initial power sum formula.

[0107] Wherein, the quantum circuit file is a given quantum circuit that needs to be analyzed, and the quantum circuit includes a plurality of quantum bits, each quantum bit having at least one quantum gate. In addition, a to-be-processed task and a pre-configured quantum gate set are also given. The to-be-processed task is a task that needs to be executed for the above-mentioned quantum circuit, i.e., the specific content of the above-mentioned analysis. The pre-configured quantum gate set is a basic quantum gate set contained in the quantum circuit.

[0108] Converting the quantum gate circuit into the initial power sum formula is based on the following content: the universal gate set of the quantum circuit can be composed of several unitary gates, which can make the non-zero items in the unitary matrix representation of the quantum circuit proportional to ωr, where ω is a unit root of a certain degree, and it is assumed that its degree is r, i.e., r is the smallest positive integer that satisfies ω r = 1. x1, x2, …, x kare variables labeled on the input and output lines, discussed in more detail below.

[0109] Exemplarily, the quantum circuit recorded in the quantum circuit file can be converted into the corresponding initial power-sum formula in the following manner shown in the accompanying drawings, including sub-step S1011 to sub-step S1013.

[0110] In sub-step S1011, a variable is configured for each line of the quantum circuit recorded in the quantum circuit file based on a pre-configured set of quantum gates.

[0111] For example, a variable can be first configured for each quantum bit; and then for each quantum gate on each quantum bit, a variable is configured for the input line and the output line of the quantum gate based on the attribute of the quantum gate, where the attribute of the quantum gate is used to represent the relationship between the input variable and the output variable of the quantum gate. For example, if the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are the same, the variable on the input line of the quantum gate is configured as the variable on the output line of the quantum gate; if the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are different, a new variable different from the variable on the input line of the quantum gate is configured on the output line of the quantum gate.

[0112] In sub-step S1012, for each quantum gate in the quantum circuit, a power expression of the quantum gate is generated based on the variable on the input line and the variable on the output line of the quantum gate.

[0113] In sub-step S1013, based on the power expression of each quantum gate in the quantum circuit and the lines between the quantum gates, an initial power-sum formula is constructed to represent the quantum circuit.

[0114] Next, the manner provided by the example is specifically introduced by taking the quantum circuit shown in the accompanying drawings as an example. Figure 2 The set of quantum gates corresponding to the quantum circuit is set

[0115] First, a variable is introduced for each quantum bit to label the corresponding line. Then, the quantum gates on each quantum bit line are considered in turn, and if an H gate is encountered, a new variable is created to label the output line of the H gate. In the setting of this set of quantum gates, this is the only way to generate a new variable. Obviously, for a quantum circuit with n quantum bits and h H gates, the total number of variables is n+h. Figure 2The circuit shown is composed of 4 H gates, 1 Z gate, 1 CZ gate and 2 CCZ gates. There are 7 variables in the circuit, x1, x2, …, x7, in which x1, x2, x3 are the initial variables of each qubit, and x4, …, x7 are the new variables introduced by H gates.

[0116] After the introduction of variables on the circuit, the corresponding expression can be written for each quantum gate. The expression of H gate is where x and y are the variables on the input and output lines of H gate; the expressions of Z, CZ and CCZ gates are (-1) x , (-1) xy , (-1) xyz respectively. This is because the unitary matrices corresponding to the three gates are all diagonal matrices, so the variables on the input and output lines are consistent. In this set of quantum gates, all the gates can be expressed as a certain power of -1, in which the H gate needs an additional normalization factor.

[0117] This power expression can be regarded as a special tensor. For example, the tensor corresponding to H gate has two legs, marked by variable indices x and y, both of which take values in {0, 1}. The correspondence between the tensor value and the indices is The tensor corresponding to CCZ gate has six legs, in which x1, x2, x3 are the indices on the three input line legs, and y1, y2, y3 are the indices on the three output line legs. If (x1, x2, x3)≠(y1, y2, y3), the value of the tensor is 0; if (x1, x2, x3)=(y1, y2, y3), the value of the tensor is In a similar way, each quantum gate corresponds to a tensor, and these tensors are connected to form a tensor network according to the line relationship. The variables on the lines can be naturally divided into internal variables or external variables according to whether they are on the input or output lines of the entire circuit. In the contraction process of the tensor network, all internal variables will be summed. Then Figure 2 the tensor corresponding to the quantum circuit in is C where f C (x1, x2, …, x7)=x1x4+x2x5+x3x5+x3x4x5+x4+x5x6+x3x7+x4x6x7. We call this summation form a power sum.

[0118] In general, for the circuit composed of gates in , the power sum is of the form where h is the number of H gates, and f Cis a multivariate linear polynomial, x and y are the variables in f, and y corresponds to the internal variable. In this case, we call -1 the basis of the power sum. Since -1 is a quadratic root of unity, the modulus of the power sum is 2, that is, f C It is evaluated modulo 2.

[0119] The expressions corresponding to some quantum gates may have more complex forms. Figure 3 As shown, the expression corresponding to the CNOT gate is This is because the CNOT gate can be decomposed into

[0120] When changing the basic quantum gate set, you may need to change the basis of the power sum and the corresponding expression of the quantum gate. The conversion to the power sum is similar.

[0121] In step S102, the power sum formula is processed based on the task type of the task to be processed for the quantum circuit to obtain a target power sum formula.

[0122] The processing of the power sum in this step refers to the "transformation on the power sum", which mainly includes algebraic simplification operations and variable replacement on the power sum. The quantum circuit itself can be simplified through certain equivalent transformation rules, and the transformed power sum can perform the corresponding operations of these rules, such as combining like terms in the sense of modulo r, and performing the simplification corresponding to HH=I on the quantum circuit. The replacement and summation of variables in the power sum correspond to the tensor connection and contraction operations in the tensor network. For example, when two pins with indices x1 and x2 are connected in the tensor network, the two variables x1 and x2 are replaced by the same variable in the power sum. It is recommended to choose x1 as the replaced variable, then the original polynomial f C All x2 in the equation are replaced by x1. The contraction of the tensor network corresponds to the summation of the internal variables in the power sum.

[0123] Exemplarily, if the task type is amplitude calculation, the input variable of the initial power sum formula is assigned to 0, the output variable of the initial power sum formula is assigned to a preset amplitude, and the internal variables of the initial power sum formula are summed to obtain the target power sum formula.

[0124] When the task is "Amplitude Calculation", the amplitude needs to be calculated <a|U|0 n >.Where U is the unitary matrix corresponding to the quantum circuit, a∈{0,1} n is a calculation basis. The operation performed on the power sum is to assign the input variable to 0, assign the output variable to the Boolean value at the corresponding position of a, and sum all internal variables. After this transformation, the initial power sum can be further rewritten as the target power sum where Nj | {y | f(y)≡j mod r} | represents the number of inputs satisfying the condition that the value of function f is equivalent to j modulo r, which can be obtained by subsequent counting operations on the multi-terminal decision diagram. The summation result of the target power sum is the amplitude to be calculated.

[0125] In this example, preferably, if the initial power sum represents that the input variable and the output variable are the same and the assignment is contradictory, the processing result of the task to be processed is set to 0. This special case is that the input variable and the output variable have a common part, but the assignment is contradictory, and the calculation result is 0.

[0126] Further exemplarily, if the task type is measurement result sampling, an expression for representing the target measurement result is determined based on the target measurement result and the initial power sum, and the expression is determined as the target power sum.

[0127] When the task to be performed is "measurement result sampling", the measurement result on each quantum bit needs to be sampled in turn according to the probability of the measurement result, and the result probability of the subsequent quantum bit needs to be conditioned on the sampling result on all previous quantum bits. Specifically, assuming that the power sum is After the quantum circuit is executed, the measurement result of the first j quantum bits is a1, a2, … a j , and the probability of >j is where x j represents all remaining output variables, x1, …, x j in f are assigned to a1, …, a j+1 in turn. After that, the probability that the measurement result of the next quantum bit x j+1 is a

[0128]

[0129] where the evaluation of the probability also relies on the subsequent multi-terminal decision diagram counting operation. The result of each quantum bit is sampled in turn according to the probability, and finally the complete sampling measurement result can be obtained.

[0130] Further exemplarily, if the task type is equivalence detection, an expression for representing the preset operation result of the unitary matrix of the two quantum circuits to be detected is determined based on the initial power sum of the two quantum circuits, and the expression is determined as the target power sum, where the preset operation result of the unitary matrix of the two quantum circuits is used to represent whether the two quantum circuits have equivalence.

[0131] The preset operation result of the unitary matrix of the two quantum circuits includes a trace of a conjugate transpose of a unitary matrix of one quantum circuit in the two quantum circuits and an inner product of a unitary matrix of another quantum circuit.

[0132] When the task to be performed is equivalence detection, it is necessary to determine whether the unitary matrices U1, U2 corresponding to the two n-qubit circuits to be detected satisfy where ω j is a complex number with a modulus of 1. Taking the conjugate transpose of the matrix corresponds to taking the negative of a multivariate linear polynomial in the power-sum formula in the sense of the modulus r. When calculating , it is assumed that The power-sum formula corresponding to the quantum circuit is It is necessary to regard the input variables and the output variables of the same quantum bit in the power-sum formula as equivalent variables, respectively, to select a representative variable for each group of equivalent variables to replace and sum up. At this time, the power-sum formula is converted into a form with only internal variables, that is, it is necessary to calculate the value of the expression The result obtained is tr(U). The subsequent evaluation steps are similar to those in amplitude calculation, that is, the result is obtained by subsequent counting operations on the multi-terminal decision graph.

[0133] In step S103, a multi-terminal binary decision graph corresponding to the target power-sum formula is constructed based on the target power-sum formula, and the multi-terminal binary decision graph is processed to obtain a processing result of the task to be processed.

[0134] The purpose of converting the power-sum formula into a multi-terminal decision graph is to use a multi-terminal decision graph (MTBDD) to represent a multivariate linear polynomial f in the power-sum formula. For example Figure 4 The decision graph in can represent the polynomial x1+x2x3+x1x3x4 in the sense of modulus 2, where the circular node represents a variable, the dashed line extending downward represents that the variable takes 0, the solid line represents that the variable takes 1, and the square node below represents the value of the function, which generally has values of 0 to r-1 in the sense of modulus r. The implementation of the underlying data structure can use the CUDD 13 , Sylvan 14 , etc. calculation engine.

[0135] Illustratively, the multi-terminal binary decision graph corresponding to the target power-sum formula is constructed in the following manner: the multiple summation terms of the multivariate linear polynomial in the target power-sum formula are divided into multiple groups, and a multi-terminal binary decision graph is constructed based on the summation terms in each group; based on the multi-terminal binary decision graphs of each group, a multi-terminal binary decision graph corresponding to the target power-sum formula is constructed.

[0136] For example, this example uses a binary recursive synthesis method, leveraging the commutative property of modular R addition to divide the summation terms into two roughly equal groups. The decision graphs within each group are first transformed and then merged. Because the order in which decision graphs are added to a polynomial affects the efficiency of constructing a multi-terminal binary decision graph, this example effectively controls the order in which decision graphs are added to the polynomial through grouping, improving the efficiency of constructing a multi-terminal binary decision graph.

[0137] As another example, a multi-terminal binary decision diagram corresponding to the target power sum formula is constructed in the following manner: first, the order of the variables in the target power sum formula in the multi-terminal binary decision diagram is determined based on at least one of the following: the order of the quantum bits involved, the order of the connected quantum gates, and the sorting results of the variables by a preset tool; next, based on the order of the variables in the target power sum formula in the multi-terminal binary decision diagram, a multi-terminal binary decision diagram corresponding to the target power sum formula is constructed.

[0138] For example, the preset tool may be a standard tensor contraction optimization tool (such as Cotengra).

[0139] Preferably, the order of the variables in the target power and the formula is determined based on the order of the quantum bits involved.

[0140] Because the order of variables in a decision diagram affects the efficiency of constructing a multi-terminal binary decision diagram, this example uses multiple dimensions to determine the order of variables in the target power and formula in the multi-terminal binary decision diagram, thereby improving the efficiency of constructing the multi-terminal binary decision diagram.

[0141] The above two examples can be applied separately to the process of constructing a multi-terminal binary decision diagram, or can be combined and applied together to the process of constructing a multi-terminal binary decision diagram.

[0142] As another example, the multi-terminal binary decision diagram is processed in the following manner to obtain the processing result of the task to be processed: a counting operation is performed on the multi-terminal binary decision diagram to obtain the processing result of the task to be processed.

[0143] For example, this example uses the GNU High Precision Arithmetic Library to implement a high-precision counting algorithm for the underlying decision graph to perform counting operations on multi-terminal binary decision graphs.

[0144] It should be understood that if the task type is amplitude calculation, the processing result obtained in this step is the amplitude to be calculated. If the task type is measurement result sampling, the processing result obtained in this step is the probability Pr[x1=a1,…,x j =a j ], and Pr[x j+1 =a j+1 |x1=a1,…,xj = a j The probability obtained each time can be returned to be used to calculate the subsequent probability. If the task type is equivalence detection, the processing result obtained in this step is the preset operation result of the unitary matrices of the two quantum circuits.

[0145] Preferably, the quantum circuit can be operated based on the processing result of the task to be processed. For example, when the task type is measurement result sampling, after the probability of obtaining a specific result a1,..., a n n is an integer greater than 1.

[0146] Please refer to the accompanying Figure 5 which exemplarily shows a logic diagram of the quantum circuit processing method obtained by combining the above multiple embodiments.

[0147] As can be seen from Figure 5 The quantum circuit processing method proposed by the present disclosure can be regarded as a solution to exploring quantum computing on a classical computing device. The "amplitude calculation" and "measurement result sampling" tasks can simulate the operation of a quantum circuit and obtain information about the operation result of the quantum circuit. The "equivalence detection" task can be used to check the correctness of the quantum compilation and quantum circuit optimization process.

[0148] From the above perspective, the method proposed by the present disclosure can be modified and implemented by quantum computing researchers based on their respective research purposes and the characteristics of the quantum circuit being studied. It can also be used as an optional method to enter the existing quantum circuit analysis framework. It can be used as a separate method for quantum circuit analysis, or as a subroutine to assist other quantum circuit analysis methods.

[0149] The present disclosure can implement related quantum circuit analysis tasks with higher efficiency, and has a significant advantage over other methods for some types of quantum circuits, helping to promote related research on quantum computing.

[0150] In quantum circuit simulation, i.e. "amplitude calculation" and "measurement result sampling" tasks, this effect is illustrated by taking Google random circuits as an example. There are two types of circuits, cz_v2 and is_v1. The basic quantum gate set of the cz_v2 type circuit is The basic quantum gate set of the is_v1 type circuit is The selected quantum circuits involve 16, 20, and 25 quantum bits. Each group of circuits consists of 10 different circuits, and the values reported in the test are the average performance on the 10 circuits.

[0151] The comparative objects are the widely used quantum simulation tools DDSIM and SliQSim. Three methods including the present disclosure independently read quantum circuit files, perform corresponding analysis tasks, and measure the required time and storage occupation.

[0152] The following table shows the comparison of the method provided by the present disclosure and other methods in the related art in the "amplitude calculation" task.

[0153] Table 1: Performance on the amplitude analysis task

[0154]

[0155] The following table shows the comparison of the method provided by the present disclosure and other methods in the related art in the "measurement result sampling" task.

[0156] Table 2: Performance on the measurement result sampling task

[0157]

[0158]

[0159] As shown in the above table 1 and table 2, the running efficiency of the present disclosure is greatly improved compared with DDSIM and SliQSim. In the 25-qubit Google random circuit, the running time of DDSIM and SliQSim is more than 1 hour, while the present disclosure can complete the analysis task within a reasonable time.

[0160] In the "equivalence detection" task, the GHZ circuit is taken as an example to illustrate this effect. The selected quantum circuit scale is 100, 500, 1000, 5000, and 10000 qubits, and the basic quantum gate set is {H, Z, CZ, CCZ}. In the equivalence detection test, Qiskit is used to rewrite the original quantum circuit equivalently to obtain a rewritten circuit equivalent to the original circuit. Then the following three sub-tests are performed: (1) compare the rewritten circuit with the original circuit; (2) randomly remove a quantum gate from the rewritten circuit and compare it with the original circuit; (3) randomly flip a CNOT gate in the rewritten circuit and compare it with the original circuit.

[0161] The comparative object is the mainstream quantum circuit equivalence detection tool MQT-QCEC, which integrates multiple equivalence detection methods based on ZX calculus and decision diagram. The present disclosure and MQT-QCEC respectively run three sub-tasks, and compare the detection time under the condition of ensuring the correctness of the results. The test results are shown in the following table:

[0162] Table 3: Performance on the equivalence detection task

[0163]

[0164]

[0165] From the results in the above table, it can be seen that, since the GHZ circuit can be finally converted into a multivariate decision diagram at a lower cost, compared with the MQT-QCEC, the present disclosure can complete the equivalence detection task related to the GHZ circuit in a shorter time.

[0166] In summary, compared with other existing methods, the quantum circuit analysis method based on classical decision diagrams proposed by the present disclosure can achieve a substantial performance improvement in part of the quantum circuit, and more efficiently complete the quantum circuit analysis task.

[0167] The present disclosure provides a quantum circuit processing method, which uses the power sum formula to relate quantum circuits and multivariate decision diagrams, converts the quantum circuit analysis task into a counting task on the multivariate decision diagram, and thus can use the structure in the Feynman path integral to analyze the quantum circuit.

[0168] The present disclosure integrates the counting capability of binary decision diagrams into quantum circuit analysis, combines the properties of quantum circuits in counting with the efficient counting algorithm of binary decision diagrams. Unlike the Schrödinger simulator that evolves state vectors using variants of binary decision diagrams, the present disclosure explores the structure of the Feynman-type exponential sum in the quantum circuit and uses the idea of Feynman path integral to perform the quantum circuit analysis task. In terms of technology, the present disclosure introduces a power sum formula framework that is flexible and efficient, and optimizes the performance of quantum circuit analysis.

[0169] The quantum circuit processing method provided by the embodiments of the present disclosure first converts the quantum circuit recorded in the quantum circuit file into a corresponding initial power sum formula; next, based on the task type of the to-be-processed task of the quantum circuit, processes the power sum formula to obtain a target power sum formula; finally, constructs a corresponding multiterminal binary decision diagram based on the target power sum formula, and processes the multiterminal binary decision diagram to obtain the processing result of the to-be-processed task. This method identifies the quantum circuit by converting it into a power sum formula, and processes the initial power sum formula based on the task type of the to-be-processed task, so that the to-be-processed task has an equivalent effect on the initial power sum formula. Finally, the to-be-processed task is completed through the multiterminal binary decision diagram corresponding to the target power sum formula to obtain the processing result. This method completes the analysis task of the quantum circuit through the multiterminal binary decision diagram corresponding to the power sum formula, not only improving the efficiency, but also reducing the demand for storage resources and computing resources.

[0170] According to a second aspect of the embodiments of the present disclosure, a quantum circuit processing device based on binary decision diagram counting is provided. Please refer to the accompanying Figure 6 , the device comprises:

[0171] The conversion module 601 is configured to convert a quantum circuit recorded in a quantum circuit file into a corresponding initial power-sum expression.

[0172] The processing module 602 is configured to process the power-sum expression based on a task type of a to-be-processed task of the quantum circuit, to obtain a target power-sum expression.

[0173] The construction module 603 is configured to construct a corresponding multi-terminal binary decision diagram based on the target power-sum expression, and process the multi-terminal binary decision diagram, to obtain a processing result of the to-be-processed task.

[0174] In a possible embodiment of the present disclosure, the conversion module is configured to:

[0175] configure a variable for each line in a quantum circuit recorded in a quantum circuit file based on a preconfigured set of quantum gates;

[0176] generate a power expression of each quantum gate in the quantum circuit based on the variable on an input line and the variable on an output line of the quantum gate;

[0177] construct an initial power-sum expression for representing the quantum circuit based on the power expression of each quantum gate in the quantum circuit and the lines between the quantum gates.

[0178] In a possible embodiment of the present disclosure, the quantum circuit includes a plurality of quantum bits, and each quantum bit has at least one quantum gate thereon.

[0179] When the conversion module is configured to configure a variable for each line in a quantum circuit recorded in a quantum circuit file based on a preconfigured set of quantum gates, the conversion module is configured to:

[0180] configure one variable for each quantum bit;

[0181] configure a variable for an input line and an output line of each quantum gate on each quantum bit based on an attribute of the quantum gate, where the attribute of the quantum gate is used to represent a relationship between an input variable and an output variable of the quantum gate.

[0182] In a possible embodiment of the present disclosure, when the conversion module is configured to configure a variable for an input line and an output line of each quantum gate on each quantum bit based on an attribute of the quantum gate, the conversion module is configured to:

[0183] if the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are the same, configure the variable on the input line of the quantum gate as the variable on the output line of the quantum gate;

[0184] If the attribute of the quantum gate represents that the input variable and the output variable of the quantum gate are different, a new variable different from the variable on the input line of the quantum gate is configured on the output line of the quantum gate.

[0185] In a possible embodiment of the present disclosure, the processing module is configured to:

[0186] If the task type is amplitude calculation, the input variable of the initial sum-of-powers formula is assigned as 0, the output variable of the initial sum-of-powers formula is assigned as a preset amplitude, and the internal variables of the initial sum-of-powers formula are summed to obtain a target sum-of-powers formula.

[0187] In a possible embodiment of the present disclosure, the processing module is further configured to:

[0188] If the initial sum-of-powers formula represents that the input variable and the output variable are the same and the assignment is contradictory, the processing result of the task to be processed is set as 0.

[0189] In a possible embodiment of the present disclosure, the processing module is configured to:

[0190] If the task type is measurement result sampling, an expression for representing a target measurement result is determined based on the target measurement result and the initial sum-of-powers formula, and the expression is determined as a target sum-of-powers formula.

[0191] In a possible embodiment of the present disclosure, the processing module is configured to:

[0192] If the task type is equivalence detection, an expression for representing a preset operation result of unitary matrices of two quantum circuits to be detected is determined based on the initial sum-of-powers formula of the two quantum circuits, and the expression is determined as a target sum-of-powers formula, wherein the preset operation result of the unitary matrices of the two quantum circuits is used to represent whether the two quantum circuits have equivalence.

[0193] In a possible embodiment of the present disclosure, the preset operation result of the unitary matrices of the two quantum circuits includes:

[0194] a trace of an inner product of a conjugate transpose of a unitary matrix of one quantum circuit and a unitary matrix of another quantum circuit in the two quantum circuits.

[0195] In a possible embodiment of the present disclosure, the construction module is configured to, when constructing a corresponding multi-terminal binary decision diagram based on the target sum-of-powers formula:

[0196] dividing a plurality of sum terms of a multivariate linear polynomial in the target sum-of-powers formula into a plurality of groups, and constructing a multi-terminal binary decision diagram based on the sum terms in each group, respectively;

[0197] Based on the multi-terminal binary decision diagram of each group, a multi-terminal binary decision diagram corresponding to the target power sum formula is constructed.

[0198] In a possible embodiment of the present disclosure, when the construction module is used to construct a multi-terminal binary decision diagram corresponding to the target power sum formula based on the target power sum formula, it is configured to:

[0199] The order of the variables in the target power sum formula in the multi-terminal binary decision diagram is determined based on at least one of the following: the order of the involved qubits, the order of the connected quantum gates, and a preset tool sorting result of the variables.

[0200] The multi-terminal binary decision diagram corresponding to the target power sum formula is constructed based on the order of the variables in the target power sum formula in the multi-terminal binary decision diagram.

[0201] In a possible embodiment of the present disclosure, when the processing module is used to process the multi-terminal binary decision diagram to obtain a processing result of the to-be-processed task, it is configured to:

[0202] The multi-terminal binary decision diagram is subjected to a counting operation to obtain a processing result of the to-be-processed task.

[0203] As to the apparatus in the above-mentioned embodiments, the specific manners in which various modules perform operations have been described in detail in the embodiments of the method in the first aspect, and thus will not be described here in detail.

[0204] According to a third aspect of the embodiments of the present disclosure, a computer program product is provided, which includes computer programs / instructions that, when executed by a processor, implement the steps of the method in the first aspect.

[0205] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, which refers to the accompanying drawings Figure 7 The electronic device includes a memory and a processor. The memory is configured to store computer instructions executable on the processor. The processor is configured to implement the method in the first aspect when the computer instructions are executed.

[0206] In the exemplary embodiments, the present disclosure also provides a non-transitory computer-readable storage medium including instructions, for example, the memory 704 including instructions, which can be executed by the processor 720 of the device 700 to complete the quantum circuit processing method of the electronic device. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0207] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the disclosure be construed as including any patents, patent applications, publications, publications, or other disclosure of the prior art that are referred to by their title or by a general identification of their content. It is intended that the disclosure encompass variations and modifications of the specific structure disclosed herein to the extent that these variations and modifications remain consistent with the general principles of the present disclosure. The specification and examples are to be regarded as exemplary in nature and not as restrictive.

[0208] It should be understood that the present disclosure is not limited to the precise structures herein described and illustrated in the drawings and that various modifications and changes can be made therein without departing from the scope thereof. The scope of the present disclosure is indicated by the appended claims.

Claims

1. A quantum circuit processing method based on binary decision diagram counting, characterized in that: The method comprises: Convert the quantum circuit recorded in the quantum circuit file into the corresponding initial power sum formula; processing the power sum based on a task type of a task to be processed for the quantum circuit to obtain a target power sum; A corresponding multi-terminal binary decision diagram is constructed based on the target power sum formula, and the multi-terminal binary decision diagram is processed to obtain a processing result of the task to be processed.

2. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The step of converting the quantum circuit recorded in the quantum circuit file into the corresponding initial power sum formula includes: Based on the pre-configured quantum gate set, configure variables for each circuit in the quantum circuit recorded in the quantum circuit file; For each quantum gate in the quantum circuit, generating a power expression of the quantum gate based on variables on an input line and a variable on an output line of the quantum gate; An initial power sum formula for characterizing the quantum circuit is constructed based on the power expression of each quantum gate in the quantum circuit and the circuits between the quantum gates.

3. The quantum circuit processing method based on binary decision diagram counting according to claim 2, characterized in that: The quantum circuit includes a plurality of quantum bits, each of which has at least one quantum gate; The configuration of variables for each circuit in the quantum circuit recorded in the quantum circuit file based on the pre-configured quantum gate set includes: Configure a variable for each qubit; For each quantum gate on each quantum bit, variables are configured for the input circuit and the output circuit of the quantum gate based on the properties of the quantum gate, wherein the properties of the quantum gate are used to characterize the relationship between the input variables and the output variables of the quantum gate.

4. The quantum circuit processing method based on binary decision diagram counting according to claim 3 is characterized in that: Configuring variables for input and output circuits of the quantum gate based on properties of the quantum gate includes: If the property of the quantum gate indicates that the input variable and the output variable of the quantum gate are the same, configuring the variable on the input line of the quantum gate as the variable on the output line of the quantum gate; If the property of the quantum gate indicates that the input variable and the output variable of the quantum gate are different, a new variable that is different from the variable on the input line of the quantum gate is configured on the output line of the quantum gate.

5. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The processing of the power sum formula based on the task type of the task to be processed for the quantum circuit to obtain a target power sum formula includes: If the task type is amplitude calculation, the input variable of the initial power sum formula is assigned to 0, the output variable of the initial power sum formula is assigned to a preset amplitude, and the internal variables of the initial power sum formula are summed to obtain a target power sum formula.

6. The quantum circuit processing method based on binary decision diagram counting according to claim 5, characterized in that: The method further comprises: If the input variables and output variables represented by the initial power sum formula are the same and the assignments are contradictory, the processing result of the task to be processed is set to 0.

7. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The processing of the power sum formula based on the task type of the task to be processed for the quantum circuit to obtain a target power sum formula includes: If the task type is measurement result sampling, an expression for representing the target measurement result is determined based on the target measurement result and the initial power sum formula, and the expression is determined as the target power sum formula.

8. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The processing of the power sum formula based on the task type of the task to be processed for the quantum circuit to obtain a target power sum formula includes: If the task type is equivalence detection, an expression for representing a preset operation result of the unitary matrices of the two quantum circuits to be detected is determined based on the initial power sum formulas of the two quantum circuits to be detected, and the expression is determined as a target power sum formula, wherein the preset operation result of the unitary matrices of the two quantum circuits is used to represent whether the two quantum circuits are equivalent.

9. The quantum circuit processing method based on binary decision diagram counting according to claim 8, characterized in that: The preset operation results of the unitary matrices of the two quantum circuits include: The trace of the inner product of the conjugate transpose of the unitary matrix of one of the two quantum circuits and the unitary matrix of the other quantum circuit.

10. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The constructing of a corresponding multi-terminal binary decision diagram based on the target power sum formula includes: Dividing the multiple summation terms of the multivariate linear polynomial in the target power sum into multiple groups, and constructing a multi-terminal binary decision diagram based on the summation terms in each group; Based on the multi-terminal binary decision diagrams of each group, a multi-terminal binary decision diagram corresponding to the target power sum is constructed.

11. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The constructing of a corresponding multi-terminal binary decision diagram based on the target power sum formula includes: Determining an order of variables in the target power sum in a multi-terminal binary decision diagram based on at least one of the following: an order of involved quantum bits, an order of connected quantum gates, and a result of a preset tool for sorting the variables; Based on the order of the variables in the target power sum formula in the multi-terminal binary decision diagram, a multi-terminal binary decision diagram corresponding to the target power sum formula is constructed.

12. The quantum circuit processing method based on binary decision diagram counting according to claim 1, characterized in that: The processing of the multi-terminal binary decision diagram to obtain a processing result of the task to be processed includes: A counting operation is performed on the multi-terminal binary decision diagram to obtain a processing result of the task to be processed.

13. A quantum circuit processing device based on binary decision diagram counting, characterized in that: The device comprises: A conversion module, used to convert the quantum circuit recorded in the quantum circuit file into the corresponding initial power sum formula; a processing module, configured to process the power sum equation based on a task type of a task to be processed for the quantum circuit, so as to obtain a target power sum equation; A construction module is used to construct a corresponding multi-terminal binary decision diagram based on the target power sum formula, and process the multi-terminal binary decision diagram to obtain a processing result of the task to be processed.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

15. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein the memory is used to store computer instructions executable on the processor, and the processor is used to implement the method according to any one of claims 1 to 12 when executing the computer instructions.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

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