Substrate modifications to suppress correlated errors in multiqubit arrays

By engineering substrates with defects and features to suppress correlated errors, quantum circuits achieve improved reliability and fault tolerance in qubit arrays, addressing the challenge of correlated noise in quantum computing.

US20250331430A1Active Publication Date: 2025-10-23WISCONSIN ALUMNI RES FOUND
View PDF 4 Cites 1 Cited by

Patent Information

Application Number
US17/546491
Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Priority Date
2020-12-10
Filing Date
2021-12-09
Publication Date
2025-10-23

Smart Images

  • Figure US20250331430A1-D00000_ABST
    Figure US20250331430A1-D00000_ABST
Patent Text Reader

Abstract

Qubit arrays having substrates that are engineered to suppress correlated dephasing errors, correlated relaxation errors, or both are provided. Also provided are quantum circuits incorporating the qubit arrays and quantum computers incorporating the quantum circuits. The engineered substrates can be used to suppress noise and correlated errors in any qubit array that suffers from charge fluctuations or other noise that creates a non-equilibrium, error-producing state in the qubit array.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Oscillator-based Solid-State Spin Sensor

    US20210263117A1

  • Superconducting qubit lifetime and coherence improvement via backside etching

    US20210399192A1

  • Chip-scale phonon-based quantum device

    US9928827B1

  • Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices

    WO2017116442A1

Cited By

  • Superconducting vacuum-bridged josephson junctions

    US20240107899A1