Multimode underwater acoustic communication system and communication method based on heterogeneous dual-core architecture

Abstract

The invention discloses a multi-mode underwater acoustic communication system and communication method based on a heterogeneous dual-core architecture, and belongs to the technical field of underwater acoustic communication. The multi-mode underwater acoustic communication system comprises a main control module, an acquisition module and a transmitting module; the main control module adopts a dual-core heterogeneous processor OMAPL138 formed by an ARM core processor and a DSP core processor; inter-core communication is carried out between the ARM core processor and the DSP core processor through a shared memory and interruption; the ARM core processor is responsible for protocol analysis, task scheduling and man-machine interaction, and the DSP core processor focuses on signal processing and real-time control and integrates four communication systems, a channel evaluation module and the like. The problems that application of a single communication mode is limited and underwater acoustic communication links in different complex sea areas are unstable are effectively solved, and the deep sea area underwater vehicle information collaboration and return and deep sea area observation and monitoring network system capacity are effectively improved and guaranteed.

Description

TECHNICAL FIELD

[0001] The application relates to a multi-mode underwater acoustic communication system and a communication method based on a heterogeneous dual-core architecture, and belongs to the technical field of underwater acoustic communication. BACKGROUND

[0002] Underwater acoustic communication faces challenges such as multipath interference, significant Doppler effect and strong channel time variation. In the prior art, a single communication system cannot adapt to a dynamic environment, resulting in a high bit error rate and limited communication distance. In addition, the traditional underwater acoustic communication system has the following problems: fixed communication system: the system cannot dynamically switch the modulation mode according to the real-time channel quality, and the communication efficiency is limited. Limited processing capacity: a single processor architecture cannot balance real-time signal processing and upper-layer protocol control, resulting in high system delay. In view of the above problems, an underwater acoustic communication system integrating multi-mode communication, dynamic compensation and intelligent decision-making is urgently needed. SUMMARY

[0003] The application provides a multi-mode underwater acoustic communication system, which adopts a dual-core heterogeneous processor architecture and combines channel evaluation to realize the following functions: multi-system dynamic switching: supporting real-time switching of multiple communication systems such as BPSK, QPSK, multi-order spread spectrum and direct sequence spread spectrum. According to the signal-to-noise ratio, bit error rate and channel characteristics, the optimal communication system is dynamically selected, and the dual-core processor is divided and cooperated to improve the real-time performance of signal modulation and demodulation and system control.

[0004] The specific technical solution is as follows:

[0005] A multi-mode underwater acoustic communication system based on a heterogeneous dual-core architecture comprises a main control module, an acquisition module and a transmitting module.

[0006] The main control module adopts a dual-core heterogeneous processor OMAPL138 composed of an ARM core processor and a DSP core processor. The ARM core processor and the DSP core processor communicate with each other through shared memory and interrupts.

[0007] The DSP core processor is responsible for receiving the modulated information of the ARM core processor, modulating and controlling the broadcast underwater acoustic communication signal, driving the transmitting module, detecting the synchronization signal and solving the system type, original signal waveform data, signal-to-noise ratio, Doppler factor and decoding information of the direct sequence spread spectrum (DSSS), multi-order frequency shift keying, binary phase shift keying and quadrature phase shift keying when on standby, and transmitting the information to the ARM core processor.

[0008] ARM core processor runs Linux system, handles network interface and serial port data from host computer, including reading network interface or serial port configuration information, information to be modulated; reading time through RTC driver, setting timing sending; reading arbitrary waveform data to memory and sending; calculating the best communication system of the current environment.

[0009] The acquisition module uses ADS8568, which supports eight-channel synchronous sampling at a maximum of 510kbps; the preamplifier amplifies weak signals and reduces noise interference; the post-amplifier amplifies and filters signals twice to improve output gain.

[0010] The transmitting module uses DA5724, which can be configured as four channels, 12 / 14 / 16-bit digital-to-analog conversion; the power amplifier amplifies the electrical signals processed by the front end, enabling it to drive the underwater acoustic transducer, convert electrical signals into acoustic signals, and radiate them into water.

[0011] Further, the ARM core processor integrates a channel quality evaluation model, which dynamically selects BPSK, QPSK, multi-order frequency shift keying, or direct sequence spread spectrum communication system based on historical bit error rate, current signal-to-noise ratio, and channel environment characteristics.

[0012] Further, the acquisition module includes ADC acquisition and ping-pong storage.

[0013] Further, the DSP core processor has a built-in matched filter signal synchronization detection algorithm, which uses a matched filter synchronization signal detection mechanism. The DSP core processor has a built-in underwater acoustic communication system identification module that can add communication system information during transmission and solve communication system information during reception.

[0014] A multi-mode underwater acoustic communication method based on a heterogeneous dual-core architecture, using a multi-mode underwater acoustic communication system based on a heterogeneous dual-core architecture, comprising the following steps:

[0015] Step 1: The host computer sets the IP and port number, packages the source data to be sent and waveform files;

[0016] Step 2: The ARM core processor listens to UDP and serial ports, parses the received data, and forwards it to the DSP core processor;

[0017] Step 3: The DSP core processor listens to shared memory, modulates the passband data according to the communication system parsed by the ARM core processor, and drives the transmitting module;

[0018] Step 4: The receiving end runs the receiving task by default, performs synchronization detection, and after successful synchronization, executes the signal processing algorithm;

[0019] Step 5, after the DSP core processor calculates the signal-to-noise ratio and channel state information, the information is returned to the ARM core processor, the ARM core processor encapsulates the data packet file of the receiver state at this time, and returns to the upper computer and writes into the log, and the ARM decides the optimal communication system according to the state information.

[0020] The application includes multi-mode underwater acoustic communication system integration, underwater acoustic signal recording, log storage and arbitrary underwater acoustic signal waveform transmission. Firstly, the system integrates direct sequence spread spectrum, multi-ary spread spectrum, binary phase shift keying and quaternary phase shift keying underwater acoustic communication systems, secondly, the system designs an underwater acoustic communication system with underwater acoustic communication modulation and demodulation, transmission and reception of underwater acoustic communication signals and recording of logs and received signal waveforms, the system also has the function of transmitting arbitrary waveforms through the upper computer and can combine the environmental evaluation module to switch the system. The application provides a multi-mode underwater acoustic communication system integration, integrates various underwater acoustic communication systems, optimizes the decision of the underwater acoustic communication system by using environmental perception, enhances the reliability of data, enhances the anti-interference ability of the system, reduces the burden of the processor and improves the real-time performance of the system.

[0021] The multi-mode underwater acoustic communication system and communication method based on the heterogeneous dual-core architecture can effectively solve the problems of limited application of single communication mode and unstable underwater acoustic communication link in different complex sea areas, and effectively improve and guarantee the information collaboration and backhaul of underwater vehicles in deep sea areas and the system capacity of deep sea observation and monitoring networks. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a system overall architecture block diagram of the application, showing the connection relationship of dual-core processors, transmission / reception modules and external interfaces.

[0023] Figure 2 It is a detailed flowchart of Figure 1 .

[0024] Figure 3 It is a data packet structure of shared memory in the embodiment.

[0025] Figure 4 It is a data packet structure of network communication in the embodiment. DETAILED DESCRIPTION

[0026] In order to further illustrate the technical means and effects taken by the application to achieve the predetermined purpose, the application is described in detail as follows in combination with the drawings and preferred embodiments:

[0027] A multi-mode underwater acoustic communication system and communication method based on a heterogeneous dual-core architecture, aiming at the key problem that a single communication mode is difficult to adapt to the complex and changeable marine environment, provides a system integration method for multi-mode underwater acoustic communication system integration, underwater acoustic signal recording, log storage, arbitrary underwater acoustic signal waveform transmission and environment adaptive system switching. Figure 1 The system adopts modular design and mainly includes a main control module, an acquisition module and a transmission module.

[0028] The main control module adopts a dual-core heterogeneous processor OMAPL138 as a core board. The OMAPL138 includes an ARM core processor and a DSP core processor. The programs of the embodiment are run on the core board, wherein the ARM core processor runs a Linux system, and the DSP core processor runs a SYS / BIOS real-time system.

[0029] The acquisition module adopts ADS8568, which supports eight-channel synchronous sampling at a maximum of 510 kbps; a preamplifier amplifies weak signals and reduces noise interference; and a post-amplifier amplifies and filters signals again to improve output gain.

[0030] The transmission module adopts DA5724, which can be configured as four channels, 12 / 14 / 16-bit digital-to-analog conversion; and a power amplifier performs power amplification on the electrical signals processed by the front end, so that it can drive the underwater acoustic transducer, convert the electrical signals into acoustic signals and radiate them into the water.

[0031] The working process of the system is performed according to Figure 2

[0032] Step 1, the upper computer sets the IP and port number, packs the source data to be sent and the waveform file;

[0033] Step 2, the ARM core processor listens to the UDP and the serial port, parses the received data, and forwards it to the DSP core processor;

[0034] Step 3, the DSP core processor listens to the shared memory, modulates the passband data according to the communication system parsed by the ARM core processor, and drives the transmission module;

[0035] Step 4, the receiving end runs the receiving task by default, performs synchronization detection, and after synchronization is successful, executes the signal processing algorithm;

[0036] Step 5, the DSP core processor calculates the signal-to-noise ratio and channel state information, and returns these information to the ARM core processor, the ARM core processor packages the data packet file of the receiver state at this time, and returns it to the upper computer and writes it into the log, and the ARM decides the optimal communication system according to the state information.

[0037] ​The above steps need the cooperation of running threads in the ARM core processor and the DSP core processor, and the thread logic is as follows:

[0038] 1、The Linux system of the ARM core processor in the embodiment is mainly responsible for the functions of host computer interaction, log storage, channel evaluation, etc. Specifically, the working state of the ARM core processor is as follows:

[0039] (1) After power-on, the Linux system provided by the core board is run, and the startup script written in the embodiment is run. The specific execution content of the startup script includes setting the static IP of the system and running the dual-core engineering script. The content of the dual-core engineering script includes: mounting the DSP core program, mounting the Syslink driver, and running the executable file of the ARM core processor. The Syslink driver provides inter-core interaction capability for ARM and DSP. In the embodiment, the shared memory provided by Syslink is mainly used as the data interaction of the ARM and DSP core processors.

[0040] (2) Specifically, after the ARM core processor is run, the following steps are executed:

[0041] 1) The Syslink module is initialized, the serial port is initialized, the serial port parameter baud rate 115200 is configured, and the serial port reading time is added to the epoll process;

[0042] 2) The core confirmation between the ARM core processor and the DSP core processor is realized by using the IPC module of Syslink. The shared memory area shared by the ARM and DSP dual-core processors is established by using Syslink;

[0043] 3) The ARM core processor thread is created, including the DSP core processor data thread, the serial port data thread, the timing trigger thread, and the network port data processing thread. Specifically, the content realized by the four threads includes:

[0044] ① The DSP core processor data thread is mainly used to realize the detection of the shared memory area, store logs, and switch the communication system, etc. The information interaction data packet structure of the shared memory in the embodiment is as follows: Figure 3The data preparation flag is detected once per second, and after the thread detects the data, the type of the message is determined, including synchronization to signal, signal saving, and one frame signal decoding completion. Respectively: after the synchronization to signal message, the thread reads the RTC time and writes it in the log file; when saving the signal, the communication signal data in the shared memory area is named according to the RTC time and written as a binary file for subsequent debugging analysis; when the signal decoding is completed, the received signal-to-noise ratio, communication system number, and decoding data content in the shared memory area are written into the log file, and the data is sent out through UDP and serial port for the next step processing by other devices or the host computer. When the writing is completed, the channel evaluation module is called to switch to the optimal communication system.

[0045] ②The main function of the serial port data waiting thread is to receive control instructions from other devices (such as environmental observation data, including CTD, ADCP, etc.) to realize data information modulation or network forwarding. The thread realizes serial port data reading through the epoll event in the initialization of the serial port. The serial port data receiving and processing function based on the epoll mechanism is mainly used for asynchronous communication management in embedded systems. The specific execution process includes: first, initialize the shared memory access pointer and data processing buffer, then enter the permanent event listening loop, and call epoll_wait to block and wait for serial port event triggering. When a readable event is detected, the system reads the data in a 256-byte block in a streaming manner, and uses a multi-level buffer splicing mechanism to handle data packeting. The number of continuous data blocks is tracked through a counter variable to realize indefinite length serial port data reception. After the complete data frame is received, a special protocol analysis function is called to decode the original binary data and extract key information. For legal data frames that pass the verification, the system performs multi-dimensional data processing: creates a log record with a timestamp; stores device working parameters (such as required communication system and power level); converts the received payload into readable hexadecimal format for debugging output; finally, writes the parsed communication data and protocol header information into the shared storage area to realize efficient data exchange with the DSP processing module.

[0046] ③ The timing task thread implements the automatic data processing and scheduling function based on file time trigger, mainly applied to the periodic task management of embedded system. The thread continuously monitors the text files in the specified directory, and executes the timing task scheduling according to the timestamp information embedded in the file name. In the loop execution process, firstly, the current local time is obtained, and then the directory is scanned, and the timestamp of the text file meeting the naming format is parsed and sorted. The system organizes the file list in time sequence through the bubble sort algorithm, ensuring the accuracy of the task execution timing. For the expired files (timestamp earlier than the current time), the thread automatically performs the cleaning operation to delete the files. When the file timestamp and the current time are detected to be exactly matched, the core processing flow is triggered: reading the file content and parsing the stored hexadecimal data therein; constructing a complete message packet containing the protocol header (including instruction identifier, data length, power level and communication system number) and data payload; writing the message packet into the shared memory to realize the data interaction with the DSP. At the same time, the operation log with timestamp is generated, which records the sent system parameters and original hexadecimal data in detail, and finally the processed file is removed. The thread is triggered periodically to ensure that the system can respond to the preset timing task requirements in real time.

[0047] ④ The network port data processing thread is based on the external data receiving and multi-task scheduling function of UDP protocol, used for the communication of the upper host. After the thread is started, it binds the 9600 port to listen to all network interfaces, and continuously receives data packets from the specified IP address (192.168.1.107). The protocol of the network port data processing thread is as follows: Figure 4 When the data is successfully received, the system executes the differentiated processing flow according to the message type in the message header: for the immediate execution instruction, the system parameters and hexadecimal data payload in the message body are directly extracted, the operation log with timestamp is generated, and the complete data packet is transmitted to the DSP shared memory area, waiting for the DSP to modulate and send signals; for the timing task instruction, the time parameters (year, month, day) and task configuration (number of repetitions and interval) in the message are parsed, and multiple timestamp text files are dynamically generated and stored in the specified directory, each file containing the original hexadecimal data string, realizing the timing sending of signals; for the time synchronization instruction, the time information carried in the message is used to accurately calibrate the system clock; for the waveform file transmission instruction, the binary reading and forwarding of waveform data is realized, which encapsulates the content of the floating point waveform file in the specified directory into a structured data packet and writes it into the DSP shared memory area.

[0048] 2、In this embodiment, the Linux system of the ARM core processor is mainly responsible for the functions of communication signal sending, signal collection, detecting communication signal and decoding, receiving parameter calculation, etc. Specifically, the working state of the DSP core processor is:

[0049] (1) DSP core processor is mounted and started after Linux boot script runs, and waits for inter-core confirmation of ARM core processor. After inter-core communication is established, the DSP core processor performs peripheral initialization, thread initialization, etc. The DSP has strong floating point operation capability, and is responsible for execution of most algorithms in the application. When the device runs, the DSP continuously solves data from the signal acquisition module to monitor whether communication signals arrive, and completes calculation of signal-to-noise ratio, identification of communication system, decoding, and forwarding to the ARM core processor, etc. In addition, the DSP core processor is responsible for listening to control instructions from the ARM core processor, and performing data modulation and sending of the corresponding modulation mode.

[0050] (2) Specifically, after the DSP core processor runs, the following steps are performed:

[0051] Peripheral initialization is performed, including GPIO, ADC, and DAC driving. After peripheral initialization is completed, the SYSBIOS built-in thread creates a DSP core processor main thread, and finally runs the BIOS;

[0052] (3) After the DSP core processor system runs, inter-core communication with the ARM is established in the DSP core processor main thread. Specifically, four core threads of the DSP are created in the DSP core processor, including a signal sending thread, a signal receiving thread, a waiting ARM core processor data thread, and a thread for sending data to the ARM core processor. Through the combination of the four threads, the DSP core processor modulates and sends communication signals, solves communication data, returns information to the ARM core processor, and is controlled by the ARM core processor, etc. Specifically, the contents of the four threads include:

[0053] ① The waiting ARM core processor data thread is based on shared memory, and is mainly used for real-time response processing of the DSP to the ARM data. After the thread is started, the data buffer is initialized and enters a continuous monitoring state. The flag bit of the shared memory area is polled to detect the data update event issued by the ARM side. When the flag bit is identified, the key communication parameters are extracted from the shared memory area, including data payload length, power level, communication system number, and receiver working mode, etc. Core configuration information. After the data extraction is completed, the thread updates the system running state: the signal sending thread is triggered through the semaphore mechanism to modulate and frame the information to be modulated according to the communication system and power level extracted by the shared memory, and finally to send signals. After all operations are performed, the thread resets the shared memory first address mark to the initial state, releases the ARM core processor data update permission, and enters the next round of detection and waiting.

[0054] ②The thread sending data to the ARM kernel processor is mainly used to realize the multi-mode communication data and channel parameter transmission from DSP to ARM, and adopts the task triggering mechanism based on semaphore and shared memory communication mode. After the thread is started, it continuously waits for the acquisition module to trigger the receiving semaphore and continuously detects whether the communication frame arrives. When the communication signal frame synchronization is successful, the communication system is determined and the corresponding system algorithm is used for demodulation and decoding. The thread is triggered by the semaphore mechanism and divided into three event types: synchronization success event; signal data saving event; decoding log event (communication decoding result, including original hexadecimal data payload, communication system identification, Doppler factor and signal-to-noise ratio, etc.). After the operation is completed, the thread will modify the read flag value and actively prompt the ARM kernel processor to perform data extraction, realizing the differentiated data transmission demand and state notification.

[0055] ③The signal sending thread realizes the real-time generation and emission control function of multi-mode underwater acoustic communication signals, which is the core processing module of the multi-mode underwater acoustic communication system. The thread is triggered by the semaphore mechanism to execute the process. First, the preset power level parameter is converted into the corresponding DAC output amplitude value. Then, the corresponding signal processing algorithm is selected according to the communication system number: for 1-4 conventional communication systems (including BPSK, QPSK, multi-order spread spectrum and direct sequence spread spectrum four modes), the received hexadecimal data is converted into binary sequence, and the special modulation algorithm is called to generate the baseband floating point signal; for arbitrary waveform mode, the preset waveform data is directly copied from the shared memory; after the signal generation is completed, the floating point data is converted into 16-bit integer format which can be directly output by DAC through amplitude scaling, and the transducer is driven to complete the emission of physical signal. After all the processes are completed, resource cleaning and state resetting are performed, including releasing the dynamically allocated signal buffer, resetting the sending flag, so that the system returns to the ready-to-receive state.

[0056] ⑤The signal receiving thread realizes the real-time signal receiving and processing function of multi-mode underwater acoustic communication signals, and is the core processing module of the multi-mode underwater acoustic communication system. The system defaults to the receiving mode, and the ADC continuously collects signals at a sampling rate of 96 kHz. Through the ping-pong buffer technology, the data is alternately stored in the two 16 kB data buffer areas in DDR2, ensuring continuous sampling without interruption. After the thread is started, the signal processing environment is first initialized, including the generation of local linear frequency modulation signals and the memory allocation of various signal processing calculation required buffer areas. In the continuous running process, the thread waits for the AD acquisition completion event through the semaphore synchronization, and triggers the data movement and quantization preprocessing after the event. In the general multi-mode receiving mode, the system uses a two-step synchronous detection algorithm to determine the signal starting position. When the valid communication signal header signal is detected, the leading signal is stored and the ARM kernel processor is notified of the synchronization success event. Then, multiple frames of data are continuously collected according to the frame structure until the predetermined frame number is reached, and the ARM is notified to store the original signal. After completing the signal acquisition, fine synchronization positioning is performed, and through two-level synchronization detection, the specific communication system (including BPSK, QPSK, multi-order spread spectrum and direct sequence spread spectrum four modes) is identified. Differentiated processing chains are performed for different systems: Doppler compensation calculation (resampling technology), fine synchronization positioning, signal demodulation, etc. Finally, the binary data obtained by decoding is converted to hexadecimal format, and the key parameters (Doppler factor, signal-to-noise ratio) and decoding results are packaged as shared memory data packets and submitted to the ARM kernel processor. After all operations are completed, resource cleaning and state resetting are performed to prepare for the next receiving task.

[0057] In the whole process, the dual-core processor has clear division of labor: the ARM kernel processor is responsible for protocol analysis, task scheduling and human-computer interaction, the DSP kernel processor is focused on signal processing and real-time control, and integrates four communication systems and channel evaluation modules, with multi-mode compatibility and adaptive environmental change processing capability, effectively improving the communication system energy, and suitable for reliable communication requirements of underwater robots, autonomous underwater vehicles and other high-speed mobile platforms.

Claims

1. A multi-mode underwater acoustic communication system based on a heterogeneous dual-core architecture, characterized in that: Including main control module, acquisition module and transmission module; The main control module adopts the dual-core heterogeneous processor OMAPL138 composed of an ARM core processor and a DSP core processor; the ARM core processor and the DSP core processor communicate with each other through shared memory and interrupts; the DSP core processor is responsible for receiving the information to be modulated from the ARM core processor, modulating and controlling the broadcast of underwater acoustic communication signals, driving the transmitting module, detecting the synchronization signal and solving the system category, original signal waveform data, signal-to-noise ratio, Doppler factor, and decoding information of direct sequence spread spectrum DSSS, multi-level frequency shift keying, binary phase shift keying, and quaternary phase shift keying when on standby, and transmits the information to the ARM core processor; the ARM core processor runs the Linux system and processes the network port and serial port data from the host computer, including reading the configuration information of the network port or serial port and the information to be modulated; reading the time through the RTC driver and setting the timed transmission; reading the arbitrary waveform data into the memory and sending it; calculating the optimal communication system for the current environment; The acquisition module uses ADS8568, which supports eight-channel synchronous sampling at a maximum rate of 510kbps; The preamplifier amplifies weak signals and reduces noise interference; the postamplifier amplifies the filtered signal for a second time and increases the output gain; The transmitting module uses DA5724, which can be configured as a four-channel, 12 / 14 / 16-bit digital-to-analog conversion; the power amplifier amplifies the electrical signal processed by the front end, so that it can drive the underwater acoustic transducer, convert the electrical signal into an acoustic signal and radiate it into the water.

2. The multi-mode underwater acoustic communication system based on heterogeneous dual-core architecture according to claim 1 is characterized in that: The ARM core processor integrates a channel quality assessment model and dynamically selects BPSK, QPSK, multi-ary frequency shift keying or direct sequence spread spectrum communication system according to historical bit error rate, current signal-to-noise ratio and channel environment characteristics.

3. The multi-mode underwater acoustic communication system based on heterogeneous dual-core architecture according to claim 1 is characterized in that: The acquisition module includes ADC acquisition and ping-pong storage.

4. The multi-mode underwater acoustic communication system based on heterogeneous dual-core architecture according to claim 1 is characterized in that: The DSP core processor has a built-in matched filter signal synchronization detection module, which adopts a matched filter synchronization signal detection mechanism; the DSP core processor has a built-in underwater acoustic communication system identification module, which can add communication system information during transmission and resolve communication system information during reception.

5. A multi-mode underwater acoustic communication method based on a heterogeneous dual-core architecture, characterized in that: A multi-mode underwater acoustic communication system based on a heterogeneous dual-core architecture according to any one of claims 1 to 4 is adopted, comprising the following steps: Step 1: The host computer sets the IP and port number, and packages the data and waveform files to be sent by the source; Step 2: The ARM core processor monitors the UDP and serial ports, parses the received data, and forwards it to the DSP core processor; Step 3: The DSP core processor monitors the shared memory, modulates the data into passband data according to the communication system analyzed by the ARM core processor, and drives the transmitter module; Step 4: The receiving end runs the receiving task by default and performs synchronization detection. After synchronization is successful, the signal processing algorithm is executed; Step 5: After calculating the signal-to-noise ratio and channel status, the DSP core processor transmits this information back to the ARM core processor. The ARM core processor encapsulates the data packet file of the receiver status at this time, transmits it back to the host computer and writes it into the log. The ARM decides the optimal communication system based on the status information.

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