Split gate field effect transistor with ESD (Electro-Static Discharge) discharge path and low-cost preparation method of split gate field effect transistor

Abstract

The invention discloses a split gate field effect transistor with an ESD discharge path and a low-cost preparation method thereof. The split gate field effect transistor comprises a low-resistance N + substrate, two ends of the low-resistance N + substrate are respectively provided with a drain metal and an epitaxial layer, the top of the epitaxial layer is provided with a plurality of grooves, the side walls of the grooves are covered with first dielectric layers, and split gates and control gates are arranged in the grooves; the control gate and the split gate are isolated through a second dielectric layer in the range of the active region, the control gate and the split gate are short-circuited in the range of the transition region, the short-circuited part of the control gate is provided with a plurality of P-type regions, and the plurality of P-type regions are connected through N-type regions. According to the split gate field effect transistor, a plurality of PN junctions are introduced between the control gate and the split gate of the transition region of the traditional split gate field effect transistor to form a back-to-back Zener diode, and when an ESD event occurs, electrostatic charges are discharged through the Zener diode, so that the voltage between the gate and the source is not higher than the rated gate-source voltage, and the gate and the source are prevented from breaking down and damaging the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a split gate field effect transistor with an ESD discharge path and a low-cost manufacturing method thereof. BACKGROUND

[0002] Split gate field effect transistor (SGT-MOS) is an advanced power semiconductor device, which uses a vertical field plate extending into a semiconductor epitaxial material to modulate the electric field of the semiconductor epitaxial material and shield between the gate and the drain, thereby reducing the specific on-resistance of the device and improving the switching efficiency of the device, thereby reducing the device loss in both steady state and dynamic state, becoming a highly competitive product category in the field of low-voltage power semiconductor devices. The related products are mainly used in emerging fields such as power management, motor control, inverter, energy storage system, etc. Due to the special structure of the split gate field effect transistor, it will face the danger of electrostatic discharge; the specific manifestations are: 1. The split gate and trench structure cause the ESD current path to be dispersed, and the pass-through protection method is difficult to cover all sensitive nodes. 2. The deep trench bottom is easy to form a high electric field area when ESD occurs, causing local avalanche breakdown. 3. The high cell density of the split gate causes the high heat generated by the ESD event to be difficult to dissipate, causing local metal melting or semiconductor material melting. 4. The split gate device uses the charge balance principle to improve the performance of the device, which is sensitive to process precision, and the ESD protection structure needs to be implemented without significantly increasing the processing cost and affecting the process precision. SUMMARY

[0003] The purpose of the present application is: in view of the problem that when ESD event occurs, a transient high voltage will be generated between the ports of the split gate field effect transistor, which will cause electrical failure and even thermal failure to cause the device to burn out if not protected, the present application proposes a split gate field effect transistor with an ESD discharge path, and in order to adapt to different split gate field effect transistor process routes, a specific implementation process scheme is given.

[0004] The technical scheme of the present application: A split gate field effect transistor with ESD discharge path, comprising a low resistance N+ substrate, a drain metal and an epitaxial layer arranged at two ends of the low resistance N+ substrate, a plurality of grooves processed on the top of the epitaxial layer, a first dielectric layer covering the sidewall of the grooves, a split gate and a control gate arranged in the grooves; the control gate and the split gate are isolated by a second dielectric layer within the active area range, the control gate and the split gate are short-circuited within the transition area range, the short-circuited part of the control gate is provided with a plurality of P-type regions, the plurality of P-type regions are connected by N-type regions, the top of the epitaxial layer is covered by a metal isolation dielectric, the top of the metal isolation dielectric is provided with a gate metal and a source metal, the middle part of the gate metal is provided with a protrusion penetrating into the control gate through the metal isolation dielectric, and the middle part of the source metal is provided with a protrusion penetrating into the split gate through the metal isolation dielectric.

[0005] The control gate and the split gate are arranged in up-down distribution or left-right distribution in the grooves. When arranged in up-down distribution, the control gate is arranged above the split gate. When arranged in left-right distribution, the control gate is arranged on both sides of the top end of the split gate.

[0006] The two sides of the plurality of P-type regions can be provided with field limiting rings.

[0007] The P-type regions are doped regions with a doping type opposite to that of the control gate, and the N-type regions are doped regions with the same doping type as that of the control gate.

[0008] When the control gate and the split gate are arranged in up-down distribution in the grooves, a low-cost preparation method of a split gate field effect transistor of the present application has the following steps: Step 1: cleaning the N+ substrate; Step 2: epitaxial growth to form an N- epitaxial layer on the N+ substrate; Step 3: etching to form grooves on the N- epitaxial layer; Step 4: forming a dielectric layer in the grooves; Step 5: forming a split gate in the dielectric layer; Step 6: etching off the top of the dielectric layer and the top of the split gate in the active area range; Step 7: forming a second dielectric layer in the etching area; Step 8: dry oxygen etching to form a gate oxide layer on the sidewall of the groove; Step 9: forming a control gate on the second dielectric layer and between the gate oxide layers; Step 10: using ion implantation to form P-type regions on the surface of the silicon wafer; Step 11: using ion implantation to form mutually independent P-type regions on the control gate located in the transition area of the chip Step 12: annealing, activating the P-type region impurities on the surface of the silicon wafer and pushing the P-type region to a certain junction depth, and simultaneously activating the mutually independent P-type region impurities on the control gate to form back-to-back Zener diodes with N-type polysilicon. Step 13: Use ion implantation to create an N+ region on the surface of the silicon wafer; Step 14: Make a dielectric layer to cover the surface of the silicon wafer; Step 15: Open contact holes in the surface dielectric layer, and simultaneously make source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation to create a high-concentration, low-resistance region in the contact hole; Step 17: Surface metal preparation to form ohmic contact with the low resistance area in the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Prepare a passivation layer and etch the passivation layer to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter an ohmic contact metal on the back side, followed by annealing to form a drain ohmic contact; Step 21: The back metal is thickened to form a drain electrode.

[0009] A low-cost method for preparing a split-gate field-effect transistor of the present invention when the control gate and the split gate are distributed left and right in the trench comprises the following steps: Step 1: N+ substrate cleaning; Step 2: epitaxial growth on the N+ substrate to form an N- epitaxial layer; Step 3: Etching a groove on the N-epitaxial layer; Step 4: Making a dielectric layer in the trench; Step 5: Making a split gate in the dielectric layer; Step 6: Etch away the top of the dielectric layer in the active area and part of the transition area; Step 7: dry oxygen to form the second dielectric layer; Step 8: Etching away the second dielectric layer on the sidewall of the split gate in the transition region; Step 9: Make the control gate, which is connected to the top of the split gate in the transition region; Step 10: Use ion implantation to create a P-type region on the surface of the silicon wafer; Step 11: Using ion implantation to produce independent P-type regions on the control gate located in the transition region of the chip; Step 12: Annealing to activate the P-type impurities on the surface of the silicon wafer and push the P-type region to a certain junction depth. At the same time, the independent P-type impurities on the control gate are activated to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Use ion implantation to create an N+ region on the surface of the silicon wafer; Step 14: Make a dielectric layer to cover the surface of the silicon wafer; Step 15: Open contact holes in the surface dielectric layer, and simultaneously make source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation makes high concentration low resistance area in the contact hole; Step 17: Surface metal preparation, forming ohmic contact with low resistance area in the contact hole; Step 18: Metal patterning forms source and gate electrodes; Step 19: Passivation layer preparation, and etching passivation layer to form wire bonding window; Step 20: Silicon wafer back thinning and back ohmic contact metal sputtering, annealing to form drain ohmic contact; Step 21: Back metal thickening to form drain electrode.

[0010] By using ion implantation to make independent P-type area on the control gate in the chip transition area, the process step is used to synchronize P-line implantation on the silicon surface between the trenches, and the subsequent heat process forms a field limiting ring in the transition area.

[0011] The beneficial effects of the present application are: The present application connects the gate and the source by setting a lateral back-to-back Zener diode in the transition area between the active area and the terminal area of the split gate field effect transistor, and builds an ESD discharge channel. When an ESD event occurs, the static charge will flow out of the device through the channel, thereby playing an ESD role for the device. In terms of product cost, the structure added by the present application is located in the transition area, and the split gate of the split gate field effect transistor needs to be grounded, so there is a natural spacing of about 20 μm between the split gate and the control gate, which is enough to set multiple independent P-type areas to form a back-to-back Zener diode. Therefore, the structure added by the present application does not increase the chip area and thus the product cost; in terms of process complexity and compatibility, the present application only needs to add one ion implantation to the traditional split gate field effect transistor process flow, and does not change the trench topography and slot wall oxide layer structure which affect the split gate structure voltage resistance and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a schematic diagram of the split gate field effect transistor with ESD discharge path of the present application.

[0013] Figure 2 is a schematic diagram of the structure connected with the metal layer when the control gate and the split gate of the present application are distributed in the upper and lower directions.

[0014] Figure 3 is a schematic diagram of the three-dimensional structure of the traditional device.

[0015] Figure 4 is a schematic diagram of the structure when the control gate and the split gate of the present application are distributed in the upper and lower directions.

[0016] Figure 5 is a schematic diagram of the structure when the control gate and the split gate of the present application are distributed in the left and right directions.

[0017] Figure 6 is a schematic diagram of a three-dimensional structure of a conventional device of a left-right split process route.

[0018] Figure 7 is a schematic diagram of a structure with a field limiting ring synchronously manufactured in a transition region according to the present application.

[0019] Figure 8 is a comparison diagram of port voltage and current curves of the present application and a conventional device under an ESD event.

[0020] Figure 9 is a process flow diagram of a transistor manufacturing method of an up-down split structure of Example 1 and Example 2.

[0021] Figure 10 is a process flow diagram of a transistor manufacturing method of a left-right split structure of Example 3.

[0022] Figures 11 to 22 is a process flow diagram of a manufacturing method of Example 1 and Example 2.

[0023] The reference signs: 1-drain metal, 2-low-resistance N+ substrate, 3-high-resistance N- epitaxial layer, 4-first dielectric layer, 5-second dielectric layer, 6-control gate, 7-split gate, 8-first P-type region, 9-first N-type region, 10-second P-type region, 11-second N-type region, 12-third P-type region, 13-gate metal, 14-source metal, 15-intermetallic isolation dielectric, 16-cell P-type region, 17-first field limiting ring P region, 18-second field limiting ring P region, 19-third field limiting ring region. DETAILED DESCRIPTION

[0024] Example 1: As Figure 1 A split gate field effect transistor with ESD protection capability includes a drain metal 1, a low-resistance N+ substrate 2 above the drain metal electrode, and a high-resistance N- epitaxial layer 3 above the low-resistance N+ substrate; a deep trench region above the high-resistance N- epitaxial layer, wherein from bottom to top, there are a dielectric layer 4, a split gate 7 vertically deep into the trench, a dielectric layer 5 provided on the left side of the upper part of the split gate, a control gate 6, a first P-type region 8, a first N-type region 9, a second P-type region 10, a second N-type region 11, and a third P-type region 12 of the device provided on the upper part of the dielectric layer 5 from left to right, and the right side of the P-type region 12 is connected with the split gate 7; a gate metal 13 above the control gate, a source metal 14 above the split gate, and a dielectric 15 between the gate metal and the source metal. The number of P-type regions and N-type regions on the upper part of the dielectric layer 5 can be adjusted.

[0025] The present application connects the gate and the source by setting a lateral back-to-back Zener diode in the transition zone between the active region and the terminal region of the split gate field effect transistor, and the two ends of the diode are connected with the gate of the active region and the source field plate at the edge of the transition zone respectively, as shown in Figure 1 When an ESD event occurs, the electrostatic potential between the gate and the source is greater than the starting voltage of the Zener diode, the electrostatic charge will be discharged through the Zener diode, and the Zener diode will clamp the potential difference between the gate and the source at the maintaining voltage of the Zener diode, thereby ensuring that the voltage between the gate and the source is not higher than the rated gate-source voltage, avoiding the gate-source breakdown and damaging the device, and the electrostatic charge will flow out of the device through the discharge path formed by the back-to-back Zener diode, thereby playing an ESD protection role for the device. In terms of product cost, the structure added by the present application is located in the transition zone, and the split gate of the split gate field effect transistor needs to be grounded, so there is a natural spacing of about 20 μm between the split gate and the control gate, which is sufficient to set multiple independent P-type regions to form a back-to-back Zener diode. (For the sake of convenience, the number of P-type regions in the drawings attached to the present application is three, but in actual application, the number of P-type regions can be increased or decreased according to demand.) Therefore, the structure added by the present application will not increase the chip area and thus the product cost; in terms of process complexity and compatibility, the present application only needs to add one ion implantation to the traditional split gate field effect transistor process flow, and does not change the trench morphology and slot wall oxide layer structure which affect the voltage resistance and reliability of the split gate structure.

[0026] To illustrate the gain effect of the present application, a traditional split gate field effect transistor is used as a comparison, the device structure is as shown in Figure 3 TCAD Sentaurus numerical simulation tool is used for simulation verification. The IV curve of the split gate field effect transistor with ESD discharge path provided by the present application and the traditional split gate field effect transistor under ESD event is as shown in Figure 8 As can be seen, under the same ESD voltage level, the present application clamps the port voltage at a lower level, while as a comparison, the port voltage of the traditional split gate field effect transistor increases sharply under the condition of discharging the same current, and when the voltage reaches the gate oxide voltage limit, the gate oxide is broken down and the device is damaged.

[0027] Embodiment 2: The process flow of the present application is as shown in Figure 9 The process flow schematic diagram is as shown in Figures 11 to 22 The final product structure diagram is as shown in Figure 2 The process flow of the present application is as shown in Step 1: N+ substrate cleaning; Step 2: epitaxial growth to form an N- epitaxial layer on the N+ substrate; Step 3: etching to form a trench on the N- epitaxial layer; Step 4: Make the first dielectric layer with thickness of 3300A in the trench; Step 5: Make the split gate in the dielectric layer, the split gate is of N type polysilicon with thickness of 8K A and sheet resistance of ; Step 6: Etch the top of the dielectric layer and the top of the split gate in the active area to a depth of 1.3 μm; Step 7: Make the second dielectric layer with thickness of 0.4 μm in the etched area; Step 8: Make the gate oxide layer with thickness of 600A in the trench side wall by dry oxygen; Step 9: Make the control gate on the second dielectric layer and between the gate oxide layers, the control gate is of N type polysilicon with thickness of 8K A and sheet resistance of ; Step 10: Make the P type region on the surface of the silicon wafer by ion implantation, impurity: B / energy: 110KeV / dose: 9.5E12cm -2 ; Step 11: Make the independent P type regions on the control gate in the excess area of the chip by ion implantation, impurity: B / energy: 40keV / dose: 4E15cm -2 .

[0028] Step 12: Anneal to activate the P type impurity on the surface of the silicon wafer and to push the P type region to a certain junction depth, and to activate the independent P type impurity on the control gate to form a back-to-back Zener diode with the N type polysilicon; Step 13: Make the N+ region on the surface of the silicon wafer by ion implantation, impurity: As / energy: 60kev / dose: 8E15cm -2 ; Step 14: Make the dielectric layer with thickness of 5k A to cover the surface of the silicon wafer; Step 15: Open the contact hole in the surface dielectric layer, and simultaneously make the source contact hole, the split gate contact hole and the control gate contact hole; Step 16: Make the high concentration and low resistance region in the contact hole by ion implantation: Impurity: BF2 / energy: 40Kev / dose: 2E15cm -2 , Impurity: B / energy: 40KeV / dose: 1E13cm -2 ; Step 17: Surface metal preparation to form ohmic contact with the low resistance region in the contact hole; Step 18: Metal patterning to form the source and gate electrodes; Step 19: Passivation layer making and etching the passivation layer to form the wire bonding window; Step 20: Thin the back surface of the silicon wafer and sputter the back surface ohmic contact metal, and anneal to form the drain ohmic contact; Step 21: The back metal is thickened to form a drain electrode.

[0029] Example 3: according to Figure 9 The process flow of the present invention can be modified appropriately to achieve the final product structure as shown in FIG. Figure 4 shown.

[0030] The modification points are: Figure 9 Step 11 of the process flow shown is modified to: Use ion implantation to create independent P-type regions on the control gate located in the transition region of the chip, and simultaneously create a field limiting ring region on the surface of the adjacent silicon wafer. Impurity: B / Energy: 40keV / Dose: 4E15cm -2 .

[0031] Example 4: like Figure 10 As shown, the split-gate field effect transistor of the ESD discharge path of the present invention can also be prepared by the following steps: Step 1: N+ substrate cleaning; Step 2: epitaxial growth on the N+ substrate to form an N- epitaxial layer; Step 3: Etching a groove on the N-epitaxial layer; Step 4: Fabricate the first dielectric layer with a thickness of 3300Å in the trench; Step 5: Make a split gate in the dielectric layer. The polysilicon type of the split gate is N-type, with a thickness of 8KÅ and a square resistance of ; Step 6: Etch away the top of the dielectric layer in the active area and part of the transition area, but the depth is 1.3 μm; Step 7: Dry oxygen is used to form the second dielectric layer and the gate oxide layer on the trench sidewalls. The gate oxide layer thickness is 600 Å, and the second oxide layer thickness on the split gate sidewall is about 1000 Å. Step 8: Etching away the second dielectric layer on the sidewall of the split gate in the transition region; Step 9: Make the control gate, the polysilicon type is N-type, the thickness is 8KÅ, and the square resistance is , which is connected to the top of the split gate in the transition region; Step 10: Use ion implantation to create a P-type region on the surface of the silicon wafer. Impurity: B / Energy: 110 KeV / Dose: 9.5E12 cm -2 ; Step 11: Use ion implantation to create independent P-type regions on the control gate located in the transition region of the chip. Impurity: B / Energy: 40keV / Dose: 4E15cm -2 ; Step 12: Annealing to activate the P-type impurities on the surface of the silicon wafer and push the P-type region to a certain junction depth. At the same time, the independent P-type impurities on the control gate are activated to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Use ion implantation to create an N+ region on the surface of the silicon wafer. Impurity: As / Energy: 60keV / Dose: 8E15cm -2 ; Step 14: Prepare a 5kÅ thick dielectric layer to cover the surface of the silicon wafer; Step 15: Open contact holes in the surface dielectric layer, and simultaneously make source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation creates a high-concentration, low-resistance region in the contact hole: Impurity: BF2 / Energy: 40Kev / Dose: 2E15cm -2 , Impurity: B / Energy: 40KeV / Dose: 1E13cm -2 ; Step 17: Surface metal preparation to form ohmic contact with the low resistance area in the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Prepare a passivation layer and etch the passivation layer to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter an ohmic contact metal on the back side, followed by annealing to form a drain ohmic contact; Step 21: The back metal is thickened to form a drain electrode.

[0032] Example 5: according to Figure 10 Another process flow of the present invention shown in FIG. 1 can be appropriately modified to achieve a final product structure such as Figure 7 shown.

[0033] The modification points are: Figure 10 Step 11 of the process flow shown is modified to: Use ion implantation to create independent P-type regions on the control gate located in the transition region of the chip, and simultaneously create a field limiting ring region on the surface of the adjacent silicon wafer. Impurity: B / Energy: 40keV / Dose: 4E15cm -2 .

Claims

1. A split-gate field-effect transistor with an ESD discharge path, characterized in that: The invention comprises a low-resistance N+ substrate (2), wherein two ends of the low-resistance N+ substrate (2) are respectively provided with a drain metal (1) and an epitaxial layer (3), a plurality of grooves are processed on the top of the epitaxial layer (3), the sidewalls of the grooves are covered with a first dielectric layer (4), and a split gate (7) and a control gate (6) are provided in the grooves; the control gate (6) and the split gate (7) are isolated by a second dielectric layer (5) within the active region, the control gate (6) and the split gate (7) are short-circuited within the transition region, and the short circuit of the control gate (6) The connection part is provided with a plurality of P-type regions, and the plurality of P-type regions are connected through an N-type region. The top of the epitaxial layer (3) is covered by an intermetallic isolation dielectric (15). The top of the intermetallic isolation dielectric (15) is provided with a gate metal (13) and a source metal (14). The middle of the gate metal (13) is provided with a protrusion that passes through the intermetallic isolation dielectric (15) and extends into the control gate (6). The middle of the source metal (14) is provided with a protrusion that passes through the intermetallic isolation dielectric (15) and extends into the split gate (7).

2. The split-gate field-effect transistor with an ESD discharge path according to claim 1, wherein: The control gate (6) and the split gate (7) are distributed vertically or horizontally in the trench; When the grid is distributed up and down, the control grid (6) is placed above the split grid (7); When the split gates are distributed left and right, the control gate (6) is placed on both sides of the top of the split gate (7).

3. The split-gate field-effect transistor with an ESD discharge path according to claim 2, wherein: When the control gate (6) is placed on both sides of the top of the split gate (7), field limiting rings are provided on both sides of the plurality of P-type regions.

4. The split-gate field-effect transistor with an ESD discharge path according to claim 1, wherein: The P-type region is a doping region having a doping type opposite to that of the control gate (6), and the N-type region is a doping region having a doping type identical to that of the control gate (6).

5. A low-cost method for preparing a split-gate field-effect transistor according to any one of claims 1 to 4, comprising the steps of: Step 1: N+ substrate cleaning; Step 2: epitaxial growth on the N+ substrate to form an N- epitaxial layer; Step 3: Etching a groove on the N-epitaxial layer; Step 4: Making a dielectric layer in the trench; Step 5: Making a split gate in the dielectric layer; Step 6: Etch away the top of the dielectric layer and the top of the split gate within the active area; Step 7: forming a second dielectric layer in the etched area; Step 8: Dry oxygen is used to form a gate oxide layer on the sidewall of the trench; Step 9: Fabricate a control gate on the second dielectric layer and between the gate oxide layers; Step 10: Use ion implantation to create a P-type region on the surface of the silicon wafer; Step 11: Use ion implantation to create independent P-type regions on the control gate located in the transition area of ​​the chip. Step 12: Annealing to activate the P-type impurities on the surface of the silicon wafer and push the P-type region to a certain junction depth. At the same time, the independent P-type impurities on the control gate are activated to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Use ion implantation to create an N+ region on the surface of the silicon wafer; Step 14: Make a dielectric layer to cover the surface of the silicon wafer; Step 15: Open contact holes in the surface dielectric layer, and simultaneously make source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation to create a high-concentration, low-resistance region in the contact hole; Step 17: Surface metal preparation to form ohmic contact with the low resistance area in the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Prepare a passivation layer and etch the passivation layer to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter an ohmic contact metal on the back side, followed by annealing to form a drain ohmic contact; Step 21: The back metal is thickened to form a drain electrode.

6. The split-gate field effect transistor with an ESD discharge path and the low-cost preparation method thereof according to claim 5, characterized in that: The steps for making the control gate are: Step 1: N+ substrate cleaning; Step 2: epitaxial growth on the N+ substrate to form an N- epitaxial layer; Step 3: Etching a groove on the N-epitaxial layer; Step 4: Making a dielectric layer in the trench; Step 5: Making a split gate in the dielectric layer; Step 6: Etch away the top of the dielectric layer in the active area and part of the transition area; Step 7: dry oxygen to form the second dielectric layer; Step 8: Etching away the second dielectric layer on the sidewall of the split gate in the transition region; Step 9: Make the control gate, which is connected to the top of the split gate in the transition region; Step 10: Use ion implantation to create a P-type region on the surface of the silicon wafer; Step 11: Using ion implantation to produce independent P-type regions on the control gate located in the transition region of the chip; Step 12: Annealing to activate the P-type impurities on the surface of the silicon wafer and push the P-type region to a certain junction depth. At the same time, the independent P-type impurities on the control gate are activated to form a back-to-back Zener diode with the N-type polysilicon. Step 13: Use ion implantation to create an N+ region on the surface of the silicon wafer; Step 14: Make a dielectric layer to cover the surface of the silicon wafer; Step 15: Open contact holes in the surface dielectric layer, and simultaneously make source contact holes, split gate contact holes, and control gate contact holes; Step 16: Ion implantation to create a high-concentration, low-resistance region in the contact hole; Step 17: Surface metal preparation to form ohmic contact with the low resistance area in the contact hole; Step 18: Metal patterning to form source and gate electrodes; Step 19: Prepare a passivation layer and etch the passivation layer to form a wire bonding window; Step 20: Thin the back side of the silicon wafer and sputter an ohmic contact metal on the back side, followed by annealing to form a drain ohmic contact; Step 21: The back metal is thickened to form a drain electrode.

7. The low-cost method for preparing a split-gate field-effect transistor according to claims 5 and 6, characterized in that: While using ion implantation to create independent P-type regions on the control gate located in the transition area of ​​the chip, this process step is used to simultaneously perform P-type implantation on the silicon surface between the trenches. Subsequent thermal processes form field limiting rings in the transition area.

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