Drive circuit with automatic dead-time switching based on dual N-power transistor DC-DC architecture

Abstract

This invention discloses a driver circuit with automatic dead-time switching based on a dual-N power transistor DC-DC architecture. It includes a driver circuit, a delay chain circuit, a switch failure prevention circuit, and a sampling logic circuit. The driver circuit transmits the input signal HSON to the output signal HSG. The delay chain circuit outputs a signal HS_DEAD_B with the same delay as signal HSG through delay control, which is then used by the sampling logic circuit for dead-time control. The sampling logic circuit determines which signal, SW or HS_DEAD_B, has a longer delay. The switch failure prevention circuit generates a signal SW_PRE whose delay is not limited by signal VH. This invention combines the delay chain and the sampled SW signal to automatically select either the delay chain or the sampled SW signal for dead-time control at different SW switching speeds, reducing dead-time across the entire load range while ensuring no crosstalk.

Description

Technical Field

[0001] This invention relates to a driving circuit, and more particularly to a driving circuit based on a dual N-power transistor DC-DC architecture with automatic dead-time switching, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] With the continuous growth of electronic products in consumer electronics, industrial electronics, and automotive electronics, the demand for power management ICs is constantly increasing, such as the widespread application of DC-DC switching power supplies and driver circuits. Simultaneously, as the load of electronic devices increases and power output rises, the requirements for high-voltage, high-current power stages are becoming increasingly stringent. Furthermore, to adapt to more complex application environments, input voltage and load current need to be able to withstand large-scale changes in real time. At the same time, to control the overall power consumption of products, the efficiency requirements for power stages are gradually increasing, especially under high current conditions, where the losses in the power stage's driver circuitry account for a significant proportion.

[0003] This presents an increasingly difficult challenge to the dead time of the drive circuit. A slow dead time reduces efficiency, but a fast dead time can easily cause series-through, leading to chip burnout. Traditional dual-N power stages, such as... Figure 7 As shown, its driving circuit is limited by the voltage rise control of the upper transistor, requiring a high-to-low level shift to detect the upper transistor signal. This limits the minimum dead time. Figure 8 As shown. There are several ways to optimize dead time. One is through multi-stage or programmable control [CN119276107A], to find a trade-off between dead time and efficiency, such as... Figure 9 As shown; secondly, the judgment is made by sampling the output voltage of the driver [CN115189565A], which has the risk of crosstalk under high current and high frequency; thirdly, the judgment is made by sampling the SW signal [CN201910145720], which is only applicable to positive current. If there is current under FPWM, it cannot be implemented and the traditional dead time needs to be retained. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a drive circuit with automatic dead-time switching based on a dual N power transistor DC-DC architecture, which solves the series problem that may be introduced by reducing the dead time.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] This is a driver circuit based on a dual-N power transistor DC-DC architecture with automatic dead-time switching. It includes a driver circuit (DRIVER), a delay chain circuit (DEAD_DELAY), a SW failure prevention circuit (SW_PROTECT), and a sampling logic circuit (HSG_SEN_LOGIC). The first input of the driver circuit is connected to the signal HSON, and the second input is connected to the input signal LSG_SEN. The first output of the driver circuit is connected to the input of the delay chain circuit DEAD_DELAY and generates the signal HSON_PRE. The second output of the driver circuit is connected to the first input of the SW failure prevention circuit SW_PROTECT and generates the signal H... SG, the first output of the delay chain circuit DEAD_DELAY is connected to the input of the sampling logic circuit HSG_SEN_LOGIC. The second output of the delay chain circuit DEAD_DELAY is connected to the second input of the SW failure prevention circuit SW_PROTECT and generates the signal HS_DELAY_B. The third input of the SW failure prevention circuit SW_PROTECT is connected to the input signal LSG_SEN. The output of the SW failure prevention circuit SW_PROTECT is connected to the second input of the sampling logic circuit HSG_SEN_LOGIC and generates the signal SW_PRE. The output of the sampling logic circuit HSG_SEN_LOGIC generates the signal HSG_SEN.

[0007] Furthermore, the driving circuit DRIVER includes inverters INV1, INV2, and INV4, NOR1, and level conversion circuit LSF1. The input terminal of inverter INV1 serves as the first input terminal of the driving circuit DRIVER and is connected to the signal HSON. The output terminal of inverter INV1 is connected to the first input terminal of NOR1 and generates the signal HSONB. The second input terminal of NOR1 serves as the second input terminal of the driving circuit DRIVER and is connected to the input signal HSON_PRE. The output terminal of NOR1 is connected to the input terminal of level conversion circuit LSF1 and serves as the first output terminal of the driving circuit DRIVER, generating the signal HSON_PRE. The output terminal of level conversion circuit LSF1 is connected to the input terminal of inverter INV2 and generates the signal HSON_H. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3 and generates the signal HSONB_H. The output terminal of inverter INV3 serves as the second output terminal of the driving circuit DRIVER and generates the signal HSG.

[0008] Furthermore, the power supply terminals of inverter INV1, NOR1, and LSF1 are connected to power supply AVDD; the power supply terminals of LSF1, INV2, and INV3 are connected to signal VH; the ground terminals of inverter INV1, NOR1, and LSF1 are grounded; and the ground terminals of LSF1, INV2, and INV3 are connected to signal SW.

[0009] Furthermore, the delay chain circuit DEAD_DELAY includes a level conversion circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2, and an inverter INV8. The input terminal of the level conversion circuit LSF2 serves as the input terminal of the delay chain circuit DEAD_DELAY and is connected to the signal HSON_PRE. The output terminal of the level conversion circuit LSF2 is connected to the input terminal of the inverter INV6 and generates the signal HSON_L. The output terminal of the inverter INV6 is connected to the input terminal of the delay module DELAY1 and generates the signal HSON_L. B_L, the output of delay module DELAY1 is connected to the input of inverter INV7 and serves as the first output of the delay chain circuit DEAD_DELAY, generating the signal HS_DEAD_B. The output of inverter INV7 is connected to the input of delay module DELAY2 and generates the signal HS_DEAD_BB. The output of delay module DELAY2 is connected to the input of inverter INV8 and generates the signal HS_DELAY. The output of inverter INV8 serves as the second output of the delay chain circuit DEAD_DELAY and generates the signal HS_DELAY_B.

[0010] Furthermore, the VDD1 terminal of the level conversion circuit LSF2, the VDD2 terminal of the level conversion circuit LSF2, the power supply terminal of the inverter INV6, the power supply terminal of the delay module DELAY1, the power supply terminal of the inverter INV7, the power supply terminal of the delay module DELAY2, and the power supply terminal of the inverter INV8 are connected to the power supply AVDD, and the VSS1 terminal of the level conversion circuit LSF2, the VSS2 terminal of the level conversion circuit LSF2, the ground terminal of the inverter INV6, the ground terminal of the delay module DELAY1, the ground terminal of the inverter INV7, the ground terminal of the delay module DELAY2, and the ground terminal of the inverter INV8 are grounded.

[0011] Furthermore, the SW_PROTECT circuit for preventing SW failure includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input terminal of the inverter INV5 is connected to the signal HSG as the first input terminal of the SW_PROTECT circuit. The output terminal of the inverter INV5 is connected to the gate of the PMOS transistor PM1. The source of the PMOS transistor PM1 is connected to the signal VH. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3. The gate of the NMOS transistor NM3 is connected to the signal PVDD. The source of the gate is connected to the drain of the NMOS transistor NM4 and serves as the output of the SW_PROTECT circuit to prevent SW failure, generating the signal SE_PRE. The source of the NMOS transistor NM4 is grounded. The first input of the AND gate AND1 serves as the second input of the SW_PROTECT circuit to prevent SW failure and is connected to the signal HS_DELAY_B. The second input of the AND gate AND1 serves as the third input of the SW_PROTECT circuit to prevent SW failure and is connected to the input signal LSG_SEN. The output of the AND gate AND1 is connected to the gate of the NMOS transistor NM4 and generates the signal LSON_SEN2.

[0012] Furthermore, the power supply terminal of the inverter INV5 is connected to signal VH, the ground terminal of the inverter INV5 is connected to signal SW, the power supply terminal of the AND gate AND1 is connected to power supply AVDD, and the ground terminal of the AND gate AND1 is grounded.

[0013] Further, the sampling logic circuit HSG_SEN_LOGIC includes resistors R3 and R4, PMOS transistors PM2, PM3, PM4, PM5, PM6, NMOS transistors NM5, NM6, and NM7. One end of resistor R3 is connected to signal SW, and the other end of resistor R3 is connected to the gate of PMOS transistor PM2. The sources of PMOS transistors PM2, PM3, PM5, and PM6 are connected to power supply PVDD. The gate of PMOS transistor PM3 is connected to its drain and the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to the gate of NMOS transistor NM5 and serves as the sampling logic circuit HSG_SEN_L. The second input terminal of OGIC is connected to the signal SW_PRE. The drain of PMOS transistor PM2 is connected to one end of resistor R4, the gate of NMOS transistor NM7, and the gate of PMOS transistor PM5. The other end of resistor R4 is connected to the drain of NMOS transistor NM5. The drain of PMOS transistor PM5 is connected to the drain of PMOS transistor PM6 and the drain of NMOS transistor NM6, and serves as the output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate the signal HSG_SEN. The gate of PMOS transistor PM6 is connected to the gate of NMOS transistor NM6, and serves as the first input terminal of the sampling logic circuit HSG_SEN_LOGIC, connected to the signal HS_DEAD_B. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7. The sources of NMOS transistor NM5 and NMOS transistor NM7 are grounded.

[0014] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a drive circuit with automatic dead-time switching based on a dual N power transistor DC-DC architecture. By combining delay chain and sampling SW, the dead time is automatically selected to control the dead time under different SW switching speeds, thereby reducing the dead time across the full load range and ensuring no crosstalk, thus optimizing the overall system efficiency. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the drive circuit with automatic dead-time switching based on the dual N power transistor DC-DC architecture of the present invention.

[0016] Figure 2 This is a circuit diagram of the driver circuit of the present invention.

[0017] Figure 3 This is the circuit diagram of the delay chain circuit DEAD_DELAY of the present invention.

[0018] Figure 4This is the circuit diagram of the SW_PROTECT circuit for preventing SW failure according to the present invention.

[0019] Figure 5 This is the circuit diagram of the sampling logic circuit HSG_SEN_LOGIC of the present invention.

[0020] Figure 6 This is a timing diagram of the drive circuit with automatic dead-time switching based on the dual N power transistor DC-DC architecture of the present invention.

[0021] Figure 7 This is a schematic diagram of the existing dual-N power transistor DC-DC architecture.

[0022] Figure 8 This is a schematic diagram of a drive dead-time control circuit in the prior art.

[0023] Figure 9 This is a schematic diagram of another existing drive dead-time control circuit. Detailed Implementation

[0024] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0025] like Figure 7 The diagram shows a prior art dual-N power transistor DC-DC architecture. The driver circuit of this invention... Figure 7 The HS_DRIVER in the diagram is equivalent to that in the DC-DC architecture of dual N power transistors. The dual N power transistor DC-DC architecture includes dual N power transistors NM1 and NM2, external inductor L, external capacitor C0, voltage divider resistors R1 and R2, upper transistor driver circuit HS_DRIVER, lower transistor driver circuit LS_DRIVER, high voltage power supply VBOOST, and control logic CONTROL LOGIC.

[0026] like Figure 1As shown, the present invention discloses a driver circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture, comprising a driver circuit (DRIVER), a delay chain circuit (DEAD_DELAY), a SW failure prevention circuit (SW_PROTECT), and a sampling logic circuit (HSG_SEN_LOGIC). The first input terminal of the driver circuit is connected to the signal HSON, the second input terminal is connected to the input signal LSG_SEN, the first output terminal of the driver circuit is connected to the input terminal of the delay chain circuit (DEAD_DELAY) and generates the signal HSON_PRE, and the second output terminal of the driver circuit is connected to the first input terminal of the SW failure prevention circuit (SW_PROTECT). The signal HSG is generated. The first output of the delay chain circuit DEAD_DELAY is connected to the input of the sampling logic circuit HSG_SEN_LOGIC. The second output of the delay chain circuit DEAD_DELAY is connected to the second input of the SW_PROTECT circuit to generate the signal HS_DELAY_B. The third input of the SW_PROTECT circuit is connected to the input signal LSG_SEN. The output of the SW_PROTECT circuit is connected to the second input of the sampling logic circuit HSG_SEN_LOGIC to generate the signal SW_PRE. The output of the sampling logic circuit HSG_SEN_LOGIC generates the signal HSG_SEN.

[0027] The driver circuit (DRIVER) is responsible for transmitting the input signal HSON to the output signal HSG. The delay chain circuit DEAD_DELAY, through the delay control of delay module DELAY1, outputs a signal HS_DEAD_B with the same delay as signal HSG, which is used for dead-time control of the sampling logic circuit HSG_SEN_LOGIC. Simultaneously, it is responsible for outputting a signal HS_DELAY_B with a longer delay than signal HSG through the delay control of delay module DELAY2, which is used for signal SW failure protection by the SW_PROJECT circuit. The sampling logic circuit HSG_SEN_LOGIC is responsible for determining which signal has a longer delay: the system input signal SW or the signal HS_DEAD_B output by the delay chain circuit DEAD_DELAY, and uses the signal with the longer delay to control the output signal HSG_SEN. Therefore, under light load, the signal SW flips slowly, while the output signal HS_DEAD_B of the fixed delay chain flips faster, and the flipping of signal HSG_SEN is determined by signal SW; under heavy load, the signal SW flips quickly, while the output signal HS_DEAD_B of the fixed delay chain flips even slower, and the flipping of signal HSG_SEN is determined by signal HS_DEAD_B. Only after signal HSG_SEN flips low and is output to the LS_DRIVER module will signal LSG flip high, thus achieving automatic dead-time switching. The SW_PROTECT circuit, which prevents SW failure, generates a signal SW_PRE whose delay is not limited by signal VH, and outputs it to the sampling logic circuit HSG_SEN_LOGIC. This prevents signal VH from failing to rise under FPWM, causing signal SW to remain at an intermediate potential, resulting in erroneous flipping of signal HSG_SEN, simultaneous high flips of signals LSG and HSG, and the problem of NMOS transistors NM1 and NM2 interconnecting. The dead-time control timing is as follows: Figure 6 As shown, at time t0, signal HSON goes low. Since the delay time of td1 is greater than the time it takes for signal SW to go low, the rising edge of signal HSG_SEN at time t1 is determined by signal HS_DEAD_B. After receiving signal HS_DEAD_B, LSG goes high after a certain delay. Because signal SW goes low before time t2, the delay of td2 does not participate in dead-time control.

[0028] like Figure 2As shown, the driver circuit includes inverters INV1, INV2, and INV4, a NOR gate NOR1, and a level shifter circuit LSF1. The input terminal of inverter INV1 serves as the first input terminal of the driver circuit and is connected to the signal HSON. The output terminal of inverter INV1 is connected to the first input terminal of NOR1 and generates the signal HSONB. The second input terminal of NOR1 serves as the second input terminal of the driver circuit and is connected to the input signal HSON_PRE. The output terminal of NOR1 is connected to the input terminal of level shifter circuit LSF1 and serves as the first output terminal of the driver circuit, generating the signal HSON_PRE. The output terminal of level shifter circuit LSF1 is connected to the input terminal of inverter INV2 and generates the signal HSON_H. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3 and generates the signal HSONB_H. The output terminal of inverter INV3 serves as the second output terminal of the driver circuit and generates the signal HSG.

[0029] The driver circuit is responsible for inverting the input signal HSON into signal HSONB, performing a OR-NOT logic with the input signal LSG_SEN, and boosting it to signal HSON_H with a high level of VH and a low level of SW. After being driven by two stages of inverters, the output signal HSG is generated.

[0030] The power supply terminals of inverter INV1, NOR1, and LSF1 are connected to power supply AVDD. The power supply terminals of LSF1, INV2, and INV3 are connected to signal VH. The ground terminals of inverter INV1, NOR1, and LSF1 are grounded. The ground terminals of LSF1, INV2, and INV3 are connected to signal SW.

[0031] like Figure 3As shown, the delay chain circuit DEAD_DELAY includes a level shifter circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2, and an inverter INV8. The input terminal of the level shifter circuit LSF2 is connected to the signal HSON_PRE as the input terminal of the delay chain circuit DEAD_DELAY. The output terminal of the level shifter circuit LSF2 is connected to the input terminal of the inverter INV6 and generates the signal HSON_L. The output terminal of the inverter INV6 is connected to the input terminal of the delay module DELAY1 and generates the signal HSONB_L. L, the output of delay module DELAY1 is connected to the input of inverter INV7 and serves as the first output of the delay chain circuit DEAD_DELAY, generating the signal HS_DEAD_B. The output of inverter INV7 is connected to the input of delay module DELAY2 and generates the signal HS_DEAD_BB. The output of delay module DELAY2 is connected to the input of inverter INV8 and generates the signal HS_DELAY. The output of inverter INV8 serves as the second output of the delay chain circuit DEAD_DELAY and generates the signal HS_DELAY_B.

[0032] The delay chain circuit DEAD_DELAY is responsible for taking the signal HSONB from the driver circuit DRIVER and the input signal LSG_SEN or the NOT-logic signal HSON_PRE, and using the same level conversion circuit LSF2 and inverter INV6 structure as the driver circuit, to output the signal HSONB_L, which is the delay of the analog signal HSONB_H. The delay control signal HS_DEAD_B of the delay module DELAY1 is matched with the delay of the signal HSG, providing dead-time control for the sampling logic circuit HSG_SEN_LOGIC. Simultaneously, the delay control output signal HS_DELAY_B of the delay module DELAY2 is also responsible for providing a longer delay than the signal HSG, providing failure protection for the SW failure prevention circuit SW_PROJECT.

[0033] The VDD1 and VDD2 terminals of the level conversion circuit LSF2, the power supply terminal of inverter INV6, the power supply terminal of delay module DELAY1, the power supply terminal of inverter INV7, the power supply terminal of delay module DELAY2, and the power supply terminal of inverter INV8 are connected to the power supply AVDD. The VSS1 and VSS2 terminals of the level conversion circuit LSF2, the ground terminal of inverter INV6, the ground terminal of delay module DELAY1, the ground terminal of inverter INV7, the ground terminal of delay module DELAY2, and the ground terminal of inverter INV8 are grounded.

[0034] like Figure 4As shown, the SW_PROTECT circuit for preventing SW failure includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input of the inverter INV5 is connected to the signal HSG as the first input of the SW_PROTECT circuit. The output of the inverter INV5 is connected to the gate of the PMOS transistor PM1. The source of the PMOS transistor PM1 is connected to the signal VH. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3. The gate of the NMOS transistor NM3 is connected to the signal PVDD. The source of the NMOS transistor NM3... The source of NMOS transistor NM4 is connected to the drain of NMOS transistor NM4 and serves as the output of the SW_PROTECT circuit to prevent SW failure, generating the signal SE_PRE. The source of NMOS transistor NM4 is grounded. The first input of AND gate AND1 serves as the second input of the SW_PROTECT circuit to prevent SW failure and is connected to the signal HS_DELAY_B. The second input of AND gate AND1 serves as the third input of the SW_PROTECT circuit to prevent SW failure and is connected to the input signal LSG_SEN. The output of AND gate AND1 is connected to the gate of NMOS transistor NM4 and generates the signal LSON_SEN2.

[0035] The SW_PROTECT circuit, which prevents SW failure, generates a signal SW_PRE that is not delayed by the power supply signal VH and outputs it to the sampling logic circuit HSG_SEN_LOGIC. When the signal HSG goes high, the signal SW_PRE goes high; when the signal HSG goes low, the signal SW_PRE goes low when the signal LSON_SEN2 goes high.

[0036] The power supply terminal of inverter INV5 is connected to signal VH, the ground terminal of inverter INV5 is connected to signal SW, the power supply terminal of AND gate AND1 is connected to power supply AVDD, and the ground terminal of AND gate AND1 is grounded.

[0037] like Figure 5As shown, the sampling logic circuit HSG_SEN_LOGIC includes resistors R3 and R4, PMOS transistors PM2, PM3, PM4, PM5, PM6, NMOS transistors NM5, NM6, and NM7. One end of resistor R3 is connected to the signal SW, and the other end of resistor R3 is connected to the gate of PMOS transistor PM2. The sources of PMOS transistors PM2, PM3, PM5, and PM6 are connected to the power supply PVDD. The gate of PMOS transistor PM3 is connected to its drain and the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to the gate of NMOS transistor NM5 and serves as the sampling logic circuit HSG_SEN_LOG. The second input terminal of the IC is connected to the signal SW_PRE. The drain of PMOS transistor PM2 is connected to one end of resistor R4, the gate of NMOS transistor NM7, and the gate of PMOS transistor PM5. The other end of resistor R4 is connected to the drain of NMOS transistor NM5. The drain of PMOS transistor PM5 is connected to the drain of PMOS transistor PM6 and the drain of NMOS transistor NM6, and serves as the output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate the signal HSG_SEN. The gate of PMOS transistor PM6 is connected to the gate of NMOS transistor NM6, and serves as the first input terminal of the sampling logic circuit HSG_SEN_LOGIC, connected to the signal HS_DEAD_B. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7. The sources of NMOS transistor NM5 and NMOS transistor NM7 are grounded.

[0038] The sampling logic circuit HSG_SEN_LOGIC is responsible for determining which signal has a longer delay: the system input signal SW or the signal HS_DEAD_B output from the delay chain circuit DEAD_DELAY. The signal with the longer delay controls the output signal HSG_SEN. If signal SW goes low first and then signal HS_DEAD_B goes high, then signal HSG_SEN is pulled low after signal HS_DEAD_B goes high; if signal HS_DEAD_B goes high first and then signal SW goes low, then signal HSG_SEN is pulled low after signal SW goes low. If signal SW remains high, and signal HS_DEAD_B goes high first, then signal HSG_SEN is pulled low after signal SW_PRE goes low.

[0039] This invention provides a drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture. By combining delay chain and sampling SW, it automatically selects the delay chain or the sampled SW signal to control the dead time at different SW switching speeds, reducing the dead time across the full load range and ensuring no crosstalk, thereby optimizing the overall system efficiency.

[0040] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture, characterized in that: It includes a driver circuit (DRIVER), a delay chain circuit (DEAD_DELAY), a SW failure prevention circuit (SW_PROTECT), and a sampling logic circuit (HSG_SEN_LOGIC). The first input of the driver circuit (DRIVER) is connected to the signal HSON, and the second input is connected to the input signal LSG_SEN. The first output of the driver circuit (DRIVER) is connected to the input of the delay chain circuit (DEAD_DELAY) and generates the signal HSON_PRE. The second output of the driver circuit (DRIVER) is connected to the first input of the SW failure prevention circuit (SW_PROTECT) and generates the signal HSG. The delay chain circuit (DEAD_DELAY)... The first output of DEAD_DELAY is connected to the input of the sampling logic circuit HSG_SEN_LOGIC. The second output of the DEAD_DELAY delay chain circuit is connected to the second input of the SW_PROTECT circuit to generate the signal HS_DELAY_B. The third input of the SW_PROTECT circuit is connected to the input signal LSG_SEN. The output of the SW_PROTECT circuit is connected to the second input of the sampling logic circuit HSG_SEN_LOGIC to generate the signal SW_PRE. The output of the sampling logic circuit HSG_SEN_LOGIC generates the signal HSG_SEN.

2. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 1, characterized in that: The driver circuit includes inverters INV1, INV2, and INV4, a NOR gate NOR1, and a level conversion circuit LSF1. The input terminal of inverter INV1 serves as the first input terminal of the driver circuit and is connected to the signal HSON. The output terminal of inverter INV1 is connected to the first input terminal of NOR1 and generates the signal HSONB. The second input terminal of NOR1 serves as the second input terminal of the driver circuit and is connected to the input signal HSON_PRE. The output terminal of NOR1 is connected to the input terminal of the level conversion circuit LSF1 and serves as the first output terminal of the driver circuit, generating the signal HSON_PRE. The output terminal of the level conversion circuit LSF1 is connected to the input terminal of inverter INV2 and generates the signal HSON_H. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3 and generates the signal HSONB_H. The output terminal of inverter INV3 serves as the second output terminal of the driver circuit and generates the signal HSG.

3. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 2, characterized in that: The power supply terminals of inverter INV1, NOR1, and LSF1 are connected to power supply AVDD. The power supply terminals of LSF1, INV2, and INV3 are connected to signal VH. The ground terminals of inverter INV1, NOR1, and LSF1 are grounded. The ground terminals of LSF1, INV2, and INV3 are connected to signal SW.

4. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 1, characterized in that: The delay chain circuit DEAD_DELAY includes a level shifter circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2, and an inverter INV8. The input terminal of the level shifter circuit LSF2 serves as the input terminal of the delay chain circuit DEAD_DELAY and is connected to the signal HSON_PRE. The output terminal of the level shifter circuit LSF2 is connected to the input terminal of the inverter INV6 and generates the signal HSON_L. The output terminal of the inverter INV6 is connected to the input terminal of the delay module DELAY1 and generates the signal HSONB_L. The output of delay module DELAY1 is connected to the input of inverter INV7 and serves as the first output of the delay chain circuit DEAD_DELAY, generating the signal HS_DEAD_B. The output of inverter INV7 is connected to the input of delay module DELAY2 and generates the signal HS_DEAD_BB. The output of delay module DELAY2 is connected to the input of inverter INV8 and generates the signal HS_DELAY. The output of inverter INV8 serves as the second output of the delay chain circuit DEAD_DELAY and generates the signal HS_DELAY_B.

5. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 4, characterized in that: The VDD1 terminal of the level conversion circuit LSF2, the VDD2 terminal of the level conversion circuit LSF2, the power supply terminal of the inverter INV6, the power supply terminal of the delay module DELAY1, the power supply terminal of the inverter INV7, the power supply terminal of the delay module DELAY2, and the power supply terminal of the inverter INV8 are connected to the power supply AVDD. The VSS1 terminal of the level conversion circuit LSF2, the VSS2 terminal of the level conversion circuit LSF2, the ground terminal of the inverter INV6, the ground terminal of the delay module DELAY1, the ground terminal of the inverter INV7, the ground terminal of the delay module DELAY2, and the ground terminal of the inverter INV8 are grounded.

6. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 1, characterized in that: The SW_PROTECT circuit for preventing SW failure includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input of inverter INV5 is connected to the signal HSG as the first input of the SW_PROTECT circuit. The output of inverter INV5 is connected to the gate of PMOS transistor PM1. The source of PMOS transistor PM1 is connected to the signal VH. The drain of PMOS transistor PM1 is connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the signal PVDD. The source of NMOS transistor NM3... The source of NMOS transistor NM4 is connected to the drain of NMOS transistor NM4 and serves as the output of the SW_PROTECT circuit to prevent SW failure, generating the signal SE_PRE. The source of NMOS transistor NM4 is grounded. The first input of AND gate AND1 serves as the second input of the SW_PROTECT circuit to prevent SW failure and is connected to the signal HS_DELAY_B. The second input of AND gate AND1 serves as the third input of the SW_PROTECT circuit to prevent SW failure and is connected to the input signal LSG_SEN. The output of AND gate AND1 is connected to the gate of NMOS transistor NM4 and generates the signal LSON_SEN2.

7. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 6, characterized in that: The power supply terminal of inverter INV5 is connected to signal VH, the ground terminal of inverter INV5 is connected to signal SW, the power supply terminal of AND gate AND1 is connected to power supply AVDD, and the ground terminal of AND gate AND1 is grounded.

8. The drive circuit with automatic dead-time switching based on a dual N-power transistor DC-DC architecture according to claim 1, characterized in that: The sampling logic circuit HSG_SEN_LOGIC includes resistors R3 and R4, PMOS transistors PM2, PM3, PM4, PM5, PM6, NMOS transistors NM5, NM6, and NM7. One end of resistor R3 is connected to the signal SW, and the other end of resistor R3 is connected to the gate of PMOS transistor PM2. The sources of PMOS transistors PM2, PM3, PM5, and PM6 are connected to the power supply PVDD. The gate of PMOS transistor PM3 is connected to its drain and the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to the gate of NMOS transistor NM5 and serves as the sampling logic circuit HSG_SEN_LOG. The second input terminal of the IC is connected to the signal SW_PRE. The drain of PMOS transistor PM2 is connected to one end of resistor R4, the gate of NMOS transistor NM7, and the gate of PMOS transistor PM5. The other end of resistor R4 is connected to the drain of NMOS transistor NM5. The drain of PMOS transistor PM5 is connected to the drain of PMOS transistor PM6 and the drain of NMOS transistor NM6, and serves as the output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate the signal HSG_SEN. The gate of PMOS transistor PM6 is connected to the gate of NMOS transistor NM6, and serves as the first input terminal of the sampling logic circuit HSG_SEN_LOGIC, connected to the signal HS_DEAD_B. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7. The sources of NMOS transistor NM5 and NMOS transistor NM7 are grounded.

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