Inverter carrier synchronization system

Abstract

This application provides an inverter carrier synchronization system, belonging to the field of inverter control technology. The system includes multiple inverter devices connected via cascaded communication. Each inverter device includes a CPLD unit, a drive unit connected to the CPLD unit, a fault output unit, and a fault identification unit. The CPLD unit generates or forwards a carrier synchronization signal. The first contact of the relay in the fault output unit outputs a fault status signal to the next-level inverter device. The first-level inverter device acts as the master, and the fault status signal output by any normal inverter device is low. When any inverter device loses power or malfunctions, its relay disconnects, causing the output fault status signal to be high. Upon detecting the high-level fault status signal, the next-level inverter device automatically switches to become the master of the downstream inverter device. This system effectively suppresses high-frequency circulating currents in the system, improving system operating efficiency and stability.

Description

Technical Field

[0001] This application relates to the field of inverter control technology, specifically to an inverter carrier synchronization system. Background Technology

[0002] In the field of new energy power generation and energy storage systems, building large-capacity energy storage systems by connecting multiple inverters in parallel has become the mainstream development direction in the industry. In such systems, the amplitude, frequency and phase of the output voltage of each inverter device must be strictly synchronized to minimize the circulating current loss between units. Excessive circulating current will lead to a decrease in system efficiency, increased device heating, and even trigger protection shutdown, directly affecting the stability and reliability of the energy storage system.

[0003] To address carrier synchronization issues, the industry commonly employs a "master-slave collaborative" architecture: one inverter is designated as the master to generate the reference carrier, while the others act as slaves to track the master's signal, supporting dynamic switching between master and slave roles to improve system redundancy. However, existing master-slave synchronization solutions suffer from significant technical bottlenecks: traditional carrier synchronization relies on communication links such as CAN and Ethernet to transmit synchronization commands. This communication process is susceptible to electromagnetic interference, leading to signal loss or distortion. Furthermore, communication latency (typically tens to hundreds of milliseconds) reduces synchronization response speed, making it difficult to meet the nanosecond-level synchronization accuracy requirements of high-frequency carriers (e.g., above 10kHz). Especially in master-slave switching scenarios, communication delays can cause brief synchronization interruptions, triggering circulating current surges and negatively impacting system stability.

[0004] Furthermore, existing solutions lack adequate fault tolerance mechanisms for synchronization anomalies: when an inverter fails to operate, the traditional master-slave switching logic requires communication negotiation to elect a new master, during which the carrier synchronization link is interrupted, further amplifying the risk of system fluctuations. Simultaneously, most designs do not consider hardware-level protection and isolation of the synchronization signal. In complex electromagnetic environments, the synchronization signal is susceptible to ground current interference, causing the slave to misjudge the master's status and exacerbating the carrier synchronization problem.

[0005] In summary, existing inverter systems face multiple technical challenges in carrier synchronization, including insufficient synchronization accuracy due to communication interference, circulating current impacts caused by switching delays, and weak hardware anti-interference capabilities. Therefore, developing an inverter carrier synchronization solution that does not rely on complex communication and possesses hardware-level rapid synchronization and seamless switching capabilities to improve the operational stability and reliability of large-capacity energy storage systems has become a critical technical issue that urgently needs to be addressed in this field. Summary of the Invention

[0006] The purpose of this invention is to provide an inverter carrier synchronization system to solve at least one of the above-mentioned technical problems.

[0007] A parallel carrier signal synchronization system for string inverters is used for parallel operation control of multiple inverters in a large-capacity energy storage system. It includes multiple inverter devices connected by cascaded communication. Each inverter device includes a CPLD unit, a drive unit connected to the first output pin of the CPLD unit, a fault output unit, and a fault identification unit.

[0008] The CPLD unit is used to generate or forward carrier synchronization signals and to control the drive unit to excite the fault output unit, so that the first contact of the relay in the fault output unit outputs a fault status signal to the next stage inverter device.

[0009] The fault identification unit is used to detect the fault status signal output by the previous inverter device in order to determine the master / slave identity of the current inverter device.

[0010] In a cascaded link, the first-stage inverter is the host, and the fault status signal output by any normal inverter is low level.

[0011] When any inverter device loses power or malfunctions, the relay in its fault output unit disconnects, causing the fault status signal output by the first contact to be at a high level. After the next-stage inverter device detects the high-level fault status signal, the next-stage inverter device automatically switches to become the host of the downstream inverter device.

[0012] Optionally, the fault output unit includes a reverse protection diode connected in parallel with the relay. The anode of the reverse protection diode is connected to the output terminal of the drive unit and the first terminal of the relay coil side, and the cathode is connected to the DC power supply and the second terminal of the relay coil side. The first contact of the relay contacts outputs a fault status signal, and the second contact is grounded.

[0013] The drive signal output by the CPLD unit is amplified by the drive unit and drives the coil of the fault output unit to be energized, so that the first contact outputs a low-level fault status signal.

[0014] Optionally, the fault identification unit includes an optocoupler transistor. The cathode of the optocoupler transistor receives the fault status signal output by the previous stage inverter device, the anode is connected to the first power supply, the transmitter is grounded, and the collector is connected to the second power supply and the input terminal of the CPLD unit respectively through a pull-up resistor.

[0015] The optocoupler transistor receives the fault status signal and performs electrical isolation, then transmits the isolated signal to the CPLD unit of the current inverter device.

[0016] When the fault identification unit of the primary inverter device has no upper-level fault status signal input, it transmits a high-level fault status signal to the CPLD unit through the optocoupler transistor.

[0017] Optionally, each inverter unit also includes a DSP unit connected to the CPLD unit, and a phase latch unit connected in series in the hardware-level synchronization signal path;

[0018] The phase latch unit is used to track the upstream carrier signal in real time and write the phase and frequency information of the carrier signal into the phase cache register integrated inside the DSP unit.

[0019] When an inverter device changes from a slave to a master, it generates a carrier signal based on the phase and frequency information written in the phase buffer register and transmits it to the downstream inverter.

[0020] Optionally, the inverter carrier synchronization system further includes:

[0021] When multiple hosts exist, at the end of each carrier cycle, each host exchanges the current carrier phase information through the CAN communication bus.

[0022] Globally unified carrier synchronization phase information is determined based on the current carrier phase information of each host.

[0023] Before determining the globally unified carrier synchronization phase information, the process of generating a carrier signal based on the phase information written in the phase buffer register and transmitting it to the downstream inverter is performed.

[0024] After determining the globally unified carrier synchronization phase information, each host generates a carrier signal according to the globally unified carrier synchronization phase information and transmits it to the downstream inverter.

[0025] Optionally, determining globally unified carrier synchronization phase information based on the current carrier phase information of each host includes:

[0026] The global phase difference matrix is ​​calculated based on the current carrier phase information of each host.

[0027] Based on the global phase difference matrix, carrier signal phase adjustment is performed to determine globally unified carrier synchronization phase information.

[0028] Optionally, each inverter device further includes a current sampling unit connected to the second output pin of the CPLD unit, used to acquire the voltage signal output by the second output pin of the CPLD unit through a built-in sampling resistor, and after amplifying the voltage signal through a built-in operational amplifier, it is filtered by a built-in filter capacitor and converted into a corresponding current detection signal.

[0029] The current detection signal is used to determine whether the corresponding inverter device is faulty.

[0030] Optionally, determining whether a fault exists in the corresponding inverter device based on the current detection signal includes:

[0031] Identify whether the current detection signal is below a preset fault threshold;

[0032] When the preset fault threshold is exceeded and the fault status signal output by the inverter is high, it is determined that the inverter has a fault.

[0033] Optionally, determining whether a fault exists in the corresponding inverter device based on the current detection signal further includes:

[0034] If the preset fault threshold is not exceeded, but the fault status signal output by the inverter is at a high level, it is determined that there is no fault in the inverter, and the fault status signal output by the inverter is changed to a low level.

[0035] Optionally, each inverter unit also includes an adjustable isolated power supply module;

[0036] The CPLD unit integrates an interference voltage detection unit, which generates a matching adjustment control signal by acquiring the fluctuation amplitude of the CAN bus differential signal.

[0037] The adjustable isolation power supply module provides a matching output isolation voltage based on the adjustment control signal, which is used to provide isolated power supply for the CPLD unit, fault identification unit and current sampling unit.

[0038] The inverter carrier synchronization system in this application has the following advantages:

[0039] 1. High-reliability parallel control. This application avoids address conflicts and data arbitration delays in traditional bus communication by using "cascaded communication + high-speed CPLD control". The fast response capability of the CPLD unit can ensure the real-time generation / forwarding of carrier synchronization signals, reduce circulating current when multiple units are connected in parallel, and improve the output power quality of the energy storage system.

[0040] 2. Fault redundancy and automatic switching can be achieved: This application relies on hardware-based fault transmission of "relay on / off + level detection", which can realize rapid identification of fault status and automatic switching of host without the need for complex software judgment; even if multiple upstream devices fail in succession, the carrier synchronization signal can still be guaranteed to be uninterrupted through "automatic replacement of the next level", which greatly improves the operational redundancy of large-capacity energy storage system and avoids the overall system shutdown due to the failure of a single device.

[0041] 3. Flexible adaptation to large-capacity scenarios: This application adopts a cascaded communication method, which can support the expansion of multiple inverter devices. Without making significant modifications to the existing hardware structure, the total power of the energy storage system can be increased by increasing the number of inverter devices, adapting to energy storage scenarios with different capacity requirements and having good scalability. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0043] Figure 1 This is a schematic diagram of the inverter carrier synchronization system in one embodiment;

[0044] Figure 2 This is a schematic diagram of the circuit structure of a single inverter device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] All terms used in this application (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0047] For example, the terms "first" and "second" used in this application are only used to distinguish similar objects and differentiate the first object from another object, rather than to describe a specific order or sequence, nor should they be interpreted as indicating or implying relative importance.

[0048] This application proposes an inverter carrier synchronization system for the parallel operation control of multiple inverters in a large-capacity energy storage system. Combined with... Figure 1 As shown, the inverter carrier synchronization system includes multiple inverter (Power Conversion System, or energy storage converter) devices connected by cascaded communication. Figure 1 An example is given of the cascaded communication connection of N inverter devices, which are labeled as PCS1, PCS2...PCSN according to the cascade order.

[0049] Each inverter unit includes a CPLD unit 120, a drive unit 130 connected to a first output pin of the CPLD unit 120, a fault output unit 140, and a fault identification unit 150.

[0050] Specifically, the CPLD unit 120 is used to generate or forward a carrier synchronization signal and to control the drive unit 130 to excite the fault output unit 140, causing the first contact of the relay in the fault output unit 140 to output a fault status signal to the next-level inverter device; the fault identification unit 150 is used to detect the fault status signal output by the previous inverter device to determine the master / slave identity of the current inverter device; in the cascaded link, the first-level inverter device is the master, and the fault status signal output by any normal inverter device is low level; when any inverter device loses power or malfunctions, the relay in its fault output unit 140 is disconnected, causing the fault status signal output by the first contact to be high level. After the next-level inverter device detects the high-level fault status signal, the next-level inverter device automatically switches to become the master of the downstream inverter device.

[0051] Large-capacity energy storage systems are energy storage systems capable of storing and releasing large amounts of electrical energy (e.g., megawatt-hours), meeting the needs of grid peak shaving and renewable energy consumption. Inverter carrier synchronization systems are control systems used to coordinate carrier signals when multiple inverters operate in parallel; they are the core control subsystem of large-capacity energy storage systems. The carrier synchronization system includes multiple inverter devices whose AC outputs are directly connected to the same AC bus to form a parallel connection. Through synchronization control, the voltage amplitude, frequency, and phase of each inverter's output are made completely consistent, achieving superposition of electrical output power. The core purpose is to improve the system's total output capacity and meet the demand for large-capacity electricity. Inverter devices are power electronic devices that convert the DC power output from the energy storage unit into AC power that meets the grid / load requirements, and also possess the signal processing and fault response capabilities required for parallel control.

[0052] Inverter cascading refers to multiple inverters connected in a chain structure where the upstream inverter's signal output (synchronization signal, fault status signal) is directly connected to the downstream inverter's signal input, forming a control architecture where "the upper level controls the lower level and faults are transmitted from one inverter to another." The core purpose is to achieve the cascading forwarding of synchronization signals and redundancy compensation after a fault.

[0053] The CPLD (Complex Programmable Logic Device) unit is the core control module of each inverter unit, possessing high-speed logic operation, signal generation, and forwarding capabilities. Its core functions in the system include two aspects: first, carrier synchronization signal processing, capable of autonomously generating carrier synchronization signals conforming to preset frequencies (e.g., 50Hz / 60Hz) and phases (master mode), or receiving synchronization signals from upper-level devices and forwarding them to lower-level devices (slave mode); second, fault linkage control, parsing the detection signals from the fault identification unit 150 through a preset logic program, driving the fault output unit 140 to achieve rapid fault status transmission and identity switching control, with a response time reaching the microsecond level, meeting the system's real-time requirements for fault handling. The carrier synchronization signal is a reference signal used to coordinate the operating sequence of multiple devices. In this system, it is a square wave signal with a fixed period and fixed duty cycle, its frequency consistent with the carrier frequency of the inverter's PWM module (e.g., 10kHz), used to ensure the synchronization of power conversion waveforms of all inverters. For example, an inverter can generate a square wave signal with a period of 100μs and a duty cycle of 50% as a carrier synchronization signal, and its rising edge can be used as the counting start point of the PWM module.

[0054] The drive unit 130 is an intermediate execution module that connects the CPLD unit 120 and the fault output unit 140. Its core function is to convert the low-level control signal (such as 3.3V / 5V logic signal) output by the CPLD unit 120 into a high-power signal that can drive the relay in the fault output unit 140 to operate.

[0055] The fault output unit 140 is a hardware module for the inverter to transmit its own fault status externally, with a relay as its core component. This unit outputs a fault status signal to the next-level inverter device through the relay's first contact (normally closed contact): When the inverter device is operating normally, the CPLD unit 120 controls the relay to engage via the drive unit 130, keeping the first contact closed and outputting a low-level fault status signal; when the device loses power or malfunctions, the relay de-energizes and opens, and the first contact switches to a high-level output, achieving rapid hardware-level transmission of the fault status. The first contact is a contact on the relay used for specific signal output and serves as the external output interface / pin for the fault status signal. The first contact acts as the connection point between the fault output unit 140 and the next-level fault identification unit 150, and its output fault status signal level is the "signal transmission node" in the cascaded link.

[0056] The fault identification unit 150 is a signal acquisition module for the inverter device to detect the status of the upstream device. Its input terminal is connected to the first contact of the fault output unit 140 of the upstream inverter device. Its working principle is as follows: it acquires the fault status signal voltage output by the upstream device in real time, compares it with the preset high and low level thresholds, converts the comparison result into a logic signal and transmits it to the CPLD unit 120. The CPLD unit 120 determines the master / slave identity of the current device based on the signal.

[0057] The first-stage inverter is the upstream inverter in the cascaded communication link. When the fault identification unit 150 of the first-stage inverter has no upstream input signal (or defaults to a low level), the CPLD unit 120 automatically identifies it as the master inverter and prioritizes entering the carrier synchronization signal generation mode. The generated synchronization signal is transmitted to its own inverter power module through internal circuitry and simultaneously forwarded to all downstream slave devices through the cascaded link, serving as the carrier reference for the entire parallel system. The fault status signal is an electrical signal used to characterize the inverter's operating status, divided into low-level signals (e.g., 0-0.8V) and high-level signals (e.g., 2.4-5V): a low-level signal corresponds to normal operation, indicating that the device has the capability to generate or forward carrier synchronization signals; a high-level signal corresponds to power failure or a fault state (e.g., power module damage, overvoltage / overcurrent protection triggering, CPLD unit 120 failure, etc.), indicating that the device can no longer participate in carrier synchronization control. This signal is transmitted through the first contact of the relay in the fault output unit 140 and serves as the basis for each device in the cascaded link to determine its own identity and switch to the master inverter.

[0058] Specifically, when the fault identification unit 150 of the first-stage inverter has no input signal from the upper-stage device, the CPLD unit 120 determines itself as the master unit based on preset logic and immediately enters the carrier synchronization signal generation mode. The internal logic circuit of the CPLD unit 120 generates a standard carrier synchronization signal (such as a sine wave synchronization signal or an SPWM carrier reference signal) based on preset system parameters (such as a grid frequency of 50Hz and a carrier ratio of 32). At the same time, the CPLD unit 120 of the first-stage inverter outputs a drive signal through the drive unit 130 to control the relay in the fault output unit 140 to engage, causing the first contact to output a low-level fault status signal. This signal is transmitted to the fault identification unit 150 of the next-stage (second) inverter.

[0059] After the fault identification unit 150 of all downstream non-primary inverter devices detects the low-level fault status signal output by the upstream device, the CPLD unit 120 determines itself as a slave device and enters the carrier synchronization signal forwarding mode: the CPLD unit 120 of the slave device receives the carrier synchronization signal transmitted by the upstream device, forwards it to the next level device after logic verification, and at the same time transmits the synchronization signal to its own inverter power module to ensure that it is consistent with the carrier signal output by the master device.

[0060] During stable system operation, the primary host device continuously generates a carrier synchronization signal, which is sent to all slave devices one by one through the cascaded link. All inverter devices control their own power modules to output AC power based on the synchronization signal, realizing the synchronization of power output of multiple machines in parallel and avoiding the generation of parallel circulating current.

[0061] Each normally operating inverter unit (including master and slave units) maintains the relay in the fault output unit 140 in an engaged state via the drive unit 130, ensuring that all fault status signals output by each unit to the next level are low. The fault identification unit 150 monitors the upstream signals in real time to confirm that the system is fault-free. Simultaneously, the fault identification unit 150 of each inverter unit collects the fault status signals transmitted from the upstream inverter unit at a preset cycle and feeds the collection results back to the CPLD unit 120. The CPLD unit 120 performs continuity verification on the signals to ensure real-time monitoring of the upstream fault status and avoid misjudgments caused by momentary interference.

[0062] When an inverter device (taking the Mth inverter device in a cascaded N inverter devices as an example) fails to operate normally due to power failure, power module failure, or protection triggering, the CPLD unit 120 of the device loses its control capability (or actively outputs a fault status signal), the drive unit 130 stops supplying power to the relay of the fault output unit 140, and the relay loses power and disconnects.

[0063] After the relay is disconnected, its first contact switches from the closed state to the open state, and the output fault status signal switches from low level to high level. This high-level signal is transmitted to the fault identification unit 150 of the next stage inverter device (the M+1th inverter device).

[0064] After the fault identification unit 150 of the M+1 inverter device collects the high-level fault status signal, it immediately converts the signal into a logic signal and transmits it to its own CPLD unit 120. After detecting the high-level signal, the CPLD unit 120 determines that the upstream M-th inverter device has a fault, triggers the host switching logic, and makes itself the host.

[0065] The CPLD unit 120 of the (M+1)th inverter device stops the carrier synchronization signal forwarding mode and switches to host mode: it autonomously generates a carrier synchronization signal that meets the system requirements, and transmits it to its own inverter power module to control its own output to maintain seamless connection with the original host signal; on the other hand, it forwards the new carrier synchronization signal to the downstream (M+2), (M+3)th...Nth inverter devices through the cascade link, becoming the new host for all downstream inverter devices.

[0066] After the fault identification unit 150 of all downstream inverter devices (M+2 and beyond) detects the low-level fault status signal output by the M+1 inverter device, it maintains its slave status, receives and forwards the carrier synchronization signal generated by the M+1 inverter device, and ensures that the inverter devices in the entire cascaded link can still maintain carrier synchronization. The parallel output power of the system is not affected by the faulty device (only the single-unit power of the faulty device is reduced).

[0067] At this point, there are two main inverters in the entire inverter carrier synchronization system: the first-level inverter unit (i.e., the first inverter unit) and the (M+1)th inverter unit. The first-level inverter unit provides carrier synchronization signals for the second to the Mth inverter units; while the (M+1)th inverter unit provides carrier synchronization signals for the (M+2)th to the Nth inverter units.

[0068] Furthermore, if the Mth inverter unit fails and the M+1th inverter unit switches to the host mode, and then the M+1th inverter unit also fails to operate due to a fault, the relay of its fault output unit 140 will disconnect, outputting a high-level fault status signal to the next level (the M+2th inverter unit). After the fault identification unit 150 of the M+2th inverter unit detects the high-level signal, it repeats the above host switching steps: the CPLD unit switches to host mode, generates a new carrier synchronization signal and forwards it downstream, becoming the new downstream host, and so on.

[0069] Regardless of how many consecutive faulty devices occur upstream in the cascaded link, as long as there is a normally operating inverter device downstream, the first normal device closest to the fault area (i.e., the device directly below the faulty device) will automatically switch to the host by detecting the high-level fault status signal. This ensures that the carrier synchronization signal of the entire system always has a reliable source of generation, realizes redundant operation of the system under fault conditions, and guarantees the continuous power supply capability of the large-capacity energy storage system.

[0070] The inverter carrier synchronization system in this application avoids address conflicts and data arbitration delays in traditional bus communication through "cascaded communication + CPLD high-speed control." The rapid response capability of the CPLD unit ensures the real-time generation / forwarding of carrier synchronization signals, reduces circulating current in multi-unit parallel operation, and improves the output power quality of the energy storage system (e.g., reducing voltage distortion rate). Furthermore, by relying on hardware-based fault transmission through "relay on / off + level detection," rapid fault identification and automatic master switching can be achieved without complex software judgments. Even if multiple upstream devices fail consecutively (e.g., master → slave 1 fails sequentially), the carrier synchronization signal can still be ensured uninterrupted through "automatic replacement at the next level" (slave 2 switches to master), significantly improving the operational redundancy of large-capacity energy storage systems and preventing system shutdown due to a single device failure. In addition, the cascaded communication method used in this system supports the expansion of N inverter devices without significant modifications to the existing hardware structure. The total power of the energy storage system can be increased by adding PCS, adapting to energy storage scenarios with different capacity requirements and possessing excellent scalability.

[0071] In one embodiment, the fault output unit 140 includes a reverse protection diode connected in parallel with the relay. The anode of the reverse protection diode is connected to the output terminal of the drive unit 130 and the first terminal of the relay coil side, and the cathode is connected to the DC power supply and the second terminal of the relay coil side. The first contact of the relay outputs a fault status signal, and the second contact is grounded. The drive signal output by the CPLD unit 120 is amplified by the drive unit 130 and drives the coil of the fault output unit 140 to be energized, so that the first contact outputs a low-level fault status signal.

[0072] In this embodiment, as Figure 2 As shown, the reverse protection diode D1 is connected in parallel across the coil of relay K1 to suppress the reverse electromotive force generated when the coil is de-energized. The first terminal of the coil side of relay K1 is connected to the anode of the reverse protection diode D1 and the output terminal of the drive unit 130 to receive the drive signal amplified by the drive unit 130. The second terminal of the coil side of relay K1 is connected to the cathode of the reverse protection diode D1 and the DC power supply, forming a complete energizing circuit with the first terminal of the coil side. When the drive unit 130 outputs a valid signal, a potential difference matching the rated voltage of the coil is formed between the first and second terminals, energizing the coil and generating a magnetic field, which drives the contacts to operate. The DC power supply provides an isolated power supply with the rated operating voltage for the relay coil in the fault output unit 140, such as 24V DC voltage or other higher suitable operating voltages.

[0073] The first contact on the contact side of relay K1 is a contact that can be turned on or off, and the first contact can output a fault status signal. After the first contact is turned on, its potential is pulled low by the grounded second contact to output a low-level (e.g., 0-0.8V) fault status signal. This signal is transmitted through the cascade link to the fault identification unit 150 of the next-level PCS (e.g., slave 1), indicating that "the current PCS is normal and there is no need to switch the master".

[0074] In this embodiment, by connecting the reverse protection diode in parallel with the relay coil, the reverse electromotive force when the coil is de-energized can be effectively discharged, preventing the power components in the drive unit 130 from being damaged. This solves the hardware damage problem caused by the reverse voltage of the inductive load in the traditional fault output unit 140, and improves the long-term reliability of the system. By directly grounding the second contact on the relay contact side and outputting a fault status signal from the first contact, the accuracy of the low-level signal output can be guaranteed, reducing the risk of misjudgment by the fault identification unit 150.

[0075] In one embodiment, such as Figure 2 As shown, the fault identification unit 150 includes an optocoupler transistor. The cathode of the optocoupler transistor receives the fault status signal output by the previous stage inverter device, the anode is connected to the first power supply, the emitter is grounded, and the collector is connected to the second power supply and the input terminal of the CPLD unit 120 respectively through a pull-up resistor. The optocoupler transistor receives the fault status signal and performs electrical isolation, transmitting the isolated signal to the CPLD unit 120 of the current inverter device. The fault identification unit 150 of the first stage inverter device has no fault status signal input from the previous stage, and transmits a high-level fault status signal to the CPLD unit 120 through the optocoupler transistor.

[0076] In this embodiment, the cathode of the optocoupler U1 receives the fault status signal output from the previous stage inverter device and is also connected to the first power supply through a resistor R1; the anode is connected to the first power supply through a second resistor. The collector is connected to the second power supply through a resistor R3 and to the input terminal of the CPLD unit 120 through a resistor R4. After receiving the external input signal (the fault status signal output from the previous stage inverter device), the optocoupler U1 processes the signal using the photoelectric conversion principle to achieve electrical isolation between the output signal and the input signal, eliminating interference from the input circuit to the output circuit, and then transmits the isolated signal to the CPLD unit 120 of the current inverter device.

[0077] Specifically, when the cathode of optocoupler U1 receives a high-level fault status signal from the previous stage, the LED in optocoupler U1 conducts and emits light due to the voltage difference. The phototransistor on the output side conducts upon receiving light, and the collector is grounded through the emitter, outputting a low-level isolation signal to CPLD unit 120. If the received input signal is low-level, the LED does not emit light, the phototransistor is cut off, and the collector is connected to the second power supply through a pull-up resistor, outputting a high-level isolation signal to CPLD unit 120. During this process, there is no direct electrical connection between the input and output sides of optocoupler U1, achieving electrical isolation and preventing interference from the upper-level circuit to the circuit containing CPLD unit 120.

[0078] Since the primary inverter unit has no upstream inverter unit in the cascaded link, its fault identification unit 150 has no upstream fault status signal input. In this case, it transmits a high-level fault status signal to the CPLD unit 120 through its own circuit characteristics. After receiving the high-level signal, the CPLD unit 120 determines itself to be the master unit.

[0079] In this embodiment, the fault identification unit 150 uses an optocoupler transistor U1 to electrically isolate the fault status signal from the previous stage using the principle of opto-isolation. This isolation prevents noise, interference, and potential differences from the previous stage circuit from being transmitted to the circuit where the CPLD unit 120 of the current inverter device is located. This not only ensures the accuracy and stability of the signal transmitted to the CPLD unit 120 and reduces misjudgments caused by interference, thus improving the anti-interference capability of the entire system, but also prevents these harmful signals from damaging sensitive low-voltage electronic components such as the CPLD unit 120, extending the service life of the components and improving the reliability of the system.

[0080] Furthermore, since the fault identification unit 150 of the primary inverter device transmits a high-level signal to the CPLD unit 120 through the optocoupler U1 when there is no upper-level fault status signal input, this design provides a clear basis for the primary inverter device to quickly and accurately determine its identity as the host during system initialization, ensuring that the system can quickly establish a carrier synchronization control system and improving the system startup efficiency.

[0081] In one embodiment, each inverter device further includes an adjustable isolation power supply module; the CPLD unit 120 integrates an interference voltage detection unit, which generates a matching adjustment control signal by acquiring the fluctuation amplitude of the CAN bus differential signal; the adjustable isolation power supply module provides a matching output isolation voltage based on the adjustment control signal, for providing isolated power supply to the CPLD unit 120, the fault identification unit 150 and the current sampling unit.

[0082] In this embodiment, the adjustable isolated power supply module is a power supply module with output voltage regulation function and input-output electrical isolation, which can dynamically adjust the output voltage according to the control signal. For example, it can output a first voltage as the first power supply and output a second voltage as the second power supply. Each inverter device adds an adjustable isolated power supply module. The input terminal of this module is connected to the device's main power supply (such as a DC bus or auxiliary power supply), and the output terminal is connected to the CPLD unit 120, the fault identification unit 150, and the current sampling unit, respectively. Electrical isolation is used to achieve potential isolation between the above units and the main circuit, while also having voltage regulation function to adapt to different interference environments.

[0083] The built-in interference detection module of the control unit monitors the signal stability of the communication bus in real time. By analyzing the degree of signal fluctuation, it generates corresponding power adjustment commands, providing a quantitative basis for the interference intensity of the power supply system. Specifically, the interference voltage detection unit integrated in the CPLD unit 120 is connected to the CAN_H and CAN_L signal lines of the CAN bus via a dedicated pin to collect the voltage changes of the differential signal in real time. The module compares the actual fluctuation amplitude with a preset threshold (such as ±2V) and generates an adjustment control signal proportional to the fluctuation amplitude (such as a 0-3.3V analog voltage or a 0-100% duty cycle PWM signal). After receiving the adjustment control signal output by the CPLD unit 120, the adjustable isolated power supply module changes the output voltage through an internal voltage adjustment circuit (such as a PWM feedback loop). For the different power supply requirements of the CPLD unit 120, the fault identification unit 150, and the current sampling unit, it outputs corresponding isolation voltages (such as 3.3V-7V, 5V-9V, ±15V-±18V) to enhance the anti-interference capability of each unit.

[0084] In this embodiment, the interference voltage detection unit of the CPLD monitors the interference intensity of the CAN bus in real time and links with the adjustable isolation power supply module to adjust the power supply voltage, thus solving the problem of insufficient power supply stability of traditional fixed voltage isolation power supplies under strong interference environment.

[0085] In one embodiment, each inverter device further includes a DSP unit 110 connected to the CPLD unit 120, and a phase latch unit connected in series in the hardware-level synchronization signal path; the phase latch unit is used to track the upstream carrier signal in real time and write the phase and frequency information of the carrier signal into the phase cache register integrated inside the DSP unit 110; when an inverter device changes from a slave to a master, it generates a carrier signal based on the phase and frequency information written in the phase cache register and transmits it to the downstream inverter.

[0086] In this embodiment, as Figure 1 and Figure 2As shown, the DSP (Digital Signal Processor) unit, as the "computational core" of the inverter, is responsible for processing phase and frequency data and executing synchronization algorithms, complementing the hardware control of the CPLD unit 120. The DSP unit 110 is responsible for the core control of power conversion. It receives the carrier synchronization signal sent by the CPLD unit 120, uses it as the synchronization source for its own PWM module, and generates pulse signals to drive the inverter power devices.

[0087] The phase latch unit is integrated into the hardware-level synchronization signal path to continuously monitor and capture the transient characteristics (such as phase and frequency information) of the carrier synchronization signal transmitted from upstream. The phase latch unit includes a phase-locked loop (PLL). The phase buffer register is a high-speed storage unit integrated inside the DSP unit 110, used to temporarily store the real-time phase and frequency data transmitted from the phase latch unit. Specifically, the DSP unit 110 communicates bidirectionally with the CPLD unit 120 via the SPI interface, receiving status commands from the CPLD unit 120 and feeding back the calculation results. The phase latch unit (e.g., based on CD4046 and a high-speed trigger) is connected in series in the LVDS hardware synchronization signal path, with its input connected to the carrier signal output of the upstream inverter and its output connected to the DSP unit 110 and the CPLD unit 120, forming a complete link of "upstream signal → phase latch → data processing → control execution". It monitors the carrier synchronization signal transmitted by the upstream inverter in real time through hardware circuitry, continuously captures and calculates the phase (angular position) and frequency (periodic change) information of the signal; at the same time, it writes this real-time data into the phase buffer register of the DSP unit 110 through an internal interface to ensure that the DSP can obtain the latest synchronization reference data at any time.

[0088] The specific workflow of the phase latch unit is as follows: the zero-crossing point of the upstream carrier signal is detected by a high-speed comparator, triggering the phase-locked loop to lock the signal frequency; the current phase is calculated in real time by a counter; the phase and frequency information are written into the phase buffer register of the DSP unit 110 through a parallel data bus; the DSP unit 110 can read the register data through an interrupt to obtain the latest synchronization information.

[0089] When a certain inverter device determines through the fault identification unit 150 that it needs to switch from slave to master, the CPLD unit 120 sends a switching command to the DSP unit 110; the DSP unit 110 reads the latest phase and frequency information stored in the phase buffer register, and generates a new carrier signal that is seamlessly connected with the original upstream carrier signal through the built-in algorithm; after the new signal is processed by the CPLD unit 120, it is transmitted to all downstream inverter devices through the hardware-level synchronization signal path.

[0090] In this embodiment, the phase latch unit tracks the carrier signal in real time and stores the data in the high-speed phase buffer register of the DSP, solving the phase deviation problem caused by signal delay or distortion in the traditional synchronization method. When the slave device switches to the master device, the collaborative architecture of the DSP unit 110 and the CPLD unit 120 can quickly complete the master device identity switch and rapidly generate a new carrier signal, so that the downstream inverter device does not need to stop and wait, and can directly receive the carrier signal of the new master device, realizing "seamless switching". This avoids the power interruption problem caused by switching delay in the traditional system, and also avoids the circulating current impact at the moment of switching, greatly improving the synchronization stability of the multi-machine parallel system.

[0091] In one embodiment, the inverter carrier synchronization system further includes: when multiple hosts exist, at the end of each carrier cycle, each host exchanges current carrier phase information via a CAN communication bus; determining globally unified carrier synchronization phase information based on the current carrier phase information of each host; before determining the globally unified carrier synchronization phase information, performing the step of generating a carrier signal based on the phase information written in the phase buffer register and transmitting it to the downstream inverter; after determining the globally unified carrier synchronization phase information, each host generates a carrier signal according to the globally unified carrier synchronization phase information and transmits it to the downstream inverter.

[0092] In this embodiment, when there are multiple hosts in the inverter carrier synchronization system, each host sends its own carrier phase information (such as the endpoint phase value) to other hosts via the CAN communication bus when its generated carrier signal completes one cycle. Simultaneously, it receives phase information from other hosts, forming a multi-host data interaction closed loop. After receiving the carrier phase information from other hosts, each host analyzes and processes all valid phase data (including its own data) using built-in algorithms (such as removing deviation exceeding limits and calculating the average phase) to jointly determine globally unified carrier synchronization phase information. For example, this phase information must satisfy the condition that the phase deviation of all hosts is less than a preset deviation threshold to ensure subsequent signal consistency. For example, carrier signal synchronization between multiple hosts can be achieved through distributed clock synchronization protocols, master-slave switching mechanisms, dynamic switching mechanisms, phase adjustment, and circulating current suppression algorithms.

[0093] Before the globally unified carrier synchronization phase information is determined, each host continues to generate carrier signals based on the phase buffer register data in the above embodiment to ensure that the signal supply of downstream slaves is not interrupted; after the global phase is determined, all hosts immediately switch to generating carrier signals based on the global phase to achieve complete synchronization of multi-host outputs.

[0094] By employing a phased generation logic (using phase buffering before determination and global phase after determination), this approach ensures that downstream slave devices always receive a valid carrier signal during the transition period, avoiding signal interruptions caused by the negotiation process. Compared to the traditional "stop-then-start" switching method, this application can significantly reduce downstream current fluctuations and significantly improve system stability.

[0095] In one embodiment, determining globally unified carrier synchronization phase information based on the current carrier phase information of each host includes: calculating a global phase difference matrix based on the current carrier phase information of each host; and adjusting the carrier signal phase based on the global phase difference matrix to determine globally unified carrier synchronization phase information.

[0096] In this embodiment, each host receives the current carrier cycle end phase information (including a consistent timestamp) from other hosts via the CAN bus, calculates the phase difference between each pair using itself as the row reference and other hosts as the column reference, arranges all phase differences in order of host ID, and constructs a global phase difference matrix, and removes and corrects outliers in the matrix to ensure that the matrix reflects the true global phase distribution.

[0097] Each host analyzes the global phase difference matrix and selects a reference host based on the "minimum deviation principle" (the carrier signal of the reference host does not need to be adjusted); the host to be adjusted calculates the phase difference with the reference host and corrects its own carrier phase increment by a preset step size (e.g., 0.05° / cycle); after each adjustment cycle, the phase data is exchanged again and the phase difference matrix is ​​updated until the absolute value of all off-diagonal elements in the latest phase difference matrix is ​​less than or equal to the convergence threshold. At this point, the phase of the reference host is the globally unified carrier synchronization phase information.

[0098] By constructing a global phase difference matrix, the abstract phase relationship between multiple inverters is transformed into an intuitive numerical matrix, which avoids the one-sidedness of traditional "point-to-point comparison". By determining the reference inverter and adjustment priority based on the matrix, phase oscillation caused by "disorderly adjustment" of multiple inverters is avoided. At the same time, by setting the adjustment step size to achieve "successive approximation", the impact circulating current caused by phase jump in downstream inverters can be effectively avoided.

[0099] In one embodiment, each inverter device further includes a current sampling unit connected to the second output pin of the CPLD unit 120, which is used to acquire the voltage signal output by the second output pin of the CPLD unit 120 through a built-in sampling resistor, and amplify the voltage signal through a built-in operational amplifier, and then filter it through a built-in filter capacitor to convert it into a corresponding current detection signal; and determine whether the corresponding inverter device has a fault based on the current detection signal.

[0100] In this embodiment, the current sampling unit of each inverter device is connected to the second output pin of the CPLD unit 120, and internally a sampling resistor, an operational amplifier and a filter capacitor are connected in series. The sampling resistor converts the voltage signal output from the second output pin into a weak voltage corresponding to the current. After being amplified by the operational amplifier, the noise is filtered out by the filter capacitor, and finally a current detection signal that can be used for fault diagnosis is generated.

[0101] The CPLD unit 120 receives the current detection signal in real time and compares it with preset fault thresholds (such as overcurrent threshold and short circuit threshold) and time conditions. When the signal exceeds the overcurrent threshold and the duration exceeds the preset duration (such as 10ms), or the signal exceeds the short circuit threshold and the duration exceeds the preset duration (such as 1ms), it is determined that there is a fault in the inverter device and triggers the corresponding protection action (such as cutting off the output).

[0102] In one embodiment, determining whether the corresponding inverter device is faulty based on the current detection signal includes: identifying whether the current detection signal is lower than a preset fault threshold; when the preset fault threshold is exceeded and the fault status signal output by the inverter device is high, determining that the inverter device is faulty; when the preset fault threshold is not exceeded, but the fault status signal output by the inverter device is high, determining that the inverter device is not faulty, and changing the fault status signal output by the inverter device to low.

[0103] In this embodiment, whether the inverter device is faulty can be determined by combining the fault status signal and the current detection signal. When both indicate that there is a fault, the inverter device is determined to be faulty. When only one indicates that there is a fault, while the other indicates that it is normal, the inverter device is still determined to be normal.

[0104] For example, CPLD unit 120 monitors the current detection signal in real time and confirms that it remains below all fault thresholds for 10ms. Simultaneously, it detects a continuous 3.3V high-level output from the FAULT pin. CPLD unit 120 determines through internal logic that while the current is normal, the fault status information is abnormal, constituting a "false fault indication," and triggers the signal correction mechanism. The signal correction process is as follows: CPLD unit 120's "false fault correction module" outputs a control signal (high level), driving the NPN transistor to conduct. The transistor's collector is connected to the FAULT pin, and its emitter is grounded. After conduction, the FAULT pin level is pulled from 3.3V to 0V (low level). Simultaneously, CPLD unit 120 records the correction event (time, original signal state) and reports the "false fault correction" log to the host computer via the CAN bus. It continuously monitors the current signal; if subsequent current anomalies occur, it can re-output a high-level fault status information, ensuring that the correction mechanism does not affect the detection of genuine faults.

[0105] This embodiment avoids misjudgment caused by a single current anomaly (such as a momentary spike) by using "dual condition judgment" (current exceeding the threshold + high level of fault status information). For any misjudgment of faults, a "false signal correction" mechanism is used to prevent erroneous fault status signals from being transmitted to the next-level inverter device, which would cause the next-level inverter device to mistakenly become the host and affect the system.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0107] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this application and form different embodiments. For example, all the embodiments above can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. An inverter carrier synchronization system for parallel operation control of multiple inverters in a large-capacity energy storage system, characterized in that, It includes multiple inverter devices connected via cascaded communication, each inverter device including a CPLD unit, a drive unit connected to the first output pin of the CPLD unit, a fault output unit, and a fault identification unit; The CPLD unit is used to generate or forward carrier synchronization signals and to control the drive unit to excite the fault output unit, so that the first contact of the relay in the fault output unit outputs a fault status signal to the next stage inverter device. The fault identification unit is used to detect the fault status signal output by the previous inverter device in order to determine the master / slave identity of the current inverter device. In a cascaded link, the first-stage inverter is the host, and the fault status signal output by any normal inverter is low level. When any inverter device loses power or malfunctions, the relay in its fault output unit disconnects, causing the fault status signal output by the first contact to be at a high level. After the next-stage inverter device detects the high-level fault status signal, the next-stage inverter device automatically switches to become the host of the downstream inverter device.

2. The inverter carrier synchronization system according to claim 1, characterized in that, The fault output unit includes a reverse protection diode connected in parallel with the relay. The anode of the reverse protection diode is connected to the output terminal of the drive unit and the first terminal of the relay coil side, and the cathode is connected to the DC power supply and the second terminal of the relay coil side. The first contact of the relay contacts outputs a fault status signal, and the second contact is grounded. The drive signal output by the CPLD unit is amplified by the drive unit and drives the coil of the fault output unit to be energized, so that the first contact outputs a low-level fault status signal.

3. The inverter carrier synchronization system according to claim 1, characterized in that, The fault identification unit includes an optocoupler transistor, which includes a light-emitting diode (LED) and a phototransistor. The cathode of the LED receives the fault status signal output by the upstream inverter device, the anode of the LED is connected to the first power supply, the emitter of the phototransistor is grounded, and the collector of the phototransistor is connected to the second power supply and the input terminal of the CPLD unit respectively through a pull-up resistor. The optocoupler transistor receives the fault status signal and performs electrical isolation, then transmits the isolated signal to the CPLD unit of the current inverter device. When the fault identification unit of the primary inverter device has no upper-level fault status signal input, it transmits a high-level fault status signal to the CPLD unit through the optocoupler transistor.

4. The inverter carrier synchronization system according to claim 1, characterized in that, Each inverter unit also includes a DSP unit connected to the CPLD unit, and a phase latch unit connected in series in the hardware-level synchronization signal path; The phase latch unit is used to track the upstream carrier signal in real time and write the phase and frequency information of the carrier signal into the phase cache register integrated inside the DSP unit. When an inverter device changes from a slave to a master, it generates a carrier signal based on the phase and frequency information written in the phase buffer register and transmits it to the downstream inverter.

5. The inverter carrier synchronization system according to claim 4, characterized in that, The inverter carrier synchronization system also includes: When multiple hosts exist, at the end of each carrier cycle, each host exchanges the current carrier phase information through the CAN communication bus. Globally unified carrier synchronization phase information is determined based on the current carrier phase information of each host. Before determining the globally unified carrier synchronization phase information, the process of generating a carrier signal based on the phase and frequency information written in the phase buffer register and transmitting it to the downstream inverter is performed. After determining the globally unified carrier synchronization phase information, each host generates a carrier signal according to the globally unified carrier synchronization phase information and transmits it to the downstream inverter.

6. The inverter carrier synchronization system according to claim 5, characterized in that, The determination of globally unified carrier synchronization phase information based on the current carrier phase information of each host includes: The global phase difference matrix is ​​calculated based on the current carrier phase information of each host. Based on the global phase difference matrix, carrier signal phase adjustment is performed to determine globally unified carrier synchronization phase information.

7. The inverter carrier synchronization system according to claim 1, characterized in that, Each inverter unit also includes a current sampling unit connected to the second output pin of the CPLD unit, which is used to acquire the voltage signal output by the second output pin of the CPLD unit through the built-in sampling resistor, and after amplifying the voltage signal through the built-in operational amplifier, it is filtered by the built-in filter capacitor and converted into the corresponding current detection signal. The current detection signal is used to determine whether the corresponding inverter device is faulty.

8. The inverter carrier synchronization system according to claim 7, characterized in that, The step of determining whether the corresponding inverter device has a fault based on the current detection signal includes: Identify whether the current detection signal is below a preset fault threshold; When the preset fault threshold is exceeded and the fault status signal output by the inverter is at a high level, it is determined that the inverter has a fault.

9. The inverter carrier synchronization system according to claim 8, characterized in that, The step of determining whether the corresponding inverter device has a fault based on the current detection signal also includes: If the preset fault threshold is not exceeded, but the fault status signal output by the inverter is at a high level, it is determined that there is no fault in the inverter, and the fault status signal output by the inverter is changed to a low level.

10. The inverter carrier synchronization system according to any one of claims 1 to 9, characterized in that, Each inverter unit also includes an adjustable isolated power supply module; The CPLD unit integrates an interference voltage detection unit, which generates a matching adjustment control signal by acquiring the fluctuation amplitude of the CAN bus differential signal. The adjustable isolation power supply module provides a matching output isolation voltage based on the adjustment control signal, which is used to provide isolated power supply for the CPLD unit, fault identification unit and current sampling unit.

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