Information modulation method and system for LLC resonant converter

Abstract

The application relates to the field of electronic communication technology and discloses an information modulation method and system for an LLC resonant converter. The application provides an information modulation method for an LLC resonant converter, which comprises the following steps: a power control loop module of the LLC resonant converter outputs a target frequency through a period conversion module; a digital signal to be transmitted is decomposed into a symbol sequence composed of a symbol A and a symbol B in a split-phase code mode; a frequency change lookup table module is established according to the target frequency, the target frequency is input, and a frequency change amount is correspondingly output; in the encoding mode of the split-phase code, a preset delay time is inserted when the symbols are switched, and actual delay time and phase shift angle are obtained according to the relationship between frequency jump and phase; and the digital signal is modulated into the LLC resonant converter through a PFM module.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic communication technology, and in particular to an information modulation method and system for an LLC resonant converter. BACKGROUND

[0002] In a conventional LLC resonant converter, information interaction usually relies on independent weak-current communication interfaces such as CAN bus and RS485 serial communication to realize data exchange with a front-end control unit or a back-end load. Since these communication links work in a low-voltage weak-current signal environment, they must be electrically isolated from the high-voltage and high-current path in the main power circuit to prevent strong electrical signals from damaging the communication module and even endangering system safety.

[0003] However, in actual engineering applications, this information transmission method based on external communication channels has multiple inherent defects, as follows: difficulty in strong-weak-current isolation and low reliability. In order to meet the requirements of functional safety and electromagnetic compatibility (EMC), the conventional scheme often needs to use optical coupling, magnetic coupling or digital isolator to realize electrical isolation of communication signals. However, such isolator devices not only increase the hardware cost and design complexity of the system, but also may introduce additional signal delay and error code risk. In addition, once the isolation layer fails, the entire communication link may be paralyzed, and even serious system failure may be caused.

[0004] The communication link is susceptible to electromagnetic interference (EMI) and has poor stability. LLC converter as a high-frequency switching power supply, there are rapidly changing voltage and current in the main power circuit, which is easy to produce strong electromagnetic interference. And the existing communication link is usually connected to the controller through PCB wiring or wire harness, which is extremely susceptible to radiation or conduction interference from power switching devices, transformers and inductors. Especially in high power density and high switching frequency application scenarios, communication signals are more likely to have error codes, packet loss or even complete interruption, which seriously affects the real-time performance and stability of the system.

[0005] Auxiliary power supply design is complex, increasing the difficulty of system integration. Since the communication module, control chip, isolation drive and other peripheral circuits usually operate at a lower voltage (such as 3.3V, 5V, etc.), it is necessary to configure multiple auxiliary power supplies with different voltage levels inside the LLC converter. The current mainstream approach is to integrate multiple small Buck converters on the main power board to generate power supply voltages for each subsystem. Although there are mature IC manufacturers providing dedicated controllers and integrated inductor solutions, the layout of dozens of DC-DC conversion circuits on a PCB still poses the following problems: 1. Limited layout space affects heat dissipation design; 2. There is potential cross interference between multiple power supplies; 3. The PCB manufacturing process requirements are increased, resulting in a decrease in production yield; 4. The overall system power consumption increases, and the maintenance and debugging complexity increases; 5. The system producibility and reliability are challenged.

[0006] With the increase in the number of auxiliary power supplies, the density of components on the main power board is significantly increased, which not only increases the difficulty of welding, testing and maintenance, but also increases the failure rate of the entire machine. Especially in harsh conditions such as high temperature, high humidity and vibration, the stability of the multi-power supply system is difficult to guarantee, thereby affecting the long-term operation reliability of the entire LLC converter.

[0007] In summary, the existing LLC converter generally relies on independent weak electric communication channels and multiple auxiliary power supplies to complete information interaction and system control. This approach has gradually exposed many limitations when faced with high integration, high reliability and strong electromagnetic interference in industrial application scenarios. These problems are essentially due to the physical separation of information transmission paths and energy transmission paths, as well as the high dependence of the system on additional communication infrastructure. SUMMARY

[0008] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art and provide an information modulation method and system for an LLC resonant converter, which realizes common channel transmission of energy and information.

[0009] The technical solution of the present application is as follows: on the one hand, the present application discloses an information modulation method for an LLC resonant converter, which comprises the following steps:

[0010] S1, the power control loop module of the LLC resonant converter outputs a target frequency through a period conversion module ;

[0011] S2, a frequency change lookup table module is established according to the target frequency The frequency change lookup table module includes a corresponding relationship between the target frequency and the frequency change amount , the target frequency is input into the frequency change lookup table module, and the frequency change amount is output correspondingly ;

[0012] S3, decomposing the digital signal to be transmitted into a symbol sequence composed of a symbol A and a symbol B in a split-phase code manner, wherein the symbol A is first in a first half period with a frequency of and in a second half period with a frequency of , and the symbol B is first in a first half period with a frequency of and in a second half period with a frequency of ;

[0013] S4, in the encoding manner of the split-phase code, inserting a preset delay time to change the phase of a subsequent waveform, adjusting the phase while frequency hopping, and obtaining an actual delay time and a phase shift angle according to the relationship between the frequency hopping and the phase;

[0014] S5, generating a variable frequency and variable phase gate drive signal through a PFM module after modulating the digital signal into the LLC resonant converter.

[0015] As can be seen from the above scheme, the delay time is inserted at the beginning of the symbol to change the phase of the subsequent waveform, so that each symbol also adjusts the phase while frequency hopping (i.e., delays a certain phase) to ensure the continuity of the waveform during the phase switching process and balance the power fluctuation. The present application designs a frequency-symmetric split-phase code to express the symbol A and the symbol B in different frequency difference orders, expresses different symbols through frequency hopping, realizes common channel transmission of energy and information, and uses the power electronic conversion process to realize information modulation function, thereby simultaneously realizing information modulation and power control. The digital signal to be transmitted is directly superimposed on the power control target of the converter, so that the output voltage or current of the converter has a small amplitude fluctuation, and the fluctuation level value is used to represent different digital baseband information. The modulation method disclosed in the present application realizes data communication through frequency coding while maintaining the power output of the LLC converter. The core idea is to use a frequency-symmetric split-phase code to encode information on the switching frequency, and to ensure power stability through phase adjustment.

[0016] In S4, the delay time corresponding to the frequency change satisfies the following formula:

[0017]

[0018] wherein is the delay time, is the phase shift angle, is the target frequency, and The frequency variation amount of the delay process.

[0019] In S4, the frequency variation amount of the delay process The following formula is satisfied:

[0020]

[0021] After transformation, it is expressed as:

[0022]

[0023] Wherein, represents the target frequency, represents the delay time, , represents the frequency variation amount of the delay process.

[0024] In S4, the phase shift angle The relationship between the frequency variation satisfies the following formula:

[0025]

[0026] Wherein, represents the phase shift angle, represents the target frequency, represents the frequency variation amount.

[0027] In S1, the power control loop first compares the sampled output voltage V out with the target V ref to obtain the error V err , and then outputs the intermediate quantity V uo through the PI controller, and then compares the sampled output current Iout with Iref, and then calculates the target switching period Ip through PI.

[0028] In S3, the frequency variation lookup table module is a frequency corresponding table.

[0029] In S3, the frequency variation lookup table module is a linear formula, and the expression of the linear formula is:

[0030]

[0031] Wherein, k is a coefficient, represents the target frequency, represents the frequency variation amount.

[0032] In another aspect, the present application discloses an information modulation system for implementing an information modulation method of a LLC resonant converter, comprising a power control loop module, a symbol generation module and a PFM module, the symbol generation module is electrically connected with the power control loop module and the PFM module respectively, the power control loop module is used for obtaining a target frequency, the symbol generation module is used for generating a symbol sequence, and the PFM module is used for realizing frequency modulation.

[0033] The power control loop module comprises a current inner loop module, a voltage outer loop module and a period conversion module, the current inner loop module is electrically connected with the voltage outer loop module and the period conversion module respectively, the voltage outer loop module is used for voltage control, the current inner loop module is used for current control, and the period conversion module is used for obtaining a target frequency. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a control loop schematic diagram of the present application;

[0035] Figure 2 is a step schematic diagram of the present application;

[0036] Figure 3 is a traditional split-phase code waveform diagram schematic diagram;

[0037] Figure 4 is a frequency symmetric split-phase code schematic diagram;

[0038] Figure 5 is a two-stage charging system block diagram with power-data multiplex modulation;

[0039] Figure 6 is an LLC converter main topology diagram;

[0040] Figure 7 is an LLC converter side information modulation schematic diagram;

[0041] Figure 8 is a load side information demodulation schematic diagram;

[0042] Figure 9 is a power control loop schematic diagram;

[0043] Figure 10 is a waveform schematic diagram when the LLC converter transmits a random digital signal. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

[0045] As Figures 1 to 10The application is a method and system for information modulation of LLC resonant converter.

[0046] Generally, power electronic converters can be decomposed into several passive network modules and switching network modules. Passive network modules are composed of linear passive devices, so there exists a transfer function G(s) such that the input X(s) and output Y(s) of the passive network module satisfy the following formula:

[0047]

[0048] The input / output waveform of the switching network module is determined by the gate signal of the switching device controlling the module, and the voltage / current at the input / output port generally contains discontinuous quantities, which is caused by the switching action of the power device in the switching network module, which discretizes continuous physical quantities and is the basic underlying physical mechanism of the power-data multiplexing modulation technology. When the gate signal is uncertain or contains a certain degree of uncertainty, the input and output waveforms of the switching network module corresponding to the signal are also in an uncertain state, so the above uncertainty can be eliminated by detecting the electrical quantities in the circuit and obtaining information.

[0049] Since the uncertainty of the above converter state is generated by the power conversion process, the information corresponding to the uncertainty is defined as "power conversion entropy". When there are variables J1, J2, …, J k When the state of the converter is completely determined, the power conversion entropy can be expressed as a function of the above state, i.e.:

[0050]

[0051] The information in the power converter is completely derived from the switching network module, and the switching network module is controlled by its corresponding gate signal, so the behavior of the power electronic converter can be studied by analyzing the signal. In the converter, the gate signal g(t) is usually a square wave signal, and for ease of description, its high and low levels can be normalized to 1 and 0, respectively. Assuming that the gate waveform in each switching period remains consistent within a time period Tb consisting of an integer number of switching periods, and the switching angular frequency is ωs, the following relationship is satisfied:

[0052]

[0053] It can be found that the characteristics of the gate square wave signal can be described and controlled by three independent parameters: frequency, phase, and duty cycle, so these three parameters are considered as three adjustable control dimensions of the gate signal.

[0054] In a conventional communication system, the symbol duration T bIt is not required to be an integer multiple of the carrier period; while in the power converter, the switching period is the most basic time unit, and all operation times for the gate signal need to be expressed in integer multiples of the period. Therefore, the symbol period for multiplex modulation must also satisfy being an integer multiple of the switching period Ts, that is, the following relationship holds:

[0055]

[0056] Therefore, the switching period is called the basic control unit in the fusion control, and the time for maintaining the constant degree of freedom of the gate signal is calculated in the basic control unit.

[0057] In information theory, the definition and calculation of entropy are important theoretical basis in the content related to discrete sources. Let the probability space of the discrete source X be:

[0058]

[0059] Where x1, x2,..., xq are all symbols in the discrete source X, P(x1), P(x2),..., P(xq) are the probabilities of the occurrence of each symbol, and satisfy the following formula:

[0060]

[0061] When the unit is bit, the self-information of a single symbol is:

[0062]

[0063] The entropy is defined as the mathematical expectation of the self-information, that is, the average self-information, and its expression is:

[0064]

[0065] The power-data multiplex modulation is realized by manipulating the gate square wave signal of the switching device, and the manipulation of the gate signal is essentially controlling the frequency, phase and duty cycle of the gate signal. Therefore, the three degrees of freedom are the three sources in the converter, and the present application is to modulate information into the power output by the LLC converter through the control of the three degrees of freedom.

[0066] For the LLC converter, the frequency is used for power control, and the average frequency value needs to be kept constant when the pulse frequency is used for communication to obtain constant power output, so additional constraints are needed. In the design of the converter, the output is generally allowed to fluctuate within a small range, and the frequency change of the LLC circuit and the output voltage change within the range are linearly related, so the frequency coding method can be used to maintain the constant output of the converter.

[0067] In one aspect, the application discloses a method for information modulation of an LLC resonant converter, comprising the following steps:

[0068] S1, a power control loop module 1 of the LLC resonant converter outputs a target frequency through a period conversion module 13 ;

[0069] S2, a frequency change lookup table module 2 is established according to the target frequency , the frequency change lookup table module 2 comprises a corresponding relationship between the target frequency and a frequency change amount , the target frequency is input in the frequency change lookup table module 2, and the frequency change amount is output correspondingly ;

[0070] S3, a digital signal to be transmitted is decomposed into a symbol sequence composed of a symbol A and a symbol B in a split-phase code manner, wherein the symbol A is first at a frequency of in a first half period and at a frequency of in a second half period, and the symbol B is first at a frequency of in the first half period and at a frequency of in the second half period ;

[0071] S4, in the coding manner of the split-phase code, a preset delay time is inserted at the symbol switching time to change the phase of a subsequent waveform, the phase is adjusted at the same time of frequency jump, and according to the relationship between the frequency jump and the phase, an actual delay time and a phase shift angle are obtained ;

[0072] S5, the digital signal is modulated into the LLC resonant converter through a PFM module 3.

[0073] In S4, the delay time corresponding to the frequency change amount satisfies the following formula:

[0074]

[0075] wherein is the delay time, is the phase shift angle, is the target frequency, is the frequency change amount.

[0076] In S4, the frequency change of the delay process satisfies the following formula:

[0077]

[0078] By transformation, it is expressed as:

[0079]

[0080] wherein, represents the target frequency, represents the delay time, , represents the frequency variation of the delay process.

[0081] In S4, the phase shift angle and the frequency variation satisfy the following formula:

[0082]

[0083] wherein, represents the phase shift angle, represents the target frequency, represents the frequency variation.

[0084] In S1, the power control loop 1 first compares the sampled output voltage V out with the target V ref to obtain the error V err , then outputs the intermediate quantity V uo through the PI controller, and then compares the sampled output current Iout with Iref and outputs the target switching period Ip through PI calculation.

[0085] In an embodiment, the frequency variation lookup table module 2 in S3 is a frequency corresponding table.

[0086] In another embodiment, the frequency variation lookup table module 2 in S3 is a linear formula, and the expression of the linear formula is:

[0087]

[0088] wherein, is a coefficient, represents the target frequency, represents the frequency variation. In this embodiment, is a minimum proportional coefficient.

[0089] The present invention also discloses an information modulation system for implementing an information modulation method for an LLC resonant converter. The information modulation system includes a power control loop module 1, a symbol generation module, and a PFM module 3. The symbol generation module is electrically connected to the power control loop module and the PFM module 3, respectively. The power control loop module 1 is used to obtain a target frequency, the symbol generation module is used to generate a symbol sequence, and the PFM module 3 is used to implement frequency conversion modulation.

[0090] The power control loop module 1 includes a current inner loop module, a voltage outer loop module, and a period conversion module 13. The current inner loop module is electrically connected to the voltage outer loop module and the period conversion module 13, respectively. The voltage outer loop module is used for voltage control, the current inner loop module is used for current control, and the period conversion module 13 is used to obtain the target frequency.

[0091] In this embodiment, the power control loop module is a common inner and outer loop structure in an LLC converter. For example... Figure 1 As shown, its parameters are as follows: Vout is the sampled output voltage; Vref is the target voltage; Verr is the voltage error; Kv1 is the voltage outer loop proportional value 1; Kv2 is the voltage outer loop proportional value 2; Vup and Vui are both process quantities in the voltage outer loop PI calculation; Ts is the sampling time; z is a complex independent variable in a mathematical transformation of a discrete sequence; Iref is the target current; the MIX module is a limiting module (its function is to select the smaller value between the target current Iref and the voltage outer loop PI calculated value Vu); Vuo is the intermediate quantity between the inner and outer loops; Iout is the sampled output current; Ierr is the current error; PI is a PI calculation process; Ip is the output value calculated by the inner loop, so period conversion can be performed to obtain the target frequency f0 of the PFM); f0 is the target frequency.

[0092] Digital signals are data signals that need to be transmitted; data allocation breaks these data down into... Figure 4 This invention employs a split-phase code encoding method, such as... Figure 3 As shown, this encoding method divides a symbol into two parts with opposite voltage levels to ensure that the encoding has no DC component, thereby ensuring that the converter output is constant.

[0093] Figure 3 The encoding shown is described in units of a single clock pulse cycle, while in an LLC converter, operation is performed in units of a single switching cycle. Therefore, if this encoding method is applied in an LLC converter, each symbol requires more than two switching cycles. Traditional split-phase encoding uses dual-level encoding, employing different positions of high and low levels to represent different symbols.

[0094] In order to express such symbols in the frequency degree of freedom, the application adopts a frequency-symmetrical split-phase code, as shown in the figure. Figure 4 This is a frequency-improved type based on the construction idea of the split-phase code. Unlike the traditional split-phase code which expresses different symbols by high and low levels, the frequency-symmetrical split-phase code expresses symbols A and B by frequency hopping. Different frequency differences are expressed in different orders. The two symbols are constructed by changing the target frequency in different ways. In the embodiment, symbol A is first at a frequency of in the first half cycle and at a frequency of in the second half cycle. Symbol B is first at a frequency of in the first half cycle and at a frequency of in the second half cycle. This definition method can be reversed, which is only a definition method and does not affect the implementation process.

[0095] In order to reduce the influence of output power, will change with the target frequency . In the embodiment, the frequency change lookup table module in Figure 1 establishes a certain lookup table method (a certain range of target frequencies or a counter period corresponds to a certain change frequency ). In another embodiment, the frequency change lookup table module in Figure 1 is a linear formula to express the corresponding relationship between and the target frequency . In the frequency decision part, according to the relationship between frequency hopping and phase, the delay time and the phase shift angle can be obtained.

[0096] The application realizes the above algorithm process in the DSP in power electronics. The microprocessor selected is the common TMS320F28035. The simulation environment is simulink, and the modulation of electric energy is realized through simulation. The algorithm part is written in C language in S-Function.

[0097] In the power control loop module, the outer loop is usually used for voltage control, and the inner loop is used for current control. The double-loop PI controller structure expressed by C language is as follows:

[0098] #include “simstruc.h”

[0099] #include“DSP28x_Project.h” / / Include the related header file of TMS320F28035

[0100] typedef struct {

[0101] real_T Kp;

[0102] real_T Ki;

[0103] real_T integral;

[0104] real_T prev_error;

[0105] } PIController;

[0106] void initPI(PIController *pi, real_T Kp, real_T Ki) {

[0107] pi->Kp = Kp;

[0108] pi->Ki = Ki; [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​real_T V_ref = ssGetInputPortRealSignal(S, 0)[0]; / / outer loop reference voltage

[0121] real_T V_out = ssGetInputPortRealSignal(S, 1)[0]; / / outer loop feedback voltage

[0122] real_T I_out = ssGetInputPortRealSignal(S, 2)[0]; / / inner loop feedback current

[0123] / / Initialize PI controllers

[0124] static PIController pi_v;

[0125] static PIController pi_i;

[0126] initPI(&pi_v, 1.0, 0.1); / / Example parameters, adjust according to actual situation

[0127] initPI(&pi_i, 1.0, 0.1);

[0128] / / Update outer loop PI controller

[0129] real_T V_err = V_ref - V_out;

[0130] real_T V_ctrl = updatePI(&pi_v, V_err, 0.001); / / Assuming sampling time is 1ms

[0131] / / Update inner loop PI controller

[0132] real_T I_err = V_ctrl - I_out; / / Use outer loop output as inner loop reference

[0133] real_T I_ctrl = updatePI(&pi_i, I_err, 0.001);

[0134] / / Output result

[0135] real_T *y = ssGetOutputPortRealSignal(S, 0);

[0136] y[0] = I_ctrl; / / Output as inner loop control variable

[0137] }

[0138] The configuration method of MS320F28035 includes the initialization of each clock system and the configuration of the PWM module, and the method corresponds to the following code:

[0139] void InitSysCtrl(void) {

[0140] EALLOW;

[0141] SysCtrlRegs.WDCR = 0x0068; / / disable watchdog

[0142] SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; / / PLL division coefficient setting

[0143] SysCtrlRegs.PLLCR.bit.DIV = 0xA; / / PLL multiplication coefficient setting, adjust according to actual frequency

[0144] EDIS;

[0145] DINT; / / disable global interrupt

[0146] InitPieCtrl(); / / initialize PIE control register

[0147] IER = 0x0000; / / clear all enabled interrupts

[0148] IFR = 0x0000; / / clear all pending interrupts

[0149] InitPieVectTable(); / / initialize PIE vector table

[0150] EALLOW;

[0151] / / Add other peripheral initialization code here

[0152] EDIS;

[0153] }

[0154] void ConfigEPwm1Example() {

[0155] EPwm1Regs.TBPRD = 1000; / / set period register

[0156] EPwm1Regs.CMPA.bit.CMPA = 500; / / Set compare register A

[0157] EPwm1Regs.TBCTL.bit.CTRMODE = 0; / / Up / Down count mode

[0158] EPwm1Regs.TBPHS.bit.TBPHS = 0; / / Phase register

[0159] EPwm1Regs.AQCTLA.bit.CAU = 1; / / Compare action: Set EPWMxA high when count value increases to CMPA

[0160] EPwm1Regs.AQCTLA.bit.CAD = 2; / / Compare action: Set EPWMxA low when count value decreases to CMPA

[0161] EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; / / High speed clock pre-division

[0162] EPwm1Regs.TBCTL.bit.CLKDIV = 0; / / Timer clock division

[0163] EPwm1Regs.ETSEL.bit.SOCAEN = 1; / / Enable SOCA event trigger

[0164] EPwm1Regs.ETPS.bit.SOCAPRD = 1; / / SOCA event occurs at end of every period

[0165] EPwm1Regs.ETSEL.bit.INTEN = 1; / / Enable interrupts

[0166] EPwm1Regs.ETPS.bit.INTPRD = 1; / / Interrupt occurs at end of every period

[0167] }

[0168] The period conversion module is used to convert to the target frequency f0, and the corresponding code is as follows:

[0169] #include "DSP28x_Project.h"

[0170] #include <math.h>

[0171] / / Define lookup table data

[0172] #define TABLE_SIZE 7

[0173] real_T Ip_table[TABLE_SIZE] = {0.0, 0.2, 0.4, 0.6, 0.7, 0.8, 1.0}; / / Normalized current

[0174] real_T f0_table[TABLE_SIZE] = {60000, 58000, 55000, 51000, 48000,45000, 40000}; / / Corresponding frequency (Hz)

[0175] / / Compensation parameters

[0176] real_T Vin_nominal = 400.0; / / Nominal input voltage

[0177] real_T freq_comp_gain = 50.0; / / Input voltage compensation gain

[0178] / / Frequency boundary limit

[0179] real_T f_min = 38000;

[0180] real_T f_max = 62000;

[0181] / **

[0182] * @brief Calculate the target frequency f0 using table lookup and linear interpolation.

[0183] * @param Ip Current normalized current

[0184] * @param Vin Current input voltage

[0185] * @return real_T Calculated target frequency

[0186] /

[0187] real_T compute_f0(real_T Ip, real_T Vin) {

[0188] / / Boundary restrictions

[0189] if (Ip < Ip_table[0]) Ip = Ip_table[0];

[0190] if (Ip > Ip_table[TABLE_SIZE - 1]) Ip = Ip_table[TABLE_SIZE - 1];

[0191] / / Find interval

[0192] int i;

[0193] for (i = 0; i < TABLE_SIZE - 1; i++) {

[0194] if (Ip >= Ip_table[i] && Ip <= Ip_table[i + 1]) {

[0195] break;

[0196] }

[0197] }

[0198] / / Linear interpolation

[0199] real_T slope = (f0_table[i + 1] - f0_table[i]) / (Ip_table[i + 1]- Ip_table[i]);

[0200] real_T f_base = f0_table[i] + slope * (Ip - Ip_table[i]);

[0201] / / Input voltage compensation: boost frequency slightly when Vin is low to maintain gain

[0202] real_T f_comp = f_base + freq_comp_gain * (Vin_nominal - Vin);

[0203] / / Output frequency limit

[0204] if (f_comp < f_min) f_comp = f_min;

[0205] if (f_comp > f_max) f_comp = f_max;

[0206] return f_comp;

[0207] }

[0208] The symbol generation module includes two processes: frequency decision and phase decision. The code is as follows:

[0209] #include <math.h>

[0210] #include "DSP28x_Project.h"

[0211] / / Symbol type definition

[0212] typedef enum {

[0213] CODE_A,

[0214] CODE_B

[0215] } CodeType;

[0216] / / Symbol structure (each symbol contains information of two switching cycles)

[0217] typedef struct {

[0218] real_T freq; / / Current cycle frequency

[0219] real_T duty; / / Current cycle duty cycle (phase shift angle)

[0220] } SwitchingCycle;

[0221] / / Symbol sequence structure

[0222] typedef struct {

[0223] SwitchingCycle cycles[2]; / / Each symbol consists of two cycles

[0224] } CodeSymbol;

[0225] / **

[0226] * @brief Generate frequency-symmetric split-phase code according to input bit, target frequency f0 and Δfi, and add phase shift compensation

[0227] * @param bit Input bit (0 or 1)

[0228] * @param f0 Target frequency

[0229] * @param delta_fi Frequency offset

[0230] * @param load_factor Load factor (for phase shift compensation)

[0231] * @param symbol The output symbol structure

[0232] /

[0233] void generateCodeSymbol(uint16 bit, real_T f0, real_T delta_fi, real_T load_factor, CodeSymbol *symbol) {

[0234] / / Select symbol type

[0235] CodeType code_type = (bit == 0) ? CODE_A : CODE_B;

[0236] / / The basic duty cycle is set to 0.5 (ideal split phase).

[0237] real_T base_duty = 0.5;

[0238] / / Phase shift compensation calculation (Therefore, in order to ensure the continuity of the waveform during phase switching, a phase shift angle is needed to compensate for the delay time)

[0239] real_T phase_compensation = 0.05 * (load_factor - 0.5); / / Example compensation formula

[0240] / / Limit within a reasonable range

[0241] if (phase_compensation > 0.1) phase_compensation = 0.1;

[0242] if (phase_compensation < -0.1) phase_compensation = -0.1;

[0243] / / Calculate parameters for two periods

[0244] if (code_type == CODE_A) {

[0245] / / Type A: High frequency first, then low frequency

[0246] symbol->cycles[0].freq = f0 + delta_fi;

[0247] symbol->cycles[0].duty = base_duty + phase_compensation;

[0248] symbol->cycles[1].freq = f0 - delta_fi;

[0249] symbol->cycles[1].duty = base_duty - phase_compensation;

[0250] } else {

[0251] / / B type: low frequency first, then high frequency

[0252] symbol->cycles[0].freq = f0 - delta_fi;

[0253] symbol->cycles[0].duty = base_duty + phase_compensation;

[0254] symbol->cycles[1].freq = f0 + delta_fi;

[0255] symbol->cycles[1].duty = base_duty - phase_compensation;

[0256] }

[0257] / / Duty cycle boundary limit

[0258] for (int i = 0; i < 2; i++) {

[0259] if (symbol->cycles[i].duty < 0.4) symbol->cycles[i].duty =0.4;

[0260] if (symbol->cycles[i].duty > 0.6) symbol->cycles[i].duty =0.6;

[0261] }

[0262] }

[0263] The parameter setting process of one of the PWMs of the PWM generation module is shown in the following code, which is called in each interrupt to implement the PFM process

[0264] void setPWMFrequency(real_T frequency, real_T duty_cycle) {

[0265] / / Assuming the ePWM module is used to configure the frequency and duty cycle

[0266] Uint32 period = (Uint32)(CPU_FREQ / (2 * frequency)); / / Dual-edge triggering

[0267] EPwm1Regs.TBPRD = period;

[0268] EPwm1Regs.CMPA.bit.CMPA = (Uint16)(duty_cycle * period);

[0269] }

[0270] The configuration diagram of the Simulink simulation environment is as follows: Figures 6-9 As shown. Figure 6 As shown, the main topology diagram of the LLC converter is the upper-level schematic diagram of an embodiment of the present invention. The device parameters, resonant cavity parameters, and operating conditions can be modified here. For example... Figure 7 As shown, this simulation model represents the PWM modulation section of an LLC converter. It illustrates the process of PFM (Pulse Frequency Modulation) combining the count value and the number of cycles. The modulated signal, after processing the count value and the number of cycles, is used to modulate the digital signal into the LLC resonant converter. Figure 8 As shown, the sampled analog-to-digital converter (ADC) is used to set the power loop through the digitization process of demand voltage and current. The digitization process of demand current and voltage involves the sampled ADC acquiring analog quantities from each node and converting them into digital quantities. The sampled ADC is then used to demodulate load-side information, such as... Figure 9 As shown, the power control loop module of the present invention adopts a classic inner and outer loop structure. In this power control loop module, the outer loop is used for voltage control, and the inner loop is used for current control.

[0271] like Figure 10 As shown, CH1 is the gate signal, CH2 is the output voltage ripple, CH3 is the transmitted digital signal, CH4 is the received digital signal, and CH5 is the spectrum of the output voltage ripple. It can be seen that all digital signals are correctly transmitted and received.

[0272] Finally, it should be noted that the above description is not intended to limit the present application, and that various changes and modifications can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application, and that any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An information modulation method for an LLC resonant converter, characterized in that: S1, the power control loop module (1) of LLC resonant converter outputs target frequency through period conversion module (13) ; S2, according to the target frequency A frequency change look-up table module (2) is established, the frequency change look-up table module (2) includes the target frequency Corresponding relationship of the frequency change amount, the target frequency Is input in the frequency change look-up table module (2), and the corresponding frequency change amount Is output ; S3, the digital signal to be sent is decomposed into a symbol sequence composed of symbol A and symbol B by means of split-phase code, wherein symbol A is first in the former half period with a frequency of , and in the latter half period with a frequency of , and symbol B is first in the former half period with a frequency of , and in the latter half period with a frequency of ; S4, in the encoding mode of the split symbol code, inserting preset delay time at symbol switching to change the phase of the subsequent waveform, to adjust the phase at the same time of frequency hopping, to obtain the actual delay time according to the relationship between frequency hopping and phase and the phase shift angle ; S5, modulating a digital signal into the LLC resonant converter through a PFM module (3); In S4, the frequency change of the delay process satisfies the following equation: , After conversion, it is expressed as: , wherein, denotes a target frequency, denotes a delay time, , denotes a frequency variation amount of the delay process; In S4, the phase shift angle The relationship between the frequency change amount satisfies the following equation: , wherein, denotes a phase shift angle, denotes a target frequency, denotes a frequency change amount.

2. The information modulation method for LLC resonant converter according to claim 1, wherein: In S4, the frequency variation amount The corresponding delay time Satisfies the following formula: , wherein, is a delay time, is a phase shift angle, is a target frequency, is a frequency change amount.

3. The information modulation method for LLC resonant converter according to claim 1, wherein: In S1, the power control loop (1) first compares the sampled output voltage V out with the target V ref to obtain an error V err , then outputs an intermediate quantity V uo through a PI controller, and then compares the sampled output current Iout with Iref to obtain the target switching period Ip through PI calculation.

4. The information modulation method for LLC resonant converter according to claim 1, wherein: In S3, the frequency change lookup table module (2) is a frequency corresponding table.

5. The information modulation method for LLC resonant converter according to claim 1, wherein: In S3, the frequency change lookup table module (2) is a linear formula, and the expression of the linear formula is: , where k is a coefficient, denotes a target frequency, denotes a frequency change amount.

6. An information modulation system for implementing the information modulation method for LLC resonant converter according to any one of claims 1-5, characterized in that: The information modulation system comprises a power control loop module (1), a symbol generation module and a PFM module (3), the symbol generation module is electrically connected with the power control loop module and the PFM module (3) respectively, the power control loop module (1) is used for obtaining a target frequency, the symbol generation module is used for generating a symbol sequence, and the PFM module (3) is used for realizing frequency modulation.

7. The information modulation system of claim 6, wherein: The power control loop module (1) comprises a current inner loop module, a voltage outer loop module and a period conversion module (13), the current inner loop module is electrically connected with the voltage outer loop module and the period conversion module (13) respectively, the voltage outer loop module is used for voltage control, the current inner loop module is used for current control, and the period conversion module (13) is used for obtaining a target frequency.

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