Device for inhibiting p-type oxide semiconductor thin film transistor inversion electron current and preparation method thereof

Abstract

The invention provides a device for inhibiting inversion electron current of a p-type oxide semiconductor thin film transistor and a preparation method thereof, and the device comprises a substrate which is provided with a first surface; the grid electrode is arranged on the first surface; the gate dielectric layer is arranged on one side, deviating from the substrate, of the gate electrode; the semiconductor layer is arranged on one side, deviating from the gate dielectric layer, of the gate dielectric layer; the source electrode and the drain electrode are arranged on the semiconductor layer, a gap is formed between a first projection, formed on the first surface, of the drain electrode and a second projection, formed on the first surface, of the grid electrode, and the first projection and the second projection are both orthographic projections. According to the invention, the inversion electron current of the semiconductor device can be reduced, so that the semiconductor device can be effectively turned off under inversion gate voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a device for suppressing inverse electron current of a p-type oxide semiconductor thin film transistor and a preparation method thereof. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Oxide semiconductor thin-film transistors (TFTs) have the advantages of high mobility, low fabrication cost, and the ability to form uniform films over large areas. Consequently, their applications are becoming increasingly widespread. P-type oxide semiconductor TFTs, a type of oxide semiconductor TFT, also have a wide range of applications.

[0004] In related art, a P-type oxide semiconductor TFT may include a substrate, a gate electrode, a gate dielectric layer, and a semiconductor layer stacked sequentially on the substrate, and a source electrode and a drain electrode on the semiconductor layer, wherein the semiconductor layer may be made of SnO.

[0005] Because the semiconductor layer contains both Sn2+ and Sn4+ oxidation states, and SnO has a narrow indirect band gap, P-type oxide semiconductor TFTs have a high inversion electron current. When semiconductor devices are used in integrated circuits, they may not be completely turned off. Summary of the Invention

[0006] In order to solve the above problems, the present invention proposes a device and a preparation method for suppressing the inversion electron current of a p-type oxide semiconductor thin film transistor. The present invention can reduce the inversion electron current of the semiconductor device, thereby enabling the semiconductor device to be effectively shut down under an inversion gate voltage.

[0007] According to some embodiments, the present invention adopts the following technical solutions:

[0008] A first aspect of the present invention provides a device for suppressing inverse electron current in a p-type oxide semiconductor thin film transistor, comprising a substrate, a gate, a gate dielectric layer, and a semiconductor layer arranged sequentially from bottom to top;

[0009] The semiconductor layer has a first surface facing away from the gate;

[0010] and a source electrode and a drain electrode, which are disposed on the semiconductor layer;

[0011] There is a gap between a first projection of the drain electrode formed on the first surface and a second projection of the gate electrode on the first surface, and both the first projection and the second projection are orthographic projections.

[0012] Of course, sometimes, when the first projection and the second projection are oblique projections, there is also a gap between the first projection formed by the drain on the first surface and the second projection of the gate on the first surface. The scheme further illustrates that the device for suppressing the inversion electron current of the p-type oxide semiconductor thin film transistor provided by the first aspect of the present invention has no overlapping area between the drain and the gate in the vertical direction.

[0013] In the above technical solution, when the semiconductor device is under an inversion gate voltage, that is, when the gate voltage is higher than the electron threshold voltage, inversion electrons will accumulate within the projected area of ​​the drain on the semiconductor layer. A gap exists between the first projection of the drain on the first surface of the semiconductor layer and the second projection of the gate on the first surface. That is, a first gap region exists in the semiconductor layer, located between the projected area of ​​the drain on the semiconductor layer and the projected area of ​​the gate on the semiconductor layer. The first gap region does not overlap with the projected area of ​​the drain on the semiconductor layer, nor does the first gap region overlap with the projected area of ​​the gate on the semiconductor layer. Therefore, the first gap region can weaken the gate's control over the semiconductor layer, thereby suppressing the accumulation of inversion electrons and facilitating the depletion of inversion electrons within the projected area of ​​the drain on the semiconductor layer. This reduces the inversion electron current and effectively shuts down the semiconductor device under the inversion gate voltage.

[0014] Furthermore, the presence of the first gap region has a minimal effect on the hole on-state current. Specifically, the hole on-state current remains unchanged, or decreases slightly but by a smaller amount, thereby maintaining the current on / off ratio. Furthermore, the presence of the first gap region also has a minimal effect on mobility, threshold voltage, and subthreshold swing.

[0015] As an optional implementation manner of the first aspect of the present invention, there is a gap between the third projection and the second projection of the source electrode on the first surface, and the third projection is an orthographic projection.

[0016] In the above solution, a second gap region exists in the semiconductor layer. This second gap region is located between the source electrode's projection on the semiconductor layer and the gate electrode's projection on the semiconductor layer. The second gap region does not overlap with the source electrode's projection on the semiconductor layer, nor does it overlap with the gate electrode's projection on the semiconductor layer. Therefore, this second gap region can weaken the gate's control over the semiconductor layer, thereby suppressing the accumulation of inversion electrons and facilitating the depletion of inversion electrons within the drain electrode's projection on the semiconductor layer. This reduces the inversion electron current and enables the semiconductor device to be effectively shut down under an inversion gate voltage.

[0017] As an optional embodiment of the first aspect of the present invention, the device further includes a first metal intercalation layer located between the drain electrode and the semiconductor layer. When the drain electrode is negatively biased, the semiconductor layer, the first metal intercalation layer, and the drain electrode form a reverse Schottky contact. Furthermore, the interface between the first metal intercalation layer and the semiconductor layer forms a barrier region. This facilitates the depletion of inversion electrons within the projected area of ​​the drain electrode on the semiconductor layer, thereby reducing the inversion electron current and enabling the semiconductor device to be effectively shut down under an inversion gate voltage.

[0018] As an optional embodiment of the first aspect of the present invention, the first projection is located within the projection range of the first metal intercalation layer on the first surface. That is, the projection range of the first metal intercalation layer on the first surface of the semiconductor layer covers the projection range of the drain electrode on the first surface of the semiconductor layer, thereby further enhancing the depletion of inversion electrons within the coverage area of ​​the drain electrode on the semiconductor layer, thereby further reducing the inversion electron current.

[0019] As an optional embodiment of the first aspect of the present invention, the device further includes a second metal intercalation layer, located between the source electrode and the semiconductor layer. The semiconductor layer, the second metal intercalation layer, and the source electrode can form an ohmic contact, i.e., the interface between the semiconductor layer and the second metal intercalation layer, and the interface between the second metal intercalation layer and the source electrode, are barrier-free. This allows holes within the projected area of ​​the source electrode on the semiconductor layer to be injected into the barrier-free interface, thereby achieving a high hole current.

[0020] As an optional embodiment of the first aspect of the present invention, the first metal intercalation layer and the second metal intercalation layer are made of the same layer and the same material. This allows the first metal intercalation layer and the second metal intercalation layer to be manufactured in the same process, resulting in a simple process flow.

[0021] As an optional embodiment of the first aspect of the present invention, the materials of both the first and second metal intercalation layers comprise high-work-function metals. High-work-function metals refer to metals with a high minimum energy required to move electrons from the interior of a solid to the surface of the solid. When both the first and second metal intercalation layers comprise high-work-function metals, hole current can be further increased and inversion electron current can be reduced.

[0022] As an optional embodiment of the first aspect of the present invention, it also includes a passivation layer, a portion of which is arranged on the source electrode, a portion is arranged on the drain electrode, and another portion is arranged on the semiconductor layer and is located in the channel between the source electrode and the drain electrode.

[0023] A second aspect of the present invention provides an integrated circuit comprising a circuit board and the semiconductor device according to the first aspect. The integrated circuit can achieve all the effects of the semiconductor device.

[0024] A third aspect of the present invention provides a chip comprising a packaging substrate and the integrated circuit described in the second aspect, wherein the integrated circuit is fixed on the packaging substrate. The chip can achieve all the effects of the integrated circuit.

[0025] A fourth aspect of the present invention provides an electronic device comprising a printed circuit board and the chip according to the third aspect, wherein the chip is electrically connected to the printed circuit board. The electronic device can achieve all the effects of the chip.

[0026] A fifth aspect of the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0027] forming a gate on the substrate;

[0028] forming a gate dielectric layer on a side of the gate facing away from the substrate;

[0029] A semiconductor layer is formed on the gate dielectric layer, and a source and a drain are formed on a first surface of the semiconductor layer away from the gate, wherein a gap exists between a first projection of the drain on the first surface and a second projection of the gate on the first surface.

[0030] As an optional implementation method of the fifth aspect, after the step of forming a semiconductor layer on the gate dielectric layer, the preparation method also includes: forming a first metal intercalation layer on the gate dielectric layer; the step of forming a source and a drain on the semiconductor layer includes: forming a source on the semiconductor layer; forming a drain on the first metal intercalation layer.

[0031] Through the above scheme, a barrier region can be formed between the first metal intercalation layer and the semiconductor layer. When the drain is negatively biased, the semiconductor layer, the first metal intercalation layer, and the drain can form a Schottky reverse contact, which facilitates the depletion of inversion electrons in the area covered by the drain in the semiconductor layer, thereby reducing the inversion electron current and enabling the semiconductor device to be effectively shut down under the inversion gate voltage.

[0032] As an optional embodiment of the fifth aspect, after the step of forming the semiconductor layer on the gate dielectric layer, the preparation method further includes: forming a second metal insertion layer on the gate dielectric layer; and forming a source electrode on the semiconductor layer, including:

[0033] A source electrode is formed on the second metal insertion layer.

[0034] As an optional implementation of the fifth aspect, it also includes: forming a passivation layer on the source and the drain, and the semiconductor layer in the channel between the source and the drain.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention provides a semiconductor device. When the semiconductor device is under an inversion gate voltage, that is, when the voltage of the gate is higher than the electron threshold voltage, inversion electrons will accumulate within the projected area of ​​the drain on the semiconductor layer. A gap exists between the first projection of the drain on the first surface of the semiconductor layer and the second projection of the gate on the first surface. In other words, a first gap region exists in the semiconductor layer. The first gap region is located between the projected area of ​​the drain on the semiconductor layer and the projected area of ​​the gate on the semiconductor layer. The first gap region does not overlap with the projected area of ​​the drain on the semiconductor layer, and the first gap region also does not overlap with the projected area of ​​the gate on the semiconductor layer. Therefore, the first gap region can weaken the control of the gate on the semiconductor layer, thereby suppressing the accumulation of inversion electrons, thereby facilitating the depletion of inversion electrons within the projected area of ​​the drain on the semiconductor layer, thereby reducing the inversion electron current, and thus enabling the semiconductor device to be effectively shut down under the inversion gate voltage.

[0037] Furthermore, in the semiconductor device provided by the present invention, the provision of the first gap region has a minimal effect on the hole on-state current. Specifically, the hole on-state current remains unchanged, or decreases slightly but by a smaller amount, thereby increasing the on-off ratio. Furthermore, the provision of the first gap region also has a minimal effect on mobility, threshold voltage, and subthreshold swing.

[0038] In summary, the present invention can reduce the inversion electron current of the semiconductor device, thereby enabling the semiconductor device to be effectively turned off under an inversion gate voltage.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0041] Figure 1 A schematic diagram of the structure of an integrated circuit in the prior art;

[0042] Figure 2 A schematic diagram of the structure of a semiconductor device in the prior art;

[0043] Figure 3 for Figure 2 Schematic diagram of the positional relationship between the gate, source and drain;

[0044] Figure 4 for Figure 3 Middle, enlarged schematic diagram of point A;

[0045] Figure 5This is a schematic structural diagram of a semiconductor device in the first embodiment of the present application;

[0046] Figure 6 for Figure 5 Schematic diagram of the positional relationship between the gate, source and drain;

[0047] Figure 7 for Figure 6 Middle, enlarged schematic diagram of point B;

[0048] Figure 8 This is a schematic structural diagram of a semiconductor device in the second embodiment of the present application;

[0049] Figure 9 for Figure 8 Schematic diagram of the positional relationship between the gate, source and drain;

[0050] Figure 10 for Figure 9 Middle, enlarged schematic diagram of point C;

[0051] Figure 11 This is a schematic structural diagram of a semiconductor device in the third embodiment of the present application;

[0052] Figure 12 Output characteristic curves obtained by simulation experiments on semiconductor devices in related technologies and embodiments of the present application;

[0053] Figure 13 This is a flow chart of a method for preparing a semiconductor device in an embodiment of the present application;

[0054] Figure 14 for Figure 5 Schematic diagram of the manufacturing process of the semiconductor device shown;

[0055] Figure 15 for Figure 8 Schematic diagram of the semiconductor device manufacturing process shown.

[0056] Icon: 1-integrated circuit; 2-semiconductor device; 21-substrate; 22-gate; 23-gate dielectric layer; 24-semiconductor layer; 241-first surface; 242-first gap region; 243-second gap region; 244-second surface; 25-source; 26-drain; 261-overlap; 262-gap; 27-first metal intercalation layer; 28-second metal intercalation layer; 29-passivation layer. DETAILED DESCRIPTION

[0057] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0058] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.

[0059] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0060] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0061] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0062] In the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0063] Oxide semiconductor thin-film transistors (TFTs) have high mobility, low preparation cost, large-area uniform film formation, can be prepared at low temperature or even room temperature, and have low off-state current and therefore low static power consumption. Therefore, they have high application value in display driver backplanes, flexible wearable sensor electronics, and thin-film integrated circuits.

[0064] Based on the conductivity type, oxide semiconductor TFTs can be divided into N-type oxide semiconductor TFTs and P-type oxide semiconductor TFTs. Among them, the conductivity of P-type oxide semiconductor TFTs is P-type conductivity, that is, hole conduction, which means that hole current is generated within the semiconductor device 2. The conductivity of N-type oxide semiconductor TFTs is N-type conductivity, that is, electron conduction, which means that electron current is generated within the semiconductor device 2.

[0065] N-type oxide semiconductor TFTs are now comparable to polysilicon TFTs in parameters such as mobility, current switching ratio, and subthreshold swing, and even surpass them in static power consumption, large-area uniformity, and temperature stability. However, to achieve integrated circuits with complex functions (high integration), low power consumption, and high noise tolerance, complementary integration is required. That is, the integrated circuit requires both N-type oxide semiconductor transistors and P-type oxide semiconductor transistors.

[0066] An embodiment of the present application provides an electronic device, which may include a printed circuit board and a chip, wherein the chip is electrically connected to the printed circuit board. The chip includes a packaging substrate and an integrated circuit, and the integrated circuit may be fixed on the packaging substrate. In one example, the integrated circuit may include a semiconductor device, wherein the semiconductor device is a P-type oxide semiconductor TFT. In another example, Figure 1 As shown, the integrated circuit 1 may include two semiconductor devices 2, one of which may be a P-type oxide semiconductor TFT and the other may be an N-type oxide semiconductor TFT. The following description will be made using the P-type oxide semiconductor TFT as an example.

[0067] In related technologies, such as Figure 2 As shown, the semiconductor device 2 may include a substrate 21, a gate 22, a gate dielectric layer 23 and a semiconductor layer 24 stacked in sequence on the substrate 21, and a source 25 and a drain 26 disposed on the semiconductor layer 24. Figure 3 and Figure 4 As shown, there is an overlap 261 between the projection of the gate 22 on the upper surface of the substrate 21 and the projection of the drain 26 on the upper surface of the substrate 21 .

[0068] The material of the semiconductor layer 24 can be SnO or NiO. Here, SnO is taken as an example to illustrate the technical problems existing in the semiconductor device 2 in the related art. On the one hand, Sn element has Sn 2+ and Sn 4+ Two oxidation states, of which Sn 2+ It is metastable. It is difficult to ensure a single Sn in the process of preparing semiconductor device 2. 2+ components, often mixed with Sn 4+SnO has P-type conductivity, while SnO2 has N-type conductivity. This results in a higher inversion electron current in semiconductor device 2 under an inversion gate voltage. On the other hand, SnO has a narrower indirect band gap, for example, 0-0.7 eV. This narrower indirect band gap also results in a higher inversion electron current in a single SnO phase when controlled by the gate field effect.

[0069] As can be seen, the semiconductor device 2 in the related art exhibits a large inversion electron current under an inversion gate voltage, i.e., exhibits bipolarity. When used in an integrated circuit 1, the semiconductor device 2 may not be completely shut down, resulting in high static power consumption, insufficient full-amplitude output, low noise margin, and even inaccurate logic output.

[0070] Based on this, the present invention provides a semiconductor device 2 through some embodiments. The semiconductor device 2 may be a P-type oxide semiconductor TFT.

[0071] Example 1

[0072] A semiconductor device 2, such as Figure 5 and Figure 6 As shown, for the convenience of description, three directions are defined: a first direction (X direction), a second direction (Y direction), and a third direction (Z direction). The X direction represents the length direction of the semiconductor device 2, the Y direction represents the width direction of the semiconductor device 2, and the Z direction represents the thickness direction of the semiconductor device 2. It can be understood that the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0073] like Figure 5 As shown, the semiconductor device 2 may include: a substrate 21, a gate 22, a gate dielectric layer 23, a semiconductor layer 24, a source 25 and a drain 26. The substrate 21 may be a silicon wafer.

[0074] like Figure 5 As shown, the gate 22 may be provided on the substrate 21. The size of the gate 22 along the X direction is smaller than the size of the substrate 21 along the X direction. The material of the gate 22 may be W, Cu, etc.

[0075] like Figure 5 As shown, the gate dielectric layer 23 is disposed on the side of the gate 22 facing away from the substrate 21. That is, the gate 22 is located between the gate dielectric layer 23 and the substrate 21. The size of the gate dielectric layer 23 along the X-direction is larger than the size of the gate 22 along the X-direction. Furthermore, the gate dielectric layer 23 can cover the projection area of ​​the gate 22 on the gate dielectric layer 23. The material of the gate dielectric layer 23 can be Al2O3, SiO2, etc.

[0076] like Figure 5As shown, the semiconductor layer 24 is disposed on a side of the gate dielectric layer 23 facing away from the gate dielectric layer 23. That is, the gate dielectric layer 23 is located between the semiconductor layer 24 and the gate 22. The semiconductor layer 24 has a first surface 241 facing away from the gate 22. The first surface 241 may be the upper surface of the semiconductor layer 24. The dimensions of the semiconductor layer 24 along the X-direction may be the same as those of the gate dielectric layer 23. The dimensions of the semiconductor layer 24 along the X-direction may be larger than the dimensions of the gate 22 along the X-direction. The semiconductor layer 24 may cover the projection of the gate 22 onto the semiconductor layer 24. The material of the semiconductor layer 24 may be SnO, NiO, etc.

[0077] like Figure 5 As shown, the source electrode 25 and the drain electrode 26 are both provided on the semiconductor layer 24. The dimension of the drain electrode 26 along the X-direction is smaller than the dimension of the semiconductor layer 24 along the X-direction, and the dimension of the source electrode 25 along the X-direction is smaller than the dimension of the semiconductor layer 24 along the X-direction. The drain electrode 26 and the source electrode 25 can be made of the same material and provided in the same layer as the source electrode 25. This facilitates the fabrication of the drain electrode 26 and the source electrode 25 in the same process.

[0078] "Same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, followed by a single patterning process using the same mask. Depending on the specific pattern, the same patterning process may include multiple exposure, development, or etching steps, and the specific patterns in the resulting layer structure may be continuous or discontinuous, at varying heights or thicknesses.

[0079] like Figure 5 As shown, a channel may be formed between the source 25 and the drain 26 , and the dimension of the channel along the X direction, that is, the length of the channel, may be adjusted according to design requirements.

[0080] During use of the semiconductor device 2 , the source 25 may be grounded, and the voltage applied to the drain 26 may be a negative voltage.

[0081] Regarding the positional relationship between the first projection of the drain 26 on the first surface 241, the second projection of the gate 22 on the first surface 241, and the third projection of the source 25 on the first surface 241, in a possible embodiment, as shown in FIG. Figure 5 、 Figure 6 and Figure 7 As shown, a gap 262 is provided between a first projection of the drain electrode 26 on the first surface 241 and a second projection of the gate electrode 22 on the first surface 241, and an overlap 261 is provided between a third projection of the source electrode 25 on the first surface 241 and the second projection of the gate electrode 22 on the first surface 241. It will be understood that the first projection of the drain electrode 26 on the first surface 241 is a planar area, and the second projection of the gate electrode 22 on the first surface 241 is also a planar area.

[0082] When the semiconductor device 2 is under an inversion gate voltage, that is, when the voltage of the gate 22 is higher than the electron threshold voltage, inversion electrons will accumulate within the projected area of ​​the drain 26 on the semiconductor layer 24. A gap 262 exists between the first projection of the drain 26 on the first surface 241 of the semiconductor layer 24 and the second projection of the gate 22 on the first surface 241. In other words, a first gap region 242 exists in the semiconductor layer 24. This first gap region 242 is located between the projected area of ​​the drain 26 on the semiconductor layer 24 and the projected area of ​​the gate 22 on the semiconductor layer 24. This first gap region 242 does not overlap with the projected area of ​​the drain 26 on the semiconductor layer 24, nor does it overlap with the projected area of ​​the gate 22 on the semiconductor layer 24. It should be understood that the projected area of ​​the drain 26 on the semiconductor layer 24 is a three-dimensional region, which can refer to the first projection of the drain 26 on the first surface 241, the projection of the drain 26 on the second surface 244 opposite the first surface 241, and the area between the two. Similarly, the projection area of ​​the gate 22 on the semiconductor layer 24 is a three-dimensional region, which can refer to the first projection of the gate 22 on the first surface 241, the projection of the gate 22 on the second surface 244 opposite the first surface 241, and the area between the two. Therefore, the first gap area 242 can weaken the control of the gate 22 on the semiconductor layer 24, thereby suppressing the accumulation of inversion electrons, and thus facilitating the depletion of inversion electrons within the projection area of ​​the drain 26 on the semiconductor layer 24, thereby reducing the inversion electron current and effectively shutting off the semiconductor device 2 under the inversion gate voltage. This can reduce the static power consumption of the semiconductor device 2, achieve full-amplitude output, improve the noise margin, and achieve accurate logic output.

[0083] Furthermore, the provision of the first gap region 242 has a minimal impact on the hole on-state current. Specifically, the hole on-state current remains unchanged, or decreases slightly but by a smaller amount, thereby improving the current switching ratio. Furthermore, the provision of the first gap region 242 has a minimal impact on mobility, threshold voltage, and subthreshold swing. Furthermore, the first gap region 242 can also prevent excessive series resistance when gate-controlling the P-type conductive on-state.

[0084] Furthermore, when designing the semiconductor device 2, in one example, the position of the gate 22 along the X direction can be kept unchanged, and the drain 26 can be moved in the direction of the X direction, that is, toward Figure X In another example, the position of the drain 26 along the X direction can be kept unchanged, and the length of the gate 22 along the X direction can be reduced.

[0085] Example 2

[0086] Regarding the positional relationship between the first projection of the drain 26 on the first surface 241, the second projection of the gate 22 on the first surface 241, and the third projection of the source 25 on the first surface 241, in another possible embodiment, as shown in FIG. Figure 8 、 Figure 9 and Figure 10 As shown, a gap 262 exists between the first projection of the drain electrode 26 on the first surface 241 and the second projection of the gate electrode 22 on the first surface 241, and a gap 262 exists between the third projection of the source electrode 25 on the first surface 241 and the second projection. In other words, a second gap region 243 also exists in the semiconductor layer 24. This second gap region 243 is located between the projection of the source electrode 25 on the semiconductor layer 24 and the projection of the gate electrode 22 on the semiconductor layer 24. The second gap region 243 does not overlap with the projection of the source electrode 25 on the semiconductor layer 24, nor does it overlap with the projection of the gate electrode 22 on the semiconductor layer 24. It should be understood that the projection of the source electrode 25 on the semiconductor layer 24 is a three-dimensional region, which can refer to the third projection of the source electrode 25 on the first surface 241, the projection of the source electrode 25 on the second surface 244 opposite the first surface 241, and the region therebetween. Therefore, the second gap region 243 can weaken the control of the gate 22 on the semiconductor layer 24, thereby suppressing the aggregation of inversion electrons, and further facilitating the depletion of inversion electrons in the projection area of ​​the drain 26 in the semiconductor layer 24, thereby reducing the inversion electron current, and enabling the semiconductor device 2 to be effectively shut down under the inversion gate voltage.

[0087] In one possible implementation, Figure 5 As shown, the semiconductor device 2 may further include a first metal intercalation layer 27 and a second metal intercalation layer 28. The first metal intercalation layer 27 is located between the drain electrode 26 and the semiconductor layer 24. The second metal intercalation layer 28 is located between the source electrode 25 and the semiconductor layer 24. Thus, when the drain electrode 26 is negatively biased, the semiconductor layer 24, the first metal intercalation layer 27, and the drain electrode 26 may form a Schottky reverse contact. Furthermore, the interface between the first metal intercalation layer 27 and the semiconductor layer 24 may form a barrier region. This facilitates the depletion of inversion electrons within the projected area of ​​the drain electrode 26 on the semiconductor layer 24, thereby reducing the inversion electron current and enabling the semiconductor device 2 to be effectively shut down under an inversion gate voltage. In this way, the semiconductor layer 24, the second metal intercalation layer 28 and the source electrode 25 can form an ohmic contact, that is, the interface between the semiconductor layer 24 and the second metal intercalation layer 28 and the interface between the second metal intercalation layer 28 and the source electrode 25 has no potential barrier, thereby allowing the holes in the projected area of ​​the source electrode 25 in the semiconductor layer 24 to be injected into the barrier-free interface, thereby achieving a higher hole current.

[0088] Regarding the coverage of the first metal intercalation layer 27 and the drain electrode 26, in one example, as shown in FIG. Figure 5As shown, the dimension of the first metal intercalation layer 27 along the X-direction is greater than the dimension of the drain electrode 26 along the X-direction. The projection range of the first metal intercalation layer 27 on the first surface 241 is greater than the first projection range of the drain electrode 26 on the first surface 241. That is, the first projection range of the drain electrode 26 on the first surface 241 of the semiconductor layer 24 is located within the projection range of the first metal intercalation layer 27 on the first surface 241. This can further enhance the depletion of inversion electrons within the coverage area of ​​the drain electrode 26 in the semiconductor layer 24, thereby further reducing the inversion electron current.

[0089] In another example, the size of the first metal insertion layer 27 along the X-direction is the same as the size of the drain electrode 26 along the X-direction. In addition, the projection of the first metal insertion layer 27 on the first surface 241 of the semiconductor layer 24 is the same as the first projection of the drain electrode 26 on the first surface 241, that is, they are the same size and position.

[0090] In another example, the dimension of the first metal insertion layer 27 along the X direction is smaller than the dimension of the drain electrode 26 along the X direction. That is, the projection of the first metal insertion layer 27 on the first surface 241 of the semiconductor layer 24 partially overlaps with the first projection of the drain electrode 26 on the first surface 241 .

[0091] Regarding the coverage of the second metal insertion layer 28 and the source 25, in one example, as Figure 5 As shown, the size of the second metal intercalation layer 28 along the X-direction is larger than the size of the source electrode 25 along the X-direction. The projection range of the second metal intercalation layer 28 on the first surface 241 is larger than the range of the first projection of the source electrode 25 on the first surface 241. That is, the first projection of the source electrode 25 on the first surface 241 of the semiconductor layer 24 is located within the projection range of the second metal intercalation layer 28 on the first surface 241. This can further enhance the depletion of inversion electrons within the coverage area of ​​the source electrode 25 in the semiconductor layer 24, thereby further reducing the inversion electron current.

[0092] In another example, the size of the second metal insertion layer 28 along the X-direction is the same as the size of the source electrode 25 along the X-direction. In addition, the projection of the second metal insertion layer 28 on the first surface 241 of the semiconductor layer 24 is the same as the first projection of the source electrode 25 on the first surface 241, that is, they are the same size and position.

[0093] In another example, the dimension of the second metal insertion layer 28 along the X direction is smaller than the dimension of the source electrode 25 along the X direction. That is, the projection of the second metal insertion layer 28 on the first surface 241 of the semiconductor layer 24 partially overlaps with the first projection of the source electrode 25 on the first surface 241 .

[0094] Moreover, if Figure 5As shown, the first metal intercalation layer 27 and the second metal intercalation layer 28 are made of the same material. Therefore, the first metal intercalation layer 27 and the second metal intercalation layer 28 can be manufactured in the same process, and the first metal intercalation layer 27 and the second metal intercalation layer 28 are manufactured through a single process, which simplifies the process flow.

[0095] Example 3

[0096] The difference from the above embodiment is that, Figure 11 As shown, the semiconductor device 2 only includes the first metal insertion layer 27 but does not include the second metal insertion layer 28 .

[0097] Furthermore, the materials of both the first metal intercalation layer 27 and the second metal intercalation layer 28 include high-work-function metals. A high-work-function metal refers to a metal with a relatively high work function, specifically a metal with a relatively high minimum energy required to move electrons from the interior of a solid to the surface of the solid. Exemplarily, a high-work-function metal may refer to a metal with a work function greater than or equal to 5, such as Be, Co, and P1. When both the first metal intercalation layer 27 and the second metal intercalation layer 28 include high-work-function metals, the hole current can be further increased and the inversion electron current can be reduced.

[0098] like Figure 5 As shown, the semiconductor device 2 may further include a passivation layer 29. The passivation layer 29 may include three parts. The first part of the passivation layer 29 is provided on the source electrode 25, and the second part of the passivation layer 29 is provided on the drain electrode 26. The third part of the passivation layer 29 is provided on the semiconductor layer 24 and is located in the channel between the source electrode 25 and the drain electrode 26. The material of the passivation layer 29 may be SiN x . Where X can be greater than 0 and less than or equal to 10.

[0099] Example 4

[0100] This embodiment is a test example. Figure 5 The semiconductor device 2 shown is subjected to testing.

[0101] There is a gap 262 between the first projection of the drain 26 on the first surface 241 and the second projection of the gate 22 on the first surface 241, and there is an overlap 261 between the third projection of the source 25 on the first surface 241 and the second projection of the gate 22 on the first surface 241. Taking the case where the dimensions of the gap 262 along the X direction are 200nm, 600nm and -1μm respectively, the source 25 is grounded, the drain 26 voltage is -3.3V, and the gate 22 voltage range is -3.3 to 3.3V as an example, the semiconductor device 2 is tested. Among them, when the gap 262 is -1μm, it indicates that the dimension of the overlap 261 along the X direction between the first projection of the drain 26 on the first surface 241 and the first projection of the gate 22 on the first surface 241 is 1μm. In the process of manufacturing the semiconductor device 2, after the passivation layer 29 is manufactured, it is annealed at 350℃ and N2 atmosphere for 30 minutes, and the output characteristics of the semiconductor device 2 are tested, and the following are obtained. Figure 12 The transfer characteristic curve is shown. Figure 12 In the figure, the abscissa represents gate voltage, and the ordinate represents current per unit width. Furthermore, the left side of each output characteristic curve represents the hole on-state current, and the right side represents the inversion electron current. Curve a1 shows the output characteristic curve of semiconductor device 2 when gap 262 is -1 μm; curve a2 shows the output characteristic curve of semiconductor device 2 when gap 262 is 200 nm; and curve a3 shows the output characteristic curve of semiconductor device 2 when gap 262 is 600 nm.

[0102] like Figure 12 As shown in FIG. 1 , curve a1 shows that when the dimension of the gap 262 along the X-direction is −1 μm, that is, when the dimension of the overlap 261 between the first projection of the drain 26 on the first surface 241 and the first projection of the gate 22 on the first surface 241 along the X-direction is 1 μm, the inversion electron current at a gate voltage of −3.3 V is similar to the hole on-state current corresponding to a gate voltage of 3.3 V. When the gate voltage is greater than 0 V, the electron current rises rapidly, which results in excessive power consumption of the integrated circuit 1.

[0103] By comparing curve a1 and curve a2, it can be seen that when the size of the gap 262 along the X direction is 200 nm, the hole on-state current decreases by 1.7 times compared with the size of the gap 262 along the X direction of -1 μm, and the inverse electron current decreases by about two orders of magnitude compared with the size of the gap 262 along the X direction of -1 μm, thereby achieving the purpose of reducing the inverse electron current with little impact on the hole on-state current.

[0104] Comparing curves a1 and a3, we can see that if gap 262 is further increased, for example, to 600 nm, the hole on-state current decreases by 3.5 times compared to when gap 262 has a dimension of -1 μm along the X-axis, and the inversion electron current decreases further. Furthermore, because gate 22's ability to control semiconductor layer 24 decreases, the resistance in first gap region 242 increases, resulting in contact resistance at drain 26.

[0105] Example 5

[0106] like Figure 12 As shown, this embodiment also provides a method for preparing a semiconductor device 2, the method comprising:

[0107] S31, provided Figure 14 The substrate 21 is shown.

[0108] As the substrate 21 , a silicon wafer can be used.

[0109] S32 , forming a gate 22 on the substrate 21 .

[0110] like Figure 14 As shown, the gate 22 pattern can be exposed on the surface of the substrate 21 using an electron beam exposure process, and the gate metal can be grown by magnetron sputtering, and then stripped to form the gate 22. The gate metal can be W, Cu, etc.

[0111] S33 , forming a gate dielectric layer 23 on a side of the gate 22 facing away from the substrate 21 .

[0112] like Figure 14 As shown, the gate dielectric layer 23 may be grown using atomic layer deposition equipment.

[0113] S34 , forming a semiconductor layer 24 on the gate dielectric layer 23 .

[0114] like Figure 14 As shown, a semiconductor layer metal can be grown by magnetron sputtering and annealed in air at 225° C. to have the characteristics of a P-type semiconductor, thereby forming a semiconductor layer 24 . The semiconductor layer 24 has a first surface 241 facing away from the gate 22 .

[0115] S35 , forming a first metal insertion layer 27 and a second metal insertion layer 28 on the gate dielectric layer 23 .

[0116] like Figure 14 As shown, the source electrode 25 and the drain electrode 26 can be patterned using an electron beam exposure process. A high work function metal can be grown as the first metal intercalation layer 27 and the second metal intercalation layer 28 using magnetron sputtering.

[0117] S36 , forming a drain electrode 26 on the first metal insertion layer 27 and a source electrode 25 on the second metal insertion layer 28 .

[0118] Among them, when the preparation method of the semiconductor device 2 of this embodiment is applied to Figure 5 When the semiconductor device 2 shown in FIG. Figure 14 As shown, there is a gap 262 between the first projection of the drain 26 on the first surface 241 and the second projection of the gate 22 on the first surface 241, and there is an overlap 261 between the third projection of the source 25 on the first surface 241 and the second projection of the gate 22 on the first surface 241. When the manufacturing method of the semiconductor device 2 of this embodiment is applied to Figure 5 When the semiconductor device 2 shown in FIG. Figure 15 As shown, a gap 262 is provided between a first projection of the drain electrode 26 on the first surface 241 and a second projection of the gate electrode 22 on the first surface 241, and a gap 262 is provided between a third projection of the source electrode 25 on the first surface 241 and the second projection of the gate electrode 22 on the first surface 241. The source electrode 25 and the drain electrode 26 can be formed by growing W by magnetron sputtering and then performing lift-off.

[0119] S37 , forming a passivation layer 29 .

[0120] Can be grown using PECVD (plasma enhanced chemical vapor deposition) Figure 14 and Figure 15 The passivation layer 29 is shown. The electrode pinning area can be exposed using UV lithography, and the passivation layer 29 can be etched away using dry etching. In an N2 atmosphere, the semi-finished semiconductor device 2 is annealed at 350°C to obtain the completed semiconductor device 2.

[0121] In the embodiment of the present application, when the semiconductor device 2 is under an inversion gate voltage, that is, when the voltage of the gate 22 is higher than the electron threshold voltage, the inversion electrons in the projection area of ​​the drain 26 in the semiconductor layer 24 will be gathered. Figure 13As shown, a gap 262 exists between the first projection of the drain electrode 26 on the first surface 241 of the semiconductor layer 24 and the second projection of the gate electrode 22 on the first surface 241. In other words, a first gap region 242 exists in the semiconductor layer 24. This first gap region 242 is located between the projection of the drain electrode 26 on the semiconductor layer 24 and the projection of the gate electrode 22 on the semiconductor layer 24. The first gap region 242 does not overlap with the projection of the drain electrode 26 on the semiconductor layer 24, nor does it overlap with the projection of the gate electrode 22 on the semiconductor layer 24. Therefore, the first gap region 242 can weaken the control of the gate electrode 22 on the semiconductor layer 24, thereby suppressing the accumulation of inversion electrons and facilitating the depletion of inversion electrons within the projection of the drain electrode 26 on the semiconductor layer 24. This can reduce the inversion electron current, thereby enabling the semiconductor device 2 to be effectively shut down under an inversion gate voltage.

[0122] Furthermore, the provision of the first gap region 242 has minimal impact on the hole on-state current. Specifically, the hole on-state current remains unchanged, or decreases slightly, thereby improving the current switching ratio. Furthermore, the provision of the first gap region 242 also has minimal impact on mobility, threshold voltage, and subthreshold swing.

[0123] Furthermore, a barrier region can be formed between the first metal intercalation layer 27 and the semiconductor layer 24. When the drain electrode 26 is negatively biased, the semiconductor layer 24, the first metal intercalation layer 27, and the drain electrode 26 can form a Schottky reverse contact, thereby facilitating the depletion of inversion electrons in the region covered by the drain electrode 26 in the semiconductor layer 24, thereby reducing the inversion electron current, thereby enabling the semiconductor device 2 to be effectively shut off under an inversion gate voltage. Furthermore, the semiconductor layer 24, the second metal intercalation layer 28, and the source electrode 25 can form an ohmic contact, that is, holes in the region covered by the source electrode 25 in the semiconductor layer 24 can be injected without a barrier, thereby achieving a higher hole current.

[0124] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made by those skilled in the art that fall within the spirit and principles of the present invention and do not require creative effort are intended to be within the scope of protection of the present invention.

Claims

1. A device for suppressing inversion electron current in a p-type oxide semiconductor thin film transistor, comprising a substrate, a gate, a gate dielectric layer, and a semiconductor layer arranged sequentially from bottom to top; The semiconductor layer has a first surface facing away from the gate; and a source electrode and a drain electrode, which are disposed on the semiconductor layer; Its characteristics are: There is a gap between a first projection of the drain electrode formed on the first surface and a second projection of the gate electrode on the first surface, and both the first projection and the second projection are orthographic projections.

2. The device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to claim 1, wherein: There is a gap between the third projection and the second projection of the source electrode on the first surface, and the third projection is an orthographic projection.

3. A device for suppressing inversion electron current in a p-type oxide semiconductor thin film transistor according to claim 1 or 2, characterized in that: The invention also includes a first metal insertion layer, which is located between the drain electrode and the semiconductor layer.

4. The device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to claim 3, wherein: The first projection is located within the projection range of the first metal insertion layer on the first surface.

5. The device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to claim 4, wherein: The invention also includes a second metal insertion layer, which is located between the source electrode and the semiconductor layer.

6. The device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to claim 5, wherein: The first metal intercalation layer and the second metal intercalation layer are made of the same material and are manufactured in the same process. The first metal intercalation layer and the second metal intercalation layer are manufactured through one process, and the process flow is simple.

7. The device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to claim 6, wherein: The materials of the first metal intercalation layer and the second metal intercalation layer both include high work function metals.

8. A device for suppressing inversion electron current in a p-type oxide semiconductor thin film transistor according to claim 1 or 2, characterized in that: It also includes a passivation layer, wherein a portion of the passivation layer is arranged on the source electrode, a portion is arranged on the drain electrode, and another portion is arranged on the semiconductor layer and is located in the channel between the source electrode and the drain electrode.

9. An integrated circuit, characterized in that: The invention comprises a circuit board and a device for suppressing inverse electron current of a p-type oxide semiconductor thin film transistor according to any one of claims 1 to 8.

10. A chip, characterized in that: The invention comprises a packaging substrate and the integrated circuit according to claim 9, wherein the integrated circuit is fixed on the packaging substrate.

11. An electronic device, characterized in that: The device comprises a printed circuit board and the chip according to claim 10, wherein the chip is electrically connected to the printed circuit board.

12. A method for preparing a device for suppressing inversion electron current of a p-type oxide semiconductor thin film transistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: forming a gate on the substrate; forming a gate dielectric layer on a side of the gate facing away from the substrate; A semiconductor layer is formed on the gate dielectric layer, and a source and a drain are formed on a first surface of the semiconductor layer away from the gate, wherein a gap exists between a first projection of the drain on the first surface and a second projection of the gate on the first surface.

13. The preparation method according to claim 12, characterized in that: After the step of forming a semiconductor layer on the gate dielectric layer, the preparation method further includes: forming a first metal intercalation layer on the gate dielectric layer; and forming a source and a drain on the semiconductor layer, including: forming a source on the semiconductor layer; and forming a drain on the first metal intercalation layer.

14. The preparation method according to claim 12, characterized in that: After the step of forming a semiconductor layer on the gate dielectric layer, the preparation method further comprises: forming a second metal insertion layer on the gate dielectric layer; The step of forming a source electrode on the semiconductor layer comprises: A source electrode is formed on the second metal insertion layer.

15. The preparation method according to any one of claims 12 to 14, characterized in that: The method further includes forming a passivation layer on the source electrode, the drain electrode, and the semiconductor layer in the channel between the source electrode and the drain electrode.

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