Chip post-simulation verification acceleration method, system and device and storage medium

Abstract

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip development, and relates to a chip post-simulation verification acceleration method, system, device and storage medium. BACKGROUND

[0002] With the continuous development of integrated circuit technology, the scale and design complexity of chips have increased dramatically, resulting in longer time spent on chip design. In the design process of large-scale integrated circuits, simulation and verification is an important link, which can be divided into pre-simulation and post-simulation. Pre-simulation is the simulation of RTL, and the goal is to analyze the correctness of the logical relationship of the circuit, and the simulation speed is fast. Post-simulation is the simulation of gate-level netlist, which takes into account the connection between the circuit and the delay unit. The result of the simulation directly affects the accuracy of power consumption evaluation and voltage drop analysis.

[0003] Traditional post-simulation is to put the entire gate-level netlist into an EDA environment for simulation. When simulating, a standard delay format file is read in, and the correctness of post-simulation is judged by applying excitation and monitoring the output and internal signals of the netlist. Although this method can well handle small and medium-sized circuits, the gate-level netlist of large-scale chips contains a large number of logic gates, complex interconnection structures and delay parameters of logic gates, resulting in extremely long simulation time.

[0004] Therefore, in the existing chip post-simulation verification method, there is a problem of low verification efficiency.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the application. SUMMARY

[0006] To have a basic understanding of some aspects of the disclosed embodiments, the following brief overview is given. The overview is not an extensive review of all of the features of the embodiments, nor is it intended to identify key / critical elements of the embodiments or delineate the scope of the embodiments. The sole purpose of the overview is to present some concepts of the disclosed embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0007] The chip post-simulation verification acceleration method, system, device and storage medium provided by the embodiments of the present disclosure solve the problem of low verification efficiency in the existing chip post-simulation verification method.

[0008] The chip post-simulation verification acceleration method in the embodiments of the present disclosure comprises:

[0009] Collecting multi-dimensional data of a large-scale chip;

[0010] Collecting all module names of a given chip, and confirming and verifying the names of control paths and data paths unrelated to the function as redundant module RTL through pre-simulation analysis and functional specification;

[0011] The mapping relationship between the redundancy module RTL and the corresponding gate-level netlist is established to ensure that the interfaces are completely consistent before and after replacement, and an automatic script is designed to identify and process the parameterized module;

[0012] After the simulation verification environment is built, the gate-level netlist and RTL are loaded as simulation file lists and the SDF file is imported, the test cases are extracted from the pre-simulation environment and the simulation is run;

[0013] The consistency of the output responses before and after replacement is verified, the time delay changes of the critical path are analyzed, the dynamic and static power consumptions of each functional module before and after replacement are calculated, and the simulation verification results are generated.

[0014] In some embodiments, the above-mentioned collection of multi-dimensional data of large-scale chips includes:

[0015] The complete RTL code is extracted from the code repository of the chip design project;

[0016] The RTL code is processed using chip design tools to generate the corresponding gate-level netlist, and the Synopsys Design Compiler tool is used to set the target library and comprehensive constraints, and then run the comprehensive command to obtain the gate-level netlist file saved in standard format;

[0017] The SDF file and the corresponding gate-level netlist file are stored in association, wherein the SDF file records the delay information of each logic gate in the gate-level netlist under different working conditions;

[0018] The test case set used in the pre-simulation stage of the chip is collected and arranged, and the test cases related to different functional modules are marked.

[0019] In some embodiments, the above-mentioned collection of all module names of a given chip includes:

[0020] According to the functional specification of the chip, the core functional module set related to the current verification function is defined, the control signals and data streams participating in the core path are identified by analyzing the pre-simulation waveform, the modules unrelated to the core path are marked, and the pre-simulation results are combined to traverse all module names. For modules not included in the core functional module set, further analyze the control path and data path of the module, if the control signal of the module does not participate in the control logic of the current verification function, and the data path of the module does not provide valid data for the current verification function, the corresponding module is marked as a candidate redundant module;

[0021] The redundant module annotation data in the historical chip design project is used as a training set, the functional description keywords of the module, the connection relationship with the core module, and the signal interaction frequency characteristics are selected, and a support vector machine or a random forest classification model is trained to predict the candidate redundant module and output the final redundant module RTL list.

[0022] In some embodiments, the above establishes the mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensures that the interfaces before and after replacement are completely consistent, and designs an automatic script to identify and process parameterized modules, including:

[0023] An automatic script based on rule matching is developed using Python language, and the mapping relationship is established by comparing the port number, name, bit width, and direction attribute of the RTL module and the gate-level netlist module. For modules with the same function but different names, the mapping table is established to associate them.

[0024] For parameterized modules, the automatic script uses regular expressions to match the parameter passing part in the module instantiation statement, extracts the parameter values and records them. In the replacement process, the parameter values of the corresponding module in the RTL code are adjusted according to the instantiation of the parameterized module in the gate-level netlist, avoiding hierarchical and naming conflicts caused by inconsistent parameters. The nested call of the parameterized module is checked, and each level of parameter passing is processed recursively to ensure the accuracy of the entire replacement process.

[0025] According to the SDF file, the critical path delay data is extracted, and the corresponding delay unit is inserted at the interface of the RTL and the gate-level netlist.

[0026] In some embodiments, the above extracts the critical path delay data from the SDF file and inserts the corresponding delay unit at the interface of the RTL and the gate-level netlist, including:

[0027] The delay information of the redundant module interface signal in the SDF file is analyzed, and the delay time that needs to be compensated is calculated;

[0028] According to the delay time, select the appropriate delay unit type, and instantiate at the interface;

[0029] The timing adapter performs timing constraints on the inserted delay unit, sets the clock offset, setup time, and hold time constraints to ensure the timing matching between the RTL and the gate-level netlist.

[0030] In some embodiments, the above builds a post-simulation verification environment, loads the gate-level netlist and RTL as simulation file lists and imports the SDF file, extracts the test cases from the pre-simulation environment and runs the simulation, including:

[0031] Based on the pre-simulation verification platform creation project, configure the simulation environment parameters, including the simulator type, simulation time accuracy, memory allocation;

[0032] Through the script automation import gate-level netlist and RTL code as simulation file list, and import SDF file into the simulation environment, ensure that the simulator can read the delay information of the gate-level netlist;

[0033] Extract the test cases from the pre-simulation environment, for the test cases written based on RTL code, according to the port name and signal definition of the gate-level netlist, modify the excitation signal and monitoring signal in the test case, extend the test case, and increase the monitoring of the interface signal between RTL and gate-level netlist;

[0034] Use the command line interface of the simulation platform, start the simulation task through the script, set breakpoints and monitoring points during the simulation process, real-time monitor the simulation state and the change of key signals, and record the simulation output results in the log file, so as to analyze the subsequent result comparison module.

[0035] In some embodiments, the consistency of the output response before and after the above verification replacement is analyzed, the time delay change of the critical path is analyzed, and the dynamic power consumption and static power consumption of each functional module before and after the replacement are calculated, including:

[0036] The comparison program automatically reads the simulation output files before and after the replacement, verifies the consistency of the output response by combining string matching and numerical calculation;

[0037] Combine the key path delay information recorded in the SDF file and the timing data in the simulation results to analyze the time delay change of the critical path;

[0038] Call the power consumption analysis tool to perform dynamic power consumption analysis on the simulation results before and after the replacement respectively, obtain the dynamic power consumption data of the target functional module, calculate the power consumption difference, and perform statistical analysis, compare the power consumption proportion change of different modules, and evaluate the influence of gate-level netlist replacement on chip power consumption.

[0039] The chip post-simulation verification acceleration system in the embodiment of the disclosure comprises:

[0040] A multi-dimensional data collection module is used to collect multi-dimensional data of a large-scale chip;

[0041] A redundant module determination module is used to collect all module names of a given chip, and confirm and verify the names of control paths and data paths irrelevant to functions as redundant module RTL through pre-simulation analysis and function specification;

[0042] The gate-level netlist replacement module is configured to establish a mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensure that the interfaces are completely consistent before and after replacement, and design an automatic script to identify and process the parameterized module.

[0043] The post-simulation verification module is configured to build a post-simulation verification environment, load the gate-level netlist and the RTL as a simulation file list and import an SDF file, extract test cases from the pre-simulation environment and run simulation.

[0044] The result comparison module is configured to verify the consistency of the output responses before and after replacement, analyze the delay changes of the critical path, calculate the dynamic power consumption and static power consumption of each functional module before and after replacement, and generate simulation verification results.

[0045] The electronic device provided in the embodiments of the present disclosure includes at least one processor;

[0046] and a memory in communication connection with the at least one processor;

[0047] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip post-simulation verification acceleration method.

[0048] The storage medium provided in the embodiments of the present disclosure stores program instructions, and the program instructions execute the chip post-simulation verification acceleration method when running.

[0049] The chip post-simulation verification acceleration method, system, device and storage medium provided in the embodiments of the present disclosure can achieve the following technical effects:

[0050] The present disclosure constructs a hybrid simulation model, replaces part of the gate-level netlist unrelated to the current simulation function with an RTL, thereby reducing the actual simulation scale of the chip and significantly shortening the long post-simulation time of the large-scale integrated circuit, and effectively improving the simulation efficiency. By replacing the gate-level netlist with the RTL, the chip simulation time can be greatly shortened, and the larger the chip scale and the more the redundant modules, the more obvious the acceleration effect. In addition, fast simulation verification makes chip design iteration more efficient, shortens the chip design cycle, accelerates the process from product design to mass production, and occupies the market.

[0051] The foregoing general description and the following description are merely exemplary and explanatory, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0052] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute a limitation on the embodiments, elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute a proportional limitation, and wherein:

[0053] Figure 1 is a flowchart of a chip post-simulation verification acceleration method provided by an embodiment of the present disclosure.

[0054] Figure 2 is a flowchart of another chip post-simulation verification acceleration method provided by an embodiment of the present disclosure.

[0055] Figure 3 is a structural diagram of a chip post-simulation verification acceleration system provided by an embodiment of the present disclosure.

[0056] Figure 4 is a structural diagram of a chip post-simulation verification acceleration device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to facilitate the drawings.

[0058] The terms "first", "second", and the like in the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0059] Unless otherwise specified, the term "a plurality of" means two or more.

[0060] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B represents: A or B.

[0061] The term "and / or" is a description of the association relationship between the objects, which means that there can be three relationships. For example, A and / or B means: A or B, or, A and B, the three relationships.

[0062] The term "corresponding" can refer to an association relationship or a binding relationship. A and B correspond to each other means that A and B have an association relationship or a binding relationship.

[0063] The chip simulation verification acceleration method, device, equipment and storage medium provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0064] Figure 1 is a flowchart of a chip post-simulation verification acceleration method provided by an embodiment of the disclosure.

[0065] As shown in Figure 1 , the chip post-simulation verification acceleration method can include:

[0066] S101, collecting multi-dimensional data of a large-scale chip;

[0067] S102, collecting all module names of a given chip, confirming and verifying the names of control paths and data paths irrelevant to the function as redundant module RTL through pre-simulation analysis and functional specification;

[0068] S103, establishing a mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensuring that the interfaces before and after replacement are completely consistent, and designing an automatic script to identify and process parameterized modules;

[0069] S104, building a post-simulation verification environment, loading the gate-level netlist and RTL as a simulation file list and importing an SDF file, extracting test cases from the pre-simulation environment and running the simulation;

[0070] S105, verifying the consistency of the output responses before and after replacement, analyzing the time delay changes of the critical path, calculating the dynamic and static power consumptions of each functional module before and after replacement, and generating simulation verification results.

[0071] In some embodiments, the above-mentioned collection of multi-dimensional data of a large-scale chip includes:

[0072] extracting complete RTL code from the code repository of a chip design project;

[0073] using chip design tools to process the sorted RTL code to generate corresponding gate-level netlists, using the Synopsys Design Compiler tool, setting the target library and synthesis constraints, running the synthesis command, and obtaining the gate-level netlist file saved in a standard format;

[0074] store the SDF file and the corresponding gate-level netlist file in association, wherein the SDF file records the delay information of each logic gate in the gate-level netlist under different working conditions;

[0075] collect and sort the test case set used in the pre-simulation stage of the chip, classify and mark the test cases related to different functional modules.

[0076] In some embodiments, the above-mentioned collection of all module names of a given chip, confirmation and verification of the names of control paths and data paths irrelevant to the function as redundant module RTL through pre-simulation analysis and functional specification includes:

[0077] According to the functional specification of the chip, a set of core function modules related to the current verification function is defined, the control signals and data streams participating in the core path are identified by analyzing the pre-simulation waveform, the modules unrelated to the core path are marked, and all module names are traversed in combination with the pre-simulation results. For modules not included in the set of core function modules, further analyze the control path and data path of the module. If the control signal of the module does not participate in the control logic of the current verification function, and its data path does not provide valid data for the current verification function, the corresponding module is marked as a candidate redundant module;

[0078] Use the redundant module annotation data in the historical chip design project as the training set, select the functional description keywords of the module, the connection relationship with the core module, and the signal interaction frequency characteristics, train the support vector machine or random forest classification model to predict the candidate redundant module, and output the final redundant module RTL list.

[0079] In some embodiments, the above establishes the mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensures that the interfaces before and after replacement are completely consistent, and designs an automatic script to identify and process parameterized modules, including:

[0080] An automatic script based on rule matching is developed using Python language, and the mapping relationship is established by comparing the port number, name, bit width, and direction attribute of the RTL module and the gate-level netlist module. For modules with the same function but different names, the mapping table is established to associate them;

[0081] For parameterized modules, the automatic script uses regular expression to match the parameter passing part in the module instantiation statement, extracts the parameter values and records them. In the replacement process, the parameter values of the corresponding module in the RTL code are adjusted according to the instantiation of the parameterized module in the gate-level netlist, to avoid hierarchical and naming conflicts caused by inconsistent parameters. The nested call condition of the parameterized module is checked, and each level of parameter passing is processed recursively to ensure the accuracy of the entire replacement process;

[0082] According to the SDF file, the key path delay data is extracted, and the corresponding delay unit is inserted at the interface of the RTL and the gate-level netlist.

[0083] In some embodiments, the above according to the SDF file extracts the key path delay data, and inserts the corresponding delay unit at the interface of the RTL and the gate-level netlist, including:

[0084] The delay information of the redundant module interface signal in the SDF file is analyzed, and the delay time that needs to be compensated is calculated;

[0085] According to the delay time, select the appropriate delay unit type, and instantiate at the interface;

[0086] The timing adapter performs timing constraints on the inserted delay cells, sets clock offset, setup time, and hold time constraints to ensure timing matching between the RTL and the gate-level netlist.

[0087] In some embodiments, the post-implementation simulation verification environment loads the gate-level netlist and the RTL as simulation file lists and imports the SDF file, extracts test cases from the pre-simulation environment, and runs the simulation, including:

[0088] Based on the pre-simulation verification platform, create a project engineering, configure simulation environment parameters, including simulator type, simulation time precision, memory allocation;

[0089] Automatically import gate-level netlist and RTL code as simulation file lists through scripts, and import SDF file into simulation environment to ensure that the simulator can read the delay information of the gate-level netlist;

[0090] Extract test cases from the pre-simulation environment, for test cases written based on RTL code, modify the excitation signals and monitoring signals in the test cases according to the port names and signal definitions of the gate-level netlist, extend the test cases, and increase the monitoring of the interface signals of the RTL and the gate-level netlist;

[0091] Use the command line interface of the simulation platform to start the simulation task through scripts, set breakpoints and monitoring points during simulation, monitor the simulation state and changes of key signals in real time, and record the simulation output results in log files for subsequent result comparison module analysis.

[0092] In some embodiments, the above-mentioned verification replaces the consistency of the output response before and after, analyzes the delay change of the critical path, calculates the dynamic power consumption and static power consumption of each functional module before and after the replacement, including:

[0093] The comparison program automatically reads the simulation output files before and after the replacement, uses a combination of string matching and numerical calculation to verify the consistency of the output response;

[0094] Combine the critical path delay information recorded in the SDF file and the timing data in the simulation results to analyze the delay change of the critical path;

[0095] Call the power consumption analysis tool to perform dynamic power consumption analysis on the simulation results before and after the replacement, obtain the dynamic power consumption data of the target functional module, calculate the power consumption difference, and perform statistical analysis, compare the power consumption proportion changes of different modules, and evaluate the impact of gate-level netlist replacement on chip power consumption.

[0096] It can be seen that, for multi-dimensional data collection, comprehensive collection of various data of large-scale chips is the basis for subsequent simulation. RTL code describes the logic function of the chip in detail. The gate-level netlist is the conversion of RTL code into specific logic gate connection relationship, which reflects the underlying circuit structure of the chip. The standard delay format SDF file records the delay information of each logic gate in the gate-level netlist. Collect the module name of the gate-level netlist in the given chip that is irrelevant to the current function to locate the redundant design module.

[0097] For determining the redundant module, collect all module names of the given chip, and confirm and verify the names of the control path and data path irrelevant to the function through pre-simulation analysis and functional specification. Artificial verification confirms the position of the redundant module in the chip architecture and its interaction with the core function.

[0098] For gate-level netlist replacement, establish the mapping relationship between the RTL of the redundant module and the corresponding gate-level netlist, and ensure that the interfaces are completely consistent before and after replacement. Design an automatic script to identify and process parameterized modules to avoid hierarchical and naming conflicts. Based on the SDF file, extract the delay characteristics of the critical path, design a timing adapter for the interface, and ensure that appropriate delay units are inserted between the RTL and the gate-level netlist.

[0099] For post-simulation verification, build a post-simulation verification environment, load the gate-level netlist and RTL as simulation file list and import the SDF file, extract the test cases from the pre-simulation environment and run the simulation.

[0100] For result comparison, verify the consistency of the output response before and after replacement, analyze the delay change of the critical path, and calculate the dynamic and static power consumption of each functional module before and after replacement.

[0101] Figure 2 is a flowchart of another chip post-simulation verification acceleration method provided by the embodiment of the disclosure, which combines Figure 2 , to Figure 1 further describe the chip post-simulation verification acceleration method in

[0102] Specifically, 1. Multi-dimensional data collection phase

[0103] Collect RTL code: extract the complete RTL code from the code repository of the chip design project. For a large-scale chip, the RTL code may consist of multiple functional module code files. These code files are organized in a specific project directory for subsequent processing.

[0104] Obtaining gate-level netlist: Using chip design tools, the RTL code is processed to generate the corresponding gate-level netlist. Using Synopsys Design Compiler tool, after setting the target library and synthesis constraints (such as area, timing, etc.), running the synthesis command, the gate-level netlist file is saved in standard format.

[0105] Organizing SDF files: SDF files record the delay information of each logic gate in the gate-level netlist under different working conditions (such as different voltages and temperatures). Store the SDF file and the corresponding gate-level netlist file together for subsequent simulation calls.

[0106] Organizing pre-simulation test cases: Collect and organize the test case set used in the pre-simulation stage of the chip. These test cases refer to the verification of the logical function correctness of the chip, usually written in a specific test platform language (such as SystemVerilog). Classify and organize the test cases, and mark the test cases related to different functional modules, so as to use them specifically in the post-simulation power consumption evaluation.

[0107] 2. Redundant module determination stage

[0108] Redundant module determination uses a rule-based screening algorithm combined with machine learning to determine redundant modules.

[0109] First, according to the functional specification of the chip, define the core functional module set related to the current verification function. By analyzing the pre-simulation waveform, identify the control signals and data flow involved in the core path, and mark the modules unrelated to the core path. For example, when verifying the image processing function of the chip, define the image acquisition module and image filtering module as core functional modules. Then, combined with the pre-simulation results, traverse all module names, and for modules not included in the core functional module set, further analyze their control paths and data paths. If the control signals of a module are not involved in the control logic of the current verification function, and its data path does not provide valid data for the current verification function, mark the module as a candidate redundant module.

[0110] Machine learning assisted screening: To improve the accuracy of redundant module determination, machine learning algorithms are introduced to perform secondary screening on candidate redundant modules. Use the redundant module annotation data from historical chip design projects as the training set, select features such as module function description keywords, connection relationship with core modules, signal interaction frequency, etc., and train a support vector machine (SVM) or random forest classification model. Through the model, the candidate redundant modules are predicted, and the final redundant module list is output.

[0111] 3. Gate-level netlist replacement stage

[0112] Mapping relationship establishment: An automated script based on rule matching is developed using Python language to establish mapping relationships by comparing the port number, name, bit width, direction, and other attributes of RTL modules and gate-level netlist modules. For modules with different names but the same function, a mapping table is established to associate them.

[0113] Parameterized module processing: For parameterized modules, the automated script uses regular expression matching to extract parameter values and record them in the instantiation statement. During the replacement process, the script automatically adjusts the parameter values of the corresponding modules in the RTL code based on the instantiation of the parameterized modules in the gate-level netlist, avoiding hierarchical and naming conflicts caused by inconsistent parameters. At the same time, the script checks the nested calls of parameterized modules and recursively processes parameter passing at each level to ensure the accuracy of the entire replacement process.

[0114] Timing adapter design: Based on the critical path delay data extracted from the SDF file, appropriate delay units are inserted at the interface between the RTL and the gate-level netlist. In specific implementation, first, analyze the delay information of the redundant module interface signals in the SDF file, calculate the delay time that needs to be compensated. Then, according to the delay time, select the appropriate delay unit type (such as D flip-flop, buffer, delay line, etc.), and instantiate it at the interface. In order to ensure the accuracy of the timing, the timing adapter will also impose timing constraints on the inserted delay units, by setting clock offset, setup time, hold time, and other constraint conditions, to ensure the timing matching between the RTL and the gate-level netlist.

[0115] 4. Post-simulation verification phase

[0116] The post-simulation verification module is based on the mainstream EDA simulation platform, and its implementation steps are as follows:

[0117] Environment setup: First, create a project engineering based on the pre-simulation verification platform, configure the simulation environment parameters, including the type of simulator, simulation time precision, memory allocation, etc. Then, automatically import the gate-level netlist and RTL code as simulation file lists through the script, and import the SDF file into the simulation environment to ensure that the simulator can read the delay information of the gate-level netlist.

[0118] Test case extraction: Extract test cases from the pre-simulation environment. Since the simulation objects of pre-simulation and post-simulation are different, for test cases written based on RTL code, the excitation signals and monitoring signals in the test cases need to be modified according to the port name and signal definition of the gate-level netlist. At the same time, in order to ensure that the test cases can cover the mixed simulation model after replacement, the test cases are expanded to increase the monitoring of the interface signals of RTL and gate-level netlist.

[0119] Simulation task execution: Use the command line interface of the simulation platform to start the simulation task through a script. During the simulation process, set breakpoints and monitoring points to monitor the simulation state and changes in key signals in real time. At the same time, record the simulation output results in a log file for subsequent analysis by the result comparison module.

[0120] 5. Result comparison phase

[0121] Output response consistency verification: The comparison program automatically reads the simulation output files before and after replacement, and verifies the consistency of the output response by combining string matching and numerical calculation. For text format output results, check whether the output content is the same by line-by-line comparison; for numerical output results, calculate the difference between the two and compare it with the preset error threshold. If the difference is within the error threshold, the output response is considered consistent.

[0122] Key path delay analysis: Combine the key path delay information recorded in the SDF file and the timing data in the simulation results to analyze the time delay changes of the key path. The comparison program extracts the signal arrival times of each node on the key path before and after replacement, calculates the time delay difference, and generates a time delay change analysis report.

[0123] Dynamic power consumption comparison: Call the power consumption analysis tool to perform dynamic power consumption analysis on the simulation results before and after replacement. The comparison program obtains the dynamic power consumption data of the main functional modules, calculates the power consumption difference, and performs statistical analysis. By comparing the power consumption proportion changes of different modules, the impact of gate-level netlist replacement on chip power consumption is evaluated.

[0124] The chip post-simulation verification acceleration method provided by the embodiments of the present disclosure can significantly shorten the problem of long post-simulation time of large-scale integrated circuits by constructing a hybrid simulation model and replacing part of the gate-level netlist unrelated to the current simulation function with RTL, thereby effectively improving the simulation efficiency.

[0125] The present disclosure at least includes the following beneficial results:

[0126] 1. Accelerate simulation efficiency: By replacing the gate-level netlist with RTL, the chip simulation time can be greatly shortened, and the larger the chip size and the more redundant modules, the more obvious the acceleration effect.

[0127] 2. Shorten the development cycle: Fast simulation verification makes chip design iteration more efficient, shortens the chip design cycle, accelerates the process from design to mass production, and occupies the market.

[0128] With Figure 1 Corresponding to the chip post-simulation verification acceleration method, the present disclosure further provides a chip post-simulation verification acceleration system, as shown in Figure 3 which can specifically include:

[0129] a multi-dimensional data collection module 301 configured to collect multi-dimensional data of a large-scale chip;

[0130] a redundancy module determination module 302 configured to collect all module names of a given chip, and determine names of control paths and data paths irrelevant to functions as redundancy module RTL through pre-simulation analysis and functional specification confirmation and verification;

[0131] a gate-level netlist replacement module 303 configured to establish a mapping relationship between the redundancy module RTL and a corresponding gate-level netlist, ensure that interfaces are completely consistent before and after replacement, and design an automatic script to identify and process parameterized modules;

[0132] a post-simulation verification module 304 configured to build a post-simulation verification environment, load gate-level netlists and RTLs as simulation file lists and import SDF files, extract test cases from a pre-simulation environment, and run simulation;

[0133] a result comparison module 305 configured to verify consistency of output responses before and after replacement, analyze time delay changes of critical paths, calculate dynamic and static power consumptions of each functional module before and after replacement, and generate simulation verification results.

[0134] In some embodiments, the multi-dimensional data of the large-scale chip is collected by:

[0135] extracting complete RTL codes from a code repository of a chip design project;

[0136] processing the sorted RTL codes by using a chip design tool to generate corresponding gate-level netlists, using a Synopsys Design Compiler tool, setting a target library and comprehensive constraints, and running a comprehensive command to obtain a gate-level netlist file saved in a standard format;

[0137] storing SDF files and corresponding gate-level netlist files in association, wherein the SDF files record delay information of each logic gate in the gate-level netlist under different working conditions;

[0138] collecting and sorting test case sets used in a pre-simulation stage of the chip, and marking test cases related to different functional modules.

[0139] In some embodiments, the redundancy module determination module 302 is configured to collect all module names of a given chip, and determine names of control paths and data paths irrelevant to functions as redundancy module RTL through pre-simulation analysis and functional specification confirmation and verification, by:

[0140] According to the functional specification of the chip, a set of core function modules related to the current verification function is defined, the control signals and data streams participating in the core path are identified by analyzing the pre-simulation simulation waveforms, the modules unrelated to the core path are marked, and all module names are traversed in combination with the pre-simulation results. For modules not included in the set of core function modules, further analyze the control path and data path of the module. If the control signal of the module does not participate in the control logic of the current verification function, and the data path of the module does not provide valid data for the current verification function, the corresponding module is marked as a candidate redundant module;

[0141] The redundant module annotation data in the historical chip design project is used as a training set, the functional description keywords of the module, the connection relationship with the core module, and the signal interaction frequency characteristics are selected, and a support vector machine or a random forest classification model is trained to predict the candidate redundant module and output the final redundant module RTL list.

[0142] In some embodiments, the above establishes the mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensures that the interfaces before and after replacement are completely consistent, and designs an automatic script to identify and process parameterized modules, including:

[0143] An automatic script based on rule matching is developed using Python language, and the mapping relationship is established by comparing the port number, name, bit width, and direction attribute of the RTL module and the gate-level netlist module. For modules with the same function but different names, the mapping table is established to associate them;

[0144] For parameterized modules, the automatic script uses regular expression to match the parameter passing part in the module instantiation statement, extracts the parameter values and records them. In the replacement process, the parameter values of the corresponding module in the RTL code are adjusted according to the instantiation of the parameterized module in the gate-level netlist, to avoid hierarchical and naming conflicts caused by inconsistent parameters. The nested call condition of the parameterized module is checked, and each level of parameter passing is processed recursively to ensure the accuracy of the entire replacement process;

[0145] According to the SDF file, the critical path delay data is extracted, and the corresponding delay unit is inserted at the interface of the RTL and the gate-level netlist.

[0146] In some embodiments, the above according to the SDF file extracts the critical path delay data, and inserts the corresponding delay unit at the interface of the RTL and the gate-level netlist, including:

[0147] The delay information of the redundant module interface signal in the SDF file is analyzed, and the delay time that needs to be compensated is calculated;

[0148] According to the delay time, select the appropriate delay unit type and instantiate it at the interface;

[0149] The timing adapter performs timing constraints on the inserted delay cells, sets clock offset, setup time and hold time constraints to ensure the timing match between RTL and gate-level netlist.

[0150] In some embodiments, the above-mentioned post-implementation simulation verification environment loads the gate-level netlist and RTL as a simulation file list and imports the SDF file, extracts test cases from the pre-simulation environment and runs the simulation, including:

[0151] Based on the pre-simulation verification platform, create a project engineering and configure simulation environment parameters, including simulator type, simulation time precision, memory allocation;

[0152] Automatically import gate-level netlist and RTL code as simulation file list through script, and import SDF file into simulation environment to ensure that the simulator can read the delay information of the gate-level netlist;

[0153] Extract test cases from the pre-simulation environment. For test cases based on RTL code, modify the excitation signals and monitoring signals in the test cases according to the port name and signal definition of the gate-level netlist, extend the test cases, and increase the monitoring of the interface signals of the RTL and gate-level netlist;

[0154] Use the command line interface of the simulation platform to start the simulation task through script, set breakpoints and monitoring points during simulation, monitor the simulation state and changes of key signals in real time, and record the simulation output results in log files for subsequent result comparison module analysis.

[0155] In some embodiments, the above-mentioned verification replaces the consistency of the output response before and after, analyzes the delay change of the critical path, calculates the dynamic power consumption and static power consumption of each functional module before and after the replacement, including:

[0156] The comparison program automatically reads the simulation output files before and after the replacement, uses a combination of string matching and numerical calculation to verify the consistency of the output response;

[0157] Combine the critical path delay information recorded in the SDF file and the timing data in the simulation results to analyze the delay change of the critical path;

[0158] Call the power consumption analysis tool to perform dynamic power consumption analysis on the simulation results before and after the replacement, obtain the dynamic power consumption data of the target functional module, calculate the power consumption difference, and perform statistical analysis. By comparing the power consumption proportion change of different modules, evaluate the impact of gate-level netlist replacement on chip power consumption.

[0159] Combine Figure 4As shown, the chip post-simulation verification acceleration device 400 provided by the embodiment of the present disclosure also includes a processor 404 and a memory 401. Optionally, the system can also include a communication interface 402 and a bus 403. The processor 404, the communication interface 402, and the memory 401 can complete communication with each other through the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can invoke the logic instructions in the memory 401 to execute the chip post-simulation verification acceleration method of the above-mentioned embodiment.

[0160] In addition, the logic instructions in the memory 401 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0161] The memory 401 as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 404 executes the function application and data processing by running the program instructions / modules stored in the memory 401, that is, implements the chip post-simulation verification acceleration method in the above-mentioned embodiment.

[0162] The memory 401 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 401 can include a high-speed random access memory, and can also include a non-volatile memory.

[0163] The embodiment of the present disclosure provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set to execute the chip post-simulation verification acceleration method.

[0164] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0165] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method of the embodiment of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. various media that can store program codes, or a transitory storage medium.

[0166] The above description and drawings are only illustrative of embodiments of the present disclosure, and thus are not restrictive of the present disclosure. Other embodiments can include structural, logical, electrical, process, and other changes. Embodiments are merely representative of possible variations. Individual components and functions are optional unless explicitly required, and the order of operations can be varied. Portions and features of some embodiments can be included in, or substituted for, those of other embodiments. As used in the description of the embodiments, the article "a" is intended to include one or more items unless the context clearly indicates otherwise. Likewise, the term "and / or" as used in this application refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, the term "comprises / comprising" and variations thereof when used in this application are taken to mean that the statement is not limited to the listed features, integers, steps, operations, elements, and / or components but that the listed features, integers, steps, operations, elements, and / or components can be present alone or in any combination or permutation thereof. Unless otherwise required by context, the use herein or reliance on terms such as "comprise / comprises / comprising" or "have / haves / having" or "include / includes / including" or "contain / contains / containing" or variations thereof, does not imply that the alternatives are the only means of improvement. For example, any implementation of the method, product, etc. disclosed herein can be used in any combination or permutation thereof. Also, the use or citation of any reference in this application is not an admission that it is prior art. Any discussion of the references is intended for that purpose only. The following claims are in no way limited to the embodiments described herein, but can include all possible embodiments that can come within the scope of the claims.

[0167] Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0168] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0169] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

[0170] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0171] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0172] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0173] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0174] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0175] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0176] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, without departing from the desired results of the technical solutions of the present disclosure, and this is not limited herein.

[0177] The specific embodiments described above are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that various modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments without departing from the spirit and principles of the present disclosure. Any further modifications, equivalent replacements, improvements, and the like made within the spirit and principles of the present disclosure should be included within the scope of the present disclosure.

Claims

1. A chip post-simulation verification acceleration method, characterized in that: The method comprises: Collecting multi-dimensional data of a large-scale chip; Collecting all module names of a given chip, confirming and verifying the names of control paths and data paths irrelevant to functions as redundant module RTL through pre-simulation analysis and functional specification; Establishing a mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensuring that the interfaces before and after replacement are completely consistent, and designing an automatic script to identify and process parameterized modules; Building a post-simulation verification environment, loading the gate-level netlist and RTL as simulation file lists and importing SDF files, extracting test cases from the pre-simulation environment and running simulation; Verifying the consistency of output responses before and after replacement, analyzing the time delay changes of critical paths, calculating the dynamic and static power consumptions of each functional module before and after replacement, and generating simulation verification results.

2. The method of claim 1, wherein, The collection of multi-dimensional data of a large-scale chip comprises: Extracting complete RTL code from the code repository of a chip design project; Using chip design tools to process the sorted RTL code to generate corresponding gate-level netlists, using the Synopsys Design Compiler tool to run the synthesis command after setting the target library and synthesis constraints, and obtaining the gate-level netlist file saved in a standard format; Storing the SDF file and the corresponding gate-level netlist file in association, wherein the SDF file records the delay information of each logic gate in the gate-level netlist under different working conditions; Collecting and sorting the test case set used in the pre-simulation stage of the chip, classifying and marking the test cases related to different functional modules.

3. The method according to claim 1, characterized in that The collection of all module names of a given chip, the confirmation and verification of the names of control paths and data paths irrelevant to functions as redundant module RTL through pre-simulation analysis and functional specification comprises: According to the functional specification of the chip, define a set of core functional modules related to the current verification function, identify the control signals and data streams involved in the core path by analyzing the pre-simulation waveforms, mark the modules unrelated to the core path, and traverse all module names based on the pre-simulation results. For modules not included in the core functional module set, further analyze their control paths and data paths. If the control signals of the module are not involved in the control logic of the current verification function, and its data path does not provide valid data for the current verification function, the corresponding module is marked as a candidate redundant module; Use the redundant module annotation data in the historical chip design project as a training set, select the functional description keywords of the module, the connection relationship with the core module, and the signal interaction frequency characteristics, train a support vector machine or random forest classification model to predict the candidate redundant module, and output the final redundant module RTL list.

4. The method of claim 1, wherein, The establishment of a mapping relationship between the redundant module RTL and the corresponding gate-level netlist, the ensuring of the complete consistency of the interfaces before and after replacement, and the design of an automatic script to identify and process parameterized modules comprise: An automation script based on rule matching is developed by using Python language, and a mapping relationship is established by comparing the port number, name, bit width and direction attribute of the RTL module and the gate-level netlist module. For the modules with the same function but different names, the mapping table is established to associate them. For the parameterized module, the automation script uses regular expression to match the parameter passing part in the instantiation statement of the module, extracts the parameter value and records it. In the replacement process, according to the instantiation of the parameterized module in the gate-level netlist, the parameter value of the corresponding module in the RTL code is adjusted to avoid the hierarchical and naming conflict caused by the inconsistent parameters. The nested call of the parameterized module is checked, and the parameter passing of each level is processed recursively to ensure the accuracy of the whole replacement process. According to the SDF file, the key path delay data is extracted, and the corresponding delay unit is inserted at the interface of the RTL and the gate-level netlist.

5. The method of claim 4, wherein, The method for inserting the delay unit at the interface of the RTL and the gate-level netlist according to the SDF file includes: Analyzing the delay information of the redundant module interface signal in the SDF file, and calculating the delay time that needs to be compensated; According to the delay time, a suitable delay unit type is selected, and the delay unit is instantiated at the interface; The timing adapter performs timing constraint on the inserted delay unit, sets the clock offset, setup time and hold time constraint conditions, and ensures the timing matching between the RTL and the gate-level netlist.

6. The method of claim 1, wherein, The method for building the post-simulation verification environment, loading the gate-level netlist and the RTL as the simulation file list and importing the SDF file, extracting the test cases from the pre-simulation environment and running the simulation, includes: Creating a project engineering based on the pre-simulation verification platform, and configuring the simulation environment parameters, including the simulator type, simulation time precision and memory allocation; Through the script, the gate-level netlist and the RTL code are automatically imported as the simulation file list, and the SDF file is imported into the simulation environment to ensure that the simulator can read the delay information of the gate-level netlist; From the pre-simulation environment, the test cases are extracted. For the test cases written based on the RTL code, the excitation signal and the monitoring signal in the test cases are modified according to the port name and the signal definition of the gate-level netlist, the test cases are expanded, and the monitoring of the interface signal of the RTL and the gate-level netlist is increased; Using the command line interface of the simulation platform, the simulation task is started through the script. During the simulation process, the breakpoints and the monitoring points are set, the simulation state and the change of the key signal are monitored in real time, and the simulation output result is recorded into the log file for subsequent analysis by the result comparison module.

7. The method of claim 1, wherein, The method for verifying the consistency of the output response before and after the replacement, analyzing the delay change of the key path, and calculating the dynamic power consumption and the static power consumption of each functional module before and after the replacement, includes: The comparison program automatically reads the simulation output files before and after the replacement, verifies the consistency of the output response by combining the string matching and the numerical calculation; The delay change of the key path is analyzed by combining the key path delay information recorded in the SDF file and the timing data in the simulation result. The method for inserting the delay unit at the interface of the RTL and the gate-level netlist according to the SDF file includes: Analyzing the delay information of the redundant module interface signal in the SDF file, and calculating the delay time that needs to be compensated; According to the delay time, a suitable delay unit type is selected, and the delay unit is instantiated at the interface; The timing adapter performs timing constraint on the inserted delay unit, sets the clock offset, setup time and hold time constraint conditions, and ensures the timing matching between the RTL and the gate-level netlist. The power consumption analysis tool is called to perform dynamic power consumption analysis on the simulation results before and after the replacement respectively, to obtain dynamic power consumption data of the target functional module, to calculate power consumption difference values, and to perform statistical analysis, to evaluate the influence of gate-level netlist replacement on chip power consumption by comparing power consumption proportion changes of different modules.

8. A post-silicon emulation verification acceleration system, comprising: The system comprises: a multi-dimensional data collection module for collecting multi-dimensional data of a large-scale chip; a redundant module determination module for collecting all module names of a given chip, and determining redundant module RTLs by confirming and verifying names of control paths and data paths irrelevant to functions through pre-simulation analysis and functional specification; a gate-level netlist replacement module for establishing a mapping relationship between the redundant module RTLs and corresponding gate-level netlists, ensuring that interfaces before and after the replacement are completely consistent, and designing an automatic script to identify and process parameterized modules; a post-simulation verification module for building a post-simulation verification environment, loading gate-level netlists and RTLs as simulation file lists and importing SDF files, extracting test cases from a pre-simulation environment and running simulation; a result comparison module for verifying consistency of output responses before and after the replacement, analyzing time delay changes of critical paths, calculating dynamic power consumption and static power consumption of each functional module before and after the replacement, and generating simulation verification results.

9. An electronic device, comprising: comprise: at least one processor; and a memory connected in communication with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7. 10.A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to perform the method of any one of claims 1-7.

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