LED display device and preparation method

Abstract

The invention relates to an LED display device and a preparation method, the LED display device comprises a substrate and a pixel layer, the pixel layer comprises pixel units, the periphery of each pixel unit is at least surrounded by an annular partition groove, each pixel unit is at least partially overlapped with the outermost annular partition groove of the adjacent pixel unit, and the outermost annular partition groove of each pixel unit is at least partially overlapped with the outermost annular partition groove of the adjacent pixel unit. A compound semiconductor is reserved in the non-overlapping area, or a compound semiconductor is reserved between each pixel unit and the outermost annular partition groove of the adjacent pixel unit, so that the pixel units and the adjacent pixel units are completely separated from each other; the top of each pixel unit is electrically connected with the corresponding second-type electrode contact, the bottom of each pixel unit is electrically connected with the corresponding first-type electrode contact, and the second-type electrode contacts are formed on the periphery of the outermost annular partition groove of the corresponding pixel unit. The invention further discloses a preparation method of the LED display device. The heat dissipation capacity of the LED device can be effectively improved, the LED device can emit light stably, and the photoelectric performance and the reliability of the LED display device are guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an LED display device and a preparation method thereof. BACKGROUND

[0002] The LED display chip usually comprises a plurality of pixel units (i.e. light emitting units). With the development of semiconductor display technology, the size of the display chip is increasingly reduced. Taking a micro-LED micro display chip as an example, the pixel size is gradually reduced to 1-5 um, or even to the nanometer level. The smaller the size, the higher the thermal density, and the heat is more easily concentrated. The main source of heat of the LED chip is the conversion efficiency problem of electrons and outgoing photons. Most of the electric energy that is not converted into outgoing light energy is converted into heat energy. These heat energy will cause the temperature of the LED chip to rise. If the temperature of the LED chip is too high, it will cause the light efficiency of the LED photoelectric device to decrease, the wavelength to shift, the service life to be low, and even seriously affect the stability and reliability of the LED display device, which cannot meet the use requirements. SUMMARY

[0003] Therefore, the technical problem to be solved by the present application is to improve the heat dissipation capacity of the LED display device in the prior art, so as to make the LED display device emit light stably and better guarantee the photoelectric performance and reliable performance of the LED display device.

[0004] To solve the above technical problems, the present application provides an LED display device, comprising,

[0005] a substrate, the substrate is a driving wafer, the driving wafer is provided with first electrode contacts and second electrode contacts, the polarities of the first electrode contacts and the second electrode contacts are opposite;

[0006] a pixel layer, the pixel layer is a compound semiconductor layer, the pixel layer is located on the upper part of the substrate, the pixel layer comprises pixel units, the periphery of each pixel unit is surrounded by at least one annular isolation groove, the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with compound semiconductor; or, the compound semiconductor is reserved between the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit to completely separate each other;

[0007] wherein the top of each pixel unit is electrically connected with the corresponding second electrode contact, the bottom of the pixel unit is electrically connected with the corresponding first electrode contact, and the second electrode contact is formed on the periphery of the annular isolation groove at the outermost periphery of each pixel unit.

[0008] In one embodiment of the present application, the LED display device further comprises interconnecting conductive members, the top of each pixel unit is electrically connected through the interconnecting conductive members and the corresponding second type of electrode contact, and the interconnecting conductive members are formed on the outer periphery of the ring-shaped isolation groove of each pixel unit.

[0009] In one embodiment of the present application, a compound semiconductor is reserved between the ring-shaped isolation groove of the outer periphery of each pixel unit and the interconnecting conductive member to form a non-light-emitting area.

[0010] In one embodiment of the present application, the upper portion of the pixel layer is provided with a first insulating layer, the first insulating layer covers the upper surface of the non-light-emitting area and the inner wall of the ring-shaped isolation groove, the inside of the ring-shaped isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer at the inner wall of the ring-shaped isolation groove, and the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.

[0011] In one embodiment of the present application, the upper portion of the pixel layer is further covered with a thin film cover layer, the upper portion of the filling area is closed by the thin film cover layer, and the first insulating layer at the upper surface of the non-light-emitting area is located below the thin film cover layer.

[0012] In one embodiment of the present application, the thin film cover layer comprises a downwardly protruding extension, the extension extends into the inside of the filling area, the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air isolation layer.

[0013] Alternatively, the extension serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

[0014] In one embodiment of the present application, the filling area contains air to form an air isolation layer, the periphery of the air isolation layer is surrounded by the first reflective layer, or

[0015] The first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

[0016] In one embodiment of the present application, the upper portion of the pixel layer is further provided with a first conductive layer, the first conductive layer is at least partially located above the first insulating layer, the upper end of the interconnecting conductive member is electrically connected through the first conductive layer and the top of the pixel unit, and the lower end is electrically connected with the corresponding second type of electrode contact.

[0017] In one embodiment of the present application, the upper end of the interconnecting conductive member is in direct contact with the first conductive layer, and a metal reinforcing member is connected to the upper portion of the first conductive layer; or, the upper end of the interconnecting conductive member is in direct contact with a metal reinforcing member, and the metal reinforcing member is connected to the first conductive layer.

[0018] In one embodiment of the present application, an etching barrier layer is provided on the upper surface of the non-light-emitting region, and the first insulating layer is provided above the etching barrier layer.

[0019] In one embodiment of the present application, the pixel layer and the substrate are bonded by a bonding layer, and the bottom surface of the annular groove is not lower than the upper surface of the bonding layer.

[0020] In one embodiment of the present application, the interconnecting conductive member is a metal member.

[0021] In one embodiment of the present application, the interconnecting conductive member comprises a core, the core is a compound semiconductor, and the core is connected to the corresponding second electrode contact through a bonding layer.

[0022] In one embodiment of the present application, the bonding layer is a metal layer, a first peripheral fence is formed on the upper portion of the bonding layer, the interconnecting conductive member is arranged inside the first peripheral fence, and the first peripheral fence and the interconnecting conductive member inside are isolated by a second insulating layer.

[0023] In one embodiment of the present application, the upper surface of the driving wafer is divided into at least one display region, each display region is covered by at least one pixel unit, and the bonding layer above each display region is arranged continuously.

[0024] In one embodiment of the present application, the bottom of each pixel unit is electrically connected to the corresponding first electrode contact, and the first electrode contact is located inside the display region where the corresponding pixel unit is located, or the first electrode contact is located in the periphery of the display region where the corresponding pixel unit is located.

[0025] In one embodiment of the present application, the bonding layer is a metal layer, and a first dielectric layer is further arranged between the pixel layer and the bonding layer.

[0026] In one embodiment of the present application, the first dielectric layer is provided with a first opening region in the area below the pixel unit, the bonding layer is provided with an embedded part corresponding to the first opening region, the embedded part is embedded in the corresponding first opening region, and the bonding layer is connected to the bottom of the pixel unit through the embedded part.

[0027] In an embodiment of the present application, each of the pixel units is surrounded by at least two of the ring-shaped grooves, and compound semiconductors are reserved between the adjacent ring-shaped grooves of each of the pixel units to form a partition wall.

[0028] In an embodiment of the present application, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second type of electrode contact is electrically connected to the first semiconductor layer in the corresponding pixel unit, the first type of electrode contact is electrically connected to the second semiconductor layer in the corresponding pixel unit, the lower end of the ring-shaped groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the ring-shaped groove extends at least to the upper surface of the first semiconductor layer.

[0029] In an embodiment of the present application, an ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the ring-shaped groove extends between the lower surface of the active layer and the lower surface of the ohmic contact layer.

[0030] In an embodiment of the present application, the maximum dimension of the ring-shaped groove in the width direction is L2, and L2 is 0.02 um to 10 um.

[0031] In an embodiment of the present application, a lens is arranged on the top of the pixel layer, and the lens covers at least one of the pixel units.

[0032] The present application further discloses a preparation method of an LED display device, comprising the following steps:

[0033] A driving wafer is selected as the substrate, and the driving wafer is provided with the first type of electrode contact and the second type of electrode contact with opposite polarities, and a compound semiconductor layer is selected as the pixel layer.

[0034] The pixel layer is connected to the upper part of the substrate.

[0035] The pixel layer is etched to obtain at least one pixel unit, each of the pixel units obtained by etching is surrounded by at least one ring-shaped groove, the ring-shaped groove at the outermost periphery of each of the pixel units at least partially overlaps with the ring-shaped groove at the outermost periphery of the adjacent pixel unit, and compound semiconductors are reserved in the non-overlapping area; or compound semiconductors are reserved between the ring-shaped groove at the outermost periphery of each of the pixel units and the ring-shaped groove at the outermost periphery of the adjacent pixel unit to completely separate each other.

[0036] The top of each of the pixel units is electrically connected to the corresponding second type of electrode contact, the bottom of each of the pixel units is electrically connected to the corresponding first type of electrode contact, and the second type of electrode contact is formed on the periphery of the ring-shaped groove at the outermost periphery of each of the pixel units.

[0037] In one embodiment of the present application, when the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

[0038] In one embodiment of the present application, when the top of each pixel unit is electrically connected to the corresponding second-type electrode contact, the method comprises,

[0039] A second-type electrode filling hole is formed in the compound semiconductor layer, and the second-type electrode filling hole penetrates the bonding layer;

[0040] A metal is filled in the second-type electrode filling hole to form an interconnection conductive member, and the interconnection conductive member is formed at the outer periphery of the annular groove at the outermost periphery of each corresponding pixel unit;

[0041] The top of each pixel unit is electrically connected to the corresponding second-type electrode contact through the interconnection conductive member.

[0042] In one embodiment of the present application, in the above method, when the second-type electrode filling hole is formed in the compound semiconductor layer, the compound semiconductor between the annular groove at the outermost periphery of each pixel unit and the adjacent second-type electrode filling hole is reserved to form a non-light-emitting area.

[0043] In one embodiment of the present application, the above method comprises,

[0044] A first cut groove is formed in the compound semiconductor layer, the first cut groove is annular, and the first cut groove penetrates the bonding layer, so that the area surrounded by the inner wall of the first cut groove is reserved to form an interconnection conductive member, the interconnection conductive member includes a core, the core is a compound semiconductor, the core is connected to the corresponding second-type electrode contact through the underlying bonding layer, and the interconnection conductive member is formed at the outer periphery of the annular groove at the outermost periphery of each corresponding pixel unit.

[0045] The top of each pixel unit is electrically connected to the corresponding second-type electrode contact through the interconnection conductive member.

[0046] In one embodiment of the present application, in the above method, when the first cut groove is formed in the compound semiconductor layer, the compound semiconductor between the annular groove at the outermost periphery of each pixel unit and the adjacent first cut groove is reserved to form a non-light-emitting area.

[0047] The above technical solutions of the present application have the following advantages compared with the prior art:

[0048] The LED display device of the present invention has good heat dissipation capability, can make the LED display device emit light stably, better ensure the photoelectric performance and reliability of the LED display device, and extend the service life of the LED display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0050] Figure 1 This is a schematic diagram of the structure of an LED display device in traditional technology;

[0051] Figure 2 1 is a schematic top view of an LED display device in the present invention (the first conductive layer is omitted);

[0052] Figure 3 yes Figure 2 A partial enlarged view of the middle BB;

[0053] Figure 4 It is along Figure 2 Partial cross-sectional view taken at B1-B1;

[0054] Figure 5 It is along Figure 2 Partial cross-sectional view taken at B2-B2;

[0055] Figure 6 This is a schematic structural diagram of an LED display device in the present invention;

[0056] Figure 7 is a schematic structural diagram of the compound semiconductor layer in the present invention;

[0057] Figure 8 This is a bonding flow chart of the pixel layer and the driver wafer in the present invention;

[0058] Figure 9 yes Figure 5 The preparation flow chart of the LED display device shown;

[0059] Figure 10 is a flow chart for preparing another LED display device of the present invention;

[0060] Figure 11 This is a schematic structural diagram of an LED display device in which the annular partition groove is hollow in the present invention;

[0061] Figure 12 yes Figure 11 A local enlarged view of M1 in the middle;

[0062] Figure 13is a structural schematic diagram of a second annular groove;

[0063] Figure 14 is a structural schematic diagram of a third annular groove;

[0064] Figure 15 is a structural schematic diagram of an LED display device in which the annular groove is in a solid structure in the present application;

[0065] Figure 16 is Figure 15 is a partial enlarged view of M2 in FIG. 15;

[0066] Figure 17 is a structural schematic diagram of an LED display device in which the annular groove has a certain etching depth in the present application;

[0067] Figure 18 is Figure 17 is a structural schematic diagram of M3 in FIG. 16;

[0068] Figure 19 is a structural schematic diagram of an LED display device in another form of annular groove;

[0069] Figure 20 is a structural schematic diagram of an LED display device in which a plurality of annular grooves are arranged at the periphery of a pixel unit in the present application;

[0070] Figure 21 is a top view schematic diagram of an LED display device in which a plurality of annular grooves are arranged at the periphery of a pixel unit in the present application;

[0071] Figure 22 is a top view schematic diagram of another LED display device in which a plurality of annular grooves are arranged at the periphery of a pixel unit in the present application;

[0072] Figure 23 is a structural schematic diagram of an LED display device provided with a metal grid in the present application;

[0073] Figure 24 is a structural schematic diagram of another LED display device provided with a metal grid in the present application;

[0074] Figure 25 is a structural schematic diagram of an LED display device provided with a first dielectric layer in the present application;

[0075] Figure 26 is Figure 25 is a partial enlarged view of M4 in FIG. 18;

[0076] Figure 27 is a structural schematic diagram of an LED display device in which a first type of electrode contact is not arranged in a display area in the present application;

[0077] Figure 28 is Figure 27 a top view layout diagram of the LED display device shown in FIG. 1;

[0078] Figure 29 is a layout diagram (top view) of driving display area on wafer in the present application;

[0079] Description of the Drawings:

[0080] 100, pixel unit; 101, first semiconductor layer; 102, active layer; 103, second semiconductor layer;

[0081] 200, substrate; 201, display area; 202, first type of electrode contact; 203, second type of electrode contact;

[0082] 300, bonding layer; 301, first peripheral bar; 302, embedded part;

[0083] 400, pixel layer; 401, annular isolation groove; 4011, filling area; 40111, first filler; 40112, air isolation layer; 402, isolation wall; 403, etching barrier layer; 404, first insulating layer; 405, thin film cover layer; 4051, extension; 406, first reflective layer; 407, second type of electrode filling hole; 408, second insulating layer; 409, first cutting groove; 410, non-light emitting area;

[0084] 500, ohmic contact layer;

[0085] 600, interconnection conductive member; 601, core;

[0086] 700, first conductive layer;

[0087] 800, peripheral electrode contact area; 900, interface; 1000, lens;

[0088] 1100, first dielectric layer; 11001, first opening area; 1200, metal reinforcement; DETAILED DESCRIPTION

[0089] The present application will be further described with reference to the drawings and specific examples, so that those skilled in the art can better understand the present application and implement it. It is obvious that the described examples are only some of the embodiments of the present disclosure, not all. The following description of at least one exemplary embodiment is actually only illustrative, and in no way limits the present disclosure and its applications or uses.

[0090] In the description of the present application, it needs to be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0091] In the description of the present application, it needs to be understood that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0092] The LED display device in the prior art has the problem of poor heat dissipation effect. Therefore, the present application provides an LED display device to improve its heat dissipation capacity, so as to better ensure the photoelectric performance and reliability of the LED display device.

[0093] It should be noted that the compound semiconductor layer in the present application refers to a layer structure with a certain thickness prepared from a compound semiconductor material. Compound semiconductors generally refer to compounds formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in the present application are mainly light emitting diode epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system, etc., which can cover the full wavelength range from ultraviolet, visible light and infrared, and the substrate material can be GaN, Si, SiC, Sapphire, GaAs, InP, etc.

[0094] Taking the field of Micro-LED as an example, some compound semiconductor materials involved in the present application are shown in Table 1. In some practical applications, the film layer of the compound semiconductor will be more complex, or there will be a situation of cross use of materials. Typical compound semiconductors mainly include P-type semiconductor material, N-type semiconductor material and MQW active quantum well sandwiched between them and other functional layers (barrier layer, confinement layer, waveguide layer, buffer layer, etc.):

[0095] Table 1: Material table of film layer of compound semiconductor

[0096]

[0097] The related structure of the LED display device of the present application will be further described below in combination with the following specific embodiments.

[0098] Embodiment one

[0099] Referring to Figures 2-10 , the embodiment discloses an LED display device, comprising a substrate 200 and a pixel layer 400,

[0100] The substrate 200 is a driving wafer, and the driving wafer is provided with a first type of electrode contact 202 and a second type of electrode contact 203, the polarities of the first type of electrode contact 202 and the second type of electrode contact 203 are opposite, one of which is positive and the other of which is negative; it can be understood that the first type of electrode contact 202 and the second type of electrode contact 203 need to be insulated and isolated to prevent short circuit caused by direct contact.

[0101] The pixel layer 400 is a compound semiconductor layer, and the pixel layer 400 is located on the upper part of the substrate 200, and the pixel layer 400 comprises a pixel unit 100, and the periphery of each pixel unit 100 is at least surrounded by an annular isolation groove 401, so as to realize pixel independence through the annular isolation groove 401 in the periphery.

[0102] It can be understood that the above-mentioned compound semiconductor layer refers to a layer body with a certain thickness prepared from a compound semiconductor material.

[0103] As shown in Figures 2-3 , the annular isolation groove in the outermost periphery of each pixel unit and the annular isolation groove in the outermost periphery of the adjacent pixel unit at least partially overlap, and a compound semiconductor material area Q1 is reserved in the non-overlapping area, that is, the annular isolation groove in the outermost periphery of each pixel unit and the annular isolation groove in the outermost periphery of the adjacent pixel unit can share a part of the annular isolation groove, for example, as shown in Figure 2 , only one annular isolation groove 401 is arranged in the periphery of the pixel unit 100, and the annular isolation grooves 401 of the two adjacent pixel units 100 have an intersection part W1, and the intersection part W1 is a shared part;

[0104] Alternatively, the annular isolation groove in the outermost periphery of each pixel unit and the annular isolation groove in the outermost periphery of the adjacent pixel unit can also be completely separated from each other by reserving a compound semiconductor therebetween, that is, the annular isolation grooves in the outermost peripheries of the two adjacent pixel units are completely non-overlapping and separated from each other, and the separated area reserves the original compound semiconductor material area, for example, as shown in Figure 21As shown, the outermost annular grooves 401 of two adjacent two-pixel units 100 are completely non-overlapping and separated from each other, and the separation area is the original compound semiconductor material area Q1.

[0105] The top of each pixel unit 100 is electrically connected to the corresponding second electrode contact 203, and the bottom of the pixel unit 100 is electrically connected to the corresponding first electrode contact 202. The second electrode contact 203 is formed on the periphery of the outermost annular groove 401 of each corresponding pixel unit, that is, the second electrode contact corresponding to each pixel unit 100 is not only located on the periphery of the corresponding pixel unit 100, but also on the periphery of the outermost annular groove 401 of the pixel unit 100.

[0106] It can be understood that the top and bottom of the pixel unit 100 are respectively two ends with opposite polarities, for example, the top is the end where the N-type semiconductor (or the end where the P-type semiconductor) is located, and the bottom is the end where the P-type semiconductor (or the end where the N-type semiconductor) is located. It needs to be connected to electrode contacts with different polarities. Among them, the pixel unit and the electrode contact (first electrode contact or second electrode contact) can be one-to-one or one-to-many, for example, one second electrode contact can correspond to one pixel unit, or multiple second electrode contacts can correspond to one pixel unit. Similarly, the first electrode contact is the same.

[0107] The second electrode contact 203 is arranged on the periphery of the outermost annular groove 401 of the corresponding pixel unit 100, which can make the pixel unit 100 maintain a relatively small size, especially suitable for the preparation of display chips with small pixel size.

[0108] Among them, the above-mentioned driving wafer is an element with a driving circuit, the first electrode contact 202 and the second electrode contact 203 are the output terminals of the driving circuit, which are used to electrically connect the driving circuit and the pixel unit, and the pixel unit 100 is a light-emitting element. The electrical connection between the driving wafer and the pixel unit 100 can control the light-emitting of the pixel unit 100.

[0109] The above-mentioned driving wafer includes but is not limited to CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) driving backplane or TFT glass substrate, etc.

[0110] The above structure can make the driving wafer and the pixel unit 100 electrically connected through the arrangement of the first electrode contact 202 and the second electrode contact 203, so as to control the light-emitting of each pixel unit 100 by the driving wafer.

[0111] In some preferred modes, each pixel unit 100 in the pixel layer 400 can independently emit light.

[0112] As can be understood, Figure 1 in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then filled with an insulating medium material G1 to achieve the independence of the pixel unit 100. The thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be timely transmitted, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device.

[0113] Table 2: Comparison table of thermal conductivities of different materials

[0114]

[0115]

[0116] As shown in Table 2, among the three materials of insulating medium, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating medium material.

[0117] As shown in Table 2, among the three materials of insulating medium, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating medium material. Figures 2-5 The above LED display device structure of the embodiment realizes the independence of the pixel unit by opening a ring-shaped separation groove in the compound semiconductor layer, so that the outermost ring-shaped separation groove of each pixel unit at least partially overlaps with the outermost ring-shaped separation groove of the adjacent pixel unit, and the non-overlapping area is reserved with a compound semiconductor material area, or the outermost ring-shaped separation groove of each pixel unit and the outermost ring-shaped separation groove of the adjacent pixel unit are completely separated by the compound semiconductor. The original compound semiconductor material can be reserved to the greatest extent, and the thermal conductivity of the compound semiconductor material is relatively high. Compared with the structure of removing most of the compound semiconductor material and filling it with an insulating medium material in the prior art, the heat dissipation effect of the device can be effectively improved.

[0118] It should be noted that, Figure 4 only when arranged according to the structure shown in Figure 2 , a cross-sectional view of three adjacent pixel units obtained along the B1-B1 section in Figure 2 is shown. Figure 5 only when arranged according to the structure shown in Figure 2 , a cross-sectional view of one pixel unit and its peripheral structure obtained along the B2-B2 section in Figure 2 is shown.

[0119] In the present application, the "width" direction is the X direction, the "height" or "up-down" direction is the Z direction, and there is also a Y direction, wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. The pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103.

[0120] The LED display device also includes an interconnection conductive member 600, and the top of each pixel unit 100 is electrically connected to the corresponding second type of electrode contact 203 through the interconnection conductive member 600. The interconnection conductive member 600 is formed on the outer periphery of the outermost annular isolation groove 401 of the corresponding each pixel unit 100. For example, the outer periphery of each pixel unit 100 is provided with two concentric annular isolation grooves 401 in sequence, and the second annular isolation groove 401 is located on the outer periphery of the first annular isolation groove 401. Then, the interconnection conductive member 600 is formed on the outer periphery of the second annular isolation groove 401 of the corresponding each pixel unit 100.

[0121] Further, the outer periphery of each pixel unit 100 is provided with an annular isolation groove 401 and an interconnection conductive member 600. In a specific arrangement, a compound semiconductor material is reserved between the annular isolation groove 401 on the outermost periphery of each pixel unit and the interconnection conductive member 600 adjacent to the annular isolation groove 401 (i.e., the interconnection conductive member 600 closest to the annular isolation groove 401 on the outermost periphery of the pixel unit) to form a non-light-emitting region 410. In this way, the compound semiconductor between the annular isolation groove 401 on the outermost periphery of the pixel unit and the corresponding interconnection conductive member 600 is not removed by etching, thereby effectively increasing the heat dissipation performance of the semiconductor device.

[0122] It can be understood that the "non-light-emitting region 410" refers to a region that is not used as a light-emitting unit, and only the "pixel unit 100" is used as a light-emitting unit. The materials of the "non-light-emitting region 410" and the "pixel unit 100" are the same, which are compound semiconductor materials.

[0123] In some embodiments, the upper portion of the pixel layer 400 is provided with a first insulating layer 404, which covers the upper surface of the non-light-emitting region 410 and the inner wall of the annular isolation groove 401. The inside of the annular isolation groove 401 has a filling region 4011, and the outer periphery of the filling region 4011 is surrounded by the first insulating layer 404 on the inner wall of the annular isolation groove 401, as shown in Figure 3 The filling region 4011 can contain an air layer 40112, i.e., the filling region 4011 has a hollow structure;

[0124] Or, as shown in Figures 15-16As shown, the filling area 4011 may also be filled with a first filler 40111 to form a solid structure.

[0125] The first filler 40111 may be an insulating medium or metal.

[0126] Among them, covering the inner wall of the annular partition 401 with the first insulating layer 404 can better isolate the pixel unit 100 and prevent leakage; making the first insulating layer 404 cover the upper surface of the non-luminous area 410 can cover the upper surface of the non-luminous area 410.

[0127] It should be noted that the inner wall of the above-mentioned annular groove 401 includes side walls and a bottom surface, and its side walls and bottom surface are covered with a first insulating layer 404. When there is an air partition layer 40112 inside the filling area 4011, the bottom surface of the air partition layer 40112 is not lower than the bottom surface of the annular groove 401.

[0128] It is understandable that in some ways, such as Figures 2-4 As shown, the pixel unit 100 and the peripheral adjacent annular partition groove 401 share a side wall, and the first insulating layer 404 on the side wall is also shared by both.

[0129] Furthermore, when there is an air barrier layer 40112 inside the filler, the minimum size of the air barrier layer 40112 along the width direction (X direction) must be greater than 0, and the maximum size of the air barrier layer 40112 along the width direction (X direction) is L3, then L3 is 0.01um~8um.

[0130] Exemplarily, the first insulating layer 404 may be a single-layer structure or a stacked-layer structure composed of one or more dielectric layers such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, aluminum nitride, and gallium nitride.

[0131] For example, the first insulating layer 404 may be a stacked structure of silicon oxide and titanium oxide, and a DBR (distributed Bragg reflector) Bragg reflector structure is constructed by utilizing the difference in refractive index between the two materials.

[0132] In some embodiments, the thickness of the first insulating layer 404 is 5 nm to 2 um.

[0133] Furthermore, when the thickness of the first insulating layer 404 is 5 nm to 1 um and there is an air spacer 40112 inside the filler, the maximum size of the air spacer 40112 along the width direction (X direction) is L3, then L3 can be 0.01 um to 8 um.

[0134] In some embodiments, the width L1 of the pixel unit 100 is 0.2 um to 80 um. The width of the pixel unit 100 can be understood as the maximum dimension of the pixel unit 100 along the width direction (X direction).

[0135] Further, the height h1 of the pixel unit 100 is 0.1 um to 5 um. The height of the pixel unit 100 refers to the distance between the upper surface of the first semiconductor layer 101 and the lower surface of the second semiconductor layer 103 in the pixel unit.

[0136] The shape of the pixel unit 100 described above includes but is not limited to a circle, an ellipse, a polygon, and other shapes, and is preferably a circle, a quadrilateral, and a hexagon.

[0137] In some embodiments, as shown in Figure 5 The upper part of the pixel layer 400 is further provided with a first conductive layer 700, which is at least partially located above the first insulating layer 404. The upper end of the interconnection conductive member 600 is electrically connected to the top of the pixel unit 100 through the first conductive layer 700, and the lower end is electrically connected to the corresponding second electrode contact 203.

[0138] The first conductive layer 700 can be a transparent conductive layer.

[0139] For example, the transparent conductive layer described above can be one or more combinations of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, or gold-doped indium tin oxide.

[0140] Further, as shown in Figure 21 and Figure 22 The pixel unit 100 and the first conductive layer 700 can be one-to-one corresponding, and the first conductive layers 700 between adjacent pixel units 100 are spaced apart.

[0141] In some embodiments, an etching stop layer 403 is provided at the upper surface of the non-emitting area 410 to be used as a mask during etching; the first insulating layer 404 is covered above the etching stop layer 403.

[0142] For example, the etching stop layer 403 described above can be a mask of silicon oxide, silicon nitride, etc., or a contact layer of ITO, metal, etc., or a stack on the dielectric layer below the contact layer. In addition to forming a contact (such as an ohmic contact) with the first semiconductor layer 101, the film layer is mainly used as a mask for patterned etching.

[0143] The etching stop layer 403 described above can be a transparent material layer.

[0144] In some embodiments, the top surface of the pixel unit 100 can be roughened to form a rough surface. By roughening the top surface, the interface of total reflection can be reduced, the light extraction rate can be increased, and the luminous brightness of the pixel unit 100 can be improved.

[0145] In some embodiments, as shown in the figure, the interconnection conductive member 600 is a metal member;

[0146] In some other embodiments, as shown in the figure, the interconnection conductive member 600 can include a core 601 made of a compound semiconductor. The bonding layer 300 below the core 601 is also retained, so that the core 601 is connected to the corresponding second electrode contact 203 through the bonding layer 300 below. The upper part of the interconnection conductive member 600 can be electrically connected to the first conductive layer 700. Figure 10

[0147] Since the metal member and the compound semiconductor both have high thermal conductivity, the interconnection conductive member 600 with the above structure can further improve the heat dissipation effect of the LED display device.

[0148] In some embodiments, the pixel layer 400 and the substrate 200 are bonded through the bonding layer 300, and the bottom surface of the annular isolation groove 401 is not lower than the upper surface of the bonding layer 300.

[0149] For example, as shown in the figure, the bonding layer 300 is made of a conductive metal layer, and the upper part of the bonding layer 300 is formed with a first peripheral fence 301. The interconnection conductive member 600 is located inside the corresponding first peripheral fence 301, and the first peripheral fence 301 and the interconnection conductive member 600 inside are isolated by a second insulating layer 408. The second insulating layer 408 can be arranged at the inner wall of the first peripheral fence 301. Figure 5

[0150] In addition, since the first electrode contact can also be connected to the bonding layer 300, the second insulating layer 408 is arranged to insulate and isolate the second electrode contact 203 from the first electrode contact 202, so as to avoid short circuit.

[0151] Further, the outer wall of the first peripheral fence 301 can also be coated with a first insulating layer 404.

[0152] The bonding layer 300 can be one or more of Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination or ITO, ITO combination. An adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.) can also be arranged between the bonding layer 300 and the driving wafer.

[0153] ​​In some preferred modes, the bonding layer 300 can be a multi-layer structure stacked in sequence along the height direction, and the layers from bottom to top are respectively a Cr layer (adhesion layer), a Pt layer (barrier depletion layer), an Au layer, a Sn layer, and an Au layer, with thicknesses of 10 nm, 50 nm, 100 nm, 150 nm, and 50 nm, respectively.

[0154] For example, the second insulating layer 408 can be one or more of a silicon oxide, an aluminum oxide, a silicon nitride, a titanium oxide, a hafnium oxide, a tantalum oxide, a niobium oxide, an aluminum nitride, a gallium nitride, or the like, to form a single-layer structure or a stacked-layer structure.

[0155] In some embodiments, the thickness of the second insulating layer 408 is 5 nm to 2 um, to ensure the insulating isolation effect.

[0156] In some embodiments, as shown in FIG. 1A, the upper surface of the driving wafer is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201. Figure 29

[0157] In some embodiments, as shown in FIG. 1A, the upper surface of the driving wafer is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201.

[0157] In some embodiments, as shown in FIG. 1A, the upper surface of the driving wafer is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201.

[0158] For example, each display area 201 has a plurality of pixel units 100 to form a pixel array above the display area 201, that is, each display area 201 is covered by a corresponding pixel array, and the projection of the pixel array on the driving wafer is located within the corresponding display area 201. The "bonding layer 300 above each display area 201" can be understood as the bonding layer whose projection on the driving wafer falls within the display area, and then at least the bonding layer above each display area needs to be continuously arranged within the corresponding display area. In specific arrangement, the bonding layer above the display area can be continuously arranged within the corresponding upper area of the display area, and the bonding layer between the display areas is discontinuous (for example, the K1 area in FIG. 1B); or a plurality of display areas 201 can share a continuous bonding layer 300, for example, two display areas 201 share a continuous bonding layer 300 (for example, the K2 area in FIG. 1C), or four display areas 201 share a continuous bonding layer 300 (for example, the K3 area in FIG. 1D), or nine display areas 201 share a continuous bonding layer 300 (for example, the K4 area in FIG. 1E). Figure 29 Figure 29 Figure 29 Figure 29 ​​The non-display region 201 (which is above the pixel units 100) can be filled with a medium layer for support.

[0159] In some embodiments, the bottom of each pixel unit 100 is electrically connected to a corresponding first electrode contact 202, which is located inside the display region 201 where the corresponding pixel unit 100 is located.

[0160] The pixel layer 400 in the present embodiment includes, from top to bottom, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103. It can be understood that the pixel units 100 are obtained by etching the pixel layer 400, and each pixel unit 100 also includes, from top to bottom, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103.

[0161] The second electrode contact 203 is used to electrically connect the first semiconductor layer 101 in the corresponding pixel unit 100, and the first electrode contact 202 is used to electrically connect the second semiconductor layer 103 in the corresponding pixel unit 100.

[0162] The first semiconductor layer 101 and the second semiconductor layer 103 are one of a P-type semiconductor layer and an N-type semiconductor layer. The active layer 102 is used for light emission and can be an MQW active quantum well.

[0163] In some embodiments, as shown in FIG. 4B, the lower end of the annular isolation groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200, and the upper end of the annular isolation groove 401 extends at least to the upper surface of the first semiconductor layer 101. Figures 4-5

[0164] Further, an ohmic contact layer 500 is arranged between the pixel layer 400 and the substrate 200, and the lower end of the annular isolation groove 401 extends between the lower surface of the active layer 102 and the lower surface of the ohmic contact layer 500.

[0165] The ohmic contact layer 500 is located between the second semiconductor layer 103 and the bonding layer 300, and is used to better realize the ohmic contact between the second semiconductor layer and the bonding layer 300.

[0166] For example, the ohmic contact layer 500 can be a transparent conductive film made of one or more of ITO, IZO, IGZO, or AZO, or can be a metal layer made of one or more of Ni, Cr, Au, Ag, Zn, Rh, Be, or Al, or can be an alloy layer, or can also be a stack of a transparent metal oxide and a metal;

[0167] ​The thickness of the ohmic contact layer 500 is 1 nm to 500 nm. If the thickness is too large, it will cause material waste, while if the thickness is too small, it will be difficult to achieve a good ohmic contact effect.

[0168] In some embodiments, as Figure 18 As shown, the minimum dimension of the annular partition groove 401 along the width direction (X direction) needs to be greater than 0, and the maximum dimension of the annular partition groove 401 along the width direction (X direction) is L2, which is 0.02um to 10um. The width should not be too large so as to retain the semiconductor material in the compound semiconductor layer to the greatest extent and improve the heat dissipation effect. It should not be too small either, as it is not conducive to processing and ensuring effective separation between the pixel units 100. Too small a width will also affect the light output effect.

[0169] In some embodiments, as Figure 6 As shown, a lens is provided on the top of the pixel layer 400 , and the lens covers at least one pixel unit 100 , that is, the lens may correspond to the pixel unit 100 one by one, or multiple pixel units 100 may correspond to one lens.

[0170] The lens may be made of insulating material. For example, the lens may be made of silicon oxide, silicon nitride, aluminum oxide, silicate glass, PMMA, silicone rubber or SU8.

[0171] In the LED display device of the above embodiment, the top of each pixel unit 100 is addressable and controllable, and can be addressed and lit.

[0172] This embodiment also discloses a method for preparing the above-mentioned LED display device, comprising the following steps:

[0173] Step S1: Select a driving wafer as the substrate 200, on which a first type of electrode contact 202 and a second type of electrode contact 203 with opposite polarities are provided, and select a compound semiconductor layer as the pixel layer 400; the structure of the compound semiconductor layer is shown in FIG. Figure 7 The compound semiconductor layer includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 arranged in sequence from top to bottom; Step S2: Figure 8 As shown, the pixel layer 400 is connected to the upper portion of the substrate 200;

[0174] Step S3: Figure 9As shown, the pixel layer 400 is subjected to etching treatment to obtain at least one pixel unit 100, and each pixel unit 100 obtained by etching is at least surrounded by one annular isolation groove 401, so that the annular isolation groove 401 at the outermost periphery of each pixel unit at least partially overlaps with the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit, and the non-overlapping area is reserved for the compound semiconductor; or, the annular isolation groove 401 at the outermost periphery of each pixel unit is reserved for the compound semiconductor to completely separate from the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit.

[0175] So that the top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203, and the bottom of the pixel unit 100 is electrically connected to the corresponding first-type electrode contact 202, and the second-type electrode contact 203 is formed on the periphery of the annular isolation groove 401 at the outermost periphery of each corresponding pixel unit 100.

[0176] In step S2, when the pixel layer 400 is connected to the upper part of the substrate 200, the pixel layer 400 is connected to the substrate 200 through the bonding layer 300.

[0177] When the pixel layer 400 and the substrate 200 are connected through the bonding layer 300, a hot-press bonding method can be used.

[0178] In some embodiments, referring to Figure 9 , step S3 can specifically include the following steps:

[0179] Step S31: An etching barrier layer 403 is arranged on the upper surface of the pixel layer 400, and the etching barrier layer 403 is subjected to etching treatment to obtain a patterned mask layer.

[0180] Step S32: As Figure 9 in stage c, the pixel layer 400 is etched by the mask layer to obtain at least one pixel unit 100, and at least one annular isolation groove 401 is formed at the periphery of each pixel unit 100, so that the annular isolation groove 401 at the outermost periphery of each pixel unit at least partially overlaps with the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit, and the non-overlapping area is reserved for the compound semiconductor; or,

[0181] the annular isolation groove 401 at the outermost periphery of each pixel unit is reserved for the compound semiconductor to completely separate from the annular isolation groove 401 at the outermost periphery of the adjacent pixel unit;

[0182] When the pixel layer 400 is etched by the mask layer, the second-type electrode filling hole 407 can also be etched above the second-type electrode contact 203, that is, the second-type electrode filling hole 407 is directly etched on the compound semiconductor layer at this time;

[0183] At this time, the compound semiconductor between the outermost annular partition groove 401 of each pixel unit and the adjacent second-type electrode filling hole 407 is retained as a non-luminous region 410 .

[0184] For example, the angle α of the pixel unit 100 obtained by etching can be 90°±45°. Preferably, the angle α of the pixel unit 100 can be 90°±20°. The angle α of the pixel unit 100 is the maximum angle between the sidewall of the pixel unit 100 and the upper surface of the substrate 200.

[0185] Step S33: Figure 9 In stage d, a first insulating layer 404 is deposited on the surface of the pixel layer 400 so that the first insulating layer 404 covers the inner wall of the annular groove 401 and the sidewalls of the pixel unit 100 , and a filling area 4011 surrounded by the first insulating layer 404 is formed inside the annular groove 401 ;

[0186] At this time, the inner wall of the second-type electrode filling hole 407 and the upper surface of the pixel layer 400 are also covered with the first insulating layer 404;

[0187] Step S34: Figure 9 In the middle e stage, the material at the bottom of the second-type electrode filling hole 407 is removed, so that the second-type electrode filling hole 407 passes through the bonding layer 300 and exposes the second-type electrode contact 203. It can be understood that this step is to remove all the material between the second-type electrode filling hole 407 and the bottom second-type electrode contact 203 to expose the second-type electrode contact 203.

[0188] Step S35: Figure 9 In the middle f stage, a second insulating layer 408 is deposited on the inner wall of the second type electrode filling hole 407;

[0189] Step S36: Figure 9 In the middle g stage, metal is filled in the second type electrode filling hole 407 to form an interconnected conductive member 600. At this time, the interconnected conductive member 600 is formed on the periphery of the outermost annular partition groove 401 of each corresponding pixel unit 100;

[0190] The interconnected conductive member 600 obtained in this way is a metal member;

[0191] Step S37: Figure 6 In the middle h stage, the top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203 through the interconnection electrode member.

[0192] After step S37, step S38 is further performed: preparing a lens on the top of the pixel layer 400, such as Figure 5As shown, the lens and the pixel unit 100 are one-to-one corresponding, or multiple pixel units 100 correspond to one lens.

[0193] In the lens preparation, the insulating medium layer can be backfilled first, and then the backfilled insulating medium layer is patterned and etched to form the lens; or after backfilling the insulating medium layer, CMP planarization is performed first, and then the lens material is plated and patterned to form the lens.

[0194] In the above process, the preparation of the second electrode filling hole 407 can also not be performed in step S32, but after the deposition of the first insulating layer 404 in step S33, at this time, the second electrode filling hole 407 can be directly through the bonding layer 300 to expose the second electrode contact 203.

[0195] In some embodiments, an ohmic contact layer 500 is further provided between the pixel layer 400 and the bonding layer 300, and when the pixel layer 400 is etched with a mask layer in step S32, the ohmic contact layer 500 can be etched to the inside of the ohmic contact layer 500 and above the lower surface thereof.

[0196] In some embodiments, in step S33, after forming the filling area 4011 surrounded by the first insulating layer 404 inside the annular isolation groove 401, air is also reserved in the filling area 4011 to form an air isolation layer 40112, that is, the filling area 4011 is formed with a hollow structure, or the filling area 4011 is filled with a first filler 40111 to make the filling area 4011 filled and form a solid structure.

[0197] In some embodiments, the width L4 of the second electrode filling hole 407 can be 0.1um-10um. Here, the width of the second electrode filling hole 407 can be understood as the maximum size of the second electrode filling hole 407 in the width direction (X direction).

[0198] In the above preparation method, when the second electrode filling hole 407 is opened on the pixel layer 400, the compound semiconductor between the annular isolation groove 401 at the outermost periphery of each pixel unit 100 and the adjacent second electrode filling hole 407 is reserved as a non-light-emitting area 410. Since the compound semiconductor material has good thermal conductivity, the compound semiconductor material of the non-light-emitting area 410 is reserved, which is more conducive to improving the heat dissipation effect of the LED display device.

[0199] In some embodiments, the bonding layer 300 can be made of metal. In step S34, the material at the bottom of the second-type electrode filling hole 407 is removed, so that when the second-type electrode filling hole 407 is formed to expose the second-type electrode contact 203 through the bonding layer 300, a metal fence, i.e., the first peripheral fence 301, is formed on the upper part of the bonding layer 300. The second insulating layer 408 deposited later is located on the inner wall of the first peripheral fence 301, and the interconnection conductive member 600 is located inside the first peripheral fence 301. The first peripheral fence 301 and the interconnection conductive member 600 are insulated and separated by the second insulating layer 408.

[0200] Further, as shown in Figure 10 , the top surface of the interconnection conductive member 600 can be higher than the first peripheral fence 301, and the height of the second insulating layer 408 can be the same as that of the interconnection conductive member 600, so as to better ensure the insulation and separation effect.

[0201] The interconnection conductive member 600 prepared by the above method is a metal member.

[0202] In other embodiments, the interconnection conductive member 600 can also have a structure with a core 601, which is a compound semiconductor. In the preparation, part of the compound semiconductor material above the second-type electrode contact 203 can be reserved as the core 601 of the interconnection conductive member 600, and the interconnection conductive member 600 is electrically connected to the second-type electrode contact 203 through the bonding layer 300.

[0203] For example, as shown in Figure 10 , in the specific preparation, the following preparation method can be used:

[0204] After the filling area 4011 is formed in step S33, as shown in Figure 10 a1 stage, the first cut groove 409 is etched in the pixel layer 400 area above the second-type electrode contact 203. The first cut groove 409 is annular, and penetrates the bonding layer 300. At this time, the compound semiconductor material surrounded by the inner wall of the first cut groove 409 is reserved as the core 601 of the interconnection conductive member 600. The bonding layer 300 below the core 601 is also reserved, so that the core 601 is electrically connected to the second-type electrode contact 203 through the bonding layer 300 below. At this time, the area surrounded by the inner wall of the first cut groove 409 (the core 601, the ohmic contact layer 500 below, and the bonding layer 300) constitutes the interconnection conductive member 600.

[0205] In the above process, the bonding layer 300 will be sputtered on the inner wall of the first groove 409 to form a metal fence - the first outer fence 301, and the interconnecting conductive part 600 is located inside the first outer fence 301; in addition, the bonding layer 300 below the internal core 601 of the interconnecting conductive part 600 will also form an internal fence part on its upper part, and the core 601 is located inside the internal fence part.

[0206] Then, step S33 is performed: a first insulating layer 404 is deposited on the upper surface of the pixel layer 400 so that the first insulating layer 404 covers the inner wall of the annular groove 401 and the sidewalls of the pixel unit 100. A filling area 4011 surrounded by the first insulating layer 404 is formed inside the annular groove 401.

[0207] At this time, air can be retained in the filling area 4011 to form an air barrier 40112, that is, a filling area 4011 with a hollow structure is formed, or a first filler 40111 is filled in the filling area 4011 so that the filling area 4011 is filled to form a solid structure.

[0208] Then, the following steps are performed: the second insulating layer 408 is filled in the first groove 409, so that the interconnected conductive member 600 is insulated and isolated from the surrounding compound semiconductor material.

[0209] Furthermore, the second insulating layer 408 may also cover the upper surface of the pixel layer 400 , so that the second insulating layer 408 on the upper surface of the pixel layer 400 covers the first insulating layer 404 .

[0210] Then, if Figures 11-16 In stage b1, the top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203 through the interconnected electrode member. For example, the top of the interconnected conductive member 600 can be electrically connected to the metal reinforcement 1200, and then the metal reinforcement 1200 is electrically connected to the top of the corresponding pixel unit 100 through the first conductive layer 700.

[0211] The metal reinforcement 1200 is made of metal material, which can better achieve current expansion and enhance conductivity.

[0212] In some embodiments, when the first groove 409 is opened on the pixel layer 400, the compound semiconductor between the outermost annular partition groove 401 of each pixel unit 100 and the adjacent first groove 409 is retained to form a non-luminous area 410. The so-called "non-luminous area 410" refers to an area that will not be used as a light-emitting unit.

[0213] By retaining the compound semiconductor material in the non-luminescent region 410 , the heat dissipation effect of the LED display device can be better improved.

[0214] The LED display device includes, but is not limited to, a Micro-LED, a Micro-Laser, and other display devices.

[0215] The LED display device obtained by the above embodiment realizes the independence of the pixel units by means of the annular grooves, and the interconnection conductive member is arranged on the compound semiconductor at the periphery of the pixel units, so that the compound semiconductor material is maximally reserved, the etching area of the compound material is reduced, the overall device heat conduction area is greatly increased, the heat aggregation problem of the pixel units can be effectively reduced, the working temperature of the device is greatly reduced, and the photoelectric performance and reliability performance of the LED device can be better guaranteed.

[0216] Embodiment Two

[0217] This embodiment will further describe the related structures of the LED display device of the present application in combination with Figures 12-14 , wherein Figure 10 are Figures 11-12 schematic diagrams of different setting forms of the annular groove 401 at M1 in the above-mentioned embodiments.

[0218] The periphery of each pixel unit 100 in the present application is provided with an annular groove 401, the inside of the annular groove 401 has a filling area 4011, the periphery of the filling area 4011 is surrounded by a first insulating layer 404 at the inner wall of the annular groove 401, and the filling area 4011 can contain an air isolation layer 40112 composed of air, or the filling area 4011 can be filled with a first filler 40111 to form a solid structure, which can have the following structures.

[0219] The first structure form:

[0220] As shown in Figure 12 , the upper part of the pixel layer 400 is provided with a first insulating layer 404, the first insulating layer 404 covers the upper surface of the non-light-emitting area 410 and the inner wall of the annular groove 401, and in addition, a thin film cover layer 405 covers the upper part of the pixel layer 400, and the upper part of the filling area 4011 is closed by the thin film cover layer 405. The first insulating layer 404 at the upper surface of the non-light-emitting area 410 is located below the thin film cover layer 405.

[0221] Preferably, the thin film cover layer 405 is an insulating medium.

[0222] In some embodiments, the thin film cover layer 405 further includes a downwardly protruding extension 4051, the extension 4051 extends into the inside of the filling area 4011.

[0223] Among them, as Figure 13As shown, the extension portion 4051 may only extend into the upper portion of the filling area 4011 , so that a hollow portion remains at the lower portion of the filling area 4011 , thereby forming the above-mentioned air barrier 40112 at the lower portion of the filling area 4011 .

[0224] Or, as Figures 15-16 As shown, the extension portion 4051 serves as the first filler 40111, and the filling area 4011 is filled with the first filler 40111 to form a solid structure. The material of the first filler 40111 is the same as that of the thin film covering layer 405, which is an insulating medium.

[0225] Furthermore, when the filler has an air barrier layer 40112 inside, the minimum dimension of the air barrier layer 40112 along the width direction needs to be greater than 0, and the maximum dimension L3 of the air barrier layer 40112 along the width direction can be 0.01um to 8um.

[0226] The thin film cover layer 405 may be made of one or more materials such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, and polyimide.

[0227] In some embodiments, the sidewalls of the pixel unit 100 are also covered with a first insulating layer 404 to ensure insulation between the first semiconductor layer 101 and the second semiconductor layer 103 in the pixel unit 100. The upper portion of the pixel unit 100 is at least partially covered with the first insulating layer 404. The first insulating layer 404 on the upper portion of the pixel unit 100 is located below the thin film covering layer 405.

[0228] In some embodiments, the thickness of the thin film cover layer 405 is 0.05 μm to 8 μm. It is understood that the thickness of the thin film cover layer 405 here refers to the thickness of the thin film cover layer 405 on the top of the pixel unit 100 , excluding the extension portion 4051 .

[0229] The second structural form:

[0230] like Figure 14 As shown, this method does not require the thin film covering layer 405, and only the first insulating layer 404 is provided on the upper part of the pixel layer 400. A gap is retained in the filling area 4011 inside the annular partition 401 to accommodate air to form an air partition layer 40112, that is, a filling area 4011 with a hollow structure is formed; or, the filling area 4011 is filled with a first filler 40111 to form a solid structure.

[0231] The first filler 40111 may be an insulating medium or metal.

[0232] For example, the filling area 4011 may be directly filled with the material of the first insulating layer 404 ; of course, a filler made of a material different from that of the first insulating layer 404 may also be used to fill the filling area 4011 .

[0233] The third structural form:

[0234] As shown in Figures 17-19 , the inner wall of the annular groove 401 is sequentially covered with a first insulating layer 404 and a first reflective layer 406, that is, the outer part of the first insulating layer 404 at the inner wall of the annular groove 401 is further provided with the first reflective layer 406, so that the filling area 4011 is filled with air to form an air separation layer 40112, and the periphery of the air separation layer 40112 is surrounded by the first reflective layer 406.

[0235] Alternatively, the first reflective layer 406 serves as the first filler 40111, and the filling area 4011 is filled with the first filler 40111 to form a solid structure.

[0236] The first reflective layer 406 can be a reflective metal layer, for example, a high-reflectivity metal layer of Al, Ag, Au, Rh, or the like in a single layer or a stack, to form an omnidirectional reflector (ODR) structure, thereby better preventing the problem of light crosstalk between pixels.

[0237] Embodiment three

[0238] This embodiment will further describe the related structures of the LED display device of the present application. Figure 4

[0239] The pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom, the second-type electrode contact 203 is used to electrically connect the first semiconductor layer 101 in the corresponding pixel unit 100, and the first-type electrode contact 202 is used to electrically connect the second semiconductor layer 103 in the corresponding pixel unit 100.

[0240] Among them, one of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.

[0241] When etching the annular groove 401, according to the etching depth of the annular groove 401, the annular groove 401 can have the following forms:

[0242] The first form: please refer to Figure 19 and Figure 19 , Figure 17 as Figure 17 ​Another structural form at M3 in FIG. In this form, an ohmic contact layer 500 is further disposed between the pixel layer 400 and the substrate 200. The ohmic contact layer 500 is located between the second semiconductor layer 103 and the bonding layer 300. The lower end of the annular groove 401 extends directly to the ohmic contact layer 500, and may extend into the interior thereof and be located above the lower surface of the ohmic contact layer. The upper end of the annular groove 401 extends at least to the upper surface of the first semiconductor layer 101, for example, directly to the upper surface of the first semiconductor layer 101 or further extending above the etch stop layer 403.

[0243] The second form: see Figure 18 and Figure 18 , Figure 17 Shown Figures 20-22 The internal structure at M3 in FIG. In this form, the lower end of the annular groove 401 is higher than the upper surface of the ohmic contact layer 500 and lower than the lower surface of the active layer 102. That is, the lower end of the annular groove 401 is located in the area between the lower surface of the active layer 102 and the upper surface of the ohmic contact layer 500.

[0244] Example 4

[0245] This embodiment will combine Figure 21 , further describes the relevant structure of the LED display device of this application.

[0246] The main difference between this embodiment and the above embodiment is that each pixel unit 100 is surrounded by at least two annular partitions 401, and compound semiconductors are retained between adjacent annular partitions 401 on the periphery of each pixel unit 100 to form partition walls 402, that is, the partition walls 402 themselves are also made of compound semiconductor material.

[0247] The method for preparing the semiconductor device in this embodiment is substantially the same as that in the first embodiment, except that when etching the pixel layer 400 using the mask layer to obtain at least one pixel unit 100, the etching is performed so as to form at least two annular partitions 401 around the periphery of each pixel unit 100, so that the compound semiconductor between adjacent annular partitions 401 around the periphery of each pixel unit 100 is retained to form partition walls 402.

[0248] In this embodiment, each pixel unit 100 is surrounded by at least two annular partition grooves 401. While improving the heat dissipation effect, the partition wall 402 structure can also better prevent metal atoms from diffusing to the side walls of the pixel unit 100, thereby better reducing the leakage risk of the device and improving the reliability of the device.

[0249] For example, when making specific arrangements, you can follow Figure 20 The arrangement is shown, wherein Figure 20 For the Figure 21A cross-sectional view of a pixel unit and its peripheral structure obtained at the middle C2-C2 cross section; as shown in Figure 22 Each pixel unit 1 can correspond to one interconnection conductive member 600 at the periphery, and the pixel unit 100 is connected to the corresponding interconnection conductive member 600 at the periphery; or, as shown in Figures 23-24 Each pixel unit 100 can correspond to multiple interconnection conductive members 600 at the periphery, and the multiple interconnection conductive members 600 are connected to the pixel unit 100, for example, four interconnection conductive members 600 can be arranged at the periphery of the pixel unit 100, and the four interconnection conductive members 600 are arranged outside the annular groove 401 at the outermost periphery of the pixel unit 100 and are electrically connected to the pixel unit 100 at the middle part.

[0250] Embodiment Five

[0251] This embodiment will further describe the related structure of the LED display device of the present application. Figure 23

[0252] In this embodiment, the pixel layer 400 is connected to the first opening area of the metal reinforcing member 1200 above, so as to achieve better current expansion, and also to further increase the heat conduction capacity and improve the reliability of the LED display device. The metal reinforcing member can be arranged in the following forms:

[0253] In some embodiments, as shown in Figure 24 The upper end of the interconnection conductive member 600 is in direct contact with the first conductive layer 700, and the first opening area of the metal reinforcing member 1200 is connected to the upper part of the first conductive layer 700;

[0254] In some embodiments, as shown in Figures 25-26 The upper end of the interconnection conductive member 600 is in direct contact with the first conductive layer 700, and the first opening area of the metal reinforcing member 1200 is connected to the upper part of the first conductive layer 700;

[0255] It can be understood that the first conductive layer 700 is located at the upper part of the pixel layer 400, and the first conductive layer 700 is in contact with the top of the pixel unit 100 to achieve electrical connection. The pixel unit 100 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in order from top to bottom, and the first conductive layer 700 is actually in contact with the first semiconductor layer 101 of the pixel unit 100 to achieve electrical connection.

[0256] ​The first conductive layer 700 can be a transparent conductive layer. When the first conductive layer 700 is connected to the pixel unit 100, if the pixel unit 100 is covered with non-transparent material or insulating material, it needs to be partially removed (the removal can be performed by planarization or etching, etc.) to expose the first semiconductor layer 101 on the top of the pixel unit 100, and then the first semiconductor layer 101 and the first conductive layer 700 are brought into contact.

[0257] The metal reinforcement 1200 may be made of one or more materials selected from the group consisting of Pt, Ni, Al, Ti and Au.

[0258] Example 6

[0259] This embodiment will combine Figures 26-26 , further describes the relevant structure of the LED display device of this application.

[0260] In this embodiment, the bonding layer 300 is a metal layer, and a first dielectric layer is provided between the pixel layer 400 and the bonding layer 300. The first dielectric layer is a low refractive index layer. The bonding layer 300 can be a metal layer with a high reflectivity to form a light ODR (omnidirectional reflector) structure, thereby better improving the brightness of the device.

[0261] Exemplarily, the first dielectric layer may include one or more of silicon oxide, silicon nitride, aluminum oxide, or magnesium fluoride. These materials all have a relatively low refractive index. Of course, other materials with a relatively low refractive index may also be used.

[0262] In some embodiments, the thickness of the first dielectric layer is 0.01 um to 0.5 um.

[0263] Exemplarily, the bonding layer 300 may include one or more of Al, Rh, Ag, or Au, all of which have high reflectivity. Of course, other films with high reflectivity may also be used.

[0264] In some embodiments, the bonding layer 300 has a thickness of 0.01 um to 0.5 um.

[0265] Further, if Figure 5 As shown, the first dielectric layer is provided with a first opening region in the area below the pixel unit 100. The bonding layer 300 is provided with an embedded portion 302 corresponding to the first opening region. The embedded portion 302 is embedded in the corresponding first opening region. The bonding layer 300 is connected to the bottom of the pixel unit 100 via the embedded portion 302, thereby ensuring good contact stability and reliability. Furthermore, the bonding layer 300 is in contact with the ohmic contact layer 500 via the embedded portion 302, and the bottom of the pixel unit 100 is in contact with the ohmic contact layer 500 for electrical connection.

[0266] Embodiment Seven

[0267] This embodiment will further describe the related structure of the LED display device of the present application in combination with Figure 27 , Figure 28 and Figure 5 .

[0268] The upper surface of the driving wafer in this embodiment is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit 100) to form an image display area 201.

[0269] Among them, the bonding layer 300 above each display area 201 is continuously arranged to further retain the bonding layer 300 material, improve the heat dissipation area, and thus improve the heat dissipation effect of the device, and at the same time, it is more conducive to the connection of the bonding layer 300 and the electrode contact. Non-alignment can be used for bonding.

[0270] When arranging the first type of electrode contact 202, the following forms can be used:

[0271] In one way: the bottom of the pixel unit 100 is electrically connected to the corresponding first type of electrode contact 202, as shown in Figure 27 , the first type of electrode contact 202 is located inside the display area 201 where the corresponding pixel unit 100 is located, for example, the first type of electrode contact 202 can be arranged inside the display area 201 corresponding to each pixel unit 100 directly below.

[0272] In another way: the bottom of the pixel unit 100 is electrically connected to the corresponding first type of electrode contact 202, as shown in Figure 28 and Figure 28 , the first type of electrode contact 202 is located at the periphery of the display area 201 where the corresponding pixel unit 100 is located, that is, the first type of electrode contact 202 is no longer arranged inside the display area 201.

[0273] For example, as shown in ​ , a peripheral electrode contact area 800 can be arranged at the periphery of the display area 201 on the driving wafer, and the first type of electrode contact 202 is arranged at the peripheral electrode contact area 800.

[0274] A plurality of interfaces 900 are also arranged on the driving wafer to connect external circuit devices (signal source or power supply, etc.), and the above-mentioned peripheral electrode contact area 800 can be connected / disconnected with the above-mentioned interface 900 as needed.

[0275] All the optional technical solutions above can be combined in any manner to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0276] It should be noted that the above embodiments are merely examples for clear illustration, and are not limitations on the embodiments. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and also impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An LED display device, characterized by: The application relates to a compound semiconductor display device, comprising: a substrate, which is a driving wafer, wherein a first type of electrode contact and a second type of electrode contact are arranged on the driving wafer, and the polarities of the first type of electrode contact and the second type of electrode contact are opposite; a pixel layer, which is a compound semiconductor layer, wherein the pixel layer is arranged on the upper portion of the substrate, and the pixel layer comprises pixel units, the periphery of each pixel unit is surrounded by at least one annular isolation groove, and the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of an adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved for the compound semiconductor; or the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of an adjacent pixel unit are completely separated from each other by the compound semiconductor reserved therebetween; wherein the top of each pixel unit is electrically connected to the corresponding second type of electrode contact, the bottom of the pixel unit is electrically connected to the corresponding first type of electrode contact, and the second type of electrode contact is formed on the periphery of the outermost annular isolation groove of each corresponding pixel unit.

2. The LED display device of claim 1, wherein: The application further comprises an interconnecting conductive member, and the top of each pixel unit is electrically connected to the corresponding second type of electrode contact through the interconnecting conductive member; and the interconnecting conductive member is formed on the periphery of the outermost annular isolation groove of each corresponding pixel unit.

3. The LED display device of claim 2, wherein: The compound semiconductor reserved between the outermost annular isolation groove of each pixel unit and the interconnecting conductive member forms a non-light-emitting area.

4. The LED display device of claim 3, wherein: The upper portion of the pixel layer is provided with a first insulating layer, the first insulating layer covers the upper surface of the non-light-emitting area and the inner wall of the annular isolation groove, the inner portion of the annular isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer at the inner wall of the annular isolation groove, and the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.

5. The LED display device of claim 4, wherein: The upper portion of the pixel layer is further covered with a thin film covering layer, the upper portion of the filling area is closed by the thin film covering layer, and the first insulating layer at the upper surface of the non-light-emitting area is located below the thin film covering layer.

6. The LED display device of claim 5, wherein: The thin film covering layer comprises an extension protruding downward, the extension extends into the inner portion of the filling area, the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air isolation layer. Alternatively, the extension serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

7. The LED display device of claim 4, wherein: The filling area contains air to form an air isolation layer, and the periphery of the air isolation layer is surrounded by the first reflective layer. Alternatively, the first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

8. The LED display device of claim 4, wherein: The upper portion of the pixel layer is further provided with a first conductive layer, the first conductive layer is at least partially located above the first insulating layer, the upper end of the interconnecting conductive member is electrically connected to the top of the pixel unit through the first conductive layer, and the lower end is electrically connected to the corresponding second type of electrode contact.

9. The LED display device of claim 8, wherein: The upper end of the interconnection conductive member is in direct contact with the first conductive layer, and the upper part of the first conductive layer is connected with a metal reinforcing member; or the upper end of the interconnection conductive member is in direct contact with a metal reinforcing member, and the metal reinforcing member is connected with the first conductive layer.

10. The LED display device according to claim 4, characterized in that: An etching blocking layer is arranged at the upper surface of the non-light-emitting area, and the first insulating layer is arranged above the etching blocking layer.

11. The LED display device of claim 2, wherein: The pixel layer and the substrate are bonded through a bonding layer, and the bottom surface of the annular groove is not lower than the upper surface of the bonding layer.

12. The LED display device of claim 11, wherein: The interconnection conductive member is a metal member.

13. The LED display device of claim 11, wherein: The interconnection conductive member comprises a core, the core is a compound semiconductor, and the core is connected with the corresponding second electrode contact through a bonding layer.

14. The LED display device according to claim 11, wherein: The bonding layer is a metal layer, a first peripheral fence is formed on the upper part of the bonding layer, the interconnection conductive member is arranged inside the first peripheral fence, and the first peripheral fence and the interconnection conductive member inside are isolated through a second insulating layer.

15. The LED display device of claim 11, wherein: The upper surface of the driving wafer is divided into at least one display area, each display area is covered by at least one pixel unit, and the bonding layer above each display area is arranged continuously.

16. The LED display device of claim 15, wherein: The bottom of each pixel unit is electrically connected with the corresponding first electrode contact, and the first electrode contact is located inside the display area where the corresponding pixel unit is located, or the first electrode contact is located at the periphery of the display area where the corresponding pixel unit is located.

17. The LED display device of claim 11, wherein: The bonding layer is a metal layer, and a first dielectric layer is further arranged between the pixel layer and the bonding layer.

18. The LED display device of claim 17, wherein: The first dielectric layer is provided with a first opening area in the region below the pixel unit, the bonding layer is provided with an embedded part corresponding to the first opening area, the embedded part is embedded in the corresponding first opening area, and the bonding layer is connected with the bottom of the pixel unit through the embedded part.

19. The LED display device of claim 1, wherein: The periphery of each pixel unit is surrounded by at least two annular grooves, and a partition wall is formed by the compound semiconductor between the adjacent annular grooves of the periphery of each pixel unit.

20. The LED display device of claim 1, wherein: The pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second electrode contact is used for electrically connecting with the first semiconductor layer in the corresponding pixel unit, the first electrode contact is used for electrically connecting with the second semiconductor layer in the corresponding pixel unit, the lower end of the annular groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the annular groove extends at least to the upper surface of the first semiconductor layer.

21. The LED display device of claim 20, wherein: An ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the annular groove extends between the lower surface of the active layer and the lower surface of the ohmic contact layer.

22. The LED display device of claim 1, wherein: The maximum size of the annular groove in the width direction is L2, and L2 is 0.02 um to 10 um.

23. The LED display device of claim 1, wherein: The top of the pixel layer is provided with a lens, and the lens covers at least one pixel unit.

24. A method for preparing an LED display device, characterized in that: The method comprises the following steps: selecting a driving wafer as a substrate, the driving wafer being provided with first electrode contacts and second electrode contacts with opposite polarities; and selecting a compound semiconductor layer as a pixel layer; connecting the pixel layer to the upper part of the substrate; and connecting the pixel layer to the upper part of the substrate. The pixel layer is etched to obtain at least one pixel unit. The periphery of each pixel unit obtained by etching is surrounded by at least one annular isolation groove. The annular isolation groove of the outermost periphery of each pixel unit and the annular isolation groove of the outermost periphery of the adjacent pixel unit at least partially overlap, and the compound semiconductor is reserved in the non-overlapping area. Alternatively, the compound semiconductor is reserved between the annular isolation groove of the outermost periphery of each pixel unit and the annular isolation groove of the outermost periphery of the adjacent pixel unit to completely separate each other. The top of each pixel unit is electrically connected to the corresponding second electrode contact, the bottom of the pixel unit is electrically connected to the corresponding first electrode contact, and the second electrode contact is formed on the periphery of the annular isolation groove of the outermost periphery of each pixel unit.

25. The method of claim 24, wherein: When the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

26. The method of claim 25, wherein: When the top of each pixel unit is electrically connected to the corresponding second electrode contact, the method comprises, A second electrode filling hole is formed in the compound semiconductor layer, and the second electrode filling hole penetrates through the bonding layer. A metal is filled in the second electrode filling hole to form an interconnection conductive part, and the interconnection conductive part is formed on the periphery of the annular isolation groove of the outermost periphery of each pixel unit. The top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive part.

27. The method of claim 26, wherein: When the second electrode filling hole is formed in the compound semiconductor layer, the compound semiconductor between the annular isolation groove of the outermost periphery of each pixel unit and the adjacent second electrode filling hole is reserved to form a non-light-emitting area.

28. The method of claim 25, wherein: When the top of each pixel unit is electrically connected to the corresponding second electrode contact, the method comprises, A first cutting groove is formed in the compound semiconductor layer, the first cutting groove is annular, and the first cutting groove penetrates through the bonding layer. The area surrounded by the inner wall of the first cutting groove is reserved to form an interconnection conductive part. The interconnection conductive part comprises a core, the core is a compound semiconductor, the core is connected to the corresponding second electrode contact through the underlying bonding layer, and the interconnection conductive part is formed on the periphery of the annular isolation groove of the outermost periphery of each pixel unit. The top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive part.

29. The method of claim 28, wherein: When the first cutting groove is formed in the compound semiconductor layer, the compound semiconductor between the annular isolation groove of the outermost periphery of each pixel unit and the adjacent first cutting groove is reserved to form a non-light-emitting area.

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