LED display device and preparation method

Abstract

The invention relates to an LED display device and a preparation method, the LED display device comprises a substrate and a pixel layer, the pixel layer comprises pixel units, the periphery of each pixel unit is at least surrounded by an annular partition groove, each pixel unit is at least partially overlapped with the outermost annular partition groove of the adjacent pixel unit, and the outermost annular partition groove of each pixel unit is at least partially overlapped with the outermost annular partition groove of the adjacent pixel unit. The compound semiconductor is reserved in the non-overlapping region; or, a compound semiconductor is reserved between each pixel unit and the outermost annular partition groove of the adjacent pixel unit, so that the pixel units and the adjacent pixel unit are completely separated from each other; the top of each pixel unit is electrically connected with the second type of electrode contacts, the bottom of each pixel unit is electrically connected with the first type of electrode contacts, the projection area of each pixel unit on the substrate is defined as a first projection area, and the second type of electrode contacts are formed in the first projection area of the corresponding pixel unit. The invention further discloses a preparation method of the LED display device. The photoelectric performance and the reliability of the LED display device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an LED display device and a preparation method thereof. BACKGROUND

[0002] An LED display chip usually comprises a plurality of pixel units (i.e. light emitting units). With the development of semiconductor display technology, the size of the display chip is increasingly reduced, and the pixel density is also increasingly high, which also leads to a higher and higher heat density of the chip, and heat is more easily concentrated. The source of heat of the LED chip is mainly the conversion efficiency problem of electrons and outgoing photons. Most of the electric energy that is not converted into outgoing light energy will be converted into heat energy. These heat energy will cause the temperature of the LED chip to rise. If the temperature of the LED chip is too high, it will lead to problems such as low light efficiency, wavelength shift and low service life of the LED photoelectric device, and even seriously affect the stability and reliability of the LED display device, which cannot meet the use requirements. SUMMARY

[0003] Therefore, the technical problem to be solved by the present application is to improve the heat dissipation capacity of the LED display device in the prior art, so that the LED display device can stably emit light and ensure the photoelectric performance and reliable performance of the LED display device.

[0004] To solve the above technical problems, the present application provides an LED display device, comprising,

[0005] a substrate, the substrate is a driving wafer, the driving wafer is provided with first electrode contacts and second electrode contacts, the polarities of the first electrode contacts and the second electrode contacts are opposite;

[0006] a pixel layer, the pixel layer is a compound semiconductor layer, the pixel layer is located on the upper part of the substrate, the pixel layer comprises pixel units, the periphery of each pixel unit is surrounded by at least one annular isolation groove, the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with compound semiconductor; or, the compound semiconductor is reserved between the annular isolation groove at the outermost periphery of each pixel unit and the annular isolation groove at the outermost periphery of the adjacent pixel unit to completely separate each other;

[0007] wherein the top of each pixel unit is electrically connected with the corresponding second electrode contact, the bottom of the pixel unit is electrically connected with the corresponding first electrode contact, the projection area of each pixel unit on the substrate is defined as a first projection area, and the second electrode contact is formed in the inside of the first projection area of the corresponding pixel unit.

[0008] In one embodiment of the present application, a plurality of second type electrode contacts are arranged in each of the first projection regions, and the plurality of second type electrode contacts are distributed in a ring shape.

[0009] In one embodiment of the present application, the first type electrode contacts and the plurality of second type electrode contacts are arranged in the interior of each of the first projection regions, and the plurality of second type electrode contacts are arranged around the periphery of at least one of the first type electrode contacts.

[0010] In one embodiment of the present application, the LED display device further comprises an interconnecting conductive member, and the top of each of the pixel units is electrically connected to the corresponding second type electrode contact through the interconnecting conductive member, and the interconnecting conductive member is formed in the interior of each of the corresponding pixel units.

[0011] In one embodiment of the present application, in each of the pixel units, the compound semiconductor on the periphery of the interconnecting conductive member constitutes a light emitting region, the top of the light emitting region is electrically connected to the upper end of the interconnecting conductive member, and the bottom is electrically connected to the corresponding second type electrode contact; the top of the light emitting region has an electrical contact region, and the light emitting region is connected to the upper end of the interconnecting conductive member through the electrical contact region.

[0012] In one embodiment of the present application, the inner wall of the ring-shaped groove is covered with a first insulating layer, the interior of the ring-shaped groove has a filling region, the periphery of the filling region is surrounded by the first insulating layer on the inner wall of the ring-shaped groove, and the interior of the filling region is filled with air to form an air layer, or the filling region is filled with a first filler to form a solid structure.

[0013] In one embodiment of the present application, the upper part of the pixel unit is at least partially covered with a first insulating layer, and the region not covered with the first insulating layer forms the electrical contact region.

[0014] In one embodiment of the present application, the upper part of the pixel unit is further covered with a first conductive layer, the first insulating layer on the upper part of the pixel unit is at least partially covered with the first conductive layer, the middle part of the top surface of the light emitting region in the pixel unit forms the electrical contact region, and all of the electrical contact regions in the pixel unit and the top of the interconnecting conductive member are in contact with the same first conductive layer.

[0015] In one embodiment of the present application, the top of each of the interconnecting conductive members in the pixel unit is connected with a second conductive layer, and each of the second conductive layers is in contact with the electrical contact region of the light emitting region on the periphery of the corresponding interconnecting conductive member.

[0016] In one embodiment of the present application, the upper portion of the pixel unit is only covered by the first conductive layer, and the top of the electrical contact area and the interconnecting conductive member of each of the pixel units is in contact with the same first conductive layer.

[0017] In one embodiment of the present application, the top of each of the interconnecting conductive members of the pixel unit is connected with a second conductive layer, and each of the second conductive layers is in contact with the electrical contact area of the peripheral light-emitting area of the corresponding interconnecting conductive member, and the area on the top surface of each of the light-emitting areas not in contact with the second conductive layer is exposed.

[0018] In one embodiment of the present application, the upper portion of the pixel layer is further covered by a thin film cover layer, and the upper portion of the filling area is closed by the thin film cover layer.

[0019] In one embodiment of the present application, the thin film cover layer comprises a downwardly protruding extension, and the extension extends into the filling area, and the extension only extends to the upper portion of the filling area, and the lower portion of the filling area forms the air gap.

[0020] Alternatively, the extension is the first filler, and the filling area is filled with the first filler to form a solid structure.

[0021] In one embodiment of the present application, the filling area is filled with air to form an air gap, and the air gap is surrounded by the first reflective layer.

[0022] Alternatively, the first reflective layer is the first filler, and the filling area is filled with the first filler to form a solid structure.

[0023] In one embodiment of the present application, the pixel layer and the substrate are bonded by a bonding layer, and the bottom surface of the annular gap is not lower than the upper surface of the bonding layer.

[0024] In one embodiment of the present application, the interconnecting conductive member is a metal member.

[0025] In one embodiment of the present application, the upper surface of the driving wafer is divided into at least one display area, each of the display areas is covered by at least one pixel unit, and the bonding layer above each of the display areas is continuously arranged.

[0026] In one embodiment of the present application, the bottom of each of the pixel units is electrically connected with the corresponding first electrode contact, and the first electrode contact is located at the periphery of the display area where the corresponding pixel unit is located.

[0027] In one embodiment of the present application, each of the pixel unit periphery is surrounded by at least two ring-shaped grooves, and compound semiconductors are reserved between adjacent ring-shaped grooves of each pixel unit periphery to form a partition wall.

[0028] In one embodiment of the present application, the pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second type of electrode contact is used to electrically connect with the first semiconductor layer in the corresponding pixel unit, the first type of electrode contact is used to electrically connect with the second semiconductor layer in the corresponding pixel unit, the lower end of the ring-shaped groove extends to between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the ring-shaped groove extends to at least the upper surface of the first semiconductor layer.

[0029] In one embodiment of the present application, an ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the ring-shaped groove extends to between the lower surface of the active layer and the lower surface of the ohmic contact layer.

[0030] In one embodiment of the present application, the maximum size of the ring-shaped groove in the width direction is L2, L2, L2 is 0.02um-10um.

[0031] In one embodiment of the present application, the top surface of the pixel unit is a convex-concave uneven plane.

[0032] The present application further discloses a preparation method of an LED display device, comprising the following steps:

[0033] A driving wafer is selected as the substrate, the driving wafer is provided with the first type of electrode contact and the second type of electrode contact with opposite polarities; and a compound semiconductor layer is selected as the pixel layer;

[0034] The pixel layer is connected to the upper part of the substrate;

[0035] The pixel layer is etched to obtain at least one pixel unit, each pixel unit obtained by etching is surrounded by at least one ring-shaped groove, so that the ring-shaped groove of the outermost periphery of each pixel unit and the ring-shaped groove of the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved with compound semiconductors; or the ring-shaped groove of the outermost periphery of each pixel unit and the ring-shaped groove of the outermost periphery of the adjacent pixel unit are reserved with compound semiconductors to be completely separated from each other;

[0036] The top of each pixel unit is electrically connected with the corresponding second type of electrode contact, the bottom of the pixel unit is electrically connected with the corresponding first type of electrode contact, the projection area of the pixel unit on the substrate is defined as a first projection area, and the second type of electrode contact is formed in the inside of the first projection area of each corresponding pixel unit.

[0037] In one embodiment of the present application, when the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

[0038] In one embodiment of the present application, when the top of each pixel unit is electrically connected to the corresponding second-type electrode contact, the method comprises,

[0039] A second-type electrode filling hole is formed in the compound semiconductor layer, and the second-type electrode filling hole penetrates through the bonding layer;

[0040] A metal is filled in the second-type electrode filling hole to form an interconnecting conductive member, and the interconnecting conductive member is formed in the interior of each corresponding pixel unit;

[0041] The top of each pixel unit is electrically connected to the corresponding second-type electrode contact through the interconnecting electrode member.

[0042] In one embodiment of the present application, when the top of each pixel unit is electrically connected to the corresponding second-type electrode contact through the interconnecting electrode member, the method comprises making the compound semiconductor in the pixel unit located at the periphery of the interconnecting conductive member constitute a light-emitting region, making the top of the light-emitting region at the periphery of the upper end of the interconnecting conductive member electrically connected, and making the lower end of the interconnecting conductive member electrically connected to the corresponding second-type electrode contact.

[0043] In one embodiment of the present application, when the top of the light-emitting region at the periphery of the upper end of the interconnecting conductive member is electrically connected, the method comprises making at least a part of the top of the light-emitting region exposed to form an electrical contact region, and making the light-emitting region connected to the upper end of the interconnecting conductive member through the electrical contact region.

[0044] The above technical solution of the present application has the following advantages compared with the prior art:

[0045] The LED display device of the present application has good heat dissipation capacity, can make the LED display device emit light stably, better guarantee the photoelectric performance and reliability of the LED display device, and improve the working life of the LED display device. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the accompanying drawings.

[0047] Figure 1 is a structural schematic diagram of an LED display device in the prior art;

[0048] Figure 2is a top view of an LED display device in the present application;

[0049] Figure 3 is Figure 2 is a partial enlarged view of DD in FIG. 1;

[0050] Figure 4 is along Figure 2 is a partial sectional view taken along D2-D2 in FIG. 1;

[0051] Figure 5 is along Figure 2 is a partial sectional view taken along D1-D1 in FIG. 1;

[0052] Figure 6 is Figure 5 is a partial enlarged view of M1 in FIG. 1;

[0053] Figure 7 is a structure diagram of a second ring-shaped groove;

[0054] Figure 8 is a structure diagram of a third ring-shaped groove;

[0055] Figure 9 is a structure diagram of a fourth ring-shaped groove;

[0056] Figure 10 is a structure diagram of a fifth ring-shaped groove; Figure 4 is a structure diagram of an LED display device shown in FIG. 1;

[0057] Figure 11 is a structure diagram of an LED display device shown in FIG. 1; Figure 4 is a structure diagram of an LED display device shown in FIG. 1;

[0058] Figure 12 is a structure diagram of a compound semiconductor layer in the present application;

[0059] Figure 13 is a bonding flow chart of a pixel layer and a driving wafer in the present application;

[0060] Figure 14 is a preparation flow chart of an LED display device shown in FIG. 1; Figure 4 is a preparation flow chart of an LED display device shown in FIG. 1;

[0061] Figure 15 is a structure diagram of a second LED display device in the present application;

[0062] Figure 16 is a structure diagram of an LED display device shown in FIG. 1; Figure 15 is a structure diagram of an LED display device shown in FIG. 1;

[0063] Figure 17 is a structure diagram of a third LED display device in the present application;

[0064] Figure 18 is a structure schematic diagram of the LED display device provided with metal reinforcing members Figure 17 is a structure schematic diagram of the LED display device provided with metal reinforcing members

[0065] Figure 19 is a structure schematic diagram of the fourth LED display device in the present application

[0066] Figure 20 is a structure schematic diagram of the LED display device provided with roughening treatment Figure 19 is a structure schematic diagram of the LED display device provided with roughening treatment

[0067] Figure 21 is a top view schematic diagram of the fifth LED display device in the present application

[0068] Figure 22 is a top view schematic diagram of the fifth LED display device in the present application Figure 21 is a partial sectional view taken at E2-E2 in the present application

[0069] Figure 23 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0070] Figure 24 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application Figure 23 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0071] Figure 25 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0072] Figure 26 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0073] Figure 27 is a structure schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application Figure 26 is a top view schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0074] Figure 28 is a top view schematic diagram of the LED display device provided with annular grooves with certain etching depth in the present application

[0075] Explanation of the drawing marks in the specification:

[0076] 100, pixel unit; 101, first semiconductor layer; 102, active layer; 103, second semiconductor layer; 104, light emitting area; 1041, electrical contact area

[0077] 200, substrate; 201, display area; 202, first type of electrode contact; 203, second type of electrode contact

[0078] 300, bonding layer; 301, first peripheral bar

[0079] 400, pixel layer; 401, annular groove; 4011, filling area; 40111, first filler; 40112, air separation layer; 402, partition wall; 403, etching barrier layer; 404, first insulating layer; 405, thin film cover layer; 4051, extension; 406, first reflective layer; 407, second type electrode filling hole; 408, second insulating layer;

[0080] 500, ohmic contact layer;

[0081] 600, interconnection conductive piece;

[0082] 700, first conductive layer;

[0083] 800, peripheral electrode contact area; 900, interface;

[0084] 1000, second conductive layer; 1100, metal reinforcement; DETAILED DESCRIPTION

[0085] The present application will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand and implement the present application. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use.

[0086] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0087] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0088] The LED display device in the prior art has the problem of poor heat dissipation effect. Therefore, the present application provides an LED display device to improve its heat dissipation capacity, so as to better ensure the photoelectric performance and reliability of the LED display device.

[0089] It should be noted that the compound semiconductor layer in the present application refers to a layer structure with a certain thickness prepared from a compound semiconductor material. Compound semiconductors generally refer to compounds formed by two or more elements, including crystalline inorganic compounds (such as III-V, II-VI compound semiconductors) and oxide semiconductors, etc. The compound semiconductors involved in the present application are mainly light emitting diode epitaxial materials, such as InGaN ternary material system or AlGaInP quaternary material system, etc., which can cover the full wavelength range from ultraviolet, visible light and infrared, and the substrate materials can be GaN, Si, SiC, sapphire, GaAs, InP, etc.

[0090] Taking the field of Micro-LED as an example, some compound semiconductor materials involved in the present application are shown in Table 1. In some practical applications, the film layer of the compound semiconductor will be more complex, or there will be a situation of cross use of materials. Typical compound semiconductors mainly include P-type semiconductor material, N-type semiconductor material and MQW active quantum well sandwiched between them and other functional layers (barrier layer, confinement layer, waveguide layer, buffer layer, etc.):

[0091] Table 1: Compound semiconductor film layer material table

[0092]

[0093]

[0094] The related structure of the LED display device of the present application will be further described below in combination with the following specific embodiments.

[0095] Embodiment one

[0096] Referring to Figures 2-14 The embodiment discloses an LED display device, which comprises a substrate 200 and a pixel layer 400.

[0097] The substrate 200 is a driving wafer, and the first electrode contact 202 and the second electrode contact 203 are arranged on the driving wafer, the polarities of the first electrode contact 202 and the second electrode contact 203 are opposite, one of which is positive and the other of which is negative. It can be understood that the first electrode contact 202 and the second electrode contact 203 need to be insulated and isolated to prevent short circuit caused by direct contact.

[0098] The pixel layer 400 is a compound semiconductor layer. It can be understood that the compound semiconductor layer refers to a layer body with a certain thickness prepared from a compound semiconductor material.

[0099] The pixel layer 400 is located on the upper portion of the substrate 200, and the pixel layer 400 includes the pixel units 100. The periphery of each pixel unit 100 is at least surrounded by one annular isolation groove 401, so as to realize pixel independence through the annular isolation groove 401 in the periphery.

[0100] The most peripheral annular isolation groove of each pixel unit and the most peripheral annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved as a compound semiconductor material area, that is, the most peripheral annular isolation groove of each pixel unit and the most peripheral annular isolation groove of the adjacent pixel unit can share a part of the annular isolation groove. For example, as shown in FIG. 1, the periphery of the pixel unit 100 is provided with only one annular isolation groove 401, and the annular isolation grooves 401 of the adjacent two pixel units share a part. Figure 2

[0101] Alternatively, the most peripheral annular isolation groove of each pixel unit and the most peripheral annular isolation groove of the adjacent pixel unit 100 can be completely separated from each other by reserving a compound semiconductor therebetween, that is, the most peripheral annular isolation grooves of the adjacent two pixel units are completely non-overlapping and separated from each other, and the separated area is reserved as the original compound semiconductor material area. For example, as shown in FIG. 2, the most peripheral annular isolation grooves 401 of the adjacent two pixel units are completely non-overlapping and separated from each other, and the separated area is reserved as the original compound semiconductor material area Q1. Figure 21

[0102] The top of each pixel unit 100 is electrically connected to the corresponding second electrode contact 203, and the bottom of the pixel unit 100 is electrically connected to the corresponding first electrode contact 202. The projection area of each pixel unit 100 on the substrate 200 is defined as a first projection area, and the second electrode contact 203 is formed inside the first projection area of the corresponding pixel unit 100.

[0103] For example, as shown in FIG. 1, Figures 2-3 ​​As shown, each pixel unit 100 corresponds to 4 second-type electrode contacts 203, which are electrically connected to the top of the pixel unit 100, and the 4 second-type electrode contacts are located in the first projection area of the pixel unit 100 on the substrate 200.

[0104] It can be understood that the top and bottom of the pixel unit 100 are respectively two ends with opposite polarities, for example, the top is the end where the N-type semiconductor (or the P-type semiconductor) is located, and the bottom is the end where the P-type semiconductor (or the N-type semiconductor) is located, which need to be connected to electrode contacts with different polarities. Among them, the pixel unit and the electrode contact (first-type electrode contact or second-type electrode contact) can be one-to-one correspondence or one-to-many form, for example, one second-type electrode contact can correspond to one pixel unit, or multiple second-type electrode contacts can correspond to one pixel unit, and the same applies to the first-type electrode contact.

[0105] The second-type electrode contacts 203 are arranged in the first projection area of the corresponding pixel unit 100, which is especially suitable for the preparation of some display chips with large pixel size, and is beneficial to enhancing the current transmission effect.

[0106] The above-mentioned driving wafer is an element with a driving circuit, the first-type electrode contacts 202 and the second-type electrode contacts 203 are the lead terminals of the driving circuit, which are used to electrically connect the driving circuit and the pixel unit, and the pixel unit 100 is a light-emitting element, and the light emission of the pixel unit 100 can be controlled through the electrical connection between the driving wafer and the pixel unit 100.

[0107] The above-mentioned driving wafer includes but is not limited to CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) driving backplane or TFT glass substrate, etc.

[0108] The above-mentioned structure can make the driving wafer electrically connected with the pixel unit 100 through the arrangement of the first-type electrode contacts 202 and the second-type electrode contacts 203, so as to control the light emission of each pixel unit 100 by using the driving wafer.

[0109] In some preferred modes, each pixel unit 100 in the pixel layer 400 can emit light independently.

[0110] It can be understood that, as Figure 1As shown, in the prior art, when the pixel unit 100 is prepared, a large amount of compound semiconductor material around the pixel unit 100 needs to be etched and removed, and then filled with an insulating medium material G1 to achieve the independence of the pixel unit 100. The thermal conductivity of the insulating medium material is lower than that of the original compound semiconductor, so that the heat generated by the device cannot be transmitted in time, resulting in an increase in the temperature of the device, thereby greatly reducing the photoelectric performance and reliability of the device.

[0111] Table 2: Comparison table of thermal conductivities of different materials

[0112]

[0113] As shown in Table 2, among the three materials of insulating medium, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating medium material.

[0114] As shown in Table 2, among the three materials of insulating medium, compound semiconductor and metal, the thermal conductivity of the metal material is higher than that of the compound semiconductor material, and the thermal conductivity of the compound semiconductor material is higher than that of the insulating medium material. Figures 2-5 As shown, the above LED display device structure of the embodiment realizes the independence of the pixel unit 100 by opening a ring-shaped separation groove 401 in the compound semiconductor layer, so that the ring-shaped separation groove at the outermost periphery of each pixel unit at least partially overlaps with the ring-shaped separation groove at the outermost periphery of the adjacent pixel unit, and the non-overlapping area is reserved with a compound semiconductor material area, or the ring-shaped separation groove at the outermost periphery of each pixel unit and the ring-shaped separation groove at the outermost periphery of the adjacent pixel unit are reserved with a compound semiconductor to be completely separated from each other, both of which can maximize the reservation of the original compound semiconductor material. The thermal conductivity of the compound semiconductor material is relatively high, and compared with the structure of removing most of the compound semiconductor material and then filling with an insulating medium material in the prior art, the heat dissipation effect of the device can be effectively improved.

[0115] It should be noted that, Figure 4 only when arranged in the form shown in Figure 2 , a cross-sectional view of one pixel unit and its peripheral structure obtained along the D2-D2 section in the middle. Figure 2 only when arranged in the form shown in Figure 5 , a cross-sectional view of three adjacent pixel units obtained along the D1-D1 section in the middle. Figure 2 Figure 2

[0116] ​​In the present application, the "width" direction is the X direction, the "height" or "up-down" direction is the Z direction, and there is also a Y direction, wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. The pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. The Z direction is the stacking direction of the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103.

[0117] In some embodiments, a plurality of second-type electrode contacts 203 are arranged in each first projection area, and the plurality of second-type electrode contacts 203 are distributed in a ring shape. For example, as shown in FIG. 2, each pixel unit 100 corresponds to four second-type electrode contacts 203, the four second-type electrode contacts 203 are electrically connected to the top of the pixel unit 100, the four second-type electrode contacts 203 are distributed in a ring shape around the center of the pixel unit 100, and the four second-type electrode contacts are located inside the projection area (the first projection area) of the pixel unit 100 on the substrate 200. Figures 2-3

[0118] Through the above arrangement of the plurality of second-type electrode contacts 203, current spreading can be better achieved, and the current intensity can be improved.

[0119] In some embodiments, a first-type electrode contact 202 and a plurality of second-type electrode contacts 203 are arranged inside each first projection area, and the plurality of second-type electrode contacts 203 surround the periphery of at least one first-type electrode contact 202. For example, one first-type electrode contact 202 located at the center of the pixel is surrounded by the plurality of second-type electrode contacts 203 on the periphery.

[0120] As shown in FIG. 2, the LED display device further includes an interconnection conductive member 600, and the top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203 through the interconnection electrode member. The interconnection conductive member 600 is formed inside each corresponding pixel unit 100. Figure 4

[0121] Further, in each pixel unit 100, the compound semiconductors on the periphery of the interconnection conductive member 600 constitute a light-emitting region 104, the top of the light-emitting region 104 on the periphery of the upper end of each interconnection conductive member 600 is electrically connected, and the lower end is electrically connected to the corresponding second-type electrode contact 203. That is, each pixel unit 100 is divided into a plurality of light-emitting regions 104 by the plurality of interconnection conductive members 600 inside.

[0122] Each light-emitting region 104 in the pixel unit 100 can correspond to one first-type electrode contact 202, or a plurality of light-emitting regions 104 can correspond to one first-type electrode contact 202.

[0123] ​​In some embodiments, as Figure 4 and Figure 5 As shown, the inner wall of the annular groove 401 is covered with a first insulating layer 404, and the interior of the annular groove 401 has a filling area 4011. The periphery of the filling area 4011 is surrounded by the first insulating layer 404 on the inner wall of the annular groove 401. The filling area 4011 is filled with air to form an air barrier 40112, that is, the filling area 4011 is a hollow structure, or the filling area 4011 can also be filled with a first filler 40111 to form a solid structure.

[0124] The first filler 40111 may be an insulating medium or metal.

[0125] The inner wall of the annular partition 401 is covered with the first insulating layer 404 , which can better isolate the pixel unit 100 and prevent leakage.

[0126] It should be noted that the inner wall of the above-mentioned annular groove 401 includes side walls and a bottom surface, and its side walls and bottom surface are covered with a first insulating layer 404. When there is an air partition layer 40112 inside the filling area 4011, the bottom surface of the air partition layer 40112 is not lower than the bottom surface of the annular groove 401.

[0127] It can be understood that in some embodiments, the pixel unit 100 and the peripheral adjacent annular partition 401 share a side wall, and in this case, the first insulating layer 404 on the side wall is also shared by both.

[0128] Further, if Figure 25 As shown, when there is an air spacer 40112 inside the filler, the minimum size of the air spacer 40112 along the width direction (X direction) must be greater than 0, and the maximum size of the air spacer 40112 along the width direction (X direction) is L3, then L3 is 0.01um~8um.

[0129] The first insulating layer 404 may be a transparent material layer.

[0130] Exemplarily, the first insulating layer 404 may be a single-layer structure or a stacked-layer structure composed of one or more dielectric layers such as silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, aluminum nitride, and gallium nitride.

[0131] For example, the first insulating layer 404 may be a stacked structure of silicon oxide and titanium oxide, and a DBR (distributed Bragg reflector) Bragg reflector structure is constructed by utilizing the difference in refractive index between the two materials.

[0132] In some embodiments, the thickness of the first insulating layer 404 is 5 nm to 2 um.

[0133] Furthermore, when the thickness of the first insulating layer 404 is 5 nm to 1 um and there is an air spacer 40112 inside the filler, the maximum dimension L3 of the air spacer 40112 along the width direction (X direction) can be 0.01 um to 8 um.

[0134] In some embodiments, the width L1 of the pixel unit 100 is 0.2 μm to 80 μm. The width of the pixel unit 100 can be understood as the maximum dimension of the pixel unit 100 along the width direction (X direction).

[0135] Furthermore, the height h1 of the pixel unit 100 is 0.1 μm to 5 μm, wherein the height of the pixel unit 100 refers to the distance between the upper surface of the first semiconductor layer 101 and the lower surface of the second semiconductor layer 103 in the pixel unit.

[0136] The shape of the pixel unit 100 includes but is not limited to a circle, an ellipse, a polygon and other shapes, preferably a circle, a quadrilateral and a hexagon.

[0137] In some embodiments, as Figure 4 As shown, the top of the light-emitting area 104 of each pixel unit 100 has an electrical contact area 1041, and the light-emitting area 104 is electrically connected to the upper end of the interconnected conductive member 600 through the electrical contact area 1041. For example, the electrical contact area 1041 and the upper end of the interconnected conductive member 600 can be connected through a conductive structure, and the above-mentioned electrical contact area 1041 and the interconnected conductive member 600 are both in contact with the conductive structure to achieve electrical connection.

[0138] Furthermore, the upper portion of the pixel unit 100 is at least partially covered by the first insulating layer 404 , and the area not covered by the first insulating layer 404 forms an electrical contact region 1041 .

[0139] Exemplarily, the upper portion of the pixel unit 100 is further covered with a first conductive layer 700 , and the first insulating layer 404 on the upper portion of the pixel unit 100 is at least partially covered by the upper first conductive layer 700 ;

[0140] The central area of ​​the top surface of the light-emitting area 104 in the pixel unit 100 forms the above-mentioned electrical contact area 1041 , and all the electrical contact areas 1041 in the pixel unit 100 and the top of the interconnected conductive member 600 are in contact with the same first conductive layer 700 .

[0141] The first conductive layer 700 may be a transparent conductive layer.

[0142] Exemplarily, the transparent conductive layer can be made of one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, or gold-doped indium tin oxide.

[0143] Further, as shown in FIG. 1A (the oblique hatched area in the figure is the area of the first conductive layer 700), the pixel units 100 and the first conductive layer 700 can be one-to-one corresponding, and the first conductive layers 700 of adjacent pixel units 100 are spaced apart from each other. Figure 2 Figure 21 Further, as shown in FIG. 1A (the oblique hatched area in the figure is the area of the first conductive layer 700), the pixel units 100 and the first conductive layer 700 can be one-to-one corresponding, and the first conductive layers 700 of adjacent pixel units 100 are spaced apart from each other.

[0144] In some embodiments, as shown in FIG. 1A, the upper part of the first conductive layer 700 can further be provided with a metal reinforcing member 1100, which can be located directly above the interconnection conductive member 600 or can be arranged at other positions. The metal reinforcing member 1100 is made of a metal material, and the addition of the metal reinforcing member 1100 can achieve better current spreading, and at the same time, can further increase the heat conduction capacity and improve the reliability of the LED display device. Figure 10 In this embodiment, the pixel layer 400 and the substrate 200 are bonded by the bonding layer 300, and the bottom surface of the annular isolation groove 401 is not lower than the upper surface of the bonding layer 300.

[0145] Exemplarily, the bonding layer 300 is made of a conductive metal layer, and the upper part of the bonding layer 300 is formed with a first peripheral fence 301, and the inside of the first peripheral fence 301 is provided with the interconnection conductive member 600, and the first peripheral fence 301 and the interconnection conductive member 600 inside are isolated by a second insulating layer 408, and the second insulating layer 408 can be arranged at the inner wall of the first peripheral fence 301;

[0146] In addition, since the first type of electrode contact 202 can also be connected on the bonding layer 300, the second insulating layer 408 is arranged to insulate and isolate the second type of electrode contact 203 from the first type of electrode contact 202, so as to avoid short circuit.

[0147] Further, the outer wall of the first peripheral fence 301 can also be coated with a first insulating layer 404.

[0148] The bonding layer 300 can be one or more of Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination, or ITO, ITO combination, and an adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.) can also be arranged between the bonding layer 300 and the driving wafer.

[0149]

[0150] ​​In some preferred modes, the bonding layer 300 can be a multi-layer structure stacked in sequence along the height direction, and the layers from bottom to top are respectively a Cr layer (adhesion layer), a Pt layer (barrier depletion layer), an Au layer, a Sn layer, and an Au layer, with thicknesses of 10 nm, 50 nm, 100 nm, 150 nm, and 50 nm, respectively.

[0151] For example, the second insulating layer 408 can be one or more of a silicon oxide, an aluminum oxide, a silicon nitride, a titanium oxide, a hafnium oxide, a tantalum oxide, a niobium oxide, an aluminum nitride, a gallium nitride, and the like, to form a single-layer structure or a stacked-layer structure.

[0152] In some embodiments, the thickness of the second insulating layer 408 can be 5 nm to 2 um to ensure the insulating isolation effect.

[0153] In some embodiments, the interconnection conductive member 600 is a metal member.

[0154] Since the metal member has high thermal conductivity, the interconnection conductive member 600 of the above structure can further improve the heat dissipation effect of the LED display device.

[0155] In the embodiment, as shown in FIG. 4, the pixel layer 400 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom. Figure 12 It can be understood that the pixel unit 100 is etched on the pixel layer 400, and each pixel unit 100 also includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom.

[0156] The second electrode contact 203 is used to electrically connect the first semiconductor layer 101 in the corresponding pixel unit 100, and the first electrode contact 202 is used to electrically connect the second semiconductor layer 103 in the corresponding pixel unit 100.

[0157] One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The active layer 102 described above is used for light emission and can be an MQW active quantum well.

[0158] In some embodiments, the lower end of the annular isolation groove 401 extends between the lower surface of the active layer 102 and the upper surface of the substrate 200, and the upper end of the annular isolation groove 401 extends at least to the upper surface of the first semiconductor layer 101.

[0159] Further, the minimum size of the annular groove 401 along the width direction (X direction) is greater than 0, and the maximum size of the annular groove 401 along the width direction (X direction) is L2, and L2 is 0.02 um to 10 um. The width should not be too large in order to maximize the retention of semiconductor materials in the compound semiconductor layer and improve the heat dissipation effect. The width should not be too small, otherwise it will be difficult to process and ensure the effective separation between the pixel units 100, and the light emission effect will also be affected by the too small width.

[0160] In some embodiments, the top of the pixel layer 400 is provided with a lens, and the lens covers at least one pixel unit 100, that is, the lens can correspond to one pixel unit 100 one by one, or a plurality of pixel units 100 can correspond to one lens.

[0161] The material of the lens can be an insulating material. For example, the lens can be made of materials such as silicon oxide, silicon nitride, aluminum oxide, silicate glass, PMMA, silicone substance, or SU8.

[0162] The LED display device of the above embodiment is addressable and controllable at the top of each pixel unit 100, and can be addressable and lighted.

[0163] The embodiment also discloses a preparation method of an LED display device, including the following steps:

[0164] Step S1: selecting a driving wafer as the substrate 200, the driving wafer being provided with a first type of electrode contact 202 and a second type of electrode contact 203 with opposite polarities, and selecting a compound semiconductor layer as the pixel layer 400, the structure of the compound semiconductor layer referring to Figure 12 , the compound semiconductor layer including a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 arranged in sequence from top to bottom;

[0165] Step S2: as shown in Figure 12 , connecting the pixel layer 400 to the upper part of the substrate 200;

[0166] Step S3: as shown in Figure 13 , etching the pixel layer 400 to obtain at least one pixel unit 100, and the periphery of each pixel unit obtained by etching is surrounded by at least one annular groove 401, so that the annular groove 401 at the outermost periphery of each pixel unit and the annular groove 401 at the outermost periphery of the adjacent pixel unit at least partially overlap, and the non-overlapping area retains the compound semiconductor; or the annular groove 401 at the outermost periphery of each pixel unit and the annular groove 401 at the outermost periphery of the adjacent pixel unit retain the compound semiconductor to completely separate each other;

[0167] The top of each pixel unit 100 is electrically connected to the corresponding second-type electrode contact 203, and the bottom of the pixel unit 100 is electrically connected to the corresponding first-type electrode contact 202. The projection area of ​​the pixel unit 100 on the substrate 200 is defined as the first projection area, so that the second-type electrode contact 203 is formed inside the first projection area of ​​each corresponding pixel unit 100.

[0168] Furthermore, when the pixel layer 400 is connected to the upper portion of the substrate 200 in step S2 , the pixel layer 400 is connected to the substrate 200 via the bonding layer 300 .

[0169] When the pixel layer 400 and the substrate 200 are connected via the bonding layer 300 , a thermocompression bonding method may be used.

[0170] In some implementations, step S3 may specifically include the following steps:

[0171] Step S31: disposing an etching stop layer 403 on the upper surface of the pixel layer 400, and etching the etching stop layer 403 to obtain a patterned mask layer;

[0172] Step S32: Figure 14 In stage c, the pixel layer 400 is etched using a mask layer to obtain at least one pixel unit 100, and at least one annular partition 401 is formed around the periphery of each pixel unit 100, so that the outermost annular partition of each pixel unit at least partially overlaps with the outermost annular partition of an adjacent pixel unit, and the compound semiconductor remains in the non-overlapping area; or

[0173] Compound semiconductors are retained between the outermost annular partition groove of each pixel unit and the outermost annular partition groove of the adjacent pixel unit to completely separate them from each other;

[0174] When etching the pixel layer 400 using the mask layer, the second type electrode filling hole 407 can also be etched above the second type electrode contact 203. That is, the second type electrode filling hole 407 is directly etched on the compound semiconductor layer.

[0175] For example, the angle α of the pixel unit 100 obtained by etching can be 90°±45°. Preferably, the angle α of the pixel unit 100 can be 90°±20°. The angle α of the pixel unit 100 is the maximum angle between the sidewall of the pixel unit 100 and the upper surface of the substrate 200.

[0176] Step S33: Figure 14In the middle d stage, the first insulating layer 404 is deposited on the surface of the pixel layer 400, so that the first insulating layer 404 covers the inner wall of the annular isolation groove 401 and the sidewall of the pixel unit 100, and the inside of the annular isolation groove 401 forms a filling area 4011 surrounded by the first insulating layer 404;

[0177] At this time, the inner wall of the second electrode filling hole 407 and the upper surface of the pixel layer 400 are also covered with the first insulating layer 404;

[0178] Step S34: as Figure 14 In the middle e stage, the material at the bottom of the second electrode filling hole 407 is removed, so that the second electrode filling hole 407 penetrates through the bonding layer 300 to expose the second electrode contact 203; it can be understood that this step is to remove all the material between the second electrode filling hole 407 and the bottom second electrode contact 203 to expose the second electrode contact 203;

[0179] Step S35: as Figure 14 In the middle f stage, the second insulating layer 408 is deposited on the inner wall of the second electrode filling hole 407;

[0180] Step S36: as Figure 14 In the middle g stage, the metal is filled in the second electrode filling hole 407 to form the interconnection conductive piece 600, and the interconnection conductive piece 600 is formed in the inside of each corresponding pixel unit 100;

[0181] The interconnection conductive piece 600 obtained in this way is a metal piece;

[0182] Step S37: as Figure 14 In the middle h stage, the top of each pixel unit 100 is electrically connected to the corresponding second electrode contact 203 through the interconnection electrode piece. For example, the top of the pixel unit 100 is connected to the top of the interconnection electrode piece through the first conductive layer 700.

[0183] After step S37, step S38 is further performed: a lens is prepared on the top of the pixel layer 400, and the lens corresponds to one pixel unit 100 or a plurality of pixel units 100.

[0184] When the lens is prepared: the insulating medium layer can be backfilled first, and then the backfilled insulating medium layer is patterned and etched to form the lens; or after the insulating medium layer is backfilled, CMP planarization is performed first, and then the lens material is coated and patterned to form the lens.

[0185] In some embodiments, an ohmic contact layer 500 is further arranged between the pixel layer 400 and the bonding layer 300. In step S32, when the pixel layer 400 is etched with a mask layer, the etching can be performed to the ohmic contact layer 500. The ohmic contact layer 500 can be located inside the ohmic contact layer and above the lower surface thereof.

[0186] In some embodiments, the width of the second electrode filling hole 407 can be 0.1 um to 10 um. Here, the width of the second electrode filling hole 407 can be understood as the maximum dimension of the second electrode filling hole 407 in the width direction (X direction).

[0187] In some embodiments, in step S33, after the filling area 4011 surrounded by the first insulating layer 404 is formed inside the annular groove 401, air is retained in the filling area 4011 to form an air isolation layer 40112, that is, the filling area 4011 has a hollow structure, or the filling area 4011 is filled with a first filling material 40111 to make the filling area 4011 solid and have a solid structure.

[0188] In the above process, in each pixel unit 100, the compound semiconductor located at the periphery of the interconnection conductive member 600 in the pixel unit 100 is the light emitting area 104. In step S37, when the top of each pixel unit 100 is electrically connected to the corresponding second electrode contact 203 through the interconnection electrode member, the upper end of the interconnection conductive member 600 in each pixel unit 100 is electrically connected to the top of the light emitting area 104 at the periphery thereof, and the lower end is electrically connected to the corresponding second electrode contact 203.

[0189] Further, when the upper end of the interconnection conductive member 600 is electrically connected to the top of the light emitting area 104 at the periphery thereof, at least part of the top of the light emitting area 104 is exposed to form an electrical contact area 1041, and the light emitting area 104 is connected to the upper end of the interconnection conductive member 600 through the electrical contact area 1041.

[0190] In specific implementation, the electrical contact area 1041 and the upper end of the interconnection conductive member 600 can be connected through a conductive structure. The conductive structure can be the first conductive layer 700, the second conductive layer 1000 or other conductive structures as described in the present application.

[0191] In some embodiments, the bonding layer 300 can be made of metal. In step S34, the material at the bottom of the second type of electrode filling hole 407 is removed, so that when the second type of electrode filling hole 407 is exposed by penetrating through the bonding layer 300, a metal fence, i.e., the first peripheral fence 301, is formed on the upper part of the bonding layer 300. In step S35, the second insulating layer 408 is deposited on the inner wall of the first peripheral fence 301, and the interconnection conductive member 600 is located inside the first peripheral fence 301, so that the first peripheral fence 301 and the interconnection conductive member 600 are insulated by the second insulating layer 408.

[0192] Further, the top surface of the interconnection conductive member 600 can be higher than the first peripheral fence 301, and the height of the second insulating layer 408 can be the same as that of the interconnection conductive member 600, so as to better ensure the insulation effect.

[0193] In some embodiments, the bonding layer 300 is made of metal, and a first dielectric layer is further arranged between the pixel layer 400 and the bonding layer 300. The first dielectric layer is a low-refractive layer, and the bonding layer 300 can be made of a high-refractive metal layer, so as to form a light ODR (omnidirectional reflector) structure, thereby better improving the brightness of the device.

[0194] In some embodiments, the thickness of the first dielectric layer is 0.01 um to 0.5 um.

[0195] For example, the first dielectric layer can include one or more of silicon oxide, silicon nitride, aluminum oxide, or magnesium fluoride, which all have low refractive indexes. Of course, other materials with low refractive indexes can also be used.

[0196] The above LED display device includes, but is not limited to, a Micro-LED, a Micro-Laser, and other display devices.

[0197] The LED display device obtained by the above embodiment realizes the independence of the pixel units by means of the annular isolation groove, and the interconnection conductive member is directly prepared on the compound semiconductor layer, so that the compound semiconductor material is maximally reserved, thereby greatly increasing the heat conduction area of the whole device, effectively reducing the heat accumulation problem of the pixel units, greatly reducing the working temperature of the LED display device, and better guaranteeing the photoelectric performance and reliability of the LED device.

[0198] Embodiment Two

[0199] This embodiment will further describe the related structures of the LED display device of the present application. Figures 11-16

[0200] ​In this embodiment, the top of the light emitting area 104 of each pixel unit 100 has an electrical contact area 1041 , and the light emitting area 104 is electrically connected to the upper end of the interconnected conductive member 600 via the electrical contact area 1041 .

[0201] Exemplarily, the electrical contact region 1041 and the upper end of the interconnecting conductive member 600 are connected via a conductive structure. Both the electrical contact region 1041 and the interconnecting conductive member 600 are in contact with the conductive structure to achieve electrical connection. The conductive structure may be arranged in the following manners:

[0202] First way:

[0203] The upper portion of the pixel unit 100 is at least partially covered by the first insulating layer 404 , and the upper portion of the pixel unit 100 not covered by the first insulating layer 404 forms an electrical contact region 1041 .

[0204] Among them, such as Figure 4 As shown, the upper portion of the pixel unit 100 is also covered with a first conductive layer 700, and the first insulating layer 404 on the upper portion of the pixel unit 100 is at least partially covered by the first conductive layer 700. The above-mentioned electrical contact region 1041 is formed in the middle portion of the top surface of the light-emitting region 104 in the pixel unit 100, and all the electrical contact regions 1041 in the pixel unit 100 and the top portion of the interconnected conductive member 600 are in contact with the same first conductive layer 700 to achieve electrical connection.

[0205] Preferably, the first conductive layer 700 may be a transparent conductive layer.

[0206] It is understandable that a thin film cover layer 405 or other layers may be further provided between the first conductive layer 700 and the first insulating layer 404 on the upper portion of the pixel unit 100 .

[0207] In one embodiment, Figure 10 As shown, the upper portion of the first conductive layer 700 may be connected to a metal mesh to achieve better current expansion, while also further increasing heat conduction capability and improving the reliability of the LED display device.

[0208] In one embodiment, Figure 11 As shown, the top surface of the pixel unit 100 can be roughened to form an uneven plane, namely, an aa surface, to reduce total reflection and increase light extraction efficiency, thereby improving the brightness of the LED display device.

[0209] Second way:

[0210] The upper portion of the pixel unit 100 is at least partially covered by the first insulating layer 404 , and the upper portion of the pixel unit 100 not covered by the first insulating layer 404 forms an electrical contact region 1041 .

[0211] As shown in Figure 15 each of the second conductive layers 1000 is in contact with the electrical contact area 1041 of the peripheral light emitting area 104 of the interconnection conductive member 600.

[0212] For example, the electrical contact area 1041 of the light emitting area 104 in each pixel unit 100 is arranged close to the adjacent interconnection conductive member 600, that is, the electrical contact area is arranged at the edge of the light emitting area 104, and each of the electrical contact areas 1041 of the peripheral light emitting area 104 of the interconnection conductive member 600 is in contact with the second conductive layer 1000 on the top of the interconnection conductive member 600 to achieve electrical connection.

[0213] In some embodiments, the second conductive layer 1000 can be made of one or more of Cr, Pt, Ni, Al, Ti or Au.

[0214] In some embodiments, the width L5 of the electrical contact area 1041 can be 0.05um-5um.

[0215] In one embodiment, as shown in Figure 16 the top surface of the pixel unit 100 can be roughened to form a convex-concave uneven plane-aa surface to reduce total reflection and increase light extraction rate, thereby improving the brightness of the LED display device.

[0216] The third way is:

[0217] As shown in Figure 17 the upper part of the pixel unit 100 is not covered by the first insulating layer 404, and the upper part of the pixel unit 100 is only covered by the first conductive layer 700.

[0218] Specifically, the upper part of the pixel unit 100 is only covered by the first conductive layer 700, and the top of the interconnection conductive member 600 and all the electrical contact areas 1041 in the pixel unit 100 are in contact with the same first conductive layer 700.

[0219] In this way, the top of the pixel layer 400 can be surface treated by CMP planarization treatment or etching treatment, etc., so as to remove the first insulating layer 404 or other layers on the top of the pixel unit 100, so that the top surface of the pixel unit 100 is completely exposed, and then the first conductive layer 700 is deposited on the top surface of the pixel unit 100.

[0220] Further, as shown in Figure 18 the upper part of the first conductive layer 700 can also be provided with a metal reinforcing member 1100 to enhance the current spreading capability.

[0221] The fourth way is:

[0222] As shown in Figure 19 , the upper part of the pixel unit 100 is not covered by the first insulating layer 404, and the top of each interconnection conductive member 600 in the pixel unit 100 is respectively connected with a second conductive layer 1000.

[0223] Specifically, the top of each interconnection conductive member 600 in the pixel unit 100 is respectively connected with a second conductive layer 1000, each second conductive layer 1000 is in contact with the electrical contact area 1041 of the peripheral light-emitting area 104 of the corresponding interconnection conductive member 600, and the area on the top surface of each light-emitting area 104 not in contact with the second conductive layer 1000 is exposed.

[0224] In this way, the top of the pixel layer 400 can be surface treated by CMP planarization processing or etching processing, etc., so as to remove the first insulating layer 404 or other layers on the top of the pixel unit 100, so that the top surface of the pixel unit 100 is completely exposed, and then a corresponding second conductive layer 1000 is plated on the top of each interconnection conductive member 600, and the area not covered by the second conductive layer 1000 is exposed.

[0225] In one embodiment, as shown in Figure 20 , the top surface of the pixel unit 100 can be roughened to form a convex-concave plane-aa surface to reduce total reflection and increase light extraction efficiency, thereby improving the brightness of the LED display device.

[0226] It can be understood that in the above four ways, the top surface of the pixel unit 100 can be roughened to form a convex-concave plane, thereby reducing total reflection and increasing light extraction efficiency, thereby improving the brightness of the LED display device.

[0227] In the above four ways, a metal reinforcing member 1100 can be arranged on the upper part of the first conductive layer 700 or the second conductive layer 1000 to achieve better current spreading, and at the same time, the heat conduction capacity can be further increased to improve the reliability of the LED display device.

[0228] The above-mentioned metal reinforcing member 1100 can be made of one or more of Pt, Ni, Al, Ti or Au.

[0229] Embodiment three

[0230] This embodiment will further describe the related structure of the LED display device of the present application in combination with Figures 5-9 , wherein Figures 6-9 are Figure 5Schematic diagram of different forms of annular isolation groove 401 at M1.

[0231] The annular isolation groove 401 is arranged at the periphery of each pixel unit 100 in the application, the inside of the annular isolation groove 401 has a filling area 4011, the periphery of the filling area 4011 is surrounded by the first insulating layer 404 at the inner wall of the annular isolation groove 401, and the filling area 4011 can accommodate air to form an air isolation layer 40112, or the filling area 4011 can be filled with a first filler 40111 to form a solid structure, which can have the following structures.

[0232] The first structure form:

[0233] The upper part of the pixel layer 400 is provided with the first insulating layer 404, which covers the upper surface of each light-emitting area 104 of the pixel unit 100 and the inner wall of the annular isolation groove 401, and in addition, as shown in Figures 5-6 , a thin film cover layer 405 is also arranged on the upper part of the pixel layer 400, the upper part of the filling area 4011 is closed by the thin film cover layer 405, and the first insulating layer 404 at the upper surface of the pixel unit 100 is located below the thin film cover layer 405.

[0234] Preferably, the thin film cover layer 405 can be an insulating medium.

[0235] In some embodiments, the thin film cover layer 405 further includes a downwardly protruding extension 4051, which extends into the inside of the filling area 4011;

[0236] As shown in Figure 6 , the extension 4051 can only extend to the upper part of the filling area 4011, so that the lower part of the filling area 4011 remains hollow, thereby forming the air isolation layer 40112 in the lower part of the filling area 4011.

[0237] Alternatively, as shown in Figure 7 , the extension 4051 is the first filler 40111, and the filling area 4011 is filled with the first filler 40111 to form a solid structure. At this time, the material of the first filler 40111 is the same as that of the thin film cover layer 405, which is an insulating medium.

[0238] Further, when the filling area has an air isolation layer 40112, the minimum size of the air isolation layer 40112 in the width direction is greater than 0, and the maximum size L3 of the air isolation layer 40112 in the width direction can be 0.01um-8um.

[0239] The thin film cover layer 405 can be one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, hafnium oxide, tantalum oxide, niobium oxide, polyimide, etc.

[0240] In some embodiments, the sidewalls of the pixel unit 100 are also covered with a first insulating layer 404 to ensure insulation between the first semiconductor layer 101 and the second semiconductor layer 103 in the pixel unit 100. The upper portion of the pixel unit 100 is at least partially covered with the first insulating layer 404. The first insulating layer 404 on the upper portion of the pixel unit 100 is located below the thin film covering layer 405.

[0241] In some embodiments, the thickness of the thin film cover layer 405 is 0.05 μm to 8 μm. It is understood that the thickness of the thin film cover layer 405 here refers to the thickness of the thin film cover layer 405 on the top of the pixel unit 100 , excluding the extension portion 4051 .

[0242] The first insulating layer 404 and the thin film cover layer 405 may both be transparent material layers.

[0243] The second structural form:

[0244] like Figure 9 As shown, this method does not require the thin film covering layer 405, and only the first insulating layer 404 is provided on the upper part of the pixel layer 400. A gap is retained in the filling area 4011 inside the annular partition 401 to accommodate air to form an air partition layer 40112, that is, a filling area 4011 with a hollow structure is formed; or, the filling area 4011 is filled with a first filler 40111 to form a solid structure.

[0245] The first filler 40111 may be an insulating medium or metal.

[0246] For example, Figure 9 As shown, the filling area 4011 can be directly filled with the material of the first insulating layer 404 ; of course, a filler different from the material of the first insulating layer 404 can also be used to fill the filling area 4011 .

[0247] The third structural form:

[0248] like Figure 8 As shown, in this method, the inner wall of the annular groove 401 is sequentially covered with a first insulating layer 404 and a first reflective layer 406. That is, the first reflective layer 406 is further provided outside the first insulating layer 404 on the inner wall of the annular groove 401, so that air is placed in the filling area 4011 to form an air barrier layer 40112, and the first reflective layer 406 surrounds the outer periphery of the air barrier layer 40112.

[0249] Alternatively, the first reflective layer 406 serves as the first filler 40111 , and the filling area 4011 is filled with the first filler 40111 to form a solid structure.

[0250] The first reflective layer 406 can be a reflective metal layer, for example, a high reflective layer metal of Al, Ag, Au, or the like, which can be prepared in a single layer or a stack, to form an omnidirectional reflector structure (ODR), so as to better prevent the problem of light crosstalk between pixels.

[0251] In the above-mentioned various modes, the etching stop layer 403 can be arranged at the upper surface of the light emitting region 104 in each pixel unit 100, and the first insulating layer 404 is arranged on the top of the pixel unit 100, and the first insulating layer 404 is located above the etching stop layer 403.

[0252] The etching stop layer 403 can be a transparent material layer.

[0253] For example, the etching stop layer 403 can be a mask of silicon oxide, silicon nitride, or the like, or a contact layer of ITO, metal, or the like, or a stack on the medium layer below the contact layer. In addition to forming a contact (such as an ohmic contact) with the first semiconductor layer 101, the film layer is mainly used as a mask for patterned etching.

[0254] Embodiment Four

[0255] This embodiment will further describe the related structure of the LED display device of the present application. Figures 23-25

[0256] The pixel layer 400 includes the first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 arranged in sequence from top to bottom, the second electrode contact 203 is used to electrically connect the first semiconductor layer 101 in the corresponding pixel unit 100, and the first electrode contact 202 is used to electrically connect the second semiconductor layer 103 in the corresponding pixel unit 100.

[0257] One of the first semiconductor layer 101 and the second semiconductor layer 103 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.

[0258] The ohmic contact layer 500 is arranged between the second semiconductor layer 103 and the bonding layer 300, so as to better realize the ohmic contact of the second conductor layer and the bonding layer 300.

[0259] The lower end of the annular isolation groove 401 extends between the lower surface of the active layer 102 and the lower surface of the ohmic contact layer 500.

[0260] During the etching of the annular isolation groove 401, according to the etching depth of the annular isolation groove 401, the annular isolation groove 401 can have the following forms:

[0261] The first form is as shown in Figure 25 Figure 25 ​​yes Figure 23 Schematic diagram of another structural form at M3 in the figure; the lower end of the annular groove 401 extends directly to the ohmic contact layer 500, and can extend into the interior thereof and be located above the lower surface of the ohmic contact layer, and the upper end of the annular groove 401 extends at least to the upper surface of the first semiconductor layer 101, for example, can directly extend to the upper surface of the first semiconductor layer 101 or continue to extend above the etch stop layer 403.

[0262] The second form: Figures 23-24 As shown, the lower end of the annular groove 401 is higher than the upper surface of the ohmic contact layer 500 and lower than the lower surface of the active layer 102, that is, the lower end of the annular groove 401 is located in the area between the lower surface of the active layer 102 and the upper surface of the ohmic contact layer 500.

[0263] Exemplarily, the ohmic contact layer 500 may be a transparent conductive film made of one or more of ITO, IZO, IGZO, or AZO, or may be a metal layer made of one or more of Ni, Cr, Au, Ag, Zn, Rh, Be, or Al, or may be an alloy layer, or may be a laminate of a transparent metal oxide and a metal;

[0264] The thickness of the ohmic contact layer 500 is 1 nm to 500 nm. If the thickness is too large, it will cause material waste, while if the thickness is too small, it will be difficult to achieve a good ohmic contact effect.

[0265] In some embodiments, the minimum dimension of the annular groove 401 along the width direction (X direction) needs to be greater than 0, and the maximum dimension L2 of the annular groove 401 along the width direction (X direction) is 0.02 um to 10 um.

[0266] Example 5

[0267] This embodiment will combine Figures 21-22 , further describes the relevant structure of the LED display device of this application.

[0268] It should be noted that Figure 22 Only shows the Figure 21 When arranged in the form shown, a Figure 21 A schematic cross-sectional view of a pixel unit and its surrounding structures obtained at the E2-E2 section.

[0269] The main difference between this embodiment and the above embodiment is that each pixel unit 100 is surrounded by at least two annular partitions 401, and compound semiconductors are retained between adjacent annular partitions on the periphery of each pixel unit to form partition walls 402, that is, the partition walls 402 themselves are also made of compound semiconductor materials.

[0270] The preparation method of the LED display device in this embodiment is substantially the same as that in Embodiment One, except that when the pixel layer 400 is etched by the mask layer to obtain at least one pixel unit 100, the etching is performed to form at least two annular isolation grooves 401 around each pixel unit 100, so that the compound semiconductor between the adjacent annular isolation grooves 401 around each pixel unit 100 is reserved to form a partition wall 402.

[0271] In this embodiment, each pixel unit 100 is surrounded by at least two annular isolation grooves 401, which can improve the heat dissipation effect, and can also better prevent the diffusion of metal atoms to the sidewall of the pixel unit 100 through the structure of the partition wall 402, so as to better reduce the risk of leakage of the device and improve the reliability of the device.

[0272] Embodiment Six

[0273] This embodiment will further describe the related structure of the LED display device of the present application in combination with Figure 4 , Figure 26 , Figure 27 and Figure 28 .

[0274] As shown in Figure 28 , the upper surface of the driving wafer in this embodiment is divided into at least one display area 201, and each display area 201 is covered by at least one pixel unit 100, that is, the display area 201 is the area covered by the pixel unit 100 (at least one pixel unit) to form an image display area 201.

[0275] Among them, the bonding layer 300 above each display area 201 is continuously arranged to further reserve the bonding layer 300 material, improve the heat dissipation area, and thus improve the heat dissipation effect of the device; at the same time, it is more conducive to the connection of the bonding layer 300 and the electrode contact, and the non-alignment method can be used for bonding.

[0276] For example, each display area 201 has a pixel array composed of a plurality of pixel units 100 above it, that is, each display area 201 is covered by a corresponding pixel array, and the projection of the pixel array on the driving wafer is located within the corresponding display area 201. The "bonding layer 300 above each display area 201" can be understood as the bonding layer whose projection on the driving wafer falls within the display area. Therefore, the bonding layer above each display area needs to be continuously arranged in the corresponding area of the display area 201. Specifically, the bonding layer above the display area can be continuously arranged in the corresponding area above the display area, and the bonding layer between the display areas is discontinuous (for example, Figure 28K1 region) or four display regions 201 share one continuous bonding layer 300 (such as Figure 28 K2 region), or nine display regions 201 share one continuous bonding layer 300 (such as Figure 28 K3 region), or nine display regions 201 share one continuous bonding layer 300 (such as Figure 28 K4 region), and so on, while the non-display regions 201 (which do not have pixel units 100 above) can be filled with a medium layer for support.

[0277] In the process of arranging the first type of electrode contact 202, the following forms can be adopted:

[0278] In one way: as shown in Figure 4 , the bottom of each pixel unit 100 is electrically connected to the corresponding first type of electrode contact 202, which is located inside the display region 201 where the corresponding pixel unit 100 is located. For example, the first type of electrode contact 202 can be arranged inside the display region 201 directly below each pixel unit 100, so that each light emitting region 104 in each pixel unit 100 is arranged with a corresponding first type of electrode contact 202, or only one first type of electrode contact 202 is arranged.

[0279] In another way: the bottom of each pixel unit 100 is electrically connected to the corresponding first type of electrode contact 202, which is located at the periphery of the display region 201 where the corresponding pixel unit 100 is located, i.e. the first type of electrode contact 202 is no longer arranged inside the display region 201.

[0280] For example, as shown in Figures 26-27 , a peripheral electrode contact region 800 can be arranged at the periphery of the display region 201 on the drive wafer, and the first type of electrode contact 202 is arranged at the peripheral electrode contact region 800.

[0281] A plurality of interfaces 900 are also arranged on the drive wafer to connect to external circuit (signal source or power supply, etc.) devices. The peripheral electrode contact region 800 can be connected / disconnected to the above-mentioned interfaces 900 as needed.

[0282] Embodiment Seven

[0283] In this embodiment, the top surface of the pixel unit 100 is a roughened plane, for example Figure 11 , Figure 16 , Figure 20 The aa surface in

[0284] Specifically, the top surface of the pixel unit 100 may be roughened to form an uneven surface, so as to reduce total reflection and increase light extraction efficiency, thereby improving the brightness of the LED display device.

[0285] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the scope of protection of this application and will not be described in detail here.

[0286] It should be noted that the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. An LED display device, characterized by: The application relates to a compound semiconductor pixel array substrate, which comprises the following parts: a substrate, which is a driving wafer, wherein a first type of electrode contact and a second type of electrode contact are arranged on the driving wafer, and the polarities of the first type of electrode contact and the second type of electrode contact are opposite; a pixel layer, which is a compound semiconductor layer, wherein the pixel layer is arranged on the upper part of the substrate, the pixel layer comprises pixel units, the periphery of each pixel unit is surrounded by at least one annular isolation groove, and the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved for the compound semiconductor; or the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit are completely separated from each other by the compound semiconductor reserved therebetween; wherein the top of each pixel unit is electrically connected with the corresponding second type of electrode contact, the bottom of the pixel unit is electrically connected with the corresponding first type of electrode contact, the projection area of each pixel unit on the substrate is defined as a first projection area, and the second type of electrode contact is formed in the inside of the first projection area of the corresponding pixel unit.

2. The LED display device of claim 1, wherein: A plurality of second type of electrode contacts are arranged in each first projection area, and the plurality of second type of electrode contacts are annularly distributed.

3. The LED display device of claim 2, wherein: The first type of electrode contact and the plurality of second type of electrode contacts are arranged in the inside of each first projection area, and the plurality of second type of electrode contacts are arranged on the periphery of at least one first type of electrode contact.

4. The LED display device of claim 1, wherein: The application further comprises an interconnecting conductive member, the top of each pixel unit is electrically connected with the corresponding second type of electrode contact through the interconnecting conductive member, and the interconnecting conductive member is formed in the inside of each corresponding pixel unit.

5. The LED display device of claim 4, wherein: In each pixel unit, the compound semiconductor on the periphery of the interconnecting conductive member constitutes a light-emitting area, the top of the light-emitting area on the periphery of the interconnecting conductive member is electrically connected with the upper end of the interconnecting conductive member, and the lower end of the interconnecting conductive member is electrically connected with the corresponding second type of electrode contact; the top of the light-emitting area has an electrical contact area, and the light-emitting area is connected with the upper end of the interconnecting conductive member through the electrical contact area.

6. The LED display device of claim 5, wherein: The inner wall of the annular isolation groove is covered with a first insulating layer, the inside of the annular isolation groove has a filling area, the periphery of the filling area is surrounded by the first insulating layer on the inner wall of the annular isolation groove, the inside of the filling area contains air to form an air isolation layer, or the filling area is filled with a first filler to form a solid structure.

7. The LED display device of claim 6, wherein: The upper part of the pixel unit is at least partially covered with the first insulating layer, and the area not covered with the first insulating layer forms the electrical contact area.

8. The LED display device of claim 7, wherein: The upper part of the pixel unit is further covered with a first conductive layer, the first insulating layer on the upper part of the pixel unit is at least partially covered with the first conductive layer, the middle part of the top surface of the light-emitting area in the pixel unit forms the electrical contact area, and all the electrical contact areas in the pixel unit are in contact with the same first conductive layer.

9. The LED display device of claim 7, wherein: The top of each interconnecting conductive member in the pixel unit is respectively connected with a second conductive layer, and each second conductive layer is in contact with the electrical contact area of the light-emitting area on the periphery of the corresponding interconnecting conductive member.

10. The LED display device of claim 6, wherein: The upper part of the pixel unit is only covered with the first conductive layer, and the top of all the electrical contact areas and the interconnecting conductive pieces in the pixel unit are in contact with the same first conductive layer.

11. The LED display device of claim 6, wherein: The top of each of the interconnecting conductive pieces in the pixel unit is connected with a second conductive layer, each of the second conductive layers is in contact with the electrical contact area of the peripheral light-emitting area of the corresponding interconnecting conductive piece, and the area on the top surface of each of the light-emitting areas not in contact with the second conductive layer is exposed.

12. The LED display device of claim 6, wherein: The upper part of the pixel layer is further covered with a thin film covering layer, and the upper part of the filling area is closed by the thin film covering layer.

13. The LED display device of claim 12, wherein: The thin film covering layer comprises a downwardly protruding extension, the extension extends into the filling area, the extension only extends to the upper part of the filling area, and the lower part of the filling area forms the air separation layer. Alternatively, the extension serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

14. The LED display device of claim 6, wherein: The filling area contains air to form an air separation layer, and the periphery of the air separation layer is surrounded by the first reflective layer. Alternatively, the first reflective layer serves as a first filler, and the filling area is filled with the first filler to form a solid structure.

15. The LED display device of claim 4, wherein: The pixel layer and the substrate are bonded by a bonding layer, and the bottom surface of the annular separation groove is not lower than the upper surface of the bonding layer.

16. The LED display device of claim 15, wherein: The interconnecting conductive piece is a metal piece.

17. The LED display device of claim 15, wherein: The upper surface of the driving wafer is divided into at least one display area, each of the display areas is covered by at least one pixel unit, and the bonding layer above each display area is continuously arranged.

18. The LED display device of claim 17, wherein: The bottom of each of the pixel units is electrically connected with a corresponding first electrode contact, and the first electrode contact is located at the periphery of the display area where the corresponding pixel unit is located.

19. The LED display device of claim 1, wherein: Each of the pixel units is surrounded by at least two annular separation grooves, and a compound semiconductor is also reserved between the adjacent annular separation grooves of the periphery of each of the pixel units to form a partition wall.

20. The LED display device of claim 1, wherein: The pixel layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence from top to bottom, the second electrode contact is used for electrically connecting with the first semiconductor layer in the corresponding pixel unit, the first electrode contact is used for electrically connecting with the second semiconductor layer in the corresponding pixel unit, the lower end of the annular separation groove extends between the lower surface of the active layer and the upper surface of the substrate, and the upper end of the annular separation groove extends at least to the upper surface of the first semiconductor layer.

21. The LED display device of claim 20, wherein: An ohmic contact layer is further arranged between the pixel layer and the substrate, and the lower end of the annular separation groove extends between the lower surface of the active layer and the lower surface of the ohmic contact layer.

22. The LED display device of claim 1, wherein: The maximum size of the annular separation groove in the width direction is L2, L2, and L2 is 0.02 um to 10 um.

23. The LED display device of claim 1, wherein: The top surface of the pixel unit is a rough plane.

24. A method of fabricating an LED display device, the method comprising: The method comprises the following steps: ​ selecting a driving wafer as a substrate, the driving wafer being provided with first electrode contacts and second electrode contacts with opposite polarities; and selecting a compound semiconductor layer as a pixel layer; connecting the pixel layer to the upper part of the substrate; and The pixel layer is etched to obtain at least one pixel unit. The periphery of each pixel unit obtained by etching is surrounded by at least one annular isolation groove, so that the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit at least partially overlap, and the non-overlapping area is reserved for the compound semiconductor; or the outermost annular isolation groove of each pixel unit and the outermost annular isolation groove of the adjacent pixel unit are reserved for the compound semiconductor to completely separate each other. The top of each pixel unit is electrically connected to the corresponding second electrode contact, the bottom of the pixel unit is electrically connected to the corresponding first electrode contact, the projection area of the pixel unit on the substrate is defined as a first projection area, and the second electrode contact is formed in the inside of the first projection area of each corresponding pixel unit.

25. The method of claim 24, wherein: When the pixel layer is connected to the upper part of the substrate, the method comprises connecting the pixel layer to the substrate through a bonding layer.

26. The method of claim 25, wherein: When the top of each pixel unit is electrically connected to the corresponding second electrode contact, the method comprises, A second electrode filling hole is formed in the compound semiconductor layer, and the second electrode filling hole penetrates through the bonding layer. The interconnection conductive member is filled in the second electrode filling hole, and the interconnection conductive member is formed in the inside of each corresponding pixel unit. The top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive member.

27. The method of claim 26, wherein: When the top of each pixel unit is electrically connected to the corresponding second electrode contact through the interconnection conductive member, the method comprises that the compound semiconductor in the periphery of the interconnection conductive member in the pixel unit constitutes a light-emitting area, the upper end of the interconnection conductive member is electrically connected to the top of the light-emitting area in the periphery, and the lower end is electrically connected to the corresponding second electrode contact.

28. The method of claim 27, wherein: When the upper end of the interconnection conductive member is electrically connected to the top of the light-emitting area in the periphery, the method comprises that at least part of the top of the light-emitting area is exposed to form an electrical contact area, and the light-emitting area is connected through the electrical contact area and the upper end of the interconnection conductive member.

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