STA data collection algorithm based on unified clock management
The STA data aggregation algorithm with unified clock management solves the problem of data acquisition disorder caused by clock asynchrony in smart grids, achieves high-precision clock synchronization and data transmission stability, improves the data availability and interoperability of power systems, and reduces operation and maintenance costs.
Patent Information
- Application Number
- CN202510953348.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-10
- Publication Date
- 2025-10-28
AI Technical Summary
In smart grid electricity consumption information collection systems, data acquisition disorder and communication reliability are caused by clock asynchrony. Especially in high-frequency data acquisition scenarios, clock deviation causes data transmission conflicts and increases the failure rate of CRC check, affecting the accuracy of grid load analysis and fault location.
The STA data aggregation algorithm based on unified clock management is adopted. By synchronizing the network clock, configuring the acquisition scheme, executing data acquisition, protocol conversion processing and communication rate optimization, microsecond-level clock synchronization of all network devices is achieved. Combined with a hierarchical data processing architecture and adaptive communication optimization strategy, the timing consistency and reliability of data acquisition are ensured.
It achieves high-precision clock synchronization, improves the stability and reliability of data transmission, reduces system operation and maintenance costs, expands coverage, and improves data interoperability and transmission efficiency.
Smart Images
Figure CN120857149A_ABST
Abstract
Description
Technical Field
[0001] This invention relates primarily to the technical field of wireless communication networks, and specifically to a STA data aggregation algorithm based on unified clock management. Background Art
[0002] In smart grid electricity consumption information acquisition systems, the core challenge of low-voltage power line carrier communication lies in the data acquisition disorder and decreased communication reliability caused by clock asynchrony. In traditional high-speed power line carrier networks, nodes such as the master station, terminals, CCO, and STA rely on local clocks to operate independently. The cumulative clock deviation can easily exceed the OFDM symbol guard interval, causing inter-symbol interference and time slot misalignment, leading to data transmission conflicts and increased CRC check failure rates. For example, when the clock error between the STA and CCO exceeds ±4μs, the Turbo-coded check bit in the frame control domain may not be correctly demodulated due to phase offset, resulting in lost reading instructions or a significant increase in the bit error rate. At the same time, clock asynchrony can cause TDMA time slot allocation failure, with multiple STAs sending data in the same time slot, causing channel contention and data collisions. Especially in high-frequency data acquisition scenarios, fixed-period acquisition tasks may miss the effective communication window due to clock deviation, leading to data backlog or missed acquisition. In addition, the lack of a unified clock reference makes it impossible to guarantee the consistency of cross-node data timing, affecting the accuracy of advanced applications such as grid load analysis and fault location. Therefore, how to achieve high-precision clock synchronization of HPLC network nodes and optimize the acquisition process and communication mechanism based on a unified clock has become a key technical bottleneck for improving the reliability of power line carrier communication. Summary of the Invention
[0003] This invention mainly provides a STA data aggregation algorithm based on unified clock management to solve the technical problems mentioned in the background.
[0004] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: The STA data aggregation algorithm based on unified clock management includes the following steps: S1. Synchronize network clock: Synchronize the network clock and generate a set of clock synchronization parameters; S2. Configure the acquisition scheme: parse the parameter set issued by the fusion terminal, and generate a configuration parameter set containing a task scheduling table by combining it with the CCO file; S3. Perform data acquisition: Start the acquisition task based on the configuration parameters. The CCO sends a reading instruction to the STA through the protocol to read the frozen minute data and generate the raw dataset after verification. S4. Protocol Conversion Processing: Identify the original data specification type, convert it to the DL / T645-2007 extended format, and generate a standard dataset through semantic mapping; S5. Communication Rate Optimization: Monitor link noise power and signal-to-noise ratio, adjust the rate according to data volume and acquisition frequency, and generate an optimized communication parameter set.
[0005] Furthermore, the HPLC communication network in S1 includes a master station, a terminal, a CCO, and a STA connected in sequence, and the CCO and STA communicate via OFDM modulation with a subcarrier spacing of 24.414 kHz, an FFT point count of 1024, and a cyclic prefix length of 18.32 μs or 10.56 μs.
[0006] Furthermore, the configuration parameter set in S2 is stored in an E2PROM storage area, and the stored content includes the STA physical address, acquisition period, and communication frequency band.
[0007] Furthermore, the copying instruction in S3 includes a frame control field and a physical block structure, and is transmitted through Turbo encoding and QPSK modulation.
[0008] Furthermore, the original dataset in S3 is encrypted using the AES-128 algorithm, and the encryption key is automatically updated every 24 hours.
[0009] Furthermore, the protocol conversion in S4 includes: Identify the preamble sequence and physical layer protocol data unit structure of the raw data frame; Map the minute-freeze data field of the 698.45 specification to the corresponding data identifier in DL / T645-2007.
[0010] Furthermore, in S5, the communication rate adjustment step size is 50kbps, the packet loss rate during the handover process is ≤0.1%, and a TDMA time slot synchronization mechanism is adopted, with each time slot containing 1024 OFDM symbols.
[0011] Furthermore, it also includes fault detection and recovery steps: When the SNR is detected to be below 5dB or three consecutive CRC checks fail, it is determined to be a communication failure. Automatically switch to the backup frequency band or enable relay routing, with a switching time of ≤2s.
[0012] Furthermore, it also includes data quality assessment steps: Perform integrity checks on the standard dataset and calculate the data integrity score; An abnormal data is detected using a sliding window filtering algorithm, and an abnormal data identifier is generated. For data with scores below 80, interpolation is performed based on historical valid values to generate a quality-optimized dataset.
[0013] Furthermore, the preamble sequence of the clock synchronization frame in S1 adopts a SYNCP / SYNCM structure, consisting of 10.5 SYNCP symbols and 2.5 SYNCM symbols, and reduces inter-symbol interference through windowing processing.
[0014] Furthermore, the collection cycle for the minute-freeze data in S3 is 1 minute, and the data storage uses a timestamp index with a timestamp precision of 1 second.
[0015] Furthermore, the communication between the CCO and STA follows the constellation point mapping rule, and when QPSK modulation is used, the constellation point phase rotation value is determined by the carrier phase number.
[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: Firstly, this invention achieves microsecond-level clock synchronization across all network devices through a unified clock management mechanism, utilizing a preamble sequence with a specific structure and windowing processing. Combined with a minute-level acquisition cycle and a high-precision timestamp index, it ensures the temporal consistency and traceability of data acquisition, providing an accurate time reference for applications such as real-time monitoring and load forecasting of the distribution network, and effectively enhancing the data's support value for business.
[0017] Secondly, the algorithm of this invention constructs a hierarchical data processing architecture, realizes standardized mapping of data formats of equipment from multiple vendors through a protocol conversion module, and automatically detects and repairs abnormal data in conjunction with integrity verification and sliding window filtering algorithms, significantly improving data availability and interoperability, solving the problems of data interoperability and quality control in heterogeneous networks, and providing a reliable data foundation for upper-level applications in the power system.
[0018] Third, this invention relies on an adaptive communication optimization strategy to dynamically adjust the transmission rate and TDMA time slot allocation. Combined with backup frequency band switching and relay routing mechanisms, it maintains a low packet loss rate and rapid fault recovery capability in complex power line environments. Simultaneously, it enhances anti-interference performance through Turbo coding, constellation point phase rotation, and other technologies, significantly improving the stability and transmission efficiency of the communication network, reducing system operation and maintenance costs, and expanding coverage. The present invention will be explained in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0019] Figure 1 This is a flowchart of the present invention. DETAILED DESCRIPTION
[0020] To facilitate understanding of the present invention, a more comprehensive description of the present invention will be given below with reference to the accompanying drawings, which illustrate several embodiments of the present invention. However, the present invention can be implemented in different forms and is not limited to the embodiments described in the text. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete.
[0021] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly associated with those skilled in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0023] This application provides an STA data aggregation algorithm based on unified clock management, as illustrated in the following diagram. Figure 1 As shown. The STA data aggregation algorithm based on unified clock management includes the following steps: S1. Synchronize network clock: Synchronize the network clock and generate a set of clock synchronization parameters; S2. Configure the acquisition scheme: parse the parameter set issued by the fusion terminal, and generate a configuration parameter set containing a task scheduling table by combining it with the CCO file; S3. Perform data acquisition: Start the acquisition task based on the configuration parameters. The CCO sends a reading instruction to the STA through the protocol to read the frozen minute data and generate the raw dataset after verification. S4. Protocol Conversion Processing: Identify the original data specification type, convert it to the DL / T645-2007 extended format, and generate a standard dataset through semantic mapping; S5. Communication Rate Optimization: Monitor link noise power and signal-to-noise ratio, adjust the rate according to data volume and acquisition frequency, and generate an optimized communication parameter set.
[0024] It should be noted that in this embodiment, the unified clock synchronization mechanism achieves microsecond-level clock synchronization accuracy across all network devices by combining SYNCP / SYNCM symbols in the preamble sequence (comprising 10.5 SYNCP symbols and 2.5 SYNCM symbols) and applying windowing processing. This eliminates data acquisition timing deviations. For example, in a pilot project in a certain distribution area, the clock synchronization error was reduced from ±500ms in the traditional scheme to ±200μs, improving the time consistency of minute-level frozen data.
[0025] The layered data processing architecture employs a pipelined design for data acquisition, protocol conversion, and communication optimization, supporting unified data formats for devices from multiple vendors. For example, it maps power parameters from the 698.45 protocol to the DL / T645-2007 standard format, enabling data interoperability between terminals from different brands, improving compatibility by 40% compared to traditional solutions.
[0026] The intelligent task scheduling strategy dynamically allocates acquisition priorities and channel resources through a task scheduling table configured with parameters. For example, during peak load periods, key user data is prioritized for acquisition, increasing channel utilization from 60% to 85% and reducing average acquisition latency by 30%.
[0027] Optional, please refer to the appendix Figure 1 The HPLC communication network in S1 includes a master station, a terminal, a CCO, and a STA connected in sequence. The CCO and STA communicate via OFDM modulation with a subcarrier spacing of 24.414 kHz, an FFT number of 1024, and a cyclic prefix length of 18.32 μs or 10.56 μs.
[0028] In this embodiment, a 24.414kHz subcarrier spacing, 1024-point FFT, and configurable cyclic prefixes of 18.32μs / 10.56μs are employed to enhance resistance to multipath fading. In a pilot project in an urban village, the signal transmission distance was extended from 300 meters to 500 meters, and the packet error rate decreased from 8% to 2%. This achieved optimized OFDM modulation parameters and a four-level network structure of master station-terminal-CCO-STA. Combined with OFDM modulation and Turbo coding, stable communication was maintained even in high-noise environments with noise power ≥-90dBm. For example, in a test in an industrial park, the data transmission success rate increased from 75% to 95%, enhancing the reliability of the multi-level network architecture.
[0029] Optional, please refer to the appendix Figure 1 The configuration parameter set in S2 is stored in an E2PROM storage area, and the stored content includes the STA physical address, acquisition period, and communication frequency band.
[0030] In this embodiment, configuration parameters are stored in E2PROM to ensure rapid recovery after device restart. In actual testing, parameter recovery time was reduced from 5 seconds using traditional Flash storage to 1 second, improving system fault recovery efficiency. Batch STA configuration updates are achieved through CCO broadcast frame control messages. In a community renovation project, the parameter synchronization time for 500 devices was reduced from 4 hours to 15 minutes.
[0031] Optional, please refer to the appendix Figure 1 The copying instructions in S3 include a frame control field and a physical block structure, and are transmitted via Turbo encoding and QPSK modulation.
[0032] In this embodiment, Turbo coding with a code rate of 1 / 2 is used, and the bit error rate is reduced to 10⁻ when the signal-to-noise ratio is ≥10dB. 5 The following points are observed: In power line noise testing, under the same conditions, the bit error rate is reduced by two orders of magnitude compared to traditional convolutional coding, improving the error correction performance of Turbo coding. Frame control uses QPSK modulation, with each subcarrier carrying 2 bits of data, doubling the transmission rate compared to BPSK. In practical applications, the frame control parsing delay is reduced from 20ms to 10ms, improving channel utilization and thus enhancing the efficiency of QPSK modulation.
[0033] Optional, please refer to the appendix Figure 1 The original dataset in S3 is encrypted using the AES-128 algorithm, and the encryption key is automatically updated every 24 hours.
[0034] In this embodiment, the AES-128 encryption algorithm, combined with a 24-hour automatic key update mechanism, is used to ensure data transmission security. Hardware acceleration is employed to accelerate the encryption process, completing data encryption and transmission within a 1-minute acquisition cycle. Real-world testing shows that the encryption latency accounts for only 5% of the acquisition cycle, without affecting real-time performance.
[0035] Optional, please refer to the appendix Figure 1 Protocol conversion in S4 includes: Identify the preamble sequence and physical layer protocol data unit structure of the raw data frame; Map the minute-freeze data field of the 698.45 specification to the corresponding data identifier in DL / T645-2007.
[0036] In this embodiment, field mapping from the 698.45 protocol to DL / T645-2007 is achieved by identifying the preamble sequence and physical layer protocol data unit structure of the original data frame. In multi-vendor equipment co-firing, the protocol conversion power reaches 99.5%. A constellation point mapping rule based on carrier phase numbering ensures phase consistency of data from different protocols. Actual measurements show that the demodulation error rate caused by phase deviation is reduced from 8% to 1%.
[0037] Optional, please refer to the appendix Figure 1 In S5, the communication rate adjustment step size is 50kbps, the packet loss rate during handover is ≤0.1%, and a TDMA time slot synchronization mechanism is adopted, with each time slot containing 1024 OFDM symbols.
[0038] In this embodiment, the transmission rate is dynamically adjusted in 50kbps steps based on the signal-to-noise ratio, keeping the packet loss rate below 0.1%. In a pilot project in a mountainous area, facing channel variations caused by diurnal temperature differences, the transmission rate was automatically switched eight times to ensure complete data transmission. Each time slot contains 1024 OFDM symbols, and a time slot synchronization mechanism reduces collisions. In practical applications, the collision probability of multi-STA concurrent transmission is reduced from 3% to 0.05%.
[0039] Optional, please refer to the appendix Figure 1 It also includes fault detection and recovery steps: When the SNR is detected to be below 5dB or three consecutive CRC checks fail, it is determined to be a communication failure. Automatically switch to the backup frequency band or enable relay routing, with a switching time of ≤2s.
[0040] In this embodiment, a fault determination mechanism based on SNR < 5dB or three consecutive CRC failures is implemented, resulting in a detection delay of < 200ms. In a test in an older cell, channel faults were successfully detected and located 12 times, with the average repair time reduced to 1.5 seconds.
[0041] Optional, please refer to the appendix Figure 1 It also includes a data quality assessment step: Perform integrity checks on the standard dataset and calculate the data integrity score; An abnormal data is detected using a sliding window filtering algorithm, and an abnormal data identifier is generated. For data with scores below 80, interpolation is performed based on historical valid values to generate a quality-optimized dataset.
[0042] In this embodiment, the accuracy rate of abnormal data detection is >95% through integrity scoring and sliding window filtering algorithms. In a power distribution network monitoring project, 23 abnormal voltage fluctuation events were identified, providing a basis for fault prediction.
[0043] Optional, please refer to the appendix Figure 1 The preamble sequence of the clock synchronization frame in S1 adopts the SYNCP / SYNCM structure, consisting of 10.5 SYNCP symbols and 2.5 SYNCM symbols. Inter-symbol interference is reduced through windowing.
[0044] In this embodiment, the SYNCP / SYNCM preamble sequence structure, combined with windowing processing, controls the clock synchronization error within ±200μs. In a cross-regional power grid synchronization test, the time deviation between different stations decreased from ±1ms to ±50μs.
[0045] Optional, please refer to the appendix Figure 1 In S3, the data collection cycle for minute-freezing data is 1 minute, and the data storage uses a timestamp index with a timestamp precision of 1 second.
[0046] In this embodiment, a 1-minute data collection cycle and a 1-second timestamp accuracy support real-time load analysis. In a commercial park application, minute-level load forecasting was achieved with an accuracy rate of 92%. The timestamp indexing mechanism supports fast data retrieval, with a single data query response time of <100ms. In a test on a provincial power platform, the efficiency of querying millions of data points was improved by 50%.
[0047] Optional, please refer to the appendix Figure 1 The communication between CCO and STA follows the constellation point mapping rule. When QPSK modulation is used, the constellation point phase rotation value is determined by the carrier phase number.
[0048] In this embodiment, constellation point phase rotation based on carrier phase numbering compensates for carrier frequency offset in the power line channel. In tests conducted in an industrial plant, the demodulation bit error rate decreased from 15% to 5%. QPSK modulation combined with phase numbering mapping rules reduces the complexity of the demodulation algorithm. On a low-cost MCU platform, the demodulation computational resource utilization rate decreased from 40% to 25%.
[0049] The present invention has been described by way of example in conjunction with the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvement made by adopting the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, shall be within the protection scope of the present invention.
Claims
1. A STA data aggregation algorithm based on unified clock management, characterized in that, The following steps are involved: S1. Synchronize network clock: Synchronize the network clock and generate a set of clock synchronization parameters; S2. Configure the acquisition scheme: parse the parameter set issued by the fusion terminal, and generate a configuration parameter set containing a task scheduling table by combining it with the CCO file; S3. Perform data acquisition: Start the acquisition task based on the configuration parameters. The CCO sends a reading instruction to the STA through the protocol to read the frozen minute data and generate the raw dataset after verification. S4. Protocol Conversion Processing: Identify the original data specification type, convert it to the DL / T645-2007 extended format, and generate a standard dataset through semantic mapping; S5. Communication Rate Optimization: Monitor link noise power and signal-to-noise ratio, adjust the rate according to data volume and acquisition frequency, and generate an optimized communication parameter set.
2. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The HPLC communication network in S1 includes a master station, a terminal, a CCO, and a STA connected in sequence. The CCO and STA communicate via OFDM modulation with a subcarrier spacing of 24.414 kHz, an FFT point count of 1024, and a cyclic prefix length of 18.32 μs or 10.56 μs.
3. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The configuration parameter set in S2 is stored in an E2PROM storage area, and the stored content includes the STA physical address, acquisition period, and communication frequency band.
4. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The copying instruction in S3 includes a frame control field and a physical block structure, and is transmitted through Turbo encoding and QPSK modulation.
5. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The original dataset in S3 is encrypted using the AES-128 algorithm, and the encryption key is automatically updated every 24 hours.
6. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The protocol conversion in S4 includes: Identify the preamble sequence and physical layer protocol data unit structure of the raw data frame; Map the minute-freeze data field of the 698.45 specification to the corresponding data identifier in DL / T645-2007.
7. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The communication rate adjustment step size in S5 is 50kbps, the packet loss rate during handover is ≤0.1%, and a TDMA time slot synchronization mechanism is adopted, with each time slot containing 1024 OFDM symbols.
8. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, It also includes fault detection and recovery steps: When the SNR is detected to be below 5dB or three consecutive CRC checks fail, it is determined to be a communication failure. Automatically switch to the backup frequency band or enable relay routing, with a switching time of ≤2s.
9. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, It also includes a data quality assessment step: Perform integrity checks on the standard dataset and calculate the data integrity score; An abnormal data is detected using a sliding window filtering algorithm, and an abnormal data identifier is generated. For data with scores below 80, interpolation is performed based on historical valid values to generate a quality-optimized dataset.
10. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The preamble sequence of the clock synchronization frame in S1 adopts a SYNCP / SYNCM structure, consisting of 10.5 SYNCP symbols and 2.5 SYNCM symbols, and reduces inter-symbol interference through windowing.
11. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The collection cycle for the minute-freeze data in S3 is 1 minute, and the data storage uses a timestamp index with a timestamp precision of 1 second.
12. The STA data aggregation algorithm based on unified clock management according to claim 1, characterized in that, The communication between the CCO and STA follows the constellation point mapping rule, and when QPSK modulation is used, the constellation point phase rotation value is determined by the carrier phase number.