Digital circuit architecture for micro-display circuit

Abstract

The invention relates to a micro-display circuit, in particular to a digital circuit architecture for a micro-display circuit, which comprises a signal input and decoding module SPII2CUARTDecoder for receiving and decoding low-speed serial port protocol data; the first multiplexer MUX1 is used for selecting the decoded data output by the signal input and decoding module SPII2CUARTDecoder / the high-speed video data processed by the input processing module VIN and writing the data into the storage module SRAM; the storage module SRAM is used for storing low-speed picture data, supporting address assignment to carry out pixel-level access and realizing pixel-level data modification; the reading module SRAM READER is used for reading the low-speed picture data stored in the storage module SRAM; according to the technical scheme provided by the invention, the defects of single transmission mode, insufficient error correction capability and relatively high power consumption in the prior art can be effectively overcome.

Description

Technical Field

[0001] This invention relates to microdisplay circuits, and more specifically to a digital circuit architecture for microdisplay circuits. Background Technology

[0002] Microdisplay technology is widely used in smart wearables (such as smartwatches), VR / AR, and other fields. Typical microdisplay circuits (such as MicroLED-related circuits) usually only have a high-speed VIN channel (dependent on external signal input) and a TPG channel for generating limited test patterns. For scenarios with relatively fixed display images and low refresh rate requirements (such as smartwatches or VR / AR lock screens), existing technologies do not differentiate between high and low refresh rate scenarios and rely entirely on external high-speed video data input, which has the following drawbacks:

[0003] 1) Limited transmission methods: The VIN channel is a high-speed video data input interface, lacking low-speed transmission methods such as SPI, I2C, and UART, and cannot adapt to low-speed serial port protocol data input scenarios;

[0004] 2) Insufficient error correction capability: When the VIN channel displays an error, it can only be corrected from the input source, and cannot achieve pixel-level data modification through low-speed control inside the micro display circuit;

[0005] 3) High power consumption: There is no scene distinction. The continuous high-speed video data input maintains high power consumption even under low refresh rate requirements, which does not meet the requirements of low power consumption design. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] In view of the above-mentioned shortcomings of the prior art, the present invention provides a digital circuit architecture for micro display circuits, which can effectively overcome the defects of the prior art, such as single transmission mode, insufficient error correction capability and high power consumption.

[0008] (II) Technical Solution

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A digital circuit architecture for microdisplay circuits includes the following components:

[0011] The signal input and decoding module SPI_I2C_UART_Decoder receives and decodes low-speed serial port protocol data;

[0012] The first multiplexer MUX1 selects the input signal and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder to the high-speed video data processed by the input processing module VIN, which is then written to the storage module SRAM.

[0013] The SRAM storage module stores low-speed image data and supports pixel-level access by specifying the address, enabling pixel-level data modification.

[0014] The SRAM_READER module reads low-speed image data stored in the SRAM storage module.

[0015] The input processing module VIN receives and processes high-speed video data;

[0016] The Test Pattern Generation (TPG) module generates internal test pattern data.

[0017] The second multiplexer MUX2 selects the low-speed image data read by the SRAM_READER module / the high-speed video data processed by the VIN input processing module / the internal test pattern data generated by the TPG test pattern generation module as the image data processing source.

[0018] The Image_Process module performs image processing on the data selected by the second multiplexer MUX2.

[0019] The display driver module receives data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0020] The configuration and control module REG configures the operating parameters of each module, enabling mode switching and power consumption control.

[0021] Preferably, when high-speed video data input is detected or a high-speed refresh display is required, the REG control circuit of the configuration and control module enters the high-speed display mode:

[0022] The configuration and control module REG controls the second multiplexer MUX2 to select high-speed video data processed by the input processing module VIN / internal test pattern data generated by the test pattern generation module TPG as the image data processing source;

[0023] The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2;

[0024] The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0025] When high-speed video data input is detected, the input processing module VIN receives and processes the high-speed video data RGB / YUV; the control signals include vref, href, and valid.

[0026] Preferably, when low-speed serial port protocol data input is detected or an external command is received, the REG control circuit of the configuration and control module enters a low-speed display mode:

[0027] The configuration and control module REG controls the first multiplexer MUX1 to select the signal input and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder into the storage module SRAM.

[0028] The SRAM_READER module reads low-speed image data stored in the SRAM module.

[0029] The configuration and control module REG controls the second multiplexer MUX2 to select the low-speed image data read by the read module SRAM_READER as the image data processing source;

[0030] The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2;

[0031] The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0032] Specifically, when low-speed serial port protocol data input is detected, the signal input and decoding module SPI_I2C_UART_Decoder receives low-speed serial port protocol data including SPI, I2C and UART.

[0033] Preferably, when the configuration and control module REG control circuit enters the low-speed display mode and needs to modify a certain pixel in the display screen, it sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through the low-speed serial port. After decoding by the signal input and decoding module SPI_I2C_UART_Decoder, the correction data is written to the target pixel SRAM address in the storage module SRAM through the first multiplexer MUX1, realizing pixel-level data modification. During subsequent display, the reading module SRAM_READER reads the correction data.

[0034] Preferably, when the configuration and control module REG controls the circuit to enter the high-speed display mode and needs to modify a certain pixel in the display screen, the configuration and control module REG controls the first multiplexer MUX1 to select the high-speed video data processed by the input processing module VIN and write it into the storage module SRAM. It sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through a low-speed serial port. After the signal input and decoding module SPI_I2C_UART_Decoder decodes the data, the first multiplexer MUX1 writes the correction data into the target pixel SRAM address in the storage module SRAM, realizing pixel-level data modification. During subsequent display, the reading module SRAM_READER reads the correction data.

[0035] Preferably, when the configuration and control module REG control circuit enters the low-speed display mode, the circuit operates at a low frame rate. The frame rate interval is controlled by the configuration and control module REG control circuit to sleep and wait, and to wake up during operation, thereby achieving low-power operation.

[0036] Preferably, after the circuit is powered on and initialized, the configuration and control module REG defaults to configuring the working mode according to external instructions.

[0037] (III) Beneficial Effects

[0038] Compared with the prior art, the digital circuit architecture for micro-display circuits provided by the present invention has the following advantages:

[0039] 1) Adaptable to diverse transmission methods: Supports low-speed serial port protocol data input such as SPI, I2C, and UART, enriching data transmission methods and adapting to different hardware connection and data transmission needs;

[0040] 2) Enhanced error correction and flexible control: By utilizing the address specification of the SRAM storage module, pixel-level data modification can be achieved through low-speed control within the circuit, solving the problem that VIN channel display errors can only be corrected from the head, thus improving the flexibility of display control;

[0041] 3) Power consumption optimization: Differentiate between high and low refresh rate scenarios, operate at low frame rate in low speed display mode, and adopt frame rate interval sleep and work wake-up mechanism to significantly reduce the power consumption of micro display products under low refresh rate requirements and extend the device's battery life. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0043] Figure 1 This is a circuit diagram of the digital circuit architecture used in micro-display circuits according to the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0045] A digital circuit architecture for micro-display circuits, such as Figure 1 As shown, it includes the following components:

[0046] The signal input and decoding module SPI_I2C_UART_Decoder receives and decodes low-speed serial port protocol data;

[0047] The first multiplexer MUX1 selects the input signal and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder to the high-speed video data processed by the input processing module VIN, which is then written to the storage module SRAM.

[0048] The SRAM storage module stores low-speed image data and supports pixel-level access by specifying the address, enabling pixel-level data modification.

[0049] The SRAM_READER module reads low-speed image data stored in the SRAM storage module.

[0050] The input processing module VIN receives and processes high-speed video data;

[0051] The Test Pattern Generation (TPG) module generates internal test pattern data.

[0052] The second multiplexer MUX2 selects the low-speed image data read by the SRAM_READER module / the high-speed video data processed by the VIN input processing module / the internal test pattern data generated by the TPG test pattern generation module as the image data processing source.

[0053] The Image_Process module performs image processing on the data selected by the second multiplexer MUX2.

[0054] The display driver module receives data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0055] The configuration and control module REG configures the operating parameters of each module and enables mode switching and power consumption control (such as frame interval sleep and work wake-up mechanisms).

[0056] In the technical solution of this application, the control methods for the digital circuit architecture used in micro-display circuits mainly include the following two categories:

[0057] 1. The circuit enters high-speed display mode.

[0058] 1) When high-speed video data input is detected or high-speed refresh display is required (such as playing dynamic video), the REG control circuit of the configuration and control module enters the high-speed display mode:

[0059] The configuration and control module REG controls the second multiplexer MUX2 to select high-speed video data processed by the input processing module VIN / internal test pattern data generated by the test pattern generation module TPG as the image data processing source;

[0060] The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2;

[0061] The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0062] When high-speed video data input is detected, the input processing module VIN receives and processes the high-speed video data RGB / YUV; the control signals include vref, href, and valid.

[0063] 2) When the configuration and control module REG controls the circuit to enter high-speed display mode and needs to modify a pixel in the display screen, REG controls the first multiplexer MUX1 to select the high-speed video data processed by the input processing module VIN and write it to the storage module SRAM. (The subsequent process is the same as when the circuit enters low-speed display mode and needs to modify a pixel in the display screen, i.e., the input is high-speed and the display is low-speed.) The REG sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through the low-speed serial port. After decoding by the SPI_I2C_UART_Decoder, the correction data is written to the target pixel SRAM address in the storage module SRAM by the first multiplexer MUX1, realizing pixel-level data modification. During subsequent display, the SRAM_READER module reads the correction data.

[0064] II. The circuit enters low-speed display mode.

[0065] 1) When low-speed serial port protocol data input is detected or an external command is received (such as a smartwatch's screen lock command), the REG control circuit of the configuration and control module enters low-speed display mode:

[0066] The configuration and control module REG controls the first multiplexer MUX1 to select the signal input and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder into the storage module SRAM.

[0067] The SRAM_READER module reads low-speed image data stored in the SRAM module.

[0068] The configuration and control module REG controls the second multiplexer MUX2 to select the low-speed image data read by the read module SRAM_READER as the image data processing source;

[0069] The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2;

[0070] The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display.

[0071] Specifically, when low-speed serial port protocol data input is detected, the signal input and decoding module SPI_I2C_UART_Decoder receives low-speed serial port protocol data including SPI, I2C and UART.

[0072] 2) When the REG control circuit of the configuration and control module enters the low-speed display mode and needs to modify a certain pixel in the display screen, it sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through the low-speed serial port. After decoding by the signal input and decoding module SPI_I2C_UART_Decoder, the correction data is written to the target pixel SRAM address in the storage module SRAM through the first multiplexer MUX1, realizing pixel-level data modification. During subsequent display, the reading module SRAM_READER reads the correction data.

[0073] 3) When the REG control circuit of the configuration and control module enters the low-speed display mode, the circuit operates at a low frame rate. The frame rate interval is controlled by the REG control circuit of the configuration and control module in sleep mode and wakes up when working, so as to achieve low power consumption operation.

[0074] In the technical solution of this application, after the circuit is powered on and initialized, the configuration and control module REG configures the working mode according to external instructions by default.

[0075] In the technical solution of this application, each functional module can be implemented using hardware such as FPGA (Field-Programmable Gate Array) and ASIC (Application-Specific Integrated Circuit). For example, on the FPGA platform, the signal input and decoding module SPI_I2C_UART_Decoder code is written using hardware description languages ​​such as Verilog to implement serial port protocol decoding; the multiplexer MUX code is written to control the data path through selection signals; the SRAM storage module can use the FPGA's internal Block RAM or an external SRAM chip, and address mapping is configured for pixel-level access to achieve pixel-level data modification; the configuration and control module REG is configured through registers to achieve mode switching, power consumption control, etc.

[0076] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital circuit architecture for micro-display circuits, characterized in that: It includes the following components: The signal input and decoding module SPI_I2C_UART_Decoder receives and decodes low-speed serial port protocol data; The first multiplexer MUX1 selects the input signal and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder to the high-speed video data processed by the input processing module VIN, which is then written to the storage module SRAM. The SRAM storage module stores low-speed image data and supports pixel-level access by specifying the address, enabling pixel-level data modification. The SRAM_READER module reads low-speed image data stored in the SRAM storage module. The input processing module VIN receives and processes high-speed video data; The Test Pattern Generation (TPG) module generates internal test pattern data. The second multiplexer MUX2 selects the low-speed image data read by the SRAM_READER module / the high-speed video data processed by the VIN input processing module / the internal test pattern data generated by the TPG test pattern generation module as the image data processing source. The Image_Process module performs image processing on the data selected by the second multiplexer MUX2. The display driver module receives data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display. The configuration and control module REG configures the operating parameters of each module, enabling mode switching and power consumption control.

2. The digital circuit architecture for micro-display circuits according to claim 1, characterized in that: When high-speed video data input is detected or a high-speed refresh display is required, the REG control circuit of the configuration and control module enters the high-speed display mode: The configuration and control module REG controls the second multiplexer MUX2 to select high-speed video data processed by the input processing module VIN / internal test pattern data generated by the test pattern generation module TPG as the image data processing source; The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2; The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display. When high-speed video data input is detected, the input processing module VIN receives and processes the high-speed video data RGB / YUV; the control signals include vref, href, and valid.

3. The digital circuit architecture for micro-display circuits according to claim 2, characterized in that: When low-speed serial port protocol data input is detected or an external command is received, the REG control circuit of the configuration and control module enters low-speed display mode: The configuration and control module REG controls the first multiplexer MUX1 to select the signal input and writes the decoded data output from the decoding module SPI_I2C_UART_Decoder into the storage module SRAM. The SRAM_READER module reads low-speed image data stored in the SRAM module. The configuration and control module REG controls the second multiplexer MUX2 to select the low-speed image data read by the read module SRAM_READER as the image data processing source; The image processing module Image_Process performs image processing on the data selected by the second multiplexer MUX2; The display driver module receives the data processed by the image processing module Image_Process and uses control signals to drive the display matrix for display. Specifically, when low-speed serial port protocol data input is detected, the signal input and decoding module SPI_I2C_UART_Decoder receives low-speed serial port protocol data including SPI, I2C and UART.

4. The digital circuit architecture for micro-display circuits according to claim 3, characterized in that: When the configuration and control module REG control circuit enters the low-speed display mode and needs to modify a certain pixel in the display screen, it sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through the low-speed serial port. After decoding by the signal input and decoding module SPI_I2C_UART_Decoder, the correction data is written to the target pixel SRAM address in the storage module SRAM through the first multiplexer MUX1, realizing pixel-level data modification. During subsequent display, the reading module SRAM_READER reads the correction data.

5. The digital circuit architecture for micro-display circuits according to claim 4, characterized in that: When the configuration and control module REG controls the circuit to enter high-speed display mode and needs to modify a certain pixel in the display screen, the configuration and control module REG controls the first multiplexer MUX1 to select the high-speed video data processed by the input processing module VIN and write it to the storage module SRAM. It sends an instruction containing the target pixel SRAM address and correction data to the signal input and decoding module SPI_I2C_UART_Decoder through a low-speed serial port. After decoding by the signal input and decoding module SPI_I2C_UART_Decoder, the correction data is written to the target pixel SRAM address in the storage module SRAM by the first multiplexer MUX1, realizing pixel-level data modification. During subsequent display, the reading module SRAM_READER reads the correction data.

6. The digital circuit architecture for micro-display circuits according to claim 5, characterized in that: When the configuration and control module REG control circuit enters the low-speed display mode, the circuit operates at a low frame rate. The frame rate interval is controlled by the configuration and control module REG control circuit to sleep and wait, and to wake up when working, so as to achieve low power consumption operation.

7. The digital circuit architecture for micro-display circuits according to claim 6, characterized in that: After the circuit is powered on and initialized, the configuration and control module REG defaults to configuring the working mode according to external instructions.

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