Inverted structure vertical cavity surface emitting laser and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor photoelectrons, and discloses a vertical-cavity surface-emitting laser with an inverted structure and a preparation method of the vertical-cavity surface-emitting laser. The vertical cavity surface emitting laser with the inverted structure comprises a heterogeneous substrate, wherein a heat dissipation functional layer, a metal adhesion layer and a metal bonding layer are arranged on the surface of the heterogeneous substrate from bottom to top; the epitaxial structure comprises a p-type electrode, an ITO current expansion layer, a SiO2 current limiting layer, a first dielectric DBR layer, a p-type GaN layer, an electron blocking layer, a quantum well active region, an n-type GaN layer, a second dielectric DBR layer and an n-type electrode from bottom to top; and the p-type electrode is positioned at the bottom of the epitaxial structure and is bonded with the metal bonding layer to form an inverted structure. According to the vertical cavity surface emitting laser with the inverted structure provided by the invention, the heat dissipation function layer and the inverted structure design effectively improve the heat dissipation capability and the current uniformity of the device, and the service life, the performance stability and the reliability of the device are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics technology, and in particular to a flip-chip vertical cavity surface-emitting laser and its fabrication method. Background Technology

[0002] Unlike ordinary light sources, lasers possess high output power, excellent directionality, monochromaticity, and extremely high coherence, making them widely used in scientific research, industry, and the medical field. Since the advent of the first ruby ​​laser, various lasers have rapidly developed and been widely applied. Among them, vertical-cavity surface-emitting lasers (VCSELs) have gradually become a research hotspot in the field of semiconductor lasers due to their advantages such as high reliability, long lifespan, excellent performance, small size, and ease of large-scale integration. They have also shown enormous application potential in many fields, including optical storage, optical communication, optical sensing, and medical diagnostics.

[0003] In the epitaxial growth of vertical-cavity surface-emitting lasers (VCSELs), traditional homogeneous substrate materials are expensive and limited in size. Therefore, researchers generally prefer to use sapphire substrates, which are cheaper and larger. However, there is a significant thermal and lattice mismatch between the sapphire substrate and the epitaxial film. This mismatch leads to a large number of defects and internal stresses during epitaxy, severely affecting the crystal quality and luminescence performance of the device. Therefore, the sapphire substrate usually needs to be removed after epitaxial growth. Currently, the widely used laser lift-off technology uses high-energy laser irradiation of the epitaxial wafer and substrate interface to melt or vaporize the GaN material near the interface to achieve substrate lift-off. Although laser lift-off technology has been widely used in the fabrication of GaN-based semiconductor devices, this method still has the following drawbacks in practical operation: ① It is easy to cause thermal damage, interface roughness, and surface defects in the device, and the surface uniformity and flatness of the epitaxial layer after lift-off are difficult to control precisely; ② The large amount of heat generated during laser lift-off may further degrade the performance and stability of the device; ③ The laser lift-off equipment is expensive, which greatly increases the manufacturing cost of the device and limits its widespread application in industrial production. In contrast, electrochemical stripping technology has advantages such as simple operation, low cost, and no thermal damage. However, its research and application in the field of vertical cavity surface-emitting lasers is still insufficient, and there is still considerable room for development.

[0004] As a crucial component of vertical-cavity surface-emitting lasers (VCSELs), distributed Bragg reflectors (DBRs) are currently widely fabricated using GaAs or GaN-based materials via epitaxial growth techniques such as metal-organic chemical vapor deposition (MOCVD). However, epitaxial growth of DBRs requires strict control over the thickness and uniformity of each layer, resulting in complex and time-consuming processes that further increase manufacturing costs. Furthermore, traditional GaN-based VCSELs typically employ a top-mounted structure, with an n-type GaN layer at the bottom and a p-type GaN layer at the top. This can easily lead to current congestion and localized heat accumulation during current injection, especially under high-power operating conditions. This heat accumulation significantly impacts device lifetime, heat dissipation performance, and long-term operational reliability.

[0005] Therefore, there is an urgent need to develop new vertical-cavity surface-emitting lasers and their fabrication methods to solve the problems of high fabrication cost, easy damage to epitaxial structures, and insufficient heat dissipation performance and long-term reliability of vertical-cavity surface-emitting lasers. Summary of the Invention

[0006] The present invention aims to at least solve one of the aforementioned technical problems existing in the prior art. Therefore, one objective of the present invention is to provide a flip-chip vertical-cavity surface-emitting laser.

[0007] The second objective of this invention is to provide a method for fabricating such a flip-chip vertical cavity surface-emitting laser.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A first aspect of the present invention provides a flip-chip vertical-cavity surface-emitting laser, comprising:

[0010] A heterogeneous substrate, wherein the surface of the heterogeneous substrate is provided with, from bottom to top: a heat dissipation functional layer, a metal adhesion layer and a metal bonding layer;

[0011] The epitaxial structure, from bottom to top, includes: a p-type electrode, an ITO current spreading layer, a SiO2 current confinement layer, a first dielectric DBR layer, a p-type GaN layer, an electron blocking layer, a quantum well active region, an n-type GaN layer, a second dielectric DBR layer, and an n-type electrode.

[0012] The p-type electrode is located at the bottom of the epitaxial structure and is bonded to the metal bonding layer to form a flip-chip structure.

[0013] In some embodiments of the present invention, the heat dissipation functional layer is selected from diamond film or multilayer graphene film.

[0014] In some embodiments of the present invention, the thickness of the heat dissipation functional layer is 5-300 nm.

[0015] In some preferred embodiments of the present invention, the thickness of the heat dissipation functional layer is 5-200 nm.

[0016] In some embodiments of the present invention, the metal adhesion layer is selected from Ti thin film, Cr thin film or NiCr thin film.

[0017] In some embodiments of the present invention, the thickness of the metal adhesion layer is 5-50 nm.

[0018] In some preferred embodiments of the present invention, the thickness of the metal adhesion layer is 10-30 nm.

[0019] In some embodiments of the present invention, the metal bonding layer is selected from Au / Sn alloy, Au / Ge alloy, Cu / Sn alloy or In alloy.

[0020] In some embodiments of the present invention, the thickness of the metal bonding layer is 1-3 μm.

[0021] In some preferred embodiments of the present invention, the thickness of the metal bonding layer is 1-2 μm.

[0022] In some embodiments of the present invention, the heterogeneous substrate is selected from Si or SiC.

[0023] In some embodiments of the present invention, the materials of the first dielectric DBR layer and the second dielectric DBR layer are independently selected from SiO2 / TiO2, Nb2O5 / SiO2 or ZrO2 / SiO2, respectively.

[0024] In some embodiments of the present invention, the p-type electrode has a Ni / Au structure; the n-type electrode has a Ti / Pt / Au structure.

[0025] In some embodiments of the present invention, the geometric distribution of the p-type electrode and the n-type electrode is independently selected from a ring-shaped or grid-like structure.

[0026] In some embodiments of the present invention, the thickness of the ITO current spreading layer is 25-35 nm.

[0027] In some embodiments of the present invention, the thickness of the SiO2 current-limiting layer is 160-240 nm.

[0028] In some embodiments of the present invention, the active region of the quantum well includes InGaN / GaN.

[0029] In some embodiments of the present invention, the electron blocking layer comprises p-AlGaN.

[0030] In some embodiments of the present invention, the thickness of the n-type GaN layer is 1-3 μm.

[0031] In some embodiments of the present invention, the thickness of the p-type GaN layer is 140-210 nm.

[0032] A second aspect of the present invention provides a method for fabricating the flip-chip vertical-cavity surface-emitting laser described in the first aspect of the present invention, comprising the following steps:

[0033] An epitaxial structure is obtained by sequentially growing a buffer layer, a loss layer, an n-type GaN layer, a quantum well active region, an electron blocking layer, and a p-type GaN layer on the substrate surface.

[0034] On the side away from the substrate, the epitaxial structure is etched into the loss layer area by photolithography and ICP etching in sequence;

[0035] A SiO2 current-confining layer and an ITO current-spreading layer are sequentially deposited and patterned on the surface of the p-type GaN layer;

[0036] A first dielectric DBR layer is fabricated and patterned on the surface of the ITO current spreading layer, followed by deposition of a p-type electrode and rapid thermal annealing.

[0037] A heat dissipation functional layer, a metal adhesion layer, and a metal bonding layer are sequentially deposited on the surface of a heterogeneous substrate;

[0038] The epitaxial structure after depositing the p-type electrode is bonded to the surface of the metal bonding layer using wafer bonding technology;

[0039] The substrate, buffer layer, and loss layer are removed using electrochemical stripping technology to expose the n-type GaN layer.

[0040] A second dielectric DBR layer is fabricated and patterned on the surface of the n-type GaN layer, followed by the deposition of an n-type electrode and rapid thermal annealing to obtain the flip-chip vertical cavity surface-emitting laser.

[0041] In some embodiments of the present invention, the substrate includes a sapphire substrate.

[0042] In some embodiments of the present invention, the growth methods of the buffer layer, loss layer, n-type GaN layer, quantum well active region, electron blocking layer and p-type GaN layer are selected from metal-organic chemical vapor deposition, hydride vapor phase epitaxy or molecular beam epitaxy.

[0043] In some embodiments of the present invention, the first dielectric DBR layer and the second dielectric DBR layer are prepared using physical vapor deposition technology.

[0044] In some preferred embodiments of the present invention, the physical vapor deposition technique is selected from thermal evaporation, magnetron sputtering or electron beam evaporation.

[0045] In some embodiments of the present invention, the SiO2 current confinement layer and the ITO current extension layer are prepared by magnetron sputtering deposition.

[0046] In some embodiments of the present invention, the structure of the buffer layer is, in sequence, a GaN nucleation layer, a lightly doped GaN layer, and an undoped GaN layer.

[0047] In some embodiments of the present invention, the thickness of the buffer layer is 2800-3000 nm.

[0048] In some embodiments of the present invention, the thickness of the GaN nucleation layer is 1800-2000 nm.

[0049] In some embodiments of the present invention, the lightly doped GaN layer is silicon-doped GaN with a doping concentration of 4 × 10⁻⁶. 18 -5×10 18 cm -3 .

[0050] In some embodiments of the present invention, the structure of the loss layer is, in sequence, a GaN heavily doped layer, a GaN doped layer, and another GaN heavily doped layer.

[0051] In some embodiments of the present invention, the thickness of the loss layer is 2500-3000 nm.

[0052] In some embodiments of the present invention, the heavily doped GaN layer is silicon-doped GaN with a doping concentration of 4 × 10⁻⁶. 19 -5×10 19 cm -3 .

[0053] In some embodiments of the present invention, the GaN doped layer is silicon-doped GaN with a doping concentration of 0.8 × 10⁻⁶. 19 -1.5×10 19 cm -3 .

[0054] In some embodiments of the present invention, the etching is required to expose the heavily doped GaN layer in the loss layer.

[0055] In some embodiments of the present invention, the heat dissipation functional layer, the metal adhesion layer, and the metal bonding layer are prepared using chemical vapor deposition technology.

[0056] In some embodiments of the present invention, the wafer bonding technology is selected from eutectic wafer bonding or metal hot pressing wafer bonding.

[0057] In some embodiments of the present invention, the wafer bonding temperature is 280-350°C and the holding time is 8-15 min.

[0058] In some embodiments of the present invention, the rapid thermal annealing treatment temperature of the p-type electrode is 350-400°C, and the holding time is 30-60s.

[0059] In some embodiments of the present invention, the rapid thermal annealing treatment temperature of the n-type electrode is 200-270°C, and the holding time is 30-60s.

[0060] In some embodiments of the present invention, the rapid thermal annealing process is performed under a protective atmosphere.

[0061] In some embodiments of the present invention, the electrolyte for electrochemical stripping comprises a 0.2-0.4 mol / L oxalic acid solution, the solution temperature is 20-30°C, and the stripping voltage is 10-20V.

[0062] Compared with the prior art, the beneficial effects of the present invention are:

[0063] 1) The flip-chip vertical cavity surface-emitting laser provided by this invention has high reflectivity of the dielectric DBR, and the heat dissipation functional layer and flip-chip structure design effectively improve the heat dissipation capacity and current uniformity of the device, significantly improving the device's service life, performance stability and reliability, and can support high power output, and has broad application prospects.

[0064] 2) The method for fabricating a flip-chip vertical cavity surface-emitting laser provided by the present invention adopts electrochemical lift-off technology. By selectively etching the sapphire substrate and buffer layer, it achieves epitaxial layer transfer with no thermal damage and high flatness, overcoming the defects of thermal damage, high cost and rough surface of traditional laser lift-off technology.

[0065] 3) The method for fabricating a flip-chip vertical cavity surface-emitting laser provided by the present invention uses physical vapor deposition medium DBR. By alternately depositing high / low refractive index dielectric films, high reflectivity (≥99%) and strong process compatibility are achieved, overcoming the defects of traditional epitaxial growth DBR (such as AlGaN / GaN) process, such as complexity, high cost and difficulty in thickness control.

[0066] 4) The method for fabricating a flip-chip vertical cavity surface-emitting laser provided by the present invention connects the p-type electrode side to a high thermal conductivity heterostructure through a metal bonding layer, which shortens the thermal path. The p-type electrode and n-type electrode are distributed in a ring or grid structure, which optimizes the current distribution, reduces light shading, improves the light output efficiency, and overcomes the defects of current congestion and poor heat dissipation in the traditional upright structure. Attached Figure Description

[0067] Figure 1 This is a schematic diagram of the epitaxial structure of the flip-chip vertical cavity surface-emitting laser of Example 1;

[0068] Figure 2 This is a schematic diagram of the etched epitaxial structure in the flip-chip vertical cavity surface-emitting laser of Example 1;

[0069] Figure 3 This is a schematic diagram of the epitaxial structure after depositing a SiO2 current-confining layer and an ITO current-spreading layer in the flip-chip vertical cavity surface-emitting laser of Example 1;

[0070] Figure 4 This is a schematic diagram of the epitaxial structure after depositing a p-type electrode in the flip-chip vertical cavity surface-emitting laser of Example 1;

[0071] Figure 5 This is a schematic diagram of the structure after the epitaxial structure and the metal bonding layer are bonded in the flip-chip vertical cavity surface-emitting laser of Example 1;

[0072] Figure 6 This is a schematic diagram of the electrochemical stripping of the flip-chip vertical cavity surface-emitting laser of Example 1;

[0073] Figure 7 This is a schematic diagram of the epitaxial structure after removing the substrate, buffer layer, and loss layer in the flip-chip vertical cavity surface-emitting laser of Example 1;

[0074] Figure 8 This is a schematic diagram of the inverted vertical cavity surface-emitting laser in Example 1. Detailed Implementation

[0075] The present invention will be further described in detail below through specific embodiments. Unless otherwise specified, the raw materials, reagents, or apparatus used in the embodiments can be obtained from conventional commercial sources or by existing technical methods. Unless otherwise specified, the experimental or testing methods are conventional methods in the art.

[0076] Figure 1 This is a schematic diagram of the epitaxial structure of the flip-chip vertical-cavity surface-emitting laser of Example 1. Figure 1 It can be seen that the epitaxial structure consists of a buffer layer, a loss layer, an n-type GaN layer, a quantum well active region, an electron blocking layer, and a p-type GaN layer, which are sequentially grown on the surface of the sapphire substrate.

[0077] Figure 2 This is a schematic diagram of the etched epitaxial structure in the flip-chip vertical-cavity surface-emitting laser of Example 1. Figure 2 It can be seen that the etching process involves etching the epitaxial structure into the loss layer on the side away from the substrate, exposing the heavily doped GaN layer in the loss layer.

[0078] Figure 3 This is a schematic diagram of the epitaxial structure after depositing a SiO2 current-confining layer and an ITO current-spreading layer in the flip-chip vertical cavity surface-emitting laser of Example 1; Figure 4 This is a schematic diagram of the epitaxial structure after depositing a p-type electrode in the flip-chip vertical cavity surface-emitting laser of Example 1; Figure 5 This is a schematic diagram of the structure after the epitaxial structure and the metal bonding layer are bonded in the flip-chip vertical cavity surface-emitting laser of Example 1; Figure 6 This is a schematic diagram of the electrochemical stripping of the flip-chip vertical cavity surface-emitting laser of Example 1; Figure 7 This is a schematic diagram of the epitaxial structure after removing the substrate, buffer layer, and loss layer in the flip-chip vertical cavity surface-emitting laser of Example 1; Figure 8 This is a schematic diagram of the inverted vertical cavity surface-emitting laser in Example 1.

[0079] The following will combine Figure 1-8 The fabrication of the flip-chip vertical-cavity surface-emitting laser in the embodiments is described below:

[0080] Example 1

[0081] This embodiment fabricates a flip-chip vertical-cavity surface-emitting laser, and the steps are as follows:

[0082] S1. A buffer layer, a loss layer, a 2μm n-type GaN layer, and a 3-period In layer are sequentially grown on a sapphire substrate using metal-organic chemical vapor deposition. 0.16 Ga 0.84 N / GaN (3nm / 10nm) quantum well active region, 20nm p-Al 0.1 Ga 0.9 N-electron blocking layer, 170nm p-type GaN layer;

[0083] The buffer layer has a thickness of 2800-3000 nm and includes an 1800-2000 nm GaN nucleation layer and a 500 nm lightly doped GaN layer (Si doped, with a doping concentration of 5 × 10⁻⁶). 18 cm -3 ) and a 500nm undoped GaN layer;

[0084] The loss layer is 2700 nm thick and includes a 10 nm heavily doped GaN layer (Si doped, with a doping concentration of 4.5 × 10⁻⁶). 19 cm -3 ), 2500nm GaN doped layer (Si doped, doping concentration of 1.0×10⁻⁶) 19 cm -3 ) and a 10nm GaN heavily doped layer (Si doped, doping concentration of 4.5×10⁻⁶) 19 cm-3 The GaN heavy doping layer is used to improve the electrochemical stripping rate and reduce crystal damage;

[0085] S2. A pattern is formed on the surface of the epitaxial structure using photolithography, and then the epitaxial structure is etched to the loss layer using ICP etching technology. The etching depth is about 2.3-4.9μm, which needs to exceed the n-type GaN layer but not the buffer layer, in order to expose the highly conductive heavily doped layer so that a uniform lateral current path can be formed during electrochemical stripping.

[0086] S3. A SiO2 current-limiting layer of about 200 nm thick is deposited on the surface of the p-type GaN layer by magnetron sputtering, followed by photolithography and ICP etching for patterning; then, an ITO film of about 30 nm thick is deposited by magnetron sputtering as a current-spreading layer and patterned to improve the uniformity of current distribution and light extraction efficiency.

[0087] S4. A first dielectric DBR layer with 10 periodic structures is formed by alternately depositing SiO2 (approximately 79 nm thick, refractive index approximately 1.46) and TiO2 (approximately 49 nm thick, refractive index approximately 2.35) using electron beam evaporation, exhibiting a reflectivity ≥99% at 460 nm wavelength. Subsequently, photoresist is coated onto the surface of the first dielectric DBR layer, and a ring-shaped or grid-shaped p-type electrode pattern is defined using photolithography. Then, Ni (approximately 20 nm thick) / Au (approximately 150 nm thick) is deposited by electron beam evaporation. The photoresist and excess metal layers are then removed using a lift-off process to form a ring-shaped or grid-shaped p-type electrode structure. Next, rapid thermal annealing is performed in a nitrogen protective atmosphere containing 5% oxygen at a temperature of 350-400°C for approximately 60 seconds to improve the ohmic contact performance between the p-type electrode and the p-type GaN layer. Measured using a circular transmission line model (CTLM), the specific contact resistance of the p-type electrode can reach ≤2×10⁻⁶. -3 The low level of Ω / cm meets the device performance requirements;

[0088] S5. A diamond film with a thickness of about 200 nm was deposited on the surface of the Si heterostructure using chemical vapor deposition as a heat dissipation functional layer. Then, a Ti film with a thickness of about 20 nm was deposited by magnetron sputtering as a metal adhesion layer. Next, an Au / Sn eutectic alloy (80 wt% Au, 20 wt% Sn) with a thickness of about 1 μm was deposited as a metal bonding layer. Finally, the epitaxial structure of the prepared p-type electrode was bonded to the heterostructure through eutectic wafer bonding at a bonding temperature of 280-320℃ and a holding time of about 10 min.

[0089] S6. Place the bonded structure in an electrochemical stripping device, using an oxalic acid solution with a concentration of 0.3 mol / L and a temperature of 25°C as the electrolyte. Connect the positive electrode to the epitaxial structure side and the negative electrode to the platinum sheet. Apply a voltage of 10-20V to perform electrochemical stripping, achieving damage-free stripping of the sapphire substrate, buffer layer and loss layer, and obtaining an epitaxial structure with a smooth and uniform surface.

[0090] S7. On the surface of the n-type GaN layer after removing the substrate, 10 pairs of periodic SiO2 (thickness approximately 79 nm, refractive index approximately 1.46) / TiO2 (thickness approximately 49 nm, refractive index approximately 2.35) second dielectric DBR layers are first deposited alternately. Then, photoresist is coated on the surface of the second dielectric DBR layer and a ring or grid-like n-type electrode pattern is defined by photolithography. Then, contact windows are opened on the DBR to expose the surface of the n-type GaN layer by ICP etching. Then, Ti (thickness approximately 20 nm) / Pt (thickness approximately 30 nm) / Au (thickness approximately 200 nm) are deposited sequentially by electron beam evaporation. Then, the photoresist and the excess metal layer on it are removed by lift-off process to form a ring or grid-like n-type electrode structure. Finally, rapid thermal annealing was performed in a nitrogen protective atmosphere, with the annealing temperature controlled at 200-250℃ and the holding time at approximately 30-60 seconds, to achieve stable and reliable ohmic contact. CTLM confirmed that the contact resistance of the Ti / Pt / Au structure after low-temperature annealing can reach ≤1×10⁻⁶. -3 The inverted vertical cavity surface-emitting laser with a strength of Ω / cm has been successfully fabricated.

[0091] Example 2

[0092] This embodiment fabricates a flip-chip vertical-cavity surface-emitting laser, and the steps are as follows:

[0093] S1. A buffer layer, a loss layer, a 2μm n-type GaN layer, and a 3-period In layer are sequentially grown on a sapphire substrate using metal-organic chemical vapor deposition. 0.16 Ga 0.84 N / GaN (3nm / 10nm) quantum well active region, 20nm p-Al 0.1 Ga 0.9 N-electron blocking layer, 170nm p-type GaN layer;

[0094] The buffer layer has a thickness of 2800-3000 nm and includes an 1800-2000 nm GaN nucleation layer and a 500 nm lightly doped GaN layer (Si doped, with a doping concentration of 5 × 10⁻⁶). 18 cm -3 ) and a 500nm undoped GaN layer;

[0095] The loss layer is 2700 nm thick and includes a 10 nm heavily doped GaN layer (Si doped, with a doping concentration of 4.5 × 10⁻⁶). 19 cm -3 ), 2500nm GaN doped layer (Si doped, doping concentration of 1.0×10⁻⁶) 19 cm -3 ) and a 10nm GaN heavily doped layer (Si doped, doping concentration of 4.5×10⁻⁶) 19 cm -3 The GaN heavy doping layer is used to improve the electrochemical stripping rate and reduce crystal damage;

[0096] S2. A pattern is formed on the surface of the epitaxial structure using photolithography, and then the epitaxial structure is etched to the loss layer using ICP etching technology. The etching depth is about 2.3-4.9μm, which needs to exceed the n-type GaN layer but not the buffer layer, in order to expose the highly conductive heavily doped layer so that a uniform lateral current path can be formed during electrochemical stripping.

[0097] S3. A SiO2 current-limiting layer of about 200 nm thick is deposited on the surface of the p-type GaN layer by magnetron sputtering, followed by photolithography and ICP etching for patterning; then, an ITO film of about 30 nm thick is deposited by magnetron sputtering as a current-spreading layer and patterned to improve the uniformity of current distribution and light extraction efficiency.

[0098] S4. A first dielectric DBR layer with 10 periodic structures is formed by alternately depositing Nb₂O₅ (approximately 52 nm thick, refractive index approximately 2.2) and SiO₂ (approximately 79 nm thick, refractive index approximately 1.46) using electron beam evaporation, exhibiting a reflectivity ≥99% at 460 nm wavelength. Subsequently, photoresist is coated onto the surface of the first dielectric DBR layer, and a ring-shaped or grid-shaped p-type electrode pattern is defined using photolithography. Then, Ni (approximately 20 nm thick) / Au (approximately 150 nm thick) is deposited by electron beam evaporation. The photoresist and excess metal layers are then removed using a lift-off process to form a ring-shaped or grid-shaped p-type electrode structure. Next, rapid thermal annealing is performed in a nitrogen protective atmosphere containing 5% oxygen at a temperature of 350-400 °C for approximately 60 seconds to improve the ohmic contact performance between the p-type electrode and the p-type GaN layer. Measured using a circular transmission line model (CTLM), the specific contact resistance of the p-type electrode can reach ≤2 × 10⁻⁶. -3 The low level of Ω / cm meets the device performance requirements;

[0099] S5. A multilayer graphene film with a thickness of about 5-10 nm is deposited on the surface of the Si heterostructure using chemical vapor deposition as a heat dissipation functional layer. Then, a Cr film with a thickness of about 20 nm is deposited by magnetron sputtering as a metal adhesion layer. Next, an Au / Ge eutectic alloy (80 wt% Au, 20 wt% Ge) with a thickness of about 1 μm is deposited as a metal bonding layer. Finally, the epitaxial structure of the prepared p-type electrode is bonded to the heterostructure through eutectic wafer bonding at a bonding temperature of 280-320℃ and a holding time of about 10 min.

[0100] S6. Place the bonded structure in an electrochemical stripping device, using an oxalic acid solution with a concentration of 0.3 mol / L and a temperature of 25°C as the electrolyte. Connect the positive electrode to the epitaxial structure side and the negative electrode to the platinum sheet. Apply a voltage of 10-20V to perform electrochemical stripping, achieving damage-free stripping of the sapphire substrate, buffer layer and loss layer, and obtaining an epitaxial structure with a smooth and uniform surface.

[0101] S7. On the surface of the n-type GaN layer after removing the substrate, 10 pairs of periodic Nb2O5 (thickness approximately 52nm, refractive index approximately 2.2) and SiO2 (thickness approximately 79nm, refractive index approximately 1.46) second dielectric DBR layers are first deposited alternately. Then, photoresist is coated on the surface of the second dielectric DBR layer and a ring or grid-like n-type electrode pattern is defined by photolithography. Then, contact windows are opened on the DBR to expose the surface of the n-type GaN layer by ICP etching. Then, Ti (thickness approximately 20nm) / Pt (thickness approximately 30nm) / Au (thickness approximately 200nm) are deposited sequentially by electron beam evaporation. Then, the photoresist and the excess metal layer on it are removed by lift-off process to form a ring or grid-like n-type electrode structure. Finally, rapid thermal annealing was performed in a nitrogen protective atmosphere, with the annealing temperature controlled at 200-250℃ and the holding time at approximately 30-60 seconds, to achieve stable and reliable ohmic contact. CTLM confirmed that the contact resistance of the Ti / Pt / Au structure after low-temperature annealing can reach ≤1×10⁻⁶. -3 The inverted vertical cavity surface-emitting laser with a strength of Ω / cm has been successfully fabricated.

[0102] Example 3

[0103] This embodiment fabricates a flip-chip vertical-cavity surface-emitting laser, and the steps are as follows:

[0104] S1. A buffer layer, a loss layer, a 2μm n-type GaN layer, and a 3-period In layer are sequentially grown on a sapphire substrate using metal-organic chemical vapor deposition. 0.16 Ga 0.84 N / GaN (3nm / 10nm) quantum well active region, 20nm p-Al 0.1 Ga 0.9N-electron blocking layer, 170nm p-type GaN layer;

[0105] The buffer layer has a thickness of 2800-3000 nm and includes an 1800-2000 nm GaN nucleation layer and a 500 nm lightly doped GaN layer (Si doped, with a doping concentration of 5 × 10⁻⁶). 18 cm -3 ) and a 500nm undoped GaN layer;

[0106] The loss layer is 2700 nm thick and includes a 10 nm heavily doped GaN layer (Si doped, with a doping concentration of 4.5 × 10⁻⁶). 19 cm -3 ), 2500nm GaN doped layer (Si doped, doping concentration of 1.0×10⁻⁶) 19 cm -3 ) and a 10nm GaN heavily doped layer (Si doped, doping concentration of 4.5×10⁻⁶) 19 cm -3 The GaN heavy doping layer is used to improve the electrochemical stripping rate and reduce crystal damage;

[0107] S2. A pattern is formed on the surface of the epitaxial structure using photolithography, and then the epitaxial structure is etched to the loss layer using ICP etching technology. The etching depth is about 2.3-4.9μm, which needs to exceed the n-type GaN layer but not the buffer layer, in order to expose the highly conductive heavily doped layer so that a uniform lateral current path can be formed during electrochemical stripping.

[0108] S3. A SiO2 current-limiting layer of about 200 nm thick is deposited on the surface of the p-type GaN layer by magnetron sputtering, followed by photolithography and ICP etching for patterning; then, an ITO film of about 30 nm thick is deposited by magnetron sputtering as a current-spreading layer and patterned to improve the uniformity of current distribution and light extraction efficiency.

[0109] S4. A first dielectric DBR layer with 10 periodic structures is formed by alternately depositing ZrO2 (approximately 56 nm thick, refractive index approximately 2.1) and SiO2 (approximately 79 nm thick, refractive index approximately 1.46) using electron beam evaporation, exhibiting a reflectivity ≥99% at 460 nm wavelength. Subsequently, photoresist is coated onto the surface of the first dielectric DBR layer, and a ring-shaped or grid-shaped p-type electrode pattern is defined using photolithography. Then, Ni (approximately 20 nm thick) / Au (approximately 150 nm thick) is deposited by electron beam evaporation. The photoresist and excess metal layers are then removed using a lift-off process to form a ring-shaped or grid-shaped p-type electrode structure. Next, rapid thermal annealing is performed in a nitrogen protective atmosphere containing 5% oxygen at a temperature of 350-400°C for approximately 60 seconds to improve the ohmic contact performance between the p-type electrode and the p-type GaN layer. Measured using a circular transmission line model (CTLM), the specific contact resistance of the p-type electrode can reach ≤2 × 10⁻⁶. -3 The low level of Ω / cm meets the device performance requirements;

[0110] S5. A diamond film with a thickness of about 200 nm was deposited on the surface of the Si heterostructure using chemical vapor deposition as a heat dissipation functional layer. Then, a NiCr film with a thickness of about 20 nm was deposited by magnetron sputtering as a metal adhesion layer. Next, a Cu / Sn eutectic alloy (80 wt% Cu, 20 wt% Sn) with a thickness of about 1 μm was deposited as a metal bonding layer. Finally, the epitaxial structure of the prepared p-type electrode was bonded to the heterostructure by hot pressing at a bonding temperature of 300-350℃ for a holding time of about 10-15 min.

[0111] S6. Place the bonded structure in an electrochemical stripping device, using an oxalic acid solution with a concentration of 0.3 mol / L and a temperature of 25°C as the electrolyte. Connect the positive electrode to the epitaxial structure side and the negative electrode to the platinum sheet. Apply a voltage of 10-20V to perform electrochemical stripping, achieving damage-free stripping of the sapphire substrate, buffer layer and loss layer, and obtaining an epitaxial structure with a smooth and uniform surface.

[0112] S7. On the surface of the n-type GaN layer after removing the substrate, 10 pairs of periodic ZrO2 (thickness approximately 56 nm, refractive index approximately 2.1) and SiO2 (thickness approximately 79 nm, refractive index approximately 1.46) second dielectric DBR layers are first deposited alternately. Then, photoresist is coated on the surface of the second dielectric DBR layer and a ring or grid-like n-type electrode pattern is defined by photolithography. Then, contact windows are opened on the DBR to expose the surface of the n-type GaN layer by ICP etching. Ti (thickness approximately 20 nm) / Pt (thickness approximately 30 nm) / Au (thickness approximately 200 nm) are deposited sequentially by electron beam evaporation. Then, the photoresist and the excess metal layer on it are removed by lift-off process to form a ring or grid-like n-type electrode structure. Finally, rapid thermal annealing was performed in a nitrogen protective atmosphere, with the annealing temperature controlled at 200-250℃ and the holding time at approximately 30-60 seconds, to achieve stable and reliable ohmic contact. CTLM confirmed that the contact resistance of the Ti / Pt / Au structure after low-temperature annealing can reach ≤1×10⁻⁶. -3 The inverted vertical cavity surface-emitting laser with a strength of Ω / cm has been successfully fabricated.

[0113] To address the problems of current congestion and poor heat dissipation in traditional upright-mounted (n-type down) vertical-cavity surface-emitting lasers, this invention provides a flip-chip vertical-cavity surface-emitting laser. By connecting the p-type electrode side to a high thermal conductivity heterostructure substrate through a metal bonding layer, the thermal path is shortened. Furthermore, the p-type and n-type electrodes are arranged in a ring or grid geometric distribution to optimize current distribution, reduce light shading, and improve light extraction efficiency.

[0114] Furthermore, this invention integrates diamond / graphene films on a heterogeneous substrate. Both heat dissipation functional layer materials possess excellent in-plane thermal conductivity. Studies have shown that polycrystalline diamond films approximately 200 nm thick, prepared using chemical vapor deposition (CVD), typically achieve a thermal conductivity of 500-800 W / m·K. Multilayer graphene films approximately 5-10 nm thick, prepared using CVD, typically exhibit a thermal conductivity of 500-1000 W / m·K. Taking a typical device structure size as an example, assuming a heat dissipation area A of 1 mm²... 2 The thickness d of the heat dissipation functional layer (diamond film) is 200nm. Calculate the thermal resistance of the heat dissipation functional layer according to the steady-state one-dimensional thermal resistance formula:

[0115]

[0116] In the formula, R th d is the thermal resistance of the heat dissipation layer, in K / W; d is the thickness of the heat dissipation layer, in m; k is the thermal conductivity of the heat dissipation layer material, in W / m·K; A is the effective cross-sectional area for heat conduction, in m². 2 ;

[0117] The calculated thermal resistance of the heat dissipation layer (diamond film) is approximately 0.3 K / W. When combined with the thermal resistance of the metal bonding layer and the heterostructure substrate (approximately 3.0 K / W), the overall thermal resistance of the device can be reduced from approximately 5.0 K / W without a heat dissipation layer to approximately 3.3 K / W. Under typical conditions of a device operating power P of 100 mW, the junction temperature rise ΔT = P × R th Theoretically, the temperature can be reduced from 0.50℃ to 0.33℃, a reduction of approximately 0.17℃. Although the theoretical temperature difference is not significant under normal power conditions, it becomes apparent when the chip or array operates at a power density of approximately 10W / mm². 2 At this time, the corresponding temperature rise ΔT can theoretically be reduced by about 17°C, which will significantly improve the device's heat dissipation efficiency and long-term operational reliability and stability. Under the same geometric conditions, using multilayer graphene films as the heat dissipation functional layer can also achieve a similar thermal resistance reduction effect as diamond films, effectively improving the device's heat dissipation performance.

Claims

1. A flip-chip vertical-cavity surface-emitting laser, characterized in that, include: A heterogeneous substrate, wherein the surface of the heterogeneous substrate is provided with, from bottom to top: a heat dissipation functional layer, a metal adhesion layer and a metal bonding layer; The epitaxial structure, from bottom to top, includes: a p-type electrode, an ITO current spreading layer, a SiO2 current confinement layer, a first dielectric DBR layer, a p-type GaN layer, an electron blocking layer, a quantum well active region, an n-type GaN layer, a second dielectric DBR layer, and an n-type electrode. The p-type electrode is located at the bottom of the epitaxial structure and is bonded to the metal bonding layer to form a flip-chip structure.

2. The inverted vertical cavity surface-emitting laser according to claim 1, characterized in that, The heat dissipation functional layer is selected from diamond film or multilayer graphene film.

3. The inverted vertical cavity surface-emitting laser according to claim 1, characterized in that, The metal adhesion layer is selected from Ti thin film, Cr thin film or NiCr thin film.

4. The inverted vertical-cavity surface-emitting laser according to claim 1, characterized in that, The metal bonding layer is selected from Au / Sn alloy, Au / Ge alloy, Cu / Sn alloy or In alloy.

5. The inverted vertical cavity surface-emitting laser according to claim 1, characterized in that, The materials of the first dielectric DBR layer and the second dielectric DBR layer are independently selected from SiO2 / TiO2, Nb2O5 / SiO2 or ZrO2 / SiO2, respectively.

6. The inverted vertical-cavity surface-emitting laser according to claim 1, characterized in that, The p-type electrode has a Ni / Au structure; the n-type electrode has a Ti / Pt / Au structure. And / or, the geometric distribution of the p-type electrode and the n-type electrode is independently selected from a ring-shaped or mesh-like structure.

7. The method for fabricating the flip-chip vertical-cavity surface-emitting laser according to any one of claims 1-6, characterized in that, Includes the following steps: An epitaxial structure is obtained by sequentially growing a buffer layer, a loss layer, an n-type GaN layer, a quantum well active region, an electron blocking layer, and a p-type GaN layer on the substrate surface. On the side away from the substrate, the epitaxial structure is etched into the loss layer area by photolithography and ICP etching in sequence; A SiO2 current-confining layer and an ITO current-spreading layer are sequentially deposited and patterned on the surface of the p-type GaN layer; A first dielectric DBR layer is fabricated and patterned on the surface of the ITO current spreading layer, followed by deposition of a p-type electrode and rapid thermal annealing. A heat dissipation functional layer, a metal adhesion layer, and a metal bonding layer are sequentially deposited on the surface of a heterogeneous substrate; The epitaxial structure after depositing the p-type electrode is bonded to the surface of the metal bonding layer using wafer bonding technology; The substrate, buffer layer, and loss layer are removed using electrochemical stripping technology to expose the n-type GaN layer. A second dielectric DBR layer is fabricated and patterned on the surface of the n-type GaN layer, followed by the deposition of an n-type electrode and rapid thermal annealing to obtain the flip-chip vertical cavity surface-emitting laser.

8. The preparation method according to claim 7, characterized in that, The structure of the buffer layer is, in sequence, a GaN nucleation layer, a GaN lightly doped layer, and a GaN undoped layer; And / or, the structure of the loss layer is, in sequence, a GaN heavily doped layer, a GaN doped layer, and a GaN heavily doped layer.

9. The preparation method according to claim 7, characterized in that, The rapid thermal annealing treatment temperature of the p-type electrode is 350-400℃, and the holding time is 30-60s; And / or, the rapid thermal annealing treatment temperature of the n-type electrode is 200-270℃, and the holding time is 30-60s.

10. The preparation method according to claim 7, characterized in that, The electrolyte for the electrochemical stripping includes a 0.2-0.4 mol / L oxalic acid solution at a temperature of 20-30°C; the stripping voltage is 10-20V.

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