Data interaction method and device, electronic equipment, storage medium and program product

Abstract

The application provides a data interaction method and device, electronic equipment, storage medium and program product; the method is applied to a data receiving end, the data receiving end comprises a first buffer for asynchronously processing and caching data, and a second buffer for controlling the sending behavior of a data sending end, the method comprises the following steps: receiving a data packet sent by the data sending end, and storing the data packet in the first buffer; reading to-be-processed data from the first buffer, processing the to-be-processed data, and deleting the to-be-processed data from the first buffer in response to the completion of the data processing; in response to the deletion of the to-be-processed data from the first buffer, generating a credit identifier between the data sending end and the data receiving end, and updating the state of the second buffer based on the credit identifier, the state being used for the data sending end to regulate the sending time of the data packet. Through the application, the stability of data interaction can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a data interaction method and device, electronic equipment, a storage medium, and a program product. BACKGROUND

[0002] In the fields of industrial automation control, medical device data transmission, and vehicle-mounted electronic communication, the demand for asynchronous data interaction between data sending ends and data receiving ends is increasingly prominent - in such scenarios, the data sending end (such as a sensor, radar, sampling module, etc.) and the data receiving end (such as a controller, processor, host, etc.) often use independent working clock domains (i.e., asynchronous clock architecture) due to differences in hardware design and functional requirements, for example, the data sending end clock frequency can be 160MHz~250MHz, and the data receiving end clock frequency can be 120MHz~200MHz, and there is no fixed synchronization relationship between the two clocks.

[0003] In scenarios with high requirements for data transmission real-time performance and reliability (such as medical ultrasound image transmission and vehicle-mounted millimeter wave radar data interaction), the data errors caused by metastability in the technical solutions of the related art can lead to deviations in medical diagnosis, and the radar data loss caused by buffer overflow can affect autonomous driving decisions, which seriously restricts the application of asynchronous data interaction systems in high-demand fields, thereby resulting in poor stability of data interaction in the related art. SUMMARY

[0004] The embodiments of the present application provide a data interaction method, device, electronic equipment, computer-readable storage medium, and computer program product, which can effectively improve the stability of data interaction.

[0005] The technical solutions of the embodiments of the present application are implemented as follows:

[0006] The embodiments of the present application provide a data interaction method applied to a data receiving end, the data receiving end including a first buffer for asynchronously processing and caching data, and a second buffer for controlling the sending behavior of a data sending end, comprising:

[0007] receiving a data packet sent by the data sending end and storing the data packet in the first buffer;

[0008] reading to-be-processed data from the first buffer, processing the to-be-processed data, and deleting the to-be-processed data from the first buffer in response to completion of the data processing;

[0009] In response to the existence of the to-be-processed data being deleted from the first buffer, a credit identifier between the data sending end and the data receiving end is generated, and a state of the second buffer is updated based on the credit identifier, the state being used for the data sending end to regulate a sending opportunity of the data packet.

[0010] Embodiments of the present application provide a data interaction method, applied to a data sending end, the data sending end comprising a first control unit for sending a data packet and a second control unit for controlling a sending behavior of the first control unit, the data sending end being communicatively connected with a data receiving end, the data receiving end comprising a second buffer for controlling a sending behavior of the data sending end, the method comprising:

[0011] The second control unit detects a state of the second buffer to obtain the state of the second buffer;

[0012] The second control unit determines control information of the first control unit based on the state;

[0013] In response to the control information indicating that a data sending opportunity is met, the first control unit sends a data packet to the data receiving end.

[0014] Embodiments of the present application provide a data interaction device, applied to a data receiving end, the data receiving end comprising a first buffer for asynchronously processing and buffering data and a second buffer for controlling a sending behavior of a data sending end, the device comprising:

[0015] A receiving module is configured to receive a data packet sent by the data sending end and store the data packet into the first buffer;

[0016] A data processing module is configured to read to-be-processed data from the first buffer, process the to-be-processed data, and delete the to-be-processed data from the first buffer in response to the data processing being completed;

[0017] A responding module is configured to, in response to the existence of the to-be-processed data being deleted from the first buffer, generate a credit identifier between the data sending end and the data receiving end, and update a state of the second buffer based on the credit identifier, the state being used for the data sending end to regulate a sending opportunity of the data packet.

[0018] In the above scheme, the first buffer is an asynchronous first-in-first-out buffer, and the responding module is further configured to, in response to the existence of the to-be-processed data being deleted from the asynchronous first-in-first-out buffer and the number of the to-be-processed data deleted in a clock cycle of the data receiving end being one, generate a credit identifier corresponding to the to-be-processed data deleted in the clock cycle.

[0019] In the above solution, the clock domain of the first buffer storing the data packet is consistent with the clock domain of the data sending end, and the clock domain of the first buffer reading the to-be-processed data is consistent with the clock domain of the data receiving end; the clock domain of the second buffer updating the state is consistent with the clock domain of the data receiving end, and the clock domain of the second buffer providing the data sending end with the state is consistent with the clock domain of the data sending end.

[0020] In the above solution, the state includes a first state for informing the data sending end that there is a credit identifier to be recycled and a second state for informing the data sending end that there is no credit identifier to be recycled; the response module is further configured to, in response to the credit identifier being generated, acquire an initial state of the second buffer; and when the initial state is the second state, update a second state of the second buffer to the first state.

[0021] In the above solution, the response module is further configured to agree, by the data receiving end and the data sending end, on an initial storage space corresponding to an initial available cache space of the first buffer, and the initial storage space is used to indicate an initial cache bearing capacity of the data receiving end agreed by the data receiving end and the data sending end; and the receiving module is configured to detect a used storage space of the first buffer, compare the used storage space with the initial storage space, and obtain a comparison result; and in response to the comparison result indicating that the used storage space is less than the initial storage space, receive the data packet sent by the data sending end.

[0022] In the above solution, the response module is further configured to determine a storage location of the to-be-processed data deleted from the first cache buffer in the first cache buffer; and when the storage location is within the initial storage space, generate a credit identifier between the data sending end and the data receiving end.

[0023] Embodiments of the present application provide a data interaction device, which is applied to a data sending end, the data sending end includes a first control unit for sending a data packet and a second control unit for controlling a sending behavior of the first control unit, the data sending end and a data receiving end are in communication connection, the data receiving end includes a second buffer for controlling a sending behavior of the data sending end, and the device includes:

[0024] A detection module is configured to perform state detection on the second buffer by the second control unit, and obtain a state of the second buffer.

[0025] A determination module is configured to determine control information of the first control unit based on the state by the second control unit.

[0026] a response module, configured to, in response to the control information indicating that the data transmission occasion is met, send, by the first control unit, a data packet to the data receiving end.

[0027] In the foregoing solution, the determination module is further configured to: obtain a current residual credit value of the second control unit; update the residual credit value based on the state to obtain an updated credit value; when the updated credit value is greater than a credit value threshold, determine that the control information of the first control unit meets the data transmission occasion; and when the updated credit value is less than or equal to the credit value threshold, determine that the control information of the first control unit does not meet the data transmission occasion.

[0028] In the foregoing solution, the determination module is further configured to: when the state is a first state used to inform the data sending end that there is a credit identifier to be recycled, add 1 to the residual credit value to obtain the updated credit value; and when the state is a second state used to inform the data sending end that there is no credit identifier to be recycled, determine the residual credit value as the updated credit value.

[0029] An electronic device is provided in an embodiment of the present application, and the electronic device comprises:

[0030] a memory configured to store computer executable instructions or computer programs;

[0031] a processor configured to execute the computer executable instructions or computer programs stored in the memory to implement the data interaction method provided in the embodiments of the present application.

[0032] A computer readable storage medium is provided in an embodiment of the present application, and the computer readable storage medium stores computer executable instructions or computer programs, and is configured to cause a processor to execute the data interaction method provided in the embodiments of the present application when the computer executable instructions or computer programs are executed.

[0033] A computer program product is provided in an embodiment of the present application, and the computer program product comprises computer programs or computer executable instructions stored in a computer readable storage medium. A processor of an electronic device reads the computer executable instructions or computer programs from the computer readable storage medium, and the processor executes the computer executable instructions or computer programs, so that the electronic device executes the data interaction method provided in the embodiments of the present application.

[0034] The embodiments of the present application have the following beneficial effects:

[0035] The first buffer zone is an asynchronous data buffer core, which stores clock domain adaptation data sending end, clock domain adaptation receiving end itself reading data, receives data packets sent by the data sending end, and stores the data packets into the first buffer zone; reads the to-be-processed data from the first buffer zone, processes the to-be-processed data, and deletes the to-be-processed data from the first buffer zone in response to the completion of data processing, ensuring the stability of the whole process from receiving to buffering to processing without error; on this basis, the receiving end generates a credit identifier after deleting the processed data in the first buffer zone, and updates the state through the second buffer zone, so that the second buffer zone becomes a bridge for accurately delivering buffer space release information, which not only ensures the real-time performance of credit feedback, but also avoids the timing risk of cross-clock domain signal transmission, so that the data sending end can accurately perceive the buffer available state of the receiving end, thereby controlling the sending opportunity to prevent the first buffer zone from overflowing due to too fast sending or data interruption due to too slow sending. The first buffer zone ensures the stability of data circulation in the receiving end, and the second buffer zone ensures the stability of the interaction rhythm between the sending end and the receiving end, and the two together build a whole-link stable mechanism from data receiving, processing to feedback control, significantly reducing the error risk caused by clock difference and rhythm mismatch in asynchronous data interaction, thereby effectively improving the stability of data interaction. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is an architecture schematic diagram of a data interaction system provided by an embodiment of the present application;

[0037] Figure 2 is a structural schematic diagram of an electronic device for data interaction provided by an embodiment of the present application Figure 1 ;

[0038] Figure 3 is a structural schematic diagram of an electronic device for data interaction provided by an embodiment of the present application Figure 2 ;

[0039] Figure 4 is a flow schematic diagram of a data interaction method provided by an embodiment of the present application Figure 1 ;

[0040] Figure 2 is a flow schematic diagram of a data interaction method provided by an embodiment of the present application Figure 6 ;

[0041] Figure 1 is a schematic diagram of the principle of a data interaction method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0043] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0044] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0046] Before the embodiments of the present application are further described in detail, the terms and phrases involved in the embodiments of the present application are explained, and the terms and phrases involved in the embodiments of the present application are applicable to the following explanations.

[0047] 1) Asynchronous first-in-first-out buffer (AFIFO): a storage component for cross-clock domain data storage and transmission, the core feature of which is that read operation and write operation can be independently executed in different clock domains, and data ordered access is realized through asynchronous management of read pointer and write pointer. The first buffer (temporary data packet) and the second buffer (feedback state) in the present application both adopt this structure: the clock domain of the write port is consistent with the data writing party (sending end or receiving end processing module), and the clock domain of the read port is consistent with the data reading party (receiving end processing module or sending end second control unit); by judging the value relationship between the read pointer and the synchronized write pointer, it can be determined that the buffer is "empty" (no data / state to be read) or "non-empty" (data / state to be read), which is the core component to solve the timing conflict of asynchronous data interaction.

[0048] 2) Credit identifier: In the asynchronous data flow control mechanism, a signal or a logical identifier representing the release of the data receiving end buffer space, usually generated by the receiving end after completing data processing and releasing the buffer. In this application, the data receiving end processing module deletes the processed data in the first buffer, and generates a credit identifier; the core function of this identifier is to feedback to the data sending end that "the receiving end has released 1 unit of initial buffer space", triggering the sending end to recover the corresponding "credit" (i.e. the remaining credit value plus 1), and then providing a basis for the sending end to judge whether it has the permission to send new data packets. It is the key feedback carrier connecting the receiving end buffer state and the sending behavior of the sending end.

[0049] 3) Asynchronous clock domain: Refers to two or more independent clock modules working in a digital system, whose clock signals have no fixed synchronization relationship in frequency and phase. For example, in the data interaction scenario of this application, the data sending end (such as a millimeter wave radar, working clock frequency 180MHz) and the data receiving end (such as an autonomous driving domain controller, working clock frequency 120MHz) are in different asynchronous clock domains, and there is no mandatory synchronization requirement for their clock signals; this feature may cause timing conflicts during cross-domain data transmission, which needs to be avoided through asynchronous adaptation design (such as clock synchronization circuit, asynchronous buffer) to avoid data loss or errors.

[0050] In the implementation process of the embodiments of the present application, the applicant finds that the related art has the following problems:

[0051] In the scene with high requirements for data transmission real-time and reliability (such as medical ultrasound image transmission, vehicle-mounted millimeter wave radar data interaction), the technical solution of the related art may cause medical diagnosis deviation due to data errors caused by metastable state, and radar data loss caused by buffer overflow may affect autonomous driving decision, which seriously restricts the application of asynchronous data interaction system in high requirement field, thereby leading to poor stability of data interaction in the related art.

[0052] The embodiments of the present application provide a data interaction method, device, electronic equipment, computer readable storage medium and computer program product, which can effectively improve the stability of data interaction. The following describes an exemplary application of the data interaction system provided by the embodiments of the present application.

[0053] Referring to Figure 1 , Figure 2 is an architecture schematic diagram of the data interaction system 100 provided by the embodiments of the present application. The terminal (exemplarily shown as the terminal 400) connects the server 200 through the network 300, and the network 300 can be a wide area network or a local area network, or a combination of the two.

[0054] The terminal 400 is used by a user to use the client 410, and a graphical interface 410-1 (exemplarily shown) displays interactive data. The terminal 400 and the server 200 are connected to each other through a wired or wireless network.

[0055] In some embodiments, the server 200 can be a stand-alone physical server, a server cluster composed of multiple physical servers, or a business system, and can also be a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and basic cloud computing services such as big data and artificial intelligence platforms. The terminal 400 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart television, a smart watch, a vehicle-mounted terminal, and the like, but is not limited thereto. The electronic device provided by the embodiments of the present application can be implemented as a terminal or a server. The terminal and the server can be directly or indirectly connected through wired or wireless communication, which is not limited in the embodiments of the present application.

[0056] In some embodiments, the server 200 is a data receiving end, and the terminal 400 is a data sending end. The terminal 400 sends a data packet, and the server 200 stores the data packet in a first buffer. The server 200 reads to-be-processed data from the first buffer, processes the to-be-processed data, and deletes the to-be-processed data from the first buffer in response to completion of the data processing. In response to the to-be-processed data being deleted from the first buffer, the server 200 generates a credit identifier between the terminal 400 and the server 200, and updates a state of a second buffer based on the credit identifier. The state is used by the terminal 400 to regulate a sending time of the data packet.

[0057] In some other embodiments, the server 200 is a data sending end, and the terminal 400 is a data receiving end. The server 200 sends a data packet, and the terminal 400 stores the data packet in a first buffer. The terminal 400 reads to-be-processed data from the first buffer, processes the to-be-processed data, and deletes the to-be-processed data from the first buffer in response to completion of the data processing. In response to the to-be-processed data being deleted from the first buffer, the terminal 400 generates a credit identifier between the server 200 and the terminal 400, and updates a state of a second buffer based on the credit identifier. The state is used by the server 200 to regulate a sending time of the data packet.

[0058] Referring to Figure 2 , Figure 1 is a structure diagram of an electronic device for data interaction provided by the embodiments of the present application Figure 2 , wherein Figure 1 The electronic device 500 shown in FIG. 13 can be Figure 2the server 200 or the terminal 400 in the network, Figure 2 The electronic device 500 shown includes at least one processor 430, a memory 450, and at least one network interface 420. The various components in the electronic device 500 are coupled together by a bus system 440. It can be appreciated that the bus system 440 is used for implementing connection communication between the components. The bus system 440 includes, in addition to a data bus, a power bus, a control bus, and a state signal bus. However, for the sake of clarity, only the data bus is shown in Figure 2 Various buses are collectively referred to as the bus system 440 in the description.

[0059] The processor 430 can be an integrated circuit chip that has the processing capability of signals, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor.

[0060] The memory 450 can be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical drives, etc. The memory 450 optionally includes one or more storage devices physically located in proximity to the processor 430.

[0061] The memory 450 includes volatile memory or non-volatile memory, and can also include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), and the volatile memory can be random access memory (RAM). The memory 450 described in the embodiments of the present application is intended to include any suitable type of memory.

[0062] In some embodiments, the memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, which are described below.

[0063] The operating system 451 includes system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0064] The network communication module 452 is configured to communicate with other electronic devices via one or more (wired or wireless) network interfaces 420, such as Bluetooth, Wireless Fidelity (WiFi), and Universal Serial Bus (USB), etc.

[0065] In some embodiments, the data interaction apparatus provided by the embodiments of the present application can be implemented in a software manner, Figure 3 The data interaction apparatus 455 stored in the memory 450 is shown, which can be software in the form of programs and plug-ins, and includes the following software modules: a receiving module 4551, a data processing module 4552, and a responding module 4553. These modules are logical, and thus can be combined or further split according to the implemented functions. The functions of the modules will be described below.

[0066] Referring to Figure 3 , Figure 2 is a structural diagram of an electronic device for data interaction provided by the embodiments of the present application Figure 3 , wherein Figure 1 The electronic device 600 shown can be the server 200 or the terminal 400 in Figure 3 , the server 200 or the terminal 400 in Figure 3 The electronic device 600 shown includes at least one processor 530, a memory 550, and at least one network interface 520. The various components in the electronic device 600 are coupled together by a bus system 540. The bus system 540 is used to realize the connection communication between the components. In addition to the data bus, the bus system 540 also includes a power bus, a control bus, and a status signal bus. However, for the purpose of clarity and conciseness, all the buses are marked as the bus system 540 in Figure 3 .

[0067] The processor 530 can be an integrated circuit chip with signal processing capability, such as a general-purpose processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0068] The memory 550 can be removable, non-removable, or a combination thereof. The exemplary hardware devices include solid-state memory, a hard disk drive, an optical disk drive, etc. The memory 550 can optionally include one or more storage devices that are physically located away from the processor 530.

[0069] The memory 550 includes volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile memory can be read only memory (ROM), and the volatile memory can be random access memory (RAM). The memory 550 described in the embodiments of the present application is intended to include any suitable type of memory.

[0070] In some embodiments, the memory 550 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, which are exemplarily explained below.

[0071] The operating system 551 includes system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.

[0072] The network communication module 552 is used to communicate with other electronic devices via one or more (wired or wireless) network interfaces 520, and exemplary network interfaces 520 include Bluetooth, Wireless Fidelity (WiFi), Universal Serial Bus (USB), and the like.

[0073] In some embodiments, the data interaction device provided by the embodiments of the present application can be realized in a software manner, Figure 4 The data interaction device 555 stored in the memory 550 is shown, which can be software in the form of programs and plug-ins, including the following software modules: a detection module 5551, a determination module 5552, and a response module 5553. These modules are logical, and thus can be combined or further split according to the functions implemented. The functions of each module will be described below.

[0074] In some embodiments, the data interaction apparatus provided by the embodiments of the present application can be implemented in a hardware manner. For example, the data interaction apparatus provided by the embodiments of the present application can be a processor in the form of a hardware decoding processor, which is programmed to execute the data interaction method provided by the embodiments of the present application. For example, the processor in the form of a hardware decoding processor can be one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), or other electronic elements.

[0075] In some embodiments, the terminal or server can implement the data interaction method provided by the embodiments of the present application by running a computer program or computer executable instruction. For example, the computer program can be a native program (for example, a dedicated data interaction program) in an operating system or a software module, for example, a data interaction module embedded in any program (for example, an instant messaging client, a photo album program, an electronic map client, a navigation client), or a native application (APP) that needs to be installed in an operating system to run. In summary, the computer program can be any form of application program, module or plug-in.

[0076] The data interaction method provided by the embodiments of the present application will be described in combination with an exemplary application and implementation of the server or terminal provided by the embodiments of the present application.

[0077] Referring to Figure 4 , Figure 1 is a flowchart of the data interaction method provided by the embodiments of the present application Figure 4 The data interaction method provided by the embodiments of the present application will be described in combination with the steps 101 to 105 shown in Figure 6 The data interaction method provided by the embodiments of the present application can be implemented by the data receiving end and the data sending end in cooperation. The data receiving end includes a first buffer for asynchronous processing and caching data, and a second buffer for controlling the sending behavior of the data sending end. In the following, the data receiving end will be described as an example of separate implementation.

[0078] In some embodiments, the first buffer is an asynchronous first-in-first-out buffer (AFIFO) having both functions of "data asynchronous processing across clock domains" and "data buffering at the receiving end". The "asynchronous processing" means that the buffer can adapt to independent clock domains of the data sending end and the data receiving end (i.e., the sending end clock and the receiving end clock are not synchronized in frequency or phase), and eliminate data sampling errors caused by cross-clock-domain transmission through an asynchronous read-write mechanism. The "data buffering" means that the buffer can temporarily store data packets sent by the data sending end until the data receiving end completes processing of the previous data, thereby avoiding data loss caused by a mismatch between the processing speeds of the sending end and the receiving end. Specifically, when the data sending end sends a data packet, the data packet is first written into the write port of the first buffer (driven by the sending end clock) and queued in the first buffer in the order of writing. The data receiving end reads the data to be processed from the first buffer in sequence through the read port (driven by the receiving end clock), thereby realizing "first-in-first-out" data flow.

[0079] In some embodiments, the second buffer is also an asynchronous first-in-first-out buffer (AFIFO), and its core function is to feed back the "credit status" to the data sending end, thereby indirectly controlling the data packet sending behavior of the sending end. Unlike the first buffer, the second buffer is not used to store actual service data, but only to pass state information (i.e., empty state or non-empty state) of "whether there is a recyclable credit". When the data receiving end reads and deletes the data to be processed from the first buffer (releases the cache space of the first buffer), a credit identifier (representing "the first buffer adds an available space") is generated, and the state of the second buffer is updated from "empty" to "non-empty" by triggering the write operation of the second buffer (driven by the receiving end clock). The data sending end perceives the "non-empty state" by monitoring the state of the read port of the second buffer (driven by the sending end clock), and then judges that the credit can be recycled and new data packets can be sent. This design enables the second buffer to complete credit feedback only through the change of the empty and full states without passing the specific value of the credit identifier, thereby greatly simplifying the complexity of cross-clock-domain synchronization. The first buffer, as an "asynchronous channel and temporary warehouse" for data transmission, solves the problems of reliable reception and temporary storage of data in an asynchronous system. The second buffer, as an "asynchronous feedback channel" for credit status, realizes flow control coordination between the sending end and the receiving end through a simple state transmission, and the combination of the two forms an efficient and low-complexity asynchronous data interaction mechanism.

[0080] In step 101, a data packet sent by the data sending end is received and stored in the first buffer.

[0081] In some embodiments, the data receiving end and the data sending end implement the starting link of asynchronous data interaction, the core is to rely on the "cross clock domain adaptation" and "data storage" dual functions of the first buffer (asynchronous first-in-first-out buffer, AFIFO), to ensure that the data packet can be safely and orderly received and stored in the scene where the sending end and the receiving end clocks are completely independent, because the data sending end and the data receiving end belong to different clock domains (i.e. the sending end clock frequency, phase and receiving end clock have no synchronization relationship), direct data packet transmission is easy to cause data error due to "clock sampling timing deviation", therefore the write port of the first buffer is designed to be bound with the data sending end clock domain (i.e. the write operation of the first buffer receiving data packet is driven by the sending end clock), to adapt to the data packet output rhythm of the sending end, which is the basis for realizing asynchronous data reception. At the same time, before executing this step, the data receiving end will first complete two state determinations: one is to determine that the first buffer is currently in a "non-full state" (i.e. the used cache space of the first buffer does not reach its total depth, and there is still remaining space to store new data packets), to avoid buffer overflow caused by data packet writing; the second is to determine that the used space of the first buffer does not exceed the initial available cache space corresponding to the initial total credit amount agreed by the data sending end and the receiving end in advance (i.e. the current remaining credit value of the sending end is still greater than 0, with sending permission), to ensure that the execution of this step is consistent with the overall Credit flow control logic. The receiving and writing process of the data packet needs to follow strict timing coordination: when the data sending end generates a data packet to be sent, it will send a "data packet sending request" signal to the data receiving end (the signal is synchronized with the sending end clock); the data receiving end recognizes the "sending request" through asynchronous signal detection logic, and triggers the "write enable" signal of the first buffer at the valid edge (usually the clock rising edge) of the sending end clock — at this time, the write port of the first buffer will sample the data packet (including data payload, data identifier, check information, etc.) transmitted by the sending end according to the timing of the sending end clock, to ensure that each bit of information of the data packet can be accurately read within the stable window of the sending end clock, avoiding "data sampling misplacement" caused by clock asynchronization. The specific storage operation of the data packet written into the first buffer: the first buffer internally contains storage units (such as register array or RAM) arranged in address order, and its write pointer (used to indicate the storage address of the next data packet to be written) adopts Gray code encoding (only 1 bit changes between adjacent addresses, to avoid metastability when synchronizing across clock domains).When the "write enable" signal is valid and the data packet sampling is completed, the first buffer writes the sampled complete data packet to the storage unit currently pointed by the write pointer; after the write operation is completed, the write pointer of the first buffer is automatically incremented by 1 bit under the driving of the sending end clock according to the Gray code rule, and points to the subsequent new data packet to be written address, so as to prepare the address for the next data packet receiving and storing. The state update and boundary protection after storage need to be completed: after the data packet is successfully written into the first buffer, the data receiving end updates the "used cache space count" of the first buffer (increases the used space value by 1) and updates the "remaining available space count" (decreases the remaining space value by 1) synchronously, so as to reflect the storage state of the first buffer in real time and provide a state basis for the subsequent step of "reading the to-be-processed data from the first buffer". If the data receiving end detects that the write pointer of the first buffer and the "synchronized read pointer" (the read pointer is synchronized from the receiving end clock domain and is used to indicate the address of the read data) satisfy the "full state judgment condition" (that is, the highest bit of the write pointer and the synchronized read pointer is opposite and the remaining bits are the same) during the execution of this step, the "write enable" signal of the first buffer will be turned off immediately, and the reception of new data packets will be stopped, until the first buffer releases space due to subsequent data reading and restores the "non-full state", and then the execution of this step is restarted, thereby completely avoiding the risk of buffer overflow. Through the clock domain adaptation design, the front state judgment, the timing cooperative writing and the boundary protection mechanism of the first buffer, the timing deviation problem of data packet receiving under asynchronous clock is solved, and through the combination with the Credit flow control logic, it is ensured that the storage process of the data packet is always in the "safe and controllable" range, thereby laying a reliable data foundation for the subsequent data processing link.

[0082] In some embodiments, before the data packet sent by the data sending end is received, the following processing can also be performed: the data receiving end and the data sending end agree on an initial storage space corresponding to the initial available cache space of the first buffer, and the initial storage space is used to indicate the initial cache carrying capacity of the data receiving end agreed by the data receiving end and the data sending end.

[0083] In some embodiments, before performing the step of "receiving the data packet sent by the data sending end", the data receiving end and the data sending end need to first complete the agreement of "initial storage space corresponding to the initial available cache space of the first buffer", which is the core basis for ensuring the "cache carrying capacity alignment" and "flow control logic synchronization" in the initialization stage of the asynchronous system. The purpose is to clearly define the initial cache acceptance limit of the data receiving end through pre-consensus, to avoid data overflow or sending block caused by inconsistent understanding of "initial available cache space" between the sending end and the receiving end, and to clearly define the definition and technical connotation of "initial storage space": the "initial storage space" is a quantitative indicator representing the "initial available cache capacity" of the first buffer, which is jointly confirmed by the data receiving end and the data sending end. The value directly corresponds to the maximum space capacity of the first buffer that can be used to store data packets after the system initialization is completed (before receiving any data packet) — this capacity needs to be determined in combination with the physical design parameters of the first buffer (such as the total storage depth of the first buffer, the hardware reserved redundant space, etc.), for example: if the total storage depth of the first buffer is 32 data packets (i.e. up to 32 standard size data packets can be stored), and no redundant space is required in the hardware design, the "initial storage space" agreed by the data receiving end and the sending end can be set to the space corresponding to 32 data packets; if 2 data packets of redundant space are required for burst data buffering, the "initial storage space" can be set to the space corresponding to 30 data packets. It should be particularly noted that the unit of "initial storage space" matches the size of data packet (such as "data packet number" or "byte number"), and the unit needs to be synchronized and clearly defined in the agreement stage to ensure that there is no bias in the understanding of "space capacity" between the two parties.

[0084] In some embodiments, the initial storage space" agreement process and implementation: this agreement process does not require real-time cross-clock domain signal interaction between the data receiving end and the sending end (avoiding asynchronous synchronization delay and metastable risk), which can be implemented by the following methods: in the system design stage (or before power-on reset), the data receiving end and the sending end reach an agreement through pre-set configuration — for example, through the hardware design document to explicitly indicate the initial available space parameters of the first buffer, or load the same "initial storage space" value through the pre-solidified configuration register (located in the data receiving end and the sending end, respectively) of both parties when the system is reset; if it is a configurable system, the same "initial storage space" configuration value can also be written to the data receiving end and the sending end by the host computer or control module, ensuring that both parties have obtained consistent initial cache capability information before the data interaction starts. The core advantage of this agreement process is that it omits the step of "the data receiving end sending an initial cache space notification signal to the sending end" in traditional asynchronous systems, avoiding the delay and metastable risk of the notification signal across the clock domain, and simplifying the system initialization process.

[0085] In some embodiments, the core role of the initial storage space" — representing the initial cache carrying capacity of the data receiving end: for the data receiving end, the "initial storage space" is the "maximum receivable data upper limit" before receiving the first data packet, and the data receiving end will use this value as the monitoring benchmark of the "first buffer used space" in the initial state, for example: if the initial storage space is 30 data packets, the data receiving end will set the "used space threshold" to 30 after initialization, and when the used space reaches 30 due to subsequent data packet reception, it will be determined that the first buffer has exhausted the initial available space, and temporarily stop receiving new data packets to avoid exceeding its initial cache carrying capacity; for the data sending end, this "initial storage space" directly corresponds to its "initial credit total" in the initialization stage (i.e., the maximum number of data packets that the sending end can initially send), and the sending end does not need to wait for the notification of the data receiving end to determine the initial sending permission (such as 30 data packets of initial storage space, then the initial remaining credit value of the sending end is 30), further confirming the basic role of "initial storage space" in synchronizing the flow control logic of both parties.

[0086] In some embodiments, the initial storage space is not a static parameter, but a reference for the buffer state monitoring in the subsequent data receiving process. When performing the step of receiving data packets and storing them in the first buffer, the data receiving end will real-time statistics the used storage space of the first buffer (the used storage space increases by 1 for each stored data packet), and compare the used storage space with the agreed initial storage space. If the used storage space is less than the initial storage space, it is determined that the first buffer still has initial available space, and the data packet receiving is allowed to continue. If the used storage space is equal to the initial storage space, it is determined that the first buffer has reached the initial buffer carrying upper limit, and the protection mechanism of “suspending receiving” is triggered until the first buffer releases space due to data reading (the used storage space is less than the initial storage space) and the receiving operation is resumed. The logic of “agreed reference-real-time monitoring-boundary protection” ensures that the initial buffer usage of the data receiving end is always in a safe and controllable range, providing a guarantee for the reliability of the initialization phase of asynchronous data interaction.

[0087] In this way, the agreed manner can completely omit the step of “the data receiving end sending an initial buffer space notification signal to the data sending end” in the traditional asynchronous data interaction system, effectively avoiding the metastable state risk and transmission delay of the notification signal in the cross-clock domain synchronization process, significantly simplifying the system initialization process and shortening the system startup time. For the data receiving end, the initial storage space provides a clear initial buffer carrying upper limit, so that it can accurately judge whether it has the receiving ability by monitoring the comparison between the used storage space and the initial value before receiving the data packet, avoiding the data packet overflow problem caused by initial buffer space cognitive bias from the source. At the same time, for the data sending end, the initial storage space can be directly mapped to the initial credit total amount in the initialization phase, without waiting for any feedback from the receiving end to quickly determine the initial sending permission range, ensuring that the sending end can start data transmission in time and improving the overall interaction efficiency. The pre-consensus of both parties can also achieve accurate matching of the sending pace of the sending end and the initial buffer carrying capacity of the receiving end, avoiding the sending blockage or buffer waste caused by the asynchronous initial buffer information in the traditional scheme. Ultimately, on the basis of ensuring the reliability of asynchronous system data interaction, the system hardware design complexity and timing control difficulty are further reduced, which meets the core application requirements of high reliability and low delay of asynchronous Credit flow control mechanism.

[0088] In some embodiments, the above receiving the data packet sent by the data sending end can be implemented by the following way: detecting the used storage space of the first buffer, and comparing the used storage space with the initial storage space to obtain a comparison result; in response to the comparison result indicating that the used storage space is less than the initial storage space, receiving the data packet sent by the data sending end.

[0089] In some embodiments, the detection manner and quantification standard of the "used storage space" are as follows: the "used storage space" refers to the total amount of cache space occupied by the currently stored data packets in the first buffer, and the quantification unit is consistent with that of the "initial storage space" (e.g., both in the unit of "number of data packets" or "number of bytes"), so as to ensure the effectiveness of the comparison logic. The data receiving end detects the used storage space in real time by the following manner: the first buffer is internally configured with a "write pointer" (driven by the sending end clock, indicating the address of the next data packet to be written) and a "read pointer" (driven by the receiving end clock, indicating the address of the next data packet to be read), both of which are encoded in Gray code to meet the synchronization requirement across clock domains; the data receiving end synchronizes the "write pointer" of the sending end clock domain to the receiving end clock domain under its own clock domain through a special synchronization circuit to obtain a "synchronized write pointer", and then calculates the difference between the "synchronized write pointer" and the local "read pointer" of the receiving end (e.g., through binary difference conversion logic, converts the difference between the Gray code pointers into the number of data packets in decimal), which is the current "used storage space" of the first buffer. This detection manner based on the difference between the pointers can accurately reflect the occupation of the cache space in real time under an asynchronous clock environment, and does not require additional counting circuits, thus simplifying the hardware implementation.

[0090] In some embodiments, before receiving the data packet, the data receiving end compares the "used storage space" detected above with the "initial storage space" agreed upon in the system initialization stage through a comparator. The comparison result is divided into two cases: if "used storage space < initial storage space", it indicates that the currently occupied space of the first buffer has not reached the initial agreed cache carrying upper limit, and there is still remaining initial available space to accommodate new data packets; if "used storage space ≥ initial storage space", it indicates that the initial available space of the first buffer has been exhausted (or has been excessively occupied), and continuing to receive data packets may exceed its initial cache carrying capacity, which poses a risk of overflow. The comparison process is completed in the data receiving end clock domain and is synchronized with the detection timing of the data packet reception request (e.g., the comparison is performed once in each receiving end clock cycle), so as to ensure that the comparison result can respond to the state change of the first buffer in real time and provide timely basis for the reception permission judgment.

[0091] In some embodiments, when the comparison result indicates that the used storage space is less than the initial storage space, the data receiving end triggers a "receive enable" signal (synchronized with the receiving end clock) to allow the write port of the first buffer to receive the data packet sent by the data sending end. Specifically, the "receive enable" signal opens the input data path of the first buffer, and the data packet sent by the sending end is written into the corresponding storage unit of the first buffer according to the timing rules described above under the driving of the sending end clock, while triggering the used storage space count update (the used storage space value is incremented by 1). If the comparison result indicates that the used storage space is greater than or equal to the initial storage space, the data receiving end keeps the receive enable signal in an invalid state to prohibit the first buffer from receiving new data packets. At this time, even if the data sending end sends data packets, the write port of the first buffer will be in a closed state to avoid buffer overflow caused by writing data packets. The essence of this comparison-enable linkage mechanism is to convert the initial storage space, which is a preset benchmark, into a real-time receive control signal to ensure that the initial buffer usage of the data receiving end is always within a safe threshold, avoiding the risk of overflow caused by blind sending of the sending end, and achieving the coordinated awareness of the initial buffer capacity of the sending end and the receiving end through binding with the initial agreement, thereby laying a foundation for stable startup and data interaction of the asynchronous system.

[0092] In this way, by dynamically monitoring the space occupation state of the first buffer in real time and taking the initial storage space agreed by both parties as the benchmark threshold, it can be ensured that the data receiving end always restricts the data packet receiving behavior within the initial buffer carrying capacity during the system initialization phase, fundamentally avoiding data packet overflow or loss caused by exceeding the initial buffer upper limit, and significantly improving the reliability of asynchronous data interaction. At the same time, this comparison logic based on the local storage state and the preset benchmark can realize receive permission judgment without additional cross-clock domain signal interaction between the data receiving end and the sending end, effectively reducing the delay and metastable state risk introduced by complex communication protocols or synchronization mechanisms in traditional solutions, simplifying the system control logic and hardware implementation complexity, and enabling the receiving rhythm of the data receiving end to be accurately matched with the initial buffer capacity, avoiding waste of buffer resources caused by blind receiving, while providing a clear feedback boundary for the initial sending behavior of the data sending end, indirectly promoting the coordination of the data interaction rhythm between the sending end and the receiving end, ultimately improving the overall data transmission efficiency on the basis of ensuring system stability, and being particularly suitable for asynchronous communication scenarios with high real-time and reliability requirements.

[0093] In step 102, the to-be-processed data is read from the first buffer, and the to-be-processed data is processed.

[0094] In some embodiments, reading the to-be-processed data from the first buffer and performing data processing to obtain a data processing result is a core link for the data receiving end to realize effective utilization of data. This process needs to consider both the data reading reliability in the asynchronous clock environment and the correctness of the processing logic, and the specific implementation is as follows: first, the data receiving end triggers the reading operation under its own clock domain (consistent with the clock of the first buffer reading port) by monitoring the state of the first buffer — when the first buffer is in a "non-empty state" (i.e., the write pointer and the read pointer after synchronization are not equal, indicating that there is to-be-processed data that has not been read), the data receiving end generates a "read enable" signal, which is synchronized with the active edge (such as the rising edge) of the receiving end clock, driving the reading port of the first buffer to read data in the "first-in, first-out" order. The read pointer (using Gray code encoding) of the first buffer is incremented according to the Gray code rule when the "read enable" signal is active, pointing to the storage address of the subsequent to-be-read data, ensuring that each reading operation corresponds to the earliest to-be-processed data written in the first buffer, avoiding data reading disorder. The to-be-processed data read will be transmitted to the processing module (such as data parsing unit, operation unit or protocol processing unit, etc.) of the data receiving end for targeted data processing: the processing can include but is not limited to data verification (such as CRC verification, parity verification, used to verify the integrity of data transmission), format conversion (such as converting serial data to parallel data, or parsing data frame structure according to a predetermined protocol), business logic operation (such as extracting valid fields in the data, executing a predetermined algorithm processing), etc. The specific processing method needs to be determined according to the application scenario of the data receiving end, but it needs to ensure the real-time and accuracy of the processing process to meet the subsequent data use requirements. The data processing result obtained after processing can be output to the subsequent functional module (such as storage module, display module or other interactive module) of the data receiving end according to the system design, or used as feedback information to participate in other control logic of the data receiving end; at the same time, the completion of this processing process marks the end of the life cycle of the corresponding to-be-processed data in the first buffer, laying a foundation for subsequent "deleting to-be-processed data from the first buffer" and "generating credit identifier".

[0095] As an example, in the context of a data receiving end applied to a CXS (Credited eXtensible Stream) high-speed interconnection interface, reading data to be processed from a first buffer, performing data processing on the data to be processed, and obtaining a data processing result are described. In the CXS interface scenario, the first buffer is an asynchronous first-in-first-out buffer (AFIFO), the read port of which is bound to the clock domain (Rx_clk, frequency 200MHz) of the data receiving end, and is used to temporarily store the data to be processed in the form of a TLP (Transaction Layer Packet) transmitted by the data sending end through the CXS interface (each TLP packet contains an 8-byte header, a 32-byte data payload, and a 4-byte CRC check field). When the data receiving end detects the "non-empty state" of the first buffer through a synchronization circuit (i.e., there is a difference between the write pointer and the read pointer after synchronization, indicating that there is an unread TLP packet in the buffer memory), the "read enable" signal will be triggered at the rising edge of Rx_clk; the read pointer (encoded using a 3-bit Gray code, with an initial value of 000) of the first buffer increments from 000 to 001 according to the Gray code rule when the "read enable" signal is valid, pointing to and reading the first written TLP packet (i.e., the earliest received TLP packet) in the buffer, and transmitting the complete data (a total of 44 bytes) of the TLP packet to the TLP processing module of the data receiving end. The TLP processing module performs the following data processing operations on the read TLP packet: first, perform CRC32 check, compare the 4-byte CRC check value at the end of the TLP packet with the CRC value calculated by the processing module according to the header and data payload, if they are consistent, it is determined that the data transmission is error-free, if they are not consistent, the TLP packet is marked as invalid and a retransmission request is triggered; second, parse the TLP header field, extract key information such as transaction type (such as "memory read request", "I / O write request"), target address (such as 0x1000_0000), and data length (32 bytes), and temporarily store these information in the registers of the processing module; third, perform targeted business processing according to the transaction type - if it is a "memory read request", send the parsed target address to the local memory controller of the data receiving end, read 32 bytes of response data from the corresponding address by the controller, and associate the response data with the transaction identifier in the original TLP header; if it is an "I / O write request", write the data payload of the TLP packet to the register corresponding to the parsed I / O address (such as 0x0000_8000), completing the configuration of the external device.After the above processing is completed, the obtained data processing result is divided into two categories according to different transaction types: for a "memory read request", the processing result is "32-byte response data associated with the transaction identification", which will be transmitted to the sending preprocessing module of the data receiving end to generate a response TLP packet and feed back to the data sending end; for an "I / O write request", the processing result is a "write operation completion status signal" (high level indicates success), which will be transmitted to the state monitoring module of the data receiving end to update the configuration state of the I / O device. In the whole process, the reading operation of the first buffer strictly follows the clock domain timing of the receiving end, and the data processing operation is deeply adapted to the protocol specification of the CXS interface, which not only ensures the reliability of data reading in the asynchronous environment, but also realizes the business value of the to-be-processed data through targeted processing, and provides necessary support for the generation of subsequent flow control credit and data interaction closed loop.

[0096] In step 103, in response to the completion of the data processing, the to-be-processed data is deleted from the first buffer.

[0097] In some embodiments, deleting the to-be-processed data from the first buffer refers to a logical operation of changing the storage unit where the to-be-processed data is located from the "occupied state" to the "reusable state" by updating the read pointer of the first buffer, rather than physically erasing the data in the storage unit. The trigger condition of the operation can be that the data receiving end has completed processing of the to-be-processed data (i.e., obtained the data processing result), ensuring that the data has been effectively utilized and avoiding data loss due to premature deletion. Specifically, the read pointer of the first buffer (encoded in Gray code to adapt to the cross-clock domain synchronization requirement) is bound to the clock domain of the data receiving end. When the data receiving end confirms that the processing of the to-be-processed data is completed, a read operation will be performed at the active edge (such as the rising edge) of the receiving end clock, and the read pointer is directly driven to increment through the read operation. At the same time, the design allows temporary saving of data through an external temporary storage mechanism after the read operation, as long as the temporary storage logic is matched with the read operation timing to prevent data loss. The signal drives the read pointer to move from the current to-be-processed data address to the next to-be-read data address (if the current one is the last to-be-processed data, the initial address is moved to). After the read pointer is updated, the storage unit where the original to-be-processed data is located is no longer considered "occupied", and its address is included in the "available address pool" of the first buffer, which can be pointed to and overwritten by the write pointer when receiving a new data packet in the future, realizing the recycling of the cache space. The deletion operation directly causes the used storage space of the first buffer to decrease by one unit (matching the storage granularity of the to-be-processed data), and the released space corresponds to the newly available cache capability of the first buffer, providing a physical basis for "generating a credit identifier in response to data deletion" - that is, through the movement of the read pointer, the release state of the cache space of the first buffer is objectively reflected, enabling the data receiving end to accurately perceive and feedback permission information to the data sending end that the data packet can continue to be sent, thereby completing the flow control closed loop of asynchronous data interaction.

[0098] In step 104, in response to the existence of the deletion of the to-be-processed data from the first buffer, a credit identifier between the data sending end and the data receiving end is generated.

[0099] In some embodiments, the generation of the credit identifier between the data sending end and the data receiving end in response to the existence of the to-be-processed data being deleted from the first buffer is a key operation for the data receiving end to feedback the buffer space release state to the data sending end, and the core is to convert the space release event of the first buffer into a flow control signal that can be transmitted across the clock domain. The trigger of this operation is strictly synchronized with the action of deleting the to-be-processed data from the first buffer, specifically, when the read pointer of the first buffer is incremented according to the Gray code rule due to data deletion, the logic circuit of the data receiving end will monitor the change of the read pointer in real time (that is, detect the occurrence of the “deletion event”), and trigger the generation logic of the credit identifier at the active edge (such as the rising edge) of the data receiving end clock domain. The generated credit identifier is not a signal containing specific numerical value or data content, but a state marker representing “the first buffer has released a unit of buffer space”, and its generation process does not require complex numerical calculation, but can be realized by simply jumping the logic level — for example, when the read pointer is detected to be incremented, a single-cycle high-level pulse signal is generated, which is the credit identifier, used to indicate that the data sending end can restore a unit of sending permission. The generation of the credit identifier is strictly bound to the clock domain of the data receiving end, ensuring that it is completely aligned in time sequence with the deletion operation of the first buffer, avoiding the generation error of the identifier caused by the delay across the clock domain. The generated credit identifier will directly serve as the trigger source for subsequent updating of the second buffer state, providing a basis for the data sending end to perceive the buffer space release and adjust the sending rhythm, thereby establishing a complete flow control link of “data processing - space release - credit feedback - sending control” in the asynchronous system.

[0100] In some embodiments, the first buffer described above is a first asynchronous first-in-first-out buffer, and the step 104 can be implemented by the following manner: in response to the existence of the to-be-processed data being deleted from the first asynchronous first-in-first-out buffer, and the number of the to-be-processed data deleted in the clock cycle of the data receiving end being one, a credit identifier corresponding to the deleted to-be-processed data is generated in the clock cycle.

[0101] In some embodiments, the first asynchronous first-in-first-out buffer, i.e., the first asynchronous FIFO, has a read port bound to the clock domain of the data receiving end, and the read operation is driven by the clock of the data receiving end. In response to the existence of a to-be-processed data to be deleted from the first asynchronous first-in-first-out buffer, and the number of to-be-processed data deleted in one clock cycle of the data receiving end being one, a credit identifier corresponding to the deleted to-be-processed data is generated in the clock cycle, which is implemented as follows: the read operation of the first asynchronous first-in-first-out buffer is subject to the timing constraint of the clock of the data receiving end, and in each clock cycle, the read pointer can at most complete one increment according to the Gray code rule (i.e., at most one to-be-processed data is read and deleted from the buffer), which is determined by the hardware timing characteristics of the asynchronous FIFO - the update of the read pointer needs to meet the setup time and hold time requirements of the clock of the data receiving end to avoid pointer synchronization errors caused by multiple updates in a single clock cycle. When the data receiving end completes the deletion of one to-be-processed data in one clock cycle (i.e., the read pointer completes one valid increment), its internal logic circuit will detect the deletion event (manifested as the jump of the read pointer) in real time, and trigger the generation logic of the credit identifier at the active edge (such as the rising edge) of the same clock cycle. The generated credit identifier forms a strict one-to-one correspondence with the to-be-processed data deleted in the clock cycle, i.e., the deletion of one to-be-processed data corresponds to the generation of one credit identifier, and the generation operation is limited to be completed in the same clock cycle, ensuring that the generation frequency of the credit identifier does not exceed the clock frequency of the data receiving end. This design not only meets the characteristic of the first asynchronous first-in-first-out buffer "one read operation processing one data", but also avoids the excessive generation of credit identifiers through the constraint of the clock cycle, so that the data sending end can accurately perceive the space release state of the first asynchronous first-in-first- out buffer based on the credit identifier, thereby realizing the accurate transmission of flow control signals in the asynchronous system.

[0102] As an example, in a scenario of applying to a high-speed serial communication interface at a data receiving end, a first asynchronous first-in-first-out buffer is an asynchronous FIFO with a depth of 8, a read port of which is bound to a clock domain of the data receiving end, and a clock frequency of the receiving end is 200 MHz, that is, each clock cycle is 5 ns. A read pointer of the asynchronous FIFO is encoded by a 3-bit Gray code, and an initial value is 000, which is used to point to a to-be-read and to-be-processed data (each data is a 32-bit wide serial deserialized data frame). After a processing module of the data receiving end completes parsing of a first to-be-processed data (stored in a storage unit corresponding to an address 0 of the asynchronous FIFO), a read enable signal is generated at a rising edge (that is, at a time of n x 5 ns) of the n th clock cycle (counting from 0 time, and the n th clock cycle corresponds to a time interval [n x 5 ns, (n + 1) x 5 ns)). The signal drives the read pointer to increase from 000 to 001 according to the Gray code rule, at this time, the to-be-processed data corresponding to the address 0 in the asynchronous FIFO is deleted (that is, the storage unit changes from an occupied state to a reusable state), and in the n th clock cycle, only the deletion operation of the to-be-processed data is completed (because the read pointer can only be effectively incremented once in a single clock cycle, which is limited by the timing constraints of the asynchronous FIFO). At the same time, the credit generation logic of the data receiving end monitors that the read pointer jumps from 000 to 001 in the n th clock cycle (that is, it is detected that a to-be-processed data is deleted), and generates a high-level pulse signal at the rising edge or the falling edge (that is, at a time of (n x 5 ns + 2.5 ns)), and the pulse signal is a credit identifier corresponding to the deleted to-be-processed data. The generation of the credit identifier is strictly limited in the n th clock cycle, and forms a one-to-one correspondence with the to-be-processed data deleted in the cycle, and the generation frequency (200 MHz) does not exceed the clock frequency of the receiving end, which ensures that the data sending end can accurately perceive the space release state of the asynchronous FIFO based on the credit identifier subsequently.

[0103] Thus, the first asynchronous first-in-first-out buffer itself has the characteristic of adapting the asynchronous clock domains of the data sending end and the receiving end, which can avoid the timing deviation of cross-clock-domain data transmission. On this basis, the number of data deleted in a single cycle is constrained by the clock period, and the credit identifier is generated correspondingly, which can make the generation of the credit identifier and the release of the space of the first asynchronous first-in-first-out buffer form a strict one-to-one correspondence, ensure that each credit identifier accurately reflects the release of a unit of cache space, effectively avoid the problem of excessive generation of credits or mismatch between credits and space release caused by multiple data deletions in a single cycle, and enable the data sending end to accurately determine the available state of the cache of the receiving end according to the credit identifier, and then accurately control the data packet sending rhythm. At the same time, the design strictly follows the hardware timing constraint that the read pointer of the first asynchronous first-in-first-out buffer can only be effectively incremented once in a single clock cycle, which can avoid the synchronization error and metastable state risk caused by frequent updating of the read pointer, and improve the timing safety of the credit generation process. In addition, the credit identifier is generated in the same clock cycle as the data deletion, which can minimize the delay of space release and credit feedback, ensure that the data sending end can obtain the change of the cache state of the receiving end in time, reduce the sending blockage or cache waste caused by feedback lag, and finally ensure the reliability of asynchronous data interaction while improving the overall data transmission efficiency, especially suitable for high-speed asynchronous communication scenarios with high requirements for timing accuracy and flow control accuracy.

[0104] In some embodiments, the above-mentioned generation of the credit identifier between the data sending end and the data receiving end can be realized by: determining the storage location of the to-be-processed data deleted from the first buffer in the first buffer; when the storage location is in the initial storage space, generating the credit identifier between the data sending end and the data receiving end.

[0105] In some embodiments, the storage units of the first buffer are arranged in a fixed address order, each storage location corresponds to a unique address code (such as a continuous integer address starting from 0), and the initial storage space corresponds to a pre-agreed continuous address range in the first buffer (for example, addresses 0 to K-1, where K is the size of the initial storage space, matching the initial cache carrying capacity agreed by the data receiving end and the sending end). When the to-be-processed data is deleted from the first buffer, the data receiving end determines the address corresponding to the storage location actually occupied by the to-be-processed data in the first buffer by reading the read pointer of the first buffer (the pointer is updated according to the Gray code rule when the data is deleted, and the value thereof can be mapped to the storage address of the deleted data after conversion). The data receiving end compares the address with the address range of the initial storage space: if the address belongs to the address interval corresponding to the initial storage space (i.e., greater than or equal to 0 and less than K), it is determined that the deleted to-be-processed data occupies the position in the initial storage space, and the generation logic of the credit identifier is triggered at this time; if the address exceeds the address interval of the initial storage space (i.e., greater than or equal to K), it is determined that the deleted data occupies the extended position outside the initial storage space, and no credit identifier is generated at this time. Based on the judgment mechanism of the storage location, it is ensured that the credit identifier is generated only when the cache in the initial storage space is released, so that the credit identifier is strictly bound with the initial agreed cache carrying capacity, avoiding the misjudgment of the data sending end on the initial credit state due to the erroneous generation of the credit identifier caused by the release of the extended space, thereby further improving the accuracy and reliability of the asynchronous flow control logic.

[0106] As an example, in a scenario of image data transmission at a data receiving end, the first buffer is a depth-16 asynchronous first-in-first-out buffer, and the storage units thereof are arranged in sequence from address 0 to address 15, each address corresponding to a 32-byte image pixel data packet storage location. The initial storage space agreed upon in advance by the data receiving end and the sending end is the first 8 storage locations of the buffer, i.e., addresses 0 to 7, corresponding to an initial cache capacity of 8 image pixel data packets. When the image processing module of the data receiving end completes decoding of a to-be-processed data (image pixel data packet), the data is deleted from the first buffer, at which time the data receiving end, through read pointer resolution logic, converts the current Gray code value of the read pointer of the first buffer (e.g., 0011) into a binary address (i.e., 3) to determine that the deleted to-be-processed data is stored at the location corresponding to address 3. Since address 3 belongs to the range of addresses 0 to 7 agreed upon in advance as the initial storage space, the credit generation logic of the data receiving end is triggered to generate a single-cycle high-level pulse as a credit identifier and feed back to the second buffer. If the to-be-processed data deleted by the subsequent processing module is stored at the location corresponding to address 8 (which is outside the range of addresses 0 to 7 agreed upon in advance as the initial storage space), the data receiving end, upon determining the storage location, determines that the location is not within the initial storage space, at which time the credit generation logic is not triggered and no credit identifier is generated. In this way, the generation of the credit identifier is strictly limited to the release of the cache within the initial storage space, ensuring that the data sending end recovers credits only within the initial agreed cache capacity, avoiding credit misjudgment due to the release of the extended cache space.

[0107] In this way, the mechanism, through range judgment of the storage location, strictly limits the generation of the credit identifier to the release of the cache corresponding to the initial storage space, ensures that each credit identifier is directly associated with the initial cache carrying capacity agreed upon in advance by the data receiving end and the sending end, effectively avoids the problem of erroneous generation of the credit identifier due to the release of the extended cache space (e.g., the additional redundant storage area of the first buffer) outside the initial storage space, thereby preventing the data sending end from misjudging the initial credit state and ensuring that the credit amount recovered by the sending end based on the credit identifier always matches the initial agreed cache capacity. At the same time, this location-based judgment logic is simple and clear, does not require complex numerical calculations or state tracking, can reduce the complexity of hardware implementation, and can naturally adapt to the address coding of the first buffer, ensuring the speed and accuracy of the judgment process. The design makes the flow control logic of the initial storage space and the extended storage space independent of each other, strictly controls the reuse of the initial cache through the credit identifier, and reserves space for flexible use of the extended cache, improving the adaptability of the system to different data transmission scenarios, and ultimately enhancing the reliability and scalability of the entire system while ensuring the accuracy of asynchronous data interaction flow control.

[0108] In step 105, the state of the second buffer is updated based on the credit identifier, and the state is used by the data sending end to regulate the sending time of the data packet.

[0109] In some embodiments, the state of the second buffer is updated based on the credit identifier, which is to convert the "first buffer initial storage space release" information represented by the credit identifier into a state signal recognizable by the data sending end, so as to provide a basis for the data sending end to regulate the sending time of the data packet. The second buffer is an asynchronous first-in-first-out buffer, and its state includes an empty state and a non-empty state. The empty state indicates that there is no available credit to be fed back to the sending end, and the non-empty state indicates that there is recyclable credit to be notified to the sending end. When the data receiving end generates the credit identifier, the credit identifier will be used as a write enable signal of the second buffer to drive the second buffer to perform a write operation. The write port of the second buffer is bound to the clock domain of the data receiving end, and in the clock cycle during which the credit identifier is valid, the write pointer is incremented according to the Gray code rule, so that the second buffer is switched from the empty state to the non-empty state (i.e., the "existence of credit to be fed back" is marked by the write operation). Since the second buffer does not need to store actual data, and only needs to transmit information through the empty and full states, the write operation does not need to write specific content, and the state update can be completed only by changing the pointer. The data sending end senses the state change of the second buffer by monitoring the state of the read port of the second buffer (the read port is bound to the clock domain of the sending end). When the second buffer is in the non-empty state, the sending end generates a read enable signal to drive the read pointer to increment, so that the second buffer is restored from the non-empty state to the empty state, and the credit recycling operation of the sending end is triggered (i.e., the current remaining credit value is increased), allowing the sending end to continue sending data packets when the remaining credit value is greater than 0; when the second buffer is in the empty state, the sending end does not perform credit recycling, and only maintains or starts the sending operation when the current remaining credit value is greater than 0.

[0110] In some embodiments, the clock domain of the first buffer storing the data packet is consistent with the clock domain of the data sending end, and the clock domain of the first buffer reading the to-be-processed data is consistent with the clock domain of the data receiving end; the clock domain of the second buffer updating the state is consistent with the clock domain of the data receiving end, and the clock domain of the second buffer for the data sending end to obtain the state is consistent with the clock domain of the data sending end.

[0111] In some embodiments, the first buffer zone is used as a core component for asynchronous processing and caching data, and the clock domain design of its read-write operation strictly adapts to the asynchronous working scenario of the data sending end and the data receiving end: during the process of storing data packets, i.e., when the first buffer zone performs a write operation, its clock domain is consistent with that of the data sending end —— because the data packets received by the first buffer zone are output by the data sending end at its own clock pace, the write operation clock is synchronized with the sending end clock, which can ensure that the data packets are accurately sampled at the valid edge (such as the rising edge) of the sending end clock and written into the storage unit of the first buffer zone, avoiding write timing deviation (such as setup time or hold time not being met) caused by clock domain mismatch, and thus preventing data packet loss or incorrect storage. During the process of reading the data to be processed, i.e., when the first buffer zone performs a read operation, its clock domain is consistent with that of the data receiving end —— because the subsequent processing (such as parsing and verification) of the data to be processed needs to be completed by the data receiving end at its own processing pace, the read operation clock is synchronized with the receiving end clock, which can enable the data receiving end to stably read the data in the first buffer zone within the valid timing of its own clock, ensuring that the read data meets the timing requirements of the receiving end processing module and avoiding metastability risk caused by cross-clock domain reading, thus guaranteeing the accuracy of data processing.

[0112] In some embodiments, the second buffer zone is used as an interactive component for delivering credit status, and the clock domain design of its state updating and state acquisition also follows asynchronous adaptation logic: during the process of updating the state, i.e., when the second buffer zone triggers a write operation (such as switching from an empty state to a non-empty state) due to the credit identifier, its clock domain is consistent with that of the data receiving end —— the credit identifier is generated by the data receiving end in its own clock domain, and the state update clock is synchronized with the receiving end clock, which can ensure that the credit identifier can immediately drive the second buffer zone to complete the state switching after being generated, avoiding state update lag caused by clock delay, so that the state of the second buffer zone can reflect the space release situation of the first buffer zone in real time. During the process of providing the data sending end with the state, i.e., when the second buffer zone performs a read operation (the data sending end monitors its empty-full state), its clock domain is consistent with that of the data sending end —— the data sending end needs to control the data packet sending time based on its own clock pace, and the read operation clock is synchronized with the sending end clock, which can enable the sending end to accurately perceive the state of the second buffer zone within the stable window of its own clock, without the need for additional cross-clock domain signal synchronization, thus avoiding metastability risk and ensuring that the sending end can adjust the sending behavior in a timely manner according to the state, achieving dynamic matching of the sending pace and the credit feedback of the receiving end.

[0113] As an example, in a high-speed data acquisition system, the data sending end is an analog-to-digital converter (ADC) with a working clock frequency of 250 MHz (i.e., the sending end clock domain is a 250 MHz clock), which is used to convert an analog signal into a 16-bit digital sampling value (data packet) and output; the data receiving end is a field programmable gate array (FPGA) processing module with a working clock frequency of 200 MHz (i.e., the receiving end clock domain is a 200 MHz clock), which is used to filter and format convert the digital sampling value. Among them, the first buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 32, and the second buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 8. The clock domain design of the two is as follows: for the first buffer, when it performs a data packet storage operation (write operation), the clock domain is consistent with the 250 MHz clock domain of the data sending end ADC: after the ADC generates a 16-bit digital sampling value, it will trigger the write enable signal of the first buffer at the rising edge of the 250 MHz clock. The write port of the first buffer accurately samples the digital sampling value output by the ADC within the timing window of the clock edge, and writes it into the internal address incrementally. Since the write clock is synchronized with the ADC clock, the sampling misalignment caused by the difference in clock frequency can be avoided, ensuring that each digital sampling value can be stably stored. When the first buffer performs a read operation (read operation) on the data to be processed, the clock domain is consistent with the 200 MHz clock domain of the data receiving end FPGA: after the FPGA processing module completes the processing of the previous frame of data, it will trigger the read enable signal of the first buffer at the rising edge of the 200 MHz clock. The read port of the first buffer transmits the digital sampling value in the storage unit to the filter module of the FPGA under the timing constraint of the clock edge; since the read clock is synchronized with the FPGA clock, the setup time and hold time requirements of the FPGA filter module for input data can be met, avoiding metastability and ensuring the accuracy of the filtering process. For the second buffer, when it performs a state update operation (write operation), the clock domain is consistent with the 200 MHz clock domain of the data receiving end FPGA: after the FPGA reads and deletes a 16-bit digital sampling value from the first buffer (releases the initial storage space), it generates a credit identifier and triggers the write enable signal of the second buffer at the falling edge of the 200 MHz clock, driving the write pointer of the second buffer to increment according to the Gray code rule, so that the state of the second buffer is updated from "empty state" to "non-empty state"; since the write clock is synchronized with the FPGA clock, the credit identifier can be triggered immediately after generation, without the lag problem caused by clock delay.When the second buffer is in a state (read operation) for the data sending end ADC to acquire, the clock domain is consistent with the 250MHz clock domain of the ADC: the ADC will monitor the state of the second buffer through the read port in each cycle of the 250MHz clock; when detecting that the second buffer is in a non-empty state, the ADC will trigger the read enable signal at the rising edge of the 250MHz clock to drive the read pointer of the second buffer to increment, so that the state returns to the empty state, and the ADC recovers one credit value to allow the sending of new digital sample values; because the read clock is synchronized with the ADC clock, the ADC can perceive the state change of the second buffer in real time, accurately determine whether the sending condition is met without additional synchronization circuit, and ensure that the sending rhythm matches the buffer release state of the FPGA.

[0114] In this way, the first buffer ensures that the data packet is accurately sampled and written under the timing constraints of the sending end clock by keeping the clock domain of the stored data packet consistent with the data sending end, avoiding sampling misplacement, data loss or non-satisfaction of setup / hold time caused by cross-clock-domain writing; at the same time, the clock domain of reading the to-be-processed data is kept consistent with the data receiving end, so that the data receiving end can read the data in the stable window of its own clock, fully adapt to the timing requirements of the subsequent data processing module, completely avoid the metastable state risk caused by cross-clock-domain reading, and fundamentally guarantee the reliable circulation of data from the sending end to the receiving end processing module. The second buffer keeps the clock domain of updating the state consistent with the data receiving end, can realize real-time synchronization of credit identification generation and state updating, avoids state feedback lag caused by clock domain difference, and ensures that the state of the second buffer can immediately reflect the space release of the first buffer; and keeping the clock domain for the data sending end to acquire the state consistent with the data sending end, the sending end can accurately perceive the state change of the second buffer under its own clock rhythm without additional cross-clock-domain synchronization circuit, timely adjust the data packet sending time according to the state, and ensure the dynamic matching of the sending rhythm and the buffer release state of the receiving end. Overall, this design can realize the asynchronous adaptation of data transmission and flow control state feedback without relying on complex clock synchronization mechanism, greatly reduce the complexity and timing optimization difficulty of hardware design, effectively adapt to the application scenario where the data sending end and receiving end clocks are completely independent, and provide solid timing support for stable execution of asynchronous data interaction and efficient operation of flow control closed loop.

[0115] In some embodiments, the state includes a first state for informing the data sending end that there is a credit identification to be recovered, and a second state for informing the data sending end that there is no credit identification to be recovered.

[0116] In some embodiments, the updating of the second buffer state based on the credit identifier can be achieved by: in response to the generation of the credit identifier, obtaining an initial state of the second buffer; and when the initial state is the second state, updating the second state of the second buffer to the first state.

[0117] In some embodiments, the state includes a first state and a second state, wherein the first state explicitly informs the data sender that there is a credit identifier to be recycled in the second buffer, i.e., the data receiver has released the initial storage space of the first buffer and generated a credit feedback, and the data sender needs to recycle the credit to restore the sending permission; and the second state explicitly informs the data sender that there is no credit identifier to be recycled in the second buffer, i.e., there is no non-feedback credit, and the data sender needs to control the sending behavior based on the existing remaining credit value.

[0118] In some embodiments, when the data receiver successfully generates the credit identifier, the credit identifier directly triggers the state updating process of the second buffer. Since the clock domain of the second buffer state updating and the clock domain of the data receiver are consistent, the credit identifier is detected as a valid signal at the valid edge (e.g., rising edge) of the receiver clock, and then the obtaining operation of the initial state of the second buffer is started. The obtaining of the initial state of the second buffer is essentially achieved by detecting the empty / full state of the second buffer. The empty / full state of the second buffer as an asynchronous first-in-first-out buffer is determined by the relative position of the read pointer and the synchronized write pointer. If the read pointer and the synchronized write pointer are consistent, it indicates that there is no credit identifier to be fed back in the buffer, and the initial state is the second state (no credit identifier to be recycled). If the values of the two are inconsistent, it indicates that there is an unrecycled credit identifier in the buffer, and the initial state is the first state (there is a credit identifier to be recycled).

[0119] In some embodiments, the initial state is judged: when the initial state is determined to be the second state, the credit identifier is used as the write enable signal of the second buffer to drive the second buffer to perform the write operation — in the active period of the receiving end clock, the write pointer of the second buffer is incremented according to the Gray code rule, at this time the read pointer and the updated write pointer value are no longer consistent, the state of the second buffer is switched from the second state to the first state, and the state update is completed; if the initial state is determined to be the first state, it indicates that the credit identifier generated previously has not been recycled by the data sending end, and there is already a credit identifier to be recycled in the second buffer, so there is no need to repeatedly perform the update operation, avoiding the misjudgment of the credit number by the sending end due to repeated state switching. The update mechanism ensures that each valid generated credit identifier triggers a state update only once when the second buffer is in the no-credit feedback state (second state) through the logic of “trigger-detect-judge-switch”, which not only avoids the confusion caused by redundant state updates, but also ensures that the state of the second buffer can accurately map the generation of the credit identifier, providing accurate state basis for the data sending end to recycle the credit by reading the second buffer state and to control the data packet sending time, further improving the closed-loop logic of asynchronous flow control.

[0120] As an example, in an industrial Ethernet data transmission scenario, a data sending end is a sensor node (working clock frequency 200 MHz) in a workshop, which is configured to periodically send a temperature and humidity sampling data packet (16 bytes per data packet); a data receiving end is an industrial controller (working clock frequency 150 MHz), which is configured to perform threshold judgment and abnormal alarm processing on the sampling data. The second buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 4, and in the state of the buffer, the first state is a non-empty state of the buffer (that is, the read pointer and the value of the synchronized write pointer are inconsistent, indicating that there is a credit identifier to be recycled), and the second state is an empty state of the buffer (that is, the read pointer and the value of the synchronized write pointer are consistent, indicating that there is no credit identifier to be recycled), and the clock domain of updating the state of the second buffer is consistent with the 150 MHz clock domain of the industrial controller. When the industrial controller completes the processing of a temperature and humidity sampling data packet in the first buffer and deletes the data packet from the first buffer, a credit identifier (single cycle 150 MHz clock high level pulse) is generated. The credit identifier triggers the state updating process of the second buffer: first, the industrial controller detects that the credit identifier is valid at the rising edge of the 150 MHz clock, and then starts the acquisition operation of the initial state of the second buffer - by reading the read pointer (encoded by a 2-bit Gray code, the current value is 00) and the synchronized write pointer (the current value is 00) of the second buffer, it is determined that the values are consistent, and it is determined that the initial state of the second buffer is the second state (there is no credit identifier to be recycled). Since the initial state is the second state, the credit identifier is directly used as the write enable signal of the second buffer, and the write pointer is driven to increase from 00 to 01 according to the Gray code rule in the same 150 MHz clock cycle. At this time, the read pointer (00) and the updated write pointer (01) of the second buffer are no longer consistent, and the state is switched from the second state to the first state, and the state updating is completed. If the industrial controller generates a credit identifier again subsequently, the read pointer of the second buffer is still 00 and the write pointer is 01 (the initial state is the first state, that is, there is a credit identifier to be recycled), it is determined that no state updating operation needs to be performed, and the state confusion caused by repeated increment of the write pointer is avoided. Subsequently, the sensor node monitors the state of the second buffer through the 200 MHz clock of the sensor node (the clock domain of the second buffer for the sending end to obtain the state is consistent with the clock domain of the sensor node), and when it is detected that the second buffer is in the first state, the read operation will be triggered to recycle the credit, and then the sending time of the next temperature and humidity sampling data packet is controlled according to the recycled credit, so as to ensure that the sending rhythm matches the buffer release state of the industrial controller.

[0121] Thus, the clear division of the state enables the data sending end to directly perceive whether there is recoverable credit without complex logic, greatly simplifies the judgment process of the credit state of the sending end, and avoids credit recovery delay or misjudgment caused by ambiguous state definition; through the operation logic of first acquiring the initial state and then deciding whether to update, repeated state updating when the second buffer is in the first state (i.e., there is unrecovered credit) can be effectively avoided, the state confusion of the second buffer caused by frequent invalid increment of the write pointer can be prevented, and it can be ensured that the state of the second buffer is always accurately matched with the actual generation and recovery of the credit identifier; at the same time, this updating mechanism only responds to the credit identifier to switch the state when there is no credit to be recovered in the second buffer, which not only reduces unnecessary hardware operations, reduces timing control difficulty and resource consumption, but also ensures that each state update corresponds to an effective credit feedback demand, so that the state of the second buffer can accurately reflect the release of the initial storage space of the first buffer, providing a reliable basis for the data sending end to regulate the data packet sending time according to the state, thereby avoiding sending blockage or buffer overflow caused by state errors, and ensuring the stability and efficiency of the asynchronous data interaction flow control closed loop.

[0122] Thus, the first buffer as the core of asynchronous data cache, its clock domain adaptation data sending end, reading data clock domain adaptation receiver itself effectively solves the cross-clock domain synchronization problem caused by independent clock of the sending end and the receiving end, avoids data packet storage misplacement, reading metastability or data loss caused by clock mismatch, and ensures the stability and error-free of the whole process from receiving to caching to processing of the data packet; on this basis, the receiving end generates a credit identifier after deleting the processed data in the first buffer, and updates the state through the second buffer, so that the second buffer becomes a bridge for accurately transmitting the cache space release information - its state update adapts to the clock domain of the receiving end, and the data sending end obtains the state to adapt to the clock domain of the data sending end, which not only ensures the real-time of the credit feedback, but also avoids the timing risk of cross-clock domain signal transmission, so that the data sending end can accurately perceive the cache available state of the receiving end, thereby regulating the sending time to prevent the first buffer from overflowing due to too fast sending or data interruption due to too slow sending. The first buffer ensures the stability of data circulation in the receiving end, and the second buffer ensures the stability of the interaction rhythm between the sending end and the receiving end, and the two together build a whole-link stable mechanism from data reception, processing to feedback regulation, which significantly reduces the error risk caused by clock difference and rhythm mismatch in asynchronous data interaction, and fundamentally improves the stability of data interaction.

[0123] As an example, refer to Figure 5The data receiving end includes a first buffer for asynchronous processing and data caching, and a second buffer for controlling the sending behavior of the data sending end. It receives data packets sent by the data sending end and stores the data packets in the first buffer; reads data to be processed from the first buffer, processes the data to be processed, and deletes the data to be processed from the first buffer in response to the completion of the data processing; in response to the deletion of the data to be processed from the first buffer, generates a credit identifier between the data sending end and the data receiving end, and updates the state of the second buffer based on the credit identifier. The state is used by the data sending end to adjust the timing of sending the data packets.

[0124] See Figure 5 , Figure 2 This is a flowchart illustrating the data interaction method provided in the embodiments of this application. Figure 5 , will combine Figure 6 Steps 201 to 203 are shown in the illustration. The data interaction method provided in this application embodiment can be implemented collaboratively by a data receiving end and a data sending end. The data sending end includes a first control unit for sending data packets and a second control unit for controlling the sending behavior of the first control unit. The data sending end and the data receiving end are communicatively connected. The data receiving end includes a second buffer for controlling the sending behavior of the data sending end. The following will be described using the implementation of the data sending end alone as an example.

[0125] In some embodiments, the core functions of the data transmitter are implemented through the collaboration of the first control unit and the second control unit. The first control unit is the core execution component that performs the data packet transmission operation. It integrates a data packet temporary storage submodule, a transmission interface circuit, and timing drive logic. It can output the data packets to be transmitted (such as business data after encoding and verification) to the communication link connected to the data receiver in a preset format (such as frame structure and bit width) according to external control signals. The second control unit is the logic control component that regulates the transmission behavior of the first control unit. Its core function is to generate transmission control signals based on the buffer status (i.e., the status of the second buffer) fed back by the data receiver, such as transmission enable signals and transmission pause signals. Through signal interaction with the first control unit, it determines when the first control unit starts transmission and when it pauses transmission, avoiding buffer overflow at the data receiver due to blind transmission.

[0126] In some embodiments, the data sending end and the data receiving end are connected through a physical communication link, which can be a high-speed serial bus, a parallel data bus or other asynchronous communication link according to the application scenario. The connection path is specifically the write interface of the first control unit sending interface of the data sending end and the first buffer (an asynchronous first-in-first-out buffer for temporarily storing received data packets) of the data receiving end, which ensures that the data packets output by the first control unit can be stably transmitted to the first buffer. At the same time, the communication link needs to adapt to the asynchronous clock characteristics of both parties to support reliable transmission of data packets in different clock domains, such as adding a synchronization header, a check field and other ways to ensure the integrity of data transmission, laying a foundation for subsequent storage, reading and processing of data packets by the data receiving end.

[0127] In some embodiments, the second buffer included in the data receiving end is a key flow control component for controlling the sending behavior of the data sending end. It is essentially an asynchronous first-in-first-out buffer that does not store actual business data, but only transmits buffer space release information through the state (the first state of existing credit identifier to be recycled, the second state of non-existing credit identifier to be recycled). The state update of the second buffer is consistent with the clock domain of the data receiving end, and the state acquisition is consistent with the clock domain of the data sending end. The second control unit of the data sending end will monitor the state of the second buffer in real time: when the second buffer is in the first state, the second control unit determines that the data receiving end has released the initial buffer space, recycles the corresponding credit value and generates a sending enable signal to allow the first control unit to send data packets; when the second buffer is in the second state, the second control unit determines whether to allow the first control unit to continue sending according to the current remaining credit value. If the remaining credit value is 0, a sending pause signal is generated to prohibit the first control unit from sending, thereby indirectly controlling the sending behavior of the data sending end by the second buffer and building a flow control closed loop for asynchronous data interaction.

[0128] In step 201, the second control unit detects the state of the second buffer.

[0129] In some embodiments, since the clock domain of the second buffer for the data sending end to acquire the state is consistent with the clock domain of the data sending end, the detection operation of the second control unit strictly follows the clock timing of the data sending end (such as the rising edge or falling edge of the sending end clock), avoiding the metastable state risk caused by cross-clock domain detection. As an asynchronous first-in-first-out buffer, the state of the second buffer is determined by the read pointer (bound to the data sending end clock domain and updated with the read operation of the sending end) and the synchronized write pointer (the write pointer of the second buffer is initially bound to the data receiving end clock domain and needs to be synchronized to the data sending end clock domain through two-stage flip-flop to ensure the stability of the pointer value), so the detection of the second control unit needs to acquire the current values of the two pointers.

[0130] In some embodiments, the second control unit triggers reading of the post-synchronization write pointer and the local read pointer in each active period of the data sending end clock: the reading of the post-synchronization write pointer is performed by the pointer output interface of the second buffer to obtain a value synchronized by the clock, which reflects the cumulative number of credit identifiers written by the data receiving end to the second buffer; the reading of the local read pointer is performed by directly obtaining the value of the pointer controlled by the second control unit itself and bound to the read port of the second buffer, which reflects the cumulative number of credit identifiers recycled by the data sending end from the second buffer.

[0131] In some embodiments, the second control unit compares the values of the read post-synchronization write pointer and the local read pointer: if the values are completely consistent, it indicates that all the credit identifiers written in the second buffer have been recycled, and there is no credit identifier to be recycled at present, and it is determined that the state of the second buffer is the second state; if the values are inconsistent (the value of the post-synchronization write pointer is greater than the value of the local read pointer, because the pointer is incremented in Gray code or binary, the difference in value is the number of credit identifiers to be recycled), it indicates that there are still credit identifiers in the second buffer that have not been recycled, and it is determined that the state of the second buffer is the first state. Based on the detection method of pointer comparison, it is not necessary to rely on complex state registers or additional feedback signals, and the state detection can be realized only by reading and judging the core pointers, which not only ensures the accuracy and real-time performance of the detection result, but also deeply adapts to the asynchronous working characteristics of the second buffer, provides a reliable basis for the second control unit to generate the sending control signal (such as sending enable and sending pause) of the first control unit based on the state, and further guarantees the stable operation of the flow control logic between the data sending end and the receiving end.

[0132] As an example, in a vehicle Ethernet data transmission scenario, the data sending end is a millimeter wave radar (working clock frequency 180MHz) for sending target detection data packets to an automatic driving domain controller (data receiving end, working clock frequency 120MHz); the second control unit is a micro control chip built in the millimeter wave radar, the second buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 4, the read pointer of which is bound to the 180MHz clock domain of the millimeter wave radar (directly controlled by the second control unit), the write pointer is initially bound to the 120MHz clock domain of the domain controller, needs to be synchronized to the 180MHz clock domain through two-stage flip-flops (forming a synchronized write pointer), and the first state of the second buffer is "existence of credit identifier to be recycled" (the read pointer and the value of the synchronized write pointer are inconsistent), and the second state is "nonexistence of credit identifier to be recycled" (the read pointer and the value of the synchronized write pointer are consistent). The state detection of the second control unit on the second buffer is strictly executed in the 180MHz clock domain of the millimeter wave radar, and the specific process is as follows: the second control unit will trigger the pointer reading operation at each rising edge of the 180MHz clock (effective detection timing) - on the one hand, through the read pointer interface of the second buffer, the current gray code value of the local read pointer is directly obtained (2-bit gray code, initial value is 00); on the other hand, through the output interface of the synchronization circuit, the gray code value of the write pointer synchronized through two-stage flip-flops is obtained (the synchronization process can eliminate the metastability across clock domains, and ensure the stability of the value).

[0133] When the domain controller has not written a credit identifier to the second buffer, the Gray code value of the synchronized write pointer is 00, the local read pointer (00) read by the second control unit is consistent with the value of the synchronized write pointer (00), and the second control unit determines through internal logic comparison that the second buffer is currently in the second state, i.e., there is no credit identifier to be recycled; when the domain controller completes the processing of a target probe data packet and generates a credit identifier, the write pointer of the second buffer is driven to increase from 00 to 01 (120 MHz clock domain), and the write pointer is transmitted to the 180 MHz clock domain of the millimeter wave radar after synchronization. At this time, the second control unit reads the synchronized write pointer as 01 on the rising edge of the 180 MHz clock, and the local read pointer is still 00. The values of the two are inconsistent, and the second control unit determines through comparison that the second buffer is currently in the first state, i.e., there is a credit identifier to be recycled. During the entire detection process, the second control unit does not need to receive additional external feedback signals, but only needs to read and compare the core pointers to complete the state judgment, and the detection result is completely synchronized with the actual state of the second buffer, providing accurate basis for the second control unit to generate a “permission to send” or “pause sending” signal (regulating the sending behavior of the first control unit of the millimeter wave radar — the data packet sending module) in the future, ensuring that the sending rhythm of the millimeter wave radar matches the buffer release state of the domain controller.

[0134] In step 202, the second control unit determines the control information of the first control unit based on the state.

[0135] In some embodiments, the second control unit internally maintains a “remaining credit value” parameter, which has an initial value of the initial credit limit agreed by the data sending end and the receiving end (corresponding to the maximum carrying capacity of the initial storage space of the first buffer, such as 8 units of credit), and is updated in real time with the credit recycling operation (recycling 1 credit identifier, the remaining credit value increases by 1, and sending 1 data packet, the remaining credit value decreases by 1). When the second control unit obtains the state of the second buffer through state detection, it will first associate and analyze the state with the remaining credit value, and then generate corresponding control information — control information specifically includes two types of “send enable signal” (allowing the first control unit to send data packets) and “send pause signal” (prohibiting the first control unit from sending data packets), which are mutually exclusive and generated only when the corresponding conditions are met.

[0136] In some embodiments, if the second control unit detects that the second buffer is in the first state (there is a credit identifier to be recovered), the credit recovery operation is first performed: the remaining credit value is increased by 1 based on the current value (because the first state corresponds to the release of 1 unit of initial storage space of the first buffer, the sending permission of the sending end needs to be recovered synchronously); then it is judged whether the updated remaining credit value is greater than 0 - since the first state itself represents that there is a recoverable credit, the updated remaining credit value must be greater than 0, at this time the second control unit generates a “sending enable signal” as control information, which contains the instruction of “allowing sending” and the constraint of “sending at most 1 data packet at a time” (to ensure that the sending quantity matches the credit limit and avoid over-sending), and transmits the signal to the first control unit to allow it to start data packet sending when the timing of itself allows.

[0137] In some embodiments, if the second control unit detects that the second buffer is in the second state (there is no credit identifier to be recovered), the credit recovery operation does not need to be performed, and the value of the current remaining credit value is directly judged: if the remaining credit value is greater than 0, it indicates that the data sending end still has unused sending permissions (the previously recovered credits have not been completely used for sending), at this time a “sending enable signal” is generated to allow the first control unit to continue sending data packets (but the remaining credit value needs to be reduced by 1 after each sending to ensure that the credit consumption matches the sending behavior); if the remaining credit value is equal to 0, it indicates that the data sending end has no available sending permission (all initial credits corresponding to the buffer space are occupied, and no new space is released), at this time a “sending pause signal” is generated as control information to prohibit the first control unit to start a new sending operation, until the second buffer is detected to switch to the first state, the credit recovery is completed, and the remaining credit value is restored to be greater than 0, then the “sending enable signal” is switched again.

[0138] In some embodiments, the step 202 can be implemented by: obtaining the current remaining credit value of the second control unit, the second control unit updating the remaining credit value based on the state to obtain an updated credit value; when the updated credit value is greater than a credit value threshold, determining that the control information of the first control unit satisfies the data sending opportunity; and when the updated credit value is less than or equal to the credit value threshold, determining that the control information of the first control unit does not satisfy the data sending opportunity.

[0139] In some embodiments, the current remaining credit value of the second control unit is obtained, which is a core parameter maintained by a dedicated register inside the second control unit, and its initial value is equal to the initial credit limit agreed by the data sending end and the data receiving end (the limit is consistent with the maximum carrying capacity of the initial storage space of the first buffer, for example, when the initial storage space can accommodate 8 data packets, the initial value of the remaining credit value is 8), and dynamically changes with the credit recovery operation (recovery of 1 credit identifier, the value increases by 1) and the data packet sending operation (sending 1 data packet, the value decreases by 1); the second control unit can obtain the current remaining credit value directly through a register read operation at each active period (such as the rising edge) of the data sending end clock domain, ensuring that the read result is completely synchronized with the real-time state.

[0140] In some embodiments, the second control unit updates the remaining credit value based on the state of the second buffer, and the specific update logic strictly corresponds to the state of the second buffer: if it is detected that the second buffer is in the first state (there is a credit identifier to be recovered), it indicates that the data receiving end has released 1 unit of initial storage space of the first buffer, and the corresponding credit needs to be recovered to restore the sending permission, at this time, the second control unit adds 1 to the value of the current remaining credit value after obtaining it, to obtain the updated credit value; if it is detected that the second buffer is in the second state (there is no credit identifier to be recovered), it indicates that there is no new credit to be recovered, and the current remaining credit value does not need to be adjusted, at this time, the updated credit value is equal to the obtained current remaining credit value. The update operation and the state detection of the second buffer are completed in the same data sending end clock period, ensuring that the updated credit value can immediately reflect the state change, avoiding the credit judgment deviation caused by the update lag.

[0141] In some embodiments, the credit value threshold is a pre-set reference value for judging whether the data packet sending condition is met, and its value is adapted to the initial credit limit and the cache characteristics of the first buffer, and is usually set to 0 - this is because when the threshold is 0, the size relationship between the updated credit value and 0 can be directly used to judge whether the data sending end has available sending permission (the updated credit value is greater than 0, which means that there is available permission, and less than or equal to 0, which means that there is no available permission), without complex calculation, and at the same time, it can match the logic of "releasing 1 unit of space corresponding to 1 credit" of the first buffer, ensuring that the threshold judgment result is consistent with the actual available state of the receiving end cache.

[0142] In some embodiments, when the updated credit value is greater than the credit value threshold, it indicates that there is available sending permission for the current data sender (i.e., the first buffer has enough free space to accommodate the newly sent data packet), and the second control unit determines that the control information of the first control unit meets the data sending opportunity, which is specifically manifested as a "sending enable signal" with a high level, which is transmitted to the enable interface of the first control unit to allow the first control unit to start the data packet sending operation according to its own timing; when the updated credit value is less than or equal to the credit value threshold, it indicates that there is no available sending permission for the current data sender (i.e., the first buffer has no free space or insufficient free space to accommodate the new data packet), and the second control unit determines that the control information of the first control unit does not meet the data sending opportunity, which is specifically manifested as a sending pause signal with a low level, which is transmitted to the first control unit to prohibit the first control unit from starting a new sending operation, until the subsequent updated credit value is greater than the credit value threshold again, and then the control information is switched to meet the sending opportunity.

[0143] As an example, in the medical ultrasound image data transmission scenario, the data sender is an ultrasound probe (working clock frequency 160 MHz), which is used to send ultrasound scan line data packets (each data packet corresponds to the gray scale data of 1 scan line, bit width 32 bits) to an image processing host (data receiver, working clock frequency 120 MHz); the first control unit is a data packet sending module built-in the ultrasound probe, which is responsible for outputting the scan line data in frame structure; the second control unit is a timing control chip of the ultrasound probe, which maintains the remaining credit value through an 8-bit register inside, and the initial credit limit (initial value of the remaining credit value) is set to 6 (which matches the capability of the first buffer to accommodate 6 scan line data packets), and the credit value threshold is pre-set to 0 (which is used to determine whether there is sending permission); the second buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 6, and the first state is "there is a credit identifier to be recycled", and the second state is "there is no credit identifier to be recycled".

[0144] Continuing the previous example, when the ultrasound probe is just started, the second control unit first performs the operation of obtaining the current remaining credit value - through the register read instruction, the current remaining credit value is read as the initial value 6. Subsequently, the second control unit detects the state of the second buffer, at this time the image processing host has not processed any data packet, has not generated a credit identifier, and the second buffer is in the second state, so there is no need to update the remaining credit value, and the updated credit value is equal to the current remaining credit value 6. Since the updated credit value 6 is greater than the credit value threshold 0, the second control unit determines that the control information of the first control unit meets the data sending opportunity, and specifically generates a "send enable signal" which is high active, and transmits it to the data packet sending module, allowing it to start sending the first ultrasound scan line data packet at the rising edge of the 160MHz clock; after the sending is completed, the second control unit automatically reduces the remaining credit value from 6 to 1, and updates it to 5, preparing for the next state judgment.

[0145] Continuing the previous example, when the ultrasound probe is just started, the second control unit first performs the operation of obtaining the current remaining credit value - through the register read instruction, the current remaining credit value is read as the initial value 6. Subsequently, the second control unit detects the state of the second buffer, at this time the image processing host has not processed any data packet, has not generated a credit identifier, and the second buffer is in the second state, so there is no need to update the remaining credit value, and the updated credit value is equal to the current remaining credit value 6. Since the updated credit value 6 is greater than the credit value threshold 0, the second control unit determines that the control information of the first control unit meets the data sending opportunity, and specifically generates a "send enable signal" which is high active, and transmits it to the data packet sending module, allowing it to start sending the first ultrasound scan line data packet at the rising edge of the 160MHz clock; after the sending is completed, the second control unit automatically reduces the remaining credit value from 6 to 1, and updates it to 5, preparing for the next state judgment.

[0146] Continuing the previous example, after 10 data receiving end clock cycles, the image processing host completes the processing of the first scan line data packet, deletes the data and generates a credit identifier, and drives the second buffer to switch from the second state to the first state. At this time, the current remaining credit value obtained by the second control unit is still 0, and after detecting that the second buffer is in the first state, the remaining credit value is updated (increased by 1) to obtain an updated credit value of 1. Since the updated credit value 1 is greater than the credit value threshold 0, the second control unit immediately switches the control information from the "send pause signal to the send enable signal, allowing the data packet sending module to send the 7th ultrasound scan line data packet; after the sending is completed, the remaining credit value is reduced from 1 to 1, and is updated to 0 again, waiting for the next credit recovery.

[0147] Thus, the remaining credit value is used as a quantitative parameter to convert the buffer release state of the data receiving end into a directly calculable numerical value, avoiding the uncertainty of fuzzy state judgment, and making the determination of the transmission opportunity have precise quantitative basis. The real-time updating mechanism based on the second buffer state ensures that the updated credit value can immediately reflect the latest buffer state of the receiving end, realizing the dynamic synchronization of credit recovery and transmission permission, and avoiding misjudgment caused by credit value lag. Furthermore, using a threshold value (usually 0) as the judgment basis simplifies the hardware implementation of the control logic, reduces the complexity of the timing design, and at the same time ensures that the judgment result strictly matches the core requirement of "whether the receiving end has enough buffer space". Through the logic of "updating the credit value greater than the threshold value to allow transmission, otherwise prohibit transmission", the blind transmission of the data sending end when the receiving end buffer is insufficient is fundamentally prevented, avoiding the risk of buffer overflow, while allowing transmission in time when there is available credit, reducing transmission congestion caused by judgment delay. Ultimately, in the asynchronous data interaction scenario, both the reliability of data transmission and the overall transmission efficiency are guaranteed, and it is especially suitable for fields with high requirements for timing accuracy and transmission stability.

[0148] In some embodiments, the second control unit updates the remaining credit value based on the state to obtain an updated credit value, which can be achieved by the following method: when the state is a first state for informing the data sending end that there is a credit identifier to be recovered, the remaining credit value is increased by 1 to obtain the updated credit value; when the state is a second state for informing the data sending end that there is no credit identifier to be recovered, the remaining credit value is determined as the updated credit value.

[0149] In some embodiments, the second control unit updates the remaining credit value based on the state of the second buffer to obtain an updated credit value, the core of which is to use numerical value adjustment logic strictly corresponding to the state type to make the updated credit value accurately reflect the release of the data receiving end buffer space and the actual transmission permission of the data sending end. After obtaining the current remaining credit value (which is stored in an internal special register and reflects the number of unused transmission permissions in real time), the second control unit first judges the type of the state of the second buffer — the judgment result is only the first state or the second state, which are mutually exclusive and cover all possible state conditions.

[0150] In some embodiments, when the state is determined to be the first state (i.e., a state indicating that there is a credit identifier to be reclaimed at the data sending end), it indicates that the data receiving end has released 1 unit of initial storage space of the first buffer (corresponding to 1 piece of data to be processed being deleted and its storage location being in the initial storage space), and 1 sending permission of the data sending end needs to be recovered synchronously. At this time, the second control unit performs a value increment operation, adds 1 to the current remaining credit value based on its existing value, and the result is the updated credit value. This add 1 operation strictly corresponds to the "1 piece of credit identifier to be reclaimed" feature of the first state, ensuring that the sending permission of the data sending end is increased by 1 synchronously for each 1 unit of initial storage space released, and realizing accurate matching of credit reclaiming and space releasing.

[0151] In some embodiments, when the state is determined to be the second state (i.e., a state indicating that there is no credit identifier to be reclaimed at the data sending end), it indicates that the data receiving end has not released new initial storage space, and no new credit needs to be reclaimed, and the number of sending permissions of the data sending end does not need to be adjusted. At this time, the second control unit does not perform any value adjustment operation, and directly determines the obtained current remaining credit value as the updated credit value, ensuring that the updated credit value is consistent with the actually available sending permission, and avoiding incorrect sending opportunity determination due to value changes without basis. Based on the differential update logic of the state type, accurate credit reclaiming in the first state is realized through the add 1 operation, and the stability of the credit value in the second state is ensured by keeping it unchanged, so that the updated credit value is always dynamically matched with the buffer release state of the data receiving end and the sending permission demand of the data sending end, providing a precise quantitative basis for determining the sending opportunity based on the comparison between the updated credit value and the threshold, and further guaranteeing the reliability and accuracy of the asynchronous flow control logic.

[0152] As an example, in an industrial automation control system, the data sending end is a pipeline temperature sensor (working clock frequency 200 MHz) for sending temperature sampling data packets (each packet containing temperature values of 8 sampling points) to a programmable logic controller (PLC, data receiving end, working clock frequency 150 MHz); the second control unit is a control chip built-in the sensor, which maintains the remaining credit value through a 16-bit register, and the initial value is set to 5 (matching the ability of the first buffer to accommodate 5 temperature data packets); the second buffer is an asynchronous first-in-first-out buffer (AFIFO) with a depth of 5, the first state is "there is a credit identifier to be reclaimed" (the read pointer and the synchronized write pointer values are not consistent), and the second state is "there is no credit identifier to be reclaimed" (the read pointer and the synchronized write pointer values are consistent).

[0153] Continuing the above example, after the PLC finishes parsing the first temperature data packet and deletes the data (whose storage location is in the initial storage space), a credit identifier is generated, and the second buffer is driven to switch from the second state to the first state. At this time, the current remaining credit value obtained by the second control unit is 4 (because 1 data packet has been sent, the initial value 5 minus 1), and it is detected that the second buffer is in the first state, and the update operation is performed - the remaining credit value 4 is added by 1 to obtain the updated credit value 5. The updated credit value 5 accurately reflects the state of "PLC releases 1 initial storage space, and sensor recycles 1 sending permission", and provides a basis for subsequent judgment of sending opportunity.

[0154] Continuing the above example, if the PLC has not yet processed the new data packet, a new credit identifier has not been generated, and the second buffer remains in the second state. At this time, the current remaining credit value obtained by the second control unit is 5 (assuming that no new data packet has been sent before), and it is detected that the state is the second state, and no value adjustment is performed, and the current remaining credit value 5 is directly determined as the updated credit value. The updated credit value 5 is consistent with the actual available sending permission, and ensures that the sending opportunity judgment will not be affected by the value change without basis.

[0155] Continuing the above example, after the sensor continuously sends 3 data packets, the current remaining credit value decreases to 2 (5-3=2), and at this time the PLC is still processing the corresponding data, and the second buffer maintains the second state. The second control unit obtains the current remaining credit value 2, and because the state is the second state, the updated credit value is still 2; then, the PLC finishes processing 1 of the data packets and generates a credit identifier, the second buffer switches to the first state, and the second control unit obtains the current remaining credit value 2 and performs the add 1 operation to obtain the updated credit value 3, which accurately reflects the state of adding 1 sending permission.

[0156] Thus, by strictly binding the first state (existence of credit identifier to be recycled) with "remaining credit value plus 1", each credit recycling corresponds to the release of one unit of initial storage space at the data receiving end, ensuring that the increment of credit value and the increment of actual available cache space form a one-to-one correspondence, fundamentally avoiding the problem of mismatch between sending permission and receiving end cache capacity caused by untimely or excessive recycling of credit. At the same time, binding the second state (non-existence of credit identifier to be recycled) with "remaining credit value remains unchanged" can prevent unnecessary value changes when there is no new credit to be recycled, ensuring that the credit value always truly reflects the current actual sending permission of the data sending end, avoiding misjudgment of sending opportunity caused by abnormal fluctuations in credit value. In addition, this state type-based differentiated update logic is simple and direct, without the need for complex calculations or state transitions, which not only reduces the timing complexity and resource consumption of hardware implementation, but also ensures that the update operation is completed within a single clock cycle, meeting the real-time requirements of asynchronous data interaction. Finally, this update method enables the remaining credit value to dynamically and accurately map the receiving end cache state and the sending end permission state, providing a reliable quantitative basis for subsequent judgment of sending opportunity based on updated credit value, further improving the stability, accuracy and efficiency of the entire asynchronous flow control system.

[0157] In step 203, in response to the control information indicating that the data sending opportunity is met, the first control unit sends a data packet to the data receiving end.

[0158] In some embodiments, when the control information generated by the second control unit is "data sending opportunity is met" (usually represented by a high-level active transmission enable signal), the signal is transmitted to the enable interface of the first control unit through the internal signal link. The first control unit, as a dedicated execution component responsible for data packet transmission, integrates a data packet storage submodule (used to temporarily store data packets to be sent, such as service data after encoding and verification processing), transmission timing control logic and timing drive circuit, and can monitor the signal state of the enable interface in real time.

[0159] In some embodiments, a complete data packet (including data field, check field, frame header and frame tail, etc. structure information) is read from the data packet storage submodule in a preset order (such as first-in first-out); then, the parallel data of the data packet is converted into serial data (or kept in parallel format, depending on the link type) adapted to the communication link through internal timing control logic, and it is ensured that the data format meets the writing requirements (such as bit width matching and timing alignment) of the first buffer of the data receiving end; then, at the active edge (such as rising edge) of the data sending end clock domain, the sending interface circuit of the first control unit transmits the converted data packet to the first buffer write interface of the data receiving end through the physical communication link (such as high-speed serial bus, parallel data bus), drives the first buffer to perform write operation, and completes the storage of the data packet.

[0160] As an example, referring to Figure 6 , the data sending end includes a first control unit for sending data packets and a second control unit (signal generation logic) for controlling the sending behavior of the first control unit, the data sending end and the data receiving end are communicatively connected, the data receiving end includes a second buffer (flow control unit) for controlling the sending behavior of the data sending end, the second control unit detects the state of the second buffer to obtain the state of the second buffer; the second control unit determines the control information of the first control unit based on the state; in response to the control information indicating that the data sending opportunity is met, the first control unit sends a data packet to the data receiving end.

[0161] In this way, a complete data packet (including data field, check field, frame header and frame tail, etc. structure information) is read from the data packet storage submodule in a preset order (such as first-in first-out); then, the parallel data of the data packet is converted into serial data (or kept in parallel format, depending on the link type) adapted to the communication link through internal timing control logic, and it is ensured that the data format meets the writing requirements (such as bit width matching and timing alignment) of the first buffer of the data receiving end; then, at the active edge (such as rising edge) of the data sending end clock domain, the sending interface circuit of the first control unit transmits the converted data packet to the first buffer write interface of the data receiving end through the physical communication link (such as high-speed serial bus, parallel data bus), drives the first buffer to perform write operation, and completes the storage of the data packet.

[0162] Thus, through the state detection of the second buffer by the second control unit, the control information determined based on the state, and the cooperative process of the first control unit sending data packets according to the control information, the stability of data interaction is significantly improved: the state detection of the second buffer by the second control unit ensures that the data sending end can accurately perceive the release condition of the buffer space of the data receiving end, avoiding sending decision errors caused by state perception deviation; the process of determining control information based on the state ensures that the sending permission is strictly matched with the actual buffer capacity of the receiving end, preventing unnecessary sending behavior, and avoiding buffer overflow of the receiving end caused by too fast sending rhythm or data transmission interruption caused by too slow sending rhythm from the source; and the first control unit only sends data packets when the sending opportunity is indicated by the control information, ensuring that each sending is within the range that can be borne by the receiving end, reducing data loss or errors caused by timing conflicts and insufficient buffer, and forming a closed-loop stability mechanism of "perception - decision - execution". Through the accurate cooperation of each link, the unstable risks caused by clock independence and rhythm mismatch in asynchronous data interaction are effectively resolved, ensuring that the data transmission from the sending end to the receiving end is always orderly and controllable, thereby significantly improving the stability of data interaction.

[0163] In the following, an exemplary application of the application embodiment in an actual flow control mechanism application scenario will be described.

[0164] In the chip design field, flow control mechanism is a key technology to ensure that data is transmitted in order, efficiently and without loss in the bus, mainly by coordinating the speed difference between the sender and the receiver to prevent data overflow or blockage.

[0165] Among various flow control mechanisms, credit-based flow control mechanism based on buffer has been widely used in high-speed interconnection bus field due to its high bandwidth and low delay. The application embodiment proposes a credit flow control mechanism suitable for asynchronous system, which uses asynchronous FIFO to make the design more clear and compact, and the space of the asynchronous FIFO part can also be used for credit generation, fully utilizing the cache. The application embodiment uses asynchronous FIFO for receiving cache, fully utilizing the cache space for asynchronous processing. The receiving cache and the asynchronous FIFO are integrated, making the overall design more compact and simple. The use of AFIFO may not be conducive to higher frequency implementation. In addition to asynchronous processing, asynchronous FIFO is also used as a receiving cache that can generate credit. The implementation mechanism of credit returning to the sending end through AFIFO, at this time AFIFO only needs to pass the empty-full relationship, without passing specific data. Credit count can be directly reset to the agreed value on both sides of the data path at reset, omitting the initialization process of receiving end notification of credit.

[0166] In some embodiments, referring toFigure 6 , Figure 6 is the principle schematic diagram of the data interaction method provided by the embodiment of the application, the embodiment of the application uses a relatively large asynchronous FIFO, which plays a role of data buffering in addition to asynchronous processing. Each time the data of the asynchronous FIFO is read out, the data buffer has new space to receive data, at this time, 1 credit should be returned. The credit is generated in the receiving end clock domain, needs to be fed back to the sending end, and needs to be asynchronously processed through another asynchronous FIFO. The credit is controlled through the structure by the CXS interface in the embodiment of the application, and the design is relatively compact and simple. Since the CXS interface uses a special interface signal CxsCrdGnt, only 1 credit is notified in each clock cycle, and the asynchronous FIFO for returning the credit only needs to transmit the empty-full relationship, and does not need to transmit real data.

[0167] In some embodiments, referring to Figure 2, the data sending end side includes a first control unit and a second control unit. The first control unit is a data packet sending execution component, and an output end of the first control unit is connected to a first buffer zone write interface of the data receiving end through a sending link, for outputting a data packet to be sent; an enable end of the first control unit is connected to an output end of the second control unit, for receiving control information (sending enable / pause signal) generated by the second control unit. The second control unit is a sending control core, and an input end of the second control unit is connected to a second buffer zone state output interface of the data receiving end through a state detection link, for obtaining a state (first state / second state) of the second buffer zone; a residual credit value register is arranged in the second control unit, a register value of the residual credit value register is dynamically updated with credit recovery (add 1) and data packet sending (subtract 1), and an output end of the residual credit value register forms a control signal link with the enable end of the first control unit. The data receiving end side includes a first buffer zone and a second buffer zone. The first buffer zone is an asynchronous data cache component, a write interface of the first buffer zone is connected to the output end of the first control unit of the data sending end (the clock domain is consistent with the sending end), for storing a received data packet; a read interface of the first buffer zone is connected to a data processing module inside the receiving end (the clock domain is consistent with the receiving end), an output end of the processing module is connected to a deletion control end of the first buffer zone, for deleting corresponding data after data processing is completed; the processing module is further provided with a credit identifier generation end connected to a write interface of the second buffer zone, for outputting a credit identifier (signal) when data is deleted. The second buffer zone is a state feedback component, a write interface of the second buffer zone is connected to the credit identifier generation end of the processing module (the update clock domain is consistent with the receiving end), and a state output interface is connected to the input end of the second control unit of the data sending end through a state detection link (the state acquisition clock domain is consistent with the sending end), for feeding back the first state (there is a credit to be recovered) or the second state (there is no credit to be recovered) to the sending end. The data packet flows from the first control unit to the first buffer zone (receiving unit) through the sending link; the data processing module reads data from the first buffer zone and outputs a deletion signal, triggering the credit identifier to flow to the second buffer zone; the state signal of the second buffer zone is fed back to the second control unit through the detection link; the control signal generated by the second control unit flows to the first control unit, forming a closed-loop logic of sending-receiving-feedback-regulation, and the clock domain information corresponding to each link is marked, embodying the asynchronous adaptation characteristic.

[0168] The following continues to illustrate an exemplary structure of the implementation of the data interaction device 455 as a software module, in some embodiments, as shown in Figure 3 The software module stored in the data interaction device 455 of the memory 450 can include: a receiving module, configured to receive a data packet sent by the data sending end and store the data packet to the first buffer zone;

[0169] a data processing module, configured to read to-be-processed data from the first buffer, perform data processing on the to-be-processed data, and delete the to-be-processed data from the first buffer in response to completion of the data processing;

[0170] a response module, configured to generate a credit identifier between the data sending end and the data receiving end in response to deletion of the to-be-processed data from the first buffer, and update a state of the second buffer based on the credit identifier, the state being used by the data sending end to regulate a sending time of the data packet.

[0171] In some embodiments, the first buffer is a first asynchronous first-in-first-out buffer, and the response module is further configured to generate the credit identifier corresponding to the to-be-processed data deleted in a clock cycle of the data receiving end in response to deletion of the to-be-processed data from the first asynchronous first-in-first-out buffer and the number of the to-be-processed data deleted in the clock cycle being one.

[0172] In some embodiments, a clock domain of the first buffer storing the data packet is consistent with a clock domain of the data sending end, a clock domain of the first buffer reading the to-be-processed data is consistent with a clock domain of the data receiving end, a clock domain of the second buffer updating the state is consistent with the clock domain of the data receiving end, and a clock domain of the second buffer for the data sending end to obtain the state is consistent with the clock domain of the data sending end.

[0173] In some embodiments, the state includes a first state used to inform the data sending end that there is to-be-recovered credit identifier and a second state used to inform the data sending end that there is no to-be-recovered credit identifier, and the response module is further configured to obtain an initial state of the second buffer in response to generation of the credit identifier, and update a second state of the second buffer to the first state when the initial state is the second state.

[0174] In some embodiments, the response module is further configured to agree, by the data receiving end and the data sending end, on an initial storage space corresponding to an initial available buffer space of the first buffer, the initial storage space being used to indicate an initial buffer carrying capacity of the data receiving end agreed by the data receiving end and the data sending end, and in some embodiments, the receiving module is configured to detect a used storage space of the first buffer, compare the used storage space with the initial storage space to obtain a comparison result, and receive the data packet sent by the data sending end in response to the comparison result indicating that the used storage space is less than the initial storage space.

[0175] In some embodiments, the response module is further configured to determine a storage location of the to-be-processed data in the first buffer area that is deleted from the first buffer area; and generate the credit identifier between the data sending end and the data receiving end when the storage location is within the initial storage space.

[0176] The following continues to illustrate an exemplary structure of the data interaction apparatus 555 implemented as a software module provided by embodiments of the present application, which is applied to a data sending end in some embodiments. The data sending end includes a first control unit for sending data packets and a second control unit for controlling sending behavior of the first control unit. The data sending end is in communication connection with a data receiving end. The data receiving end includes a second buffer for controlling sending behavior of the data sending end, as shown in Figure 3 The software module stored in the data interaction apparatus 555 of the memory 550 can include a detection module configured to perform state detection on the second buffer by the second control unit to obtain a state of the second buffer.

[0177] A determination module configured to determine control information of the first control unit based on the state by the second control unit.

[0178] A response module configured to send a data packet by the first control unit to the data receiving end in response to the control information indicating that a data sending occasion is met.

[0179] In some embodiments, the determination module is further configured to obtain a current remaining credit value of the second control unit. The second control unit updates the remaining credit value based on the state to obtain an updated credit value. When the updated credit value is greater than a credit value threshold, the control information of the first control unit is determined to meet the data sending occasion. When the updated credit value is less than or equal to the credit value threshold, the control information of the first control unit is determined to not meet the data sending occasion.

[0180] In some embodiments, the determination module is further configured to add 1 to the remaining credit value to obtain the updated credit value when the state is a first state for informing the data sending end that there is a credit identifier to be recycled. When the state is a second state for informing the data sending end that there is no credit identifier to be recycled, the remaining credit value is determined as the updated credit value.

[0181] The embodiment of the present application provides a computer program product, which comprises a computer program or computer executable instructions stored in a computer readable storage medium. The processor of the electronic device reads the computer executable instructions or the computer program from the computer readable storage medium, and the processor executes the computer executable instructions or the computer program, so that the electronic device executes the data interaction method provided by the embodiment of the present application.

[0182] The embodiment of the present application provides a computer readable storage medium storing computer executable instructions or a computer program, wherein the computer executable instructions or the computer program are stored in the computer readable storage medium. When the computer executable instructions or the computer program are executed by the processor, the processor will execute the data interaction method provided by the embodiment of the present application, for example, the data interaction method shown in the embodiment of the present application. ​ The embodiment of the present application provides a computer readable storage medium storing computer executable instructions or a computer program, wherein the computer executable instructions or the computer program are stored in the computer readable storage medium. When the computer executable instructions or the computer program are executed by the processor, the processor will execute the data interaction method provided by the embodiment of the present application, for example, the data interaction method shown in the embodiment of the present application.

[0183] In some embodiments, the computer readable storage medium can be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM, etc. memory; it can also be various electronic devices including one or any combination of the above memories.

[0184] In some embodiments, the computer executable instructions or the computer program can be in the form of programs, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as independent programs or being deployed as modules, components, subroutines or other units suitable for use in a computing environment.

[0185] As an example, the computer executable instructions or the computer program can but not necessarily correspond to a file in a file system, can be stored in a part of a file storing other programs or data, for example, stored in one or more scripts in a hyper text markup language (HTML, Hyper Text Markup Language) document, stored in a single file dedicated to the program in question, or stored in multiple cooperative files (for example, files storing one or more modules, subroutines or code parts).

[0186] As an example, the computer executable instructions or the computer program can be deployed to execute on one electronic device, or on multiple electronic devices located in one place, or on multiple electronic devices distributed in multiple places and interconnected through a communication network.

[0187] In summary, the embodiment of the present application has the following beneficial effects:

[0188] (1) The first buffer zone is used as an asynchronous data buffer core, which stores clock domain adaptation data sending end, clock domain adaptation receiving end itself for reading data, receives data packets sent by the data sending end, and stores the data packets into the first buffer zone; the data to be processed is read from the first buffer zone, the data to be processed is processed, and the data to be processed is deleted from the first buffer zone in response to the completion of data processing, so as to ensure the stability of the whole process from receiving to buffering and then processing the data packet without error; on this basis, the receiving end generates a credit identifier after deleting the processed data in the first buffer zone, and updates the state through the second buffer zone, so that the second buffer zone becomes a bridge for accurately delivering buffer space release information, which not only ensures the real-time performance of credit feedback, but also avoids the timing risk of cross-clock domain signal transmission, so that the data sending end can accurately perceive the buffer available state of the receiving end, thereby controlling the sending opportunity to prevent the first buffer zone from overflowing due to too fast sending or data interruption due to too slow sending. The first buffer zone ensures the stability of data circulation in the receiving end, and the second buffer zone ensures the stability of the interaction rhythm between the sending end and the receiving end, and the two together build a whole-link stable mechanism from data receiving, processing to feedback control, which significantly reduces the error risk caused by clock difference and rhythm mismatch in asynchronous data interaction, and fundamentally improves the stability of data interaction.

[0189] (2) The conventional asynchronous data interaction system can completely omit the step of "the data receiving end sending an initial buffer space notification signal to the data sending end", effectively avoiding the metastable state risk and transmission delay of the notification signal in the cross-clock domain synchronization process, significantly simplifying the system initialization process and shortening the system startup time; for the data receiving end, the initial storage space provides a clear initial buffer carrying upper limit, so that it can accurately judge whether it has the receiving capacity by monitoring the ratio of the used storage space to the initial value before receiving the data packet, thereby avoiding the data packet overflow problem caused by initial buffer space recognition deviation from the source; at the same time, for the data sending end, the initial storage space can be directly mapped to the initial credit amount in the initialization stage, without waiting for any feedback from the receiving end, so as to quickly determine the initial sending permission range and ensure that the sending end can start data transmission in time, thereby improving the overall interaction efficiency; the pre-consensus of both parties can also realize the accurate matching of the sending rhythm of the sending end and the initial buffer carrying capacity of the receiving end, avoid the sending blockage or buffer waste caused by the asynchronous initial buffer information in the traditional scheme, and finally further reduce the system hardware design complexity and timing control difficulty on the basis of ensuring the reliability of asynchronous system data interaction, which meets the core application requirements of high reliability and low delay of asynchronous Credit flow control mechanism.

[0190] (3) By real-time dynamic monitoring of the space occupation state of the first buffer area, and taking the initial storage space agreed by both parties as the reference threshold, it can ensure that the data receiving end always restricts the data packet receiving behavior within the initial cache carrying capacity range during the system initialization phase, fundamentally avoiding data packet overflow or loss due to exceeding the initial cache upper limit, and significantly improving the reliability of asynchronous data interaction. At the same time, this comparison logic based on local storage state and preset reference can realize receiving permission judgment without additional cross-clock domain signal interaction between the data receiving end and the sending end, effectively reducing the delay and metastable state risk introduced by complex communication protocols or synchronization mechanisms in traditional solutions, simplifying the system control logic and hardware implementation complexity; it can make the receiving rhythm of the data receiving end accurately match the initial cache capacity, avoid wasting cache resources due to blind receiving, and at the same time provide clear feedback boundaries for the initial sending behavior of the data sending end, indirectly promote the coordination of the data interaction rhythm between the sending end and the receiving end, ultimately improve the overall data transmission efficiency on the basis of ensuring system stability, especially suitable for asynchronous communication scenarios with high real-time and reliability requirements.

[0191] (4) The first asynchronous first-in-first-out buffer area itself has the characteristics of adapting to the asynchronous clock domains of the data sending end and the receiving end, which can avoid the timing deviation of cross-clock domain data transmission. On this basis, by restricting the number of data deleted in a single cycle and generating a credit identifier corresponding to it, a strict one-to-one correspondence between the generation of the credit identifier and the release of the space of the first asynchronous first-in-first-out buffer area is formed, ensuring that each credit identifier accurately reflects the release of a unit of cache space, effectively avoiding the problem of excessive generation of credits or mismatch between credits and space release due to multiple data deletions in a single cycle, so that the data sending end can accurately judge the cache available state of the receiving end according to the credit identifier, and then accurately control the data packet sending rhythm. At the same time, this design strictly follows the hardware timing constraint that the read pointer of the first asynchronous first-in-first-out buffer area can only be incremented once in a single clock cycle, which can avoid synchronization errors and metastable state risks caused by frequent updates of the read pointer, improving the timing safety of the credit generation process. In addition, the credit identifier is generated in the same clock cycle as the data deletion, which can minimize the delay between space release and credit feedback, ensuring that the data sending end can timely obtain the cache state change of the receiving end, reducing the sending blockage or cache waste caused by feedback lag, and ultimately improving the overall data transmission efficiency while ensuring the reliability of asynchronous data interaction, especially suitable for high-speed asynchronous communication scenarios with high timing accuracy and flow control accuracy requirements.

[0192] (5) The mechanism determines the range of storage locations, strictly limiting the generation of credit identifiers to the cache release scenario corresponding to the initial storage space. This ensures that each credit identifier is directly associated with the initial cache carrying capacity pre-agreed upon by the data receiver and sender, effectively avoiding the problem of incorrectly generating credit identifiers due to the release of extended cache space outside the initial storage space (such as the extra redundant storage area of ​​the first buffer). This prevents the data sender from misjudging the initial credit status and ensures that the credit amount recovered by the sender based on the credit identifier always matches the initially agreed cache capacity. At the same time, this location-based judgment logic is simple and clear, requiring no complex numerical calculations or state tracking, which reduces the complexity of hardware implementation and is naturally compatible with the address encoding of the first buffer, ensuring the speed and accuracy of the judgment process. The design makes the flow control logic of the initial storage space and the extended storage space independent of each other. It strictly controls the reuse of the initial cache through credit identifiers while reserving space for the flexible use of the extended cache, improving the system's adaptability to different data transmission scenarios. Ultimately, while ensuring the accuracy of asynchronous data interaction flow control, it enhances the reliability and scalability of the entire system.

[0193] (6) The first buffer ensures that the data packets are accurately sampled and written under the timing constraints of the sending end's clock by keeping the clock domain of the stored data packets consistent with that of the sending end. This avoids problems such as sampling misalignment, data loss, or failure to meet setup / hold time due to cross-clock domain writing. At the same time, it keeps the clock domain of the data to be processed consistent with that of the receiving end, so that the receiving end can read the data within the stable window of its own clock, fully adapting to the timing requirements of the subsequent data processing module, completely avoiding the metastability risk caused by cross-clock domain reading, and fundamentally ensuring the reliable flow of data from the sending end to the receiving end processing module. The second buffer keeps the clock domain of the updated state consistent with that of the receiving end, which can realize real-time synchronization of credit identifier generation and state update, avoid the state feedback lag caused by clock domain differences, and ensure that the state of the second buffer can reflect the space release status of the first buffer in real time. Meanwhile, it keeps the clock domain of the state obtained by the sending end consistent with that of the sending end, so that the sending end does not need to add an additional cross-clock domain synchronization circuit, and can accurately perceive the state changes of the second buffer under its own clock rhythm, and adjust the timing of data packet transmission in a timely manner according to the state, ensuring the dynamic matching of the transmission rhythm and the buffer release status of the receiving end. Overall, this design can simultaneously achieve asynchronous adaptation of data transmission and flow control status feedback without relying on complex clock synchronization mechanisms, significantly reducing the complexity of hardware design and the difficulty of timing optimization. It effectively adapts to application scenarios where the clocks of the data sender and receiver are completely independent, providing solid timing support for the stable execution of asynchronous data interaction and the efficient operation of the flow control closed loop.

[0194] (7) The clear division of states enables the data sending end to directly perceive whether there is recoverable credit without complex logic, greatly simplifies the judgment process of the credit state of the sending end, avoids credit recovery delay or misjudgment caused by ambiguous state definition, and effectively avoids repeated state updates when the second buffer is in the first state (i.e., there is unrecovered credit), prevents state confusion of the second buffer caused by frequent invalid increments of the write pointer, and ensures that the state of the second buffer is always accurately matched with the actual generation and recovery of the credit identifier. At the same time, this updating mechanism only responds to the credit identifier for state switching when there is no credit to be recovered in the second buffer, which not only reduces unnecessary hardware operations, reduces timing control difficulty and resource consumption, but also ensures that each state update corresponds to an effective credit feedback demand, so that the state of the second buffer can accurately reflect the release of the initial storage space of the first buffer, providing a reliable basis for the data sending end to control the data packet sending time according to the state, thereby avoiding sending blockage or buffer overflow caused by state errors, and ensuring the stability and efficiency of the asynchronous data interaction flow control closed loop.

[0195] (8) The remaining credit value as a quantitative parameter converts the buffer release state of the data receiving end into a directly calculable numerical value, avoiding the uncertainty based on fuzzy state judgment, and making the determination of the sending time have accurate quantitative basis. Based on the real-time updating mechanism of the second buffer state, it ensures that the updated credit value can immediately reflect the latest buffer state of the receiving end, realizes the dynamic synchronization of credit recovery and sending permission, and avoids misjudgment caused by credit value lag. Furthermore, using the threshold value (usually 0) as the judgment basis simplifies the hardware implementation of the control logic, reduces the complexity of timing design, and ensures that the judgment result strictly matches the core requirement of "whether the receiving end has enough buffer space". Through the logic of "updating credit value greater than threshold value allows sending, otherwise prohibits sending", the data sending end is fundamentally prevented from blindly sending when the receiving end buffer is insufficient, avoiding the risk of buffer overflow, while allowing sending in time when there is available credit, reducing transmission blockage caused by judgment delay, and ultimately ensuring the reliability of data transmission and improving the overall transmission efficiency in the asynchronous data interaction scenario, especially suitable for fields with high requirements for timing accuracy and transmission stability.

[0196] (9) By strictly binding the first state (existence of a credit identifier to be recycled) and "remaining credit value + 1", each credit recycling accurately corresponds to the release of one unit of initial storage space at the data receiving end, ensuring that the increment of credit value and the increment of actual available cache space form a one-to-one correspondence, fundamentally avoiding the problem of mismatch between sending permissions and receiving end cache capabilities caused by untimely or excessive credit recycling; at the same time, binding the second state (non-existence of a credit identifier to be recycled) and "remaining credit value remains unchanged" can prevent value changes without basis when there is no new credit to be recycled, ensuring that the credit value always truly reflects the current actual sending permission of the data sending end, avoiding misjudgment of sending opportunity caused by abnormal fluctuations in credit value; in addition, this state type-based differentiated update logic is simple and direct, without the need for complex calculations or state transitions, which not only reduces the timing complexity and resource consumption of hardware implementation, but also ensures that the update operation is completed within a single clock cycle, meeting the real-time requirements of asynchronous data interaction; ultimately, this update method enables the remaining credit value to dynamically and accurately map the receiving end cache state and the sending end permission state, providing a reliable quantitative basis for subsequent judgment of sending opportunity based on updated credit value, further improving the stability, accuracy and efficiency of the entire asynchronous flow control system.

[0197] (10) A complete data packet (including data fields, check fields, frame headers and frame tails, etc. structure information) is read from the data packet storage submodule in a predetermined order (such as first-in first-out); then, the internal timing control logic converts the parallel data of the data packet into serial data (or keeps the parallel format, depending on the link type) adapted to the communication link, and ensures that the data format meets the writing requirements of the first buffer of the data receiving end (such as bit width matching, timing alignment); next, at the active edge (such as the rising edge) of the data sending end clock domain, the sending interface circuit of the first control unit transmits the converted data packet to the first buffer writing interface of the data receiving end through the physical communication link (such as high-speed serial bus, parallel data bus), drives the first buffer to perform a write operation, and completes the storage of the data packet.

[0198] (11) Through the state detection of the second buffer by the second control unit, the control information determined based on the state, and the cooperative process of the first control unit sending data packets according to the control information, the stability of data interaction is significantly improved: the state detection of the second buffer by the second control unit ensures that the data sending end can accurately perceive the release of the buffer space of the data receiving end, avoiding sending decision errors caused by state perception deviation; the process of determining control information based on the state makes the sending permission strictly match the actual buffer capacity of the receiving end, preventing sending behavior without basis, and avoiding buffer overflow of the receiving end caused by too fast sending rhythm or data transmission interruption caused by too slow sending rhythm from the source; and the first control unit only sends data packets when the control information indicates that the sending opportunity is met, ensuring that each sending is within the range that the receiving end can withstand, reducing data loss or errors caused by timing conflicts and insufficient buffer, and forming a closed-loop stable mechanism of "perception - decision - execution". Through the accurate cooperation of each link, the unstable risks caused by independent clock and rhythm mismatch in asynchronous data interaction are effectively resolved, ensuring that the transmission of data from the sending end to the receiving end is always orderly and controllable, thereby significantly improving the stability of data interaction.

[0199] The above is only an embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A data interaction method, characterized in that, The method is applied to a data receiving end, the data receiving end comprises a first buffer for asynchronously processing and buffering data, and a second buffer for controlling sending behavior of a data sending end, the method comprises: receiving a data packet sent by the data sending end and storing the data packet into the first buffer; reading to-be-processed data from the first buffer, processing the to-be-processed data, and deleting the to-be-processed data from the first buffer in response to completion of the processing; generating a credit identifier between the data sending end and the data receiving end in response to existence of deletion of the to-be-processed data from the first buffer; updating a state of the second buffer based on the credit identifier, the state being used for regulating sending time of the data packet by the data sending end.

2. The method of claim 1, wherein, The first buffer is an asynchronous first-in-first-out buffer, and the generating the credit identifier between the data sending end and the data receiving end in response to existence of deletion of the to-be-processed data from the first buffer comprises: generating the credit identifier corresponding to the deleted to-be-processed data in a clock cycle of the data receiving end in response to existence of deletion of the to-be-processed data from the asynchronous first-in-first-out buffer and the number of the to-be-processed data deleted in the clock cycle being one.

3. The method of claim 1, wherein, The clock domain of the first buffer for storing the data packet is consistent with the clock domain of the data sending end, and the clock domain of the first buffer for reading the to-be-processed data is consistent with the clock domain of the data receiving end; the clock domain of the second buffer for updating the state is consistent with the clock domain of the data receiving end, and the clock domain of the second buffer for obtaining the state by the data sending end is consistent with the clock domain of the data sending end.

4. The method of claim 1, wherein, The state comprises a first state for informing the data sending end of existence of to-be-recovered credit identifiers and a second state for informing the data sending end of non-existence of to-be-recovered credit identifiers; the updating the state of the second buffer based on the credit identifier comprises: obtaining an initial state of the second buffer in response to generation of the credit identifier; updating the second state of the second buffer to the first state when the initial state is the second state.

5. The method of claim 1, wherein, Before the receiving the data packet sent by the data sending end, the method further comprises: the data receiving end and the data sending end agree on an initial storage space corresponding to an initial available buffer space of the first buffer, the initial storage space being used for indicating initial buffer bearing capacity of the data receiving end agreed by the data receiving end and the data sending end; the receiving the data packet sent by the data sending end comprises: detecting used storage space of the first buffer, comparing the used storage space with the initial storage space, and obtaining a comparison result; receiving the data packet sent by the data sending end in response to the comparison result indicating that the used storage space is less than the initial storage space.

6. The method of claim 5, wherein, the generating the credit identifier between the data sending end and the data receiving end comprises: determining a storage position of the to-be-processed data in the first buffer area which is to be deleted from the first buffer area; generating a credit identifier between the data sending end and the data receiving end when the storage position is within the initial storage space.

7. A data interaction method, characterized by, The application is applied to a data sending end, the data sending end comprises a first control unit for sending data packets and a second control unit for controlling the sending behavior of the first control unit, the data sending end and a data receiving end are communicatively connected, the data receiving end comprises a second buffer area for controlling the sending behavior of the data sending end, and the method comprises the following steps: The second control unit detects the state of the second buffer area to obtain the state of the second buffer area; The second control unit determines the control information of the first control unit based on the state; In response to the control information indicating that the data sending occasion is met, the first control unit sends a data packet to the data receiving end.

8. The method of claim 7, wherein, The second control unit determines the control information of the first control unit based on the state, comprising: obtaining the current remaining credit value of the second control unit, the second control unit updates the remaining credit value based on the state to obtain an updated credit value; when the updated credit value is greater than a credit value threshold, the control information of the first control unit is determined to meet the data sending occasion; when the updated credit value is less than or equal to the credit value threshold, the control information of the first control unit is determined to not meet the data sending occasion.

9. The method of claim 8, wherein, The second control unit updates the remaining credit value based on the state to obtain an updated credit value, comprising: when the state is a first state for informing the data sending end that there is a credit identifier to be recycled, the remaining credit value is increased by 1 to obtain the updated credit value; when the state is a second state for informing the data sending end that there is no credit identifier to be recycled, the remaining credit value is determined as the updated credit value.

10. A data interaction device, characterized by The application is applied to a data receiving end, the data receiving end comprises a first buffer area for asynchronously processing and caching data, and a second buffer area for controlling the sending behavior of a data sending end, and the device comprises: a receiving module for receiving a data packet sent by the data sending end and storing the data packet into the first buffer area; a data processing module for reading to-be-processed data from the first buffer area, processing the to-be-processed data, and deleting the to-be-processed data from the first buffer area in response to the completion of the data processing; a response module for generating a credit identifier between the data sending end and the data receiving end in response to the deletion of the to-be-processed data from the first buffer area, and updating the state of the second buffer area based on the credit identifier, the state being used for the data sending end to regulate the sending occasion of the data packet.

11. A data interaction device, characterized by The device is applied to a data sending end, the data sending end comprises a first control unit for sending data packets and a second control unit for controlling the sending behavior of the first control unit, the data sending end is in communication connection with a data receiving end, the data receiving end comprises a second buffer for controlling the sending behavior of the data sending end, and the device comprises: a detection module configured to detect, by the second control unit, a state of the second buffer to obtain a state of the second buffer; a determination module configured to determine, by the second control unit, control information of the first control unit based on the state; a response module configured to send, by the first control unit, data packets to the data receiving end in response to the control information indicating that a data sending opportunity is met.

12. An electronic device, comprising: The electronic device comprises: a memory configured to store computer executable instructions or computer programs; a processor configured to execute the computer executable instructions or computer programs stored in the memory to implement the data interaction method in any one of claims 1 to 9.

13. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, The computer executable instructions or computer programs are executed by the processor to implement the data interaction method in any one of claims 1 to 9.

14. A computer program product comprising computer programs or computer executable instructions, characterized in that, The computer program or computer executable instructions are executed by the processor to implement the data interaction method in any one of claims 1 to 9. The computer program or computer executable instructions are executed by the processor to implement the data interaction method in any one of claims 1 to 9.

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