Transmit (TX) receive (RX) phased array system

Abstract

A millimeter wave (mmW) communication system on a millimeter wave integrated circuit (MMW-IC) includes a phase shifter selectively connected to a receive path through a first electromagnetic (EM) element and selectively connected to a transmit path through a second EM element, the first EM element is configured to receive a transmit signal and configured to receive a receive signal from a low noise amplifier (LNA), and the second EM element is configured to receive a phase shifted transmit signal or a phase shifted receive signal from a phase shifter, and wherein the second EM element is configured to selectively provide the phase shifted transmit signal to a power amplifier on the mmW-IC and to provide the phase shifted receive signal to a receive signal processing circuit located outside the mmW-IC.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to phase shifters in transceivers. Background Technology

[0002] Wireless communication devices and technologies are becoming increasingly prevalent, with communication devices operating at millimeter-wave (mmW) and sub-THz frequencies becoming more common. Wireless communication devices typically transmit and / or receive communication signals. In radio frequency (RF) transceivers, communication signals are typically amplified and transmitted by the transmitting section, and received communication signals are amplified and processed by the receiving section. Transceivers used for communication in 5G and 6G applications can communicate using millimeter-wave (mmW) frequency signals and / or sub-THz frequencies, and can utilize so-called zero-IF (ZIF) or low-IF architectures.

[0003] Transceivers used in 5G communication systems can increase system capacity using a technique called beamforming. Beamforming typically uses individual transmit and receive elements, where phase shifters change the phase of the signal. Typically, many such elements and phase shifters are implemented in such systems. Typically, each TX / RX element uses two phase shifters, one for transmitting and one for receiving.

[0004] A typical system architecture can implement four phase shifters for two adjacent TX / RX elements. Each phase shifter may include a hybrid quadrature generator (HQG) and combinational circuitry, and therefore occupies a large area on the circuit.

[0005] Therefore, it is desirable to minimize the number of phase shifters in such a system. Summary of the Invention

[0006] Various implementations of the systems, methods, and apparatus within the scope of the appended claims each have several aspects, none of which are solely responsible for the desired properties described herein. Certain prominent features are described herein without limiting the scope of the appended claims.

[0007] Details of one or more implementations of the subject matter described in the specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the specification, drawings, and claims. It should be noted that the relative dimensions in the following drawings may not be drawn to scale.

[0008] One aspect of this disclosure provides a millimeter-wave (mmW) communication system on a millimeter-wave integrated circuit (MMW-IC), comprising: a phase shifter selectively connected to a receive path via a first electromagnetic (EM) element and selectively connected to a transmit path via a second EM element; the first EM element being configured to receive a transmit signal and to receive a receive signal from a low-noise amplifier (LNA); the second EM element being configured to receive a phase-shifted transmit signal or a phase-shifted receive signal from the phase shifter; and wherein the second EM element is configured to selectively provide the phase-shifted transmit signal to a power amplifier on the mmW-IC and to a receive signal processing circuit located outside the mmW-IC.

[0009] Another aspect of this disclosure provides a method for phase-shifting a signal, including selectively applying a transmitted signal or a received signal to a shared phase shifter, phase-shifting the transmitted signal or the received signal, and selectively applying the phase-shifted transmitted signal to a power amplifier or selectively applying the phase-shifted received signal to a phased array output.

[0010] Another aspect of this disclosure provides an apparatus for phase-shifting a signal, comprising: a unit for selectively applying a transmitted signal or a received signal to a shared phase shifter; a unit for phase-shifting the transmitted signal or the received signal; and a unit for selectively applying the phase-shifted transmitted signal to a power amplifier or selectively applying the phase-shifted received signal to a phased array output.

[0011] Another aspect of this disclosure provides a phased array element including a receiving circuit, a transmitting circuit, a first electromagnetic (EM) element coupled to the receiving circuit, a second EM element coupled to the transmitting circuit, and a phase shifter coupled between the first EM element and the second EM element, wherein the phased array element is configured such that the phase shifter is shared by the receiving circuit and the transmitting circuit. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise indicated, similar reference numerals refer to similar parts throughout the various views. For reference numerals with letter names such as "102a" or "102b", these letter names can distinguish two similar parts or elements appearing in the same drawing. The letter names of the reference numerals may be omitted when the aim is to have the reference numerals cover all parts with the same reference numeral in all drawings.

[0013] Figure 1 This is a diagram showing a wireless device communicating with a wireless communication system.

[0014] Figure 2AThis is a block diagram illustrating a wireless device in which exemplary technologies can be implemented according to the present disclosure.

[0015] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies can be implemented according to the present disclosure.

[0016] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies can be implemented according to the present disclosure.

[0017] Figure 3 This is a block diagram of two transmit (TX) and receive (RX) elements in a phased array system.

[0018] Figure 4A and Figure 4B yes Figure 3 A schematic diagram of an embodiment of a three-coil circuit.

[0019] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of an embodiment of a three-coil circuit.

[0020] Figure 6 This is a flowchart illustrating an example of the operation of a method for processing signals.

[0021] Figure 7 It is a functional block diagram of a device used for signal processing. Detailed Implementation

[0022] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred over or superior to other aspects.

[0023] According to an exemplary embodiment, the TX / RX radio architecture has a single phase shifter that can be shared between the transmitting and receiving elements, thereby reducing the circuit area.

[0024] According to an exemplary embodiment, the TX / RX radio architecture has a phase shifter implemented in a single direction, wherein the transmitted and received signals are selectively routed via the phase shifter.

[0025] According to an exemplary embodiment, the TX / RX radio architecture uses one or more three-coil electromagnetic (EM) structures to combine signals, including providing impedance matching and reducing the load on the transmitting and receiving elements.

[0026] According to an exemplary embodiment, the TX / RX radio architecture can be single-ended in the receive mode after the phase shifter.

[0027] Figure 1This diagram illustrates a wireless device 110 communicating with a wireless communication system 120. The wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Typically, a wireless communication system may include any number of base stations and any set of network entities.

[0028] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet computer, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet, cordless phone, medical device, automobile, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from a broadcast station (e.g., broadcast station 134) and / or may communicate with satellites (e.g., one or more satellites 150 in a Global Navigation Satellite System (GNSS)) or satellites from which signals can be received by wireless device 110, etc. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub-6 5G, 6G, UWB, etc.

[0029] Wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some embodiments, carrier aggregation is used to transmit a single data stream on multiple carriers, for example, relative to separate carriers used for the respective data streams. Wireless device 110 may be able to operate in a variety of communication frequency bands, including those used, for example, by LTE, WiFi, 5G, or other communication bands over a wide frequency range. Wireless device 110 may also be able to communicate directly with other wireless devices without communicating through a network.

[0030] Generally, carrier aggregation (CA) can be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0031] Figure 2A This is a block diagram illustrating an exemplary wireless device 200 in which the present disclosure can be implemented. The wireless device 200 may be, for example, Figure 1 An embodiment of the wireless device 110 shown in the figure.

[0032] Figure 2A An example of a transceiver 220 with a transmitter 230 and a receiver 250 is shown. Typically, signal conditioning in the transmitter 230 and receiver 250 can be performed by one or more stages such as amplifiers, filters, up-converters, down-converters, etc. These circuit blocks can be used with... Figure 2A The configurations shown are arranged differently. Furthermore, Figure 2A Other circuit blocks, not shown, can also be used to regulate signals in transmitter 230 and receiver 250. Unless otherwise stated, Figure 2A Any signal or any other diagram in the figure may be a single-ended signal or a differential signal. Figure 2A Some circuit blocks can also be omitted.

[0033] exist Figure 2A In the example shown, wireless device 200 typically includes transceiver 220 and data processor 210. Data processor 210 may include processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code, typically indicated by reference numeral 299, and may typically include analog and / or digital processing components. Processor 296 and memory 298 may cooperate to control, configure, program, or otherwise fully or partially control some or all of the operation of embodiments of the TX LO leakage calibration circuit described herein.

[0034] Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Typically, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0035] Transmitters or receivers can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between radio frequency (RF) and baseband in multiple stages; for example, for a receiver, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0036] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by data processor 210 into I and Q analog output signals, such as I and Q output currents, for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 digitally provides data (e.g., for I and Q) to transceiver 220.

[0037] Within transmitter 230, baseband (e.g., low-pass) filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted images caused by the previous digital-to-analog conversion. Amplifiers 234a and 234b amplify the signals from baseband filters 232a and 232b, respectively, and provide the I and Q baseband signals. Upconverter 240, with upconverters 241a and 241b, upconverts the I and Q baseband signals with the I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 290, and provides the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted images caused by upconversion and noise in the receive band. Power amplifier 244 amplifies the signal from filter 242 to obtain the desired output power level and provides the transmit RF signal. The transmit RF signal can be routed via a duplexer or switch 246 and transmitted via antenna 248. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that transceiver components can be configured to utilize polarization modulation.

[0038] In the receiving path, antenna 248 receives the communication signal and provides the received RF signal, which is routed through a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with a specific receive (RX) to TX duplexer frequency separation, thus isolating the RX signal from the TX signal. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal.

[0039] Downconverters 261a and 261b in downconverter 260 mix the output of filter 254 with the I and Q received (RX)LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by baseband (e.g., low-pass) filters 264a and 264b to obtain the I and Q analog input signals provided to data processor 210. In the illustrated exemplary embodiment, data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals for further processing by data processor 210. In some embodiments, ADCs 216a and 216b are included in transceiver 220 and digitally provide data to data processor 210.

[0040] exist Figure 2A In this configuration, TX LO signal generator 290 generates I and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I or Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from TX LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from RX LO signal generator 280.

[0041] The wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein can be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0042] Some components of transceiver 220 Figure 2AThe transceiver 220 is functionally illustrated, and the configurations shown may or may not represent physical device configurations in some implementations. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board such as a printed circuit board (PCB) having various modules, chips, and / or components. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components shown in the transceiver 220 may be implemented in a single transceiver chip.

[0043] Power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components. The power amplifier may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0044] In an exemplary embodiment of the superheterodyne architecture, PA 244 and LNA 252 (and in some examples filters 242 and / or 254) may be implemented separately from other components in transmitter 230 and receiver 250, and may be implemented on millimeter-wave integrated circuits. Figure 2B An example superheterodyne architecture is shown in the figure.

[0045] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies can be implemented according to the present disclosure. Figure 2B Certain components of the wireless device 200a (e.g., which may be indicated by the same reference numerals) may be compatible with... Figure 2A The components in the wireless device 200 shown are similarly configured, and Figure 2B The descriptions of items with the same number will not be repeated.

[0046] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture, in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and intermediate frequency (IF). The IF signal can be a low IF (LIF) signal or a zero (or near-zero) IF (ZIF) signal. For example, upconverter 240 can be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include upconverter mixer 276. A summation function 278, which may be part of upconverter 240, combines the I and Q outputs of upconverter 240 and provides a non-quadrature signal to mixer 276. The non-quadrature signal can be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TX RF LO signal generator 277, and provide the upconverted RF signal to phase shift circuit 281. Although PLL 292 is Figure 2B The phase shift circuit 281 is shown as being shared by signal generators 290 and 277, but a corresponding PLL can be implemented for each signal generator. In an exemplary embodiment, the phase shift circuit 281 may be part of a millimeter-wave integrated circuit (mmW-IC) or may be located on the millimeter-wave integrated circuit.

[0047] In an exemplary embodiment, the components in the phase shift circuit 281 may include one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor 210 via connection 294, and operate the adjustable or variable phased array elements based on the received control signals.

[0048] In an exemplary embodiment, the phase shift circuit 281 includes a phase shifter 283 and a phased array element 287. Although three phase shifters 283 and three phased array elements 287 are shown for ease of illustration, the phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287. For example, one or two arrays of four or five antennas and corresponding phase shifters / phased array elements may be implemented.

[0049] Each phase shifter 283 can be configured to receive an RF transmit signal from the upconverter 275, change its phase by a certain amount, and provide the RF signal to a corresponding phased array element 287. Each phased array element 287 may include transmit and receive circuitry, including one or more filters, amplifiers, drive amplifiers, and / or power amplifiers. In some embodiments, the phase shifter 283 may be incorporated within the corresponding phased array element 287.

[0050] The output of phase shift circuit 281 is provided to antenna array 248. In an exemplary embodiment, antenna array 248 includes a plurality of antennas typically corresponding to the number of phase shifters 283 and phased array elements 287, such that each antenna element is coupled to a corresponding phased array element 287. In an exemplary embodiment, phase shift circuit 281 and antenna array 248 may be referred to as a phased array.

[0051] In the receiving direction, the output of phase shift circuit 281 is provided to downconverter 285. In an exemplary embodiment, downconverter 285 may include downconverter mixer 286. In an exemplary embodiment, mixer 286 downconverts the received RF signal provided by phase shift circuit 281 to an IF signal based on the RX RF LO signal provided by RX RF LO signal generator 279. I / Q generation function 291 in downconverter 260 receives the IF signal from mixer 286 and generates I and Q signals for downconverter 260, which downconverts the IF signal to baseband, as described above. Although PLL 282 is in Figure 2B The PLL is shown as being shared by signal generators 280 and 279, but a corresponding PLL can be implemented for each signal generator.

[0052] In some embodiments, upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, summation function 278 and I / Q generation function 291 are implemented separately from mixers 276 and 286, such that mixers 276, 286, and phase shift circuit 281 are implemented on a common IC, but summation function 278 and I / Q generation function 291 are not (e.g., summation function 278 and I / Q generation function 291 are implemented in another IC coupled to the IC having mixers 276, 286). In some embodiments, LO signal generators 277, 279 are included in a common IC. In some embodiments where the phase shift circuit is implemented on a common IC having 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some embodiments, the phase-shifting circuit 281 (e.g., a chip on which the phase-shifting circuit 281 is implemented) is coupled to the antenna array 248 via interconnects or both are mounted to the substrate. For example, components of the antenna array 248 may be implemented on the substrate and coupled to the integrated circuit implementing the phase-shifting circuit 281 via flexible printed circuitry, or the integrated circuit may be mounted to the opposite side of the substrate.

[0053] In some embodiments, Figure 2A The architecture shown and Figure 2B The architectures shown both are implemented within the same device. For example, wireless devices 110 or 200 can be configured to use... Figure 2A The architecture shown is used to communicate with signals at frequencies below approximately 20 GHz and utilizes Figure 2B The architecture shown is for communicating with signals at frequencies higher than approximately 20 GHz. In devices implementing both architectures, Figure 2A and 2B One or more components with the same number can be shared between the two architectures. For example, signals that have been directly down-converted from RF to baseband and signals that have been down-converted from RF to baseband via an IF stage can both be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the implementation Figure 2A The architecture of the device is included in the second version of filter 264 in the implementation. Figure 2B The architecture of the device is described herein. While certain example frequencies are described herein, other implementations are possible. For example, a direct conversion architecture can be used to transmit and / or receive signals with frequencies higher than about 20 GHz (e.g., with mmW frequencies). In such embodiments, for example, a phased array can be implemented in a direct conversion architecture.

[0054] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies can be implemented according to the present disclosure. Figure 2C Certain components of the wireless device 200b (e.g., which may be indicated by the same reference numerals) may be compatible with... Figure 2A The wireless device 200 and / or shown Figure 2B The components in the wireless device 200a shown are similarly configured, and Figure 2C The descriptions of items with the same number will not be repeated.

[0055] Figure 2C Wireless device 200b is incorporated into the direct conversion architecture ( Figure 2B The phase shift circuit 281, wherein the mmW transmitted signal is up-converted and down-converted between baseband and RF without using intermediate frequency (IF) signal conversion. For example, Figure 2C The LO signal in the architecture can include signals at frequencies of tens of GHz.

[0056] In some embodiments, the upconverter 240, downconverter 260, and phase shift circuit 281 are implemented on a common IC. In some embodiments, LO signal generators 280 and 290 are included in the common IC. In some embodiments, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some embodiments, phase shift circuit 281 (e.g., a chip on which phase shift circuit 281 is implemented) is coupled to antenna array 248 via interconnects or both are mounted to a substrate. For example, components of antenna array 248 can be implemented on the substrate and coupled to the integrated circuit implementing phase shift circuit 281 via flexible printed circuitry, or the integrated circuit can be mounted to the opposite side of the substrate.

[0057] Figure 3 This is a block diagram 300 of two transmit (TX) and receive (RX) elements in a phased array system, for example, that may be included in phase shift circuit 281. The elements of FIG300 may be located on a millimeter-wave integrated circuit (mmW-IC). A first element 310, which may be an example of phased array element 287, may include an electromagnetic (EM) element 312 configured to couple the TX and RX paths of the first element 310 to an antenna or antenna port 311. In an exemplary embodiment, EM element 312 may include a first inductor element 313, a second inductor element 314, and a third inductor element 315. If EM element 312 is implemented as a transformer (or a three-coil magnetic circuit), then the first inductor element 313 may be primary-side (or primary coil), the second inductor element 314 may be secondary-side (or secondary coil), and the third inductor element 315 may be a tertiary coil. In an exemplary embodiment, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as the transmitted signal may pass through EM element 312 in a direction opposite to the direction of the received signal.

[0058] In an exemplary embodiment, the first element 310 may further include a power amplifier (PA) 318, a drive amplifier (DA) 319, and an EM element 328. In some embodiments, more than two stages of transmit signal amplification may be implemented. In an exemplary embodiment, the EM element 328 may include a first inductor 332, a second inductor 331, and a third inductor 329. If the EM element 328 is implemented as a transformer (or a three-coil magnetic circuit), the first inductor 332 may be the primary side (or primary coil), the second inductor 331 may be the secondary side (or secondary coil), and the third inductor 329 may be a three-coil circuit. In an exemplary embodiment, the third inductor 329 may include switches 333 and 335 located on either side of the center tap of the third inductor 329 and close to the center tap. In an exemplary embodiment, the center tap may be connected to a bias voltage, Vbias.

[0059] In an exemplary embodiment, the first element 310 may further include an RX circuit comprising a first-stage low-noise amplifier (LNA) 316 and a second-stage LNA 317, but different numbers of LNA stages may be implemented. The output of the second-stage LNA 317 may be provided to the EM element 321. In an exemplary embodiment, the EM element 321 may include a first inductor 322, a second inductor 323, and a third inductor 324. If the EM element 321 is implemented as a transformer (or a three-coil magnetic circuit), the first inductor 322 may be the primary side (or primary coil), the second inductor 323 may be the secondary side (or secondary coil), and the third inductor 324 may be the tertiary coil. In an exemplary embodiment, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as the transmitted signal can pass through the EM element 321, such that the first inductor 322 may be considered the primary coil, and the third inductor 324 may be considered the secondary coil. However, the received signal can pass through EM element 321, allowing the second sensing element 323 to be considered a primary coil and the third sensing element 324 to be considered a secondary coil. In an exemplary embodiment, the side of the second inductor 323 opposite to the second-stage LNA 317 can be connected to the system voltage, VDD. In an exemplary embodiment, the first inductor 322 may include switches 325 and 327 located on either side of the center tap of the first inductor 322 and close to the center tap. In an exemplary embodiment, the center tap can be connected to the system voltage, VDD.

[0060] In an exemplary embodiment, the first element 310 includes a phase shifter 320 coupled between EM elements 321 and EM elements 328. The phase shifter 320 is shown as including a hybrid quadrature generator (HQG) 340 and variable gain amplifiers (VGAs) 334 and 336, but other implementations of the phase shifter may be used. For example, a phase shifter with a polyphase filter and an active or passive VGA may be implemented. In an exemplary embodiment, the HQG 340 may be configured to generate in-phase (I) signals and quadrature (Q) signals separated by 90 degrees. For example, the VGA 334 may be configured to operate on the in-phase signal, and the VGA 336 may be configured to operate on the quadrature signal. In an exemplary embodiment, a vector modulator driver (VMDR) 326 may be coupled to EM element 321 and configured to operate on a transmit signal, such as providing a differential transmit signal to the opposite end of inductor element 322.

[0061] In an exemplary embodiment, the output of VGA 334 is provided to the opposite side of inductor 332, and the output of VGA 336 is provided to the opposite side of inductor 332 of EM element 328. In an exemplary embodiment, switch 337 may be connected between one end of inductor 331 and ground, and switch 338 may be connected between the other end of inductor 331 and ground. Switch 337 may be controlled by control signal Rx_en, and switch 338 may be controlled by control signal Rx_enb, such that when switch 337 is on, switch 338 is not on, and when switch 338 is on, switch 337 is not on. Complementary control signals Rx_en and Rx_enb may be controlled by data processor (210, Figure 2C (or provided by another controller.)

[0062] A second element 350, which may be another example of a phased array element 287, may include an electromagnetic (EM) element 352 configured to couple the TX and TX paths of the second element 350 to an antenna or antenna port 351. In an exemplary embodiment, the EM element 352 may include a first inductor element 353, a second inductor element 354, and a third inductor element 355. If the EM element 352 is implemented as a transformer (or a three-coil magnetic circuit), the first inductor element 353 may be the primary side (or primary coil), the second inductor element 354 may be the secondary side (or secondary coil), and the third inductor element 355 may be a tertiary coil. In an exemplary embodiment, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as transmitted signals may pass through the EM element 352 in a direction opposite to the direction of received signals.

[0063] In an exemplary embodiment, the second element 350 may further include a power amplifier (PA) 358, a drive amplifier 359, and an EM element 368. In some embodiments, more than two stages of transmit signal amplification may be implemented. In an exemplary embodiment, the EM element 368 may include a first inductor 372, a second inductor 371, and a third inductor 369. If the EM element 368 is implemented as a transformer (or a three-coil magnetic circuit), the first inductor 372 may be the primary side (or primary coil), the second inductor 371 may be the secondary side (or secondary coil), and the third inductor 369 may be a three-coil circuit. In an exemplary embodiment, the third inductor 369 may include switches 373 and 375 located on either side of the center tap of the third inductor 369 and close to the center tap of the third inductor 329. In an exemplary embodiment, the center tap may be connected to a bias voltage, Vbias.

[0064] In an exemplary embodiment, the second element 350 may further include an RX circuit comprising a first-stage low-noise amplifier (LNA) 356 and a second-stage LNA 357, but different numbers of LNA stages may be implemented. The output of the second-stage LNA 357 may be provided to the EM element 361. In an exemplary embodiment, the EM element 361 may include a first inductor 362, a second inductor 363, and a third inductor 364. If the EM element 361 is implemented as a transformer (or a three-coil magnetic circuit), the first inductor 362 may be the primary side (or primary coil), the second inductor 363 may be the secondary side (or secondary coil), and the third inductor 364 may be the tertiary coil. In an exemplary embodiment, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as the transmitted signal can pass through the EM element 361, such that the first inductor 362 may be considered the primary coil, and the inductor 364 may be considered the secondary coil. However, the received signal can pass through EM element 361, allowing inductor element 363 to be considered as the primary coil and inductor element 364 to be considered as the secondary coil. In an exemplary embodiment, the side of the second inductor element 363 opposite to the second-stage LNA 357 can be connected to the system voltage, VDD. In an exemplary embodiment, the first inductor element 362 may include switches 365 and 367 located on either side of the center tap of the first inductor element 362 and close to the center tap of the first inductor element 322. In an exemplary embodiment, the center tap can be connected to the system voltage, VDD.

[0065] In an exemplary embodiment, the second element 350 includes a phase shifter 370 coupled between EM elements 361 and EM elements 368. The phase shifter 370 is shown as including a hybrid quadrature generator (HQG) 380 and variable gain amplifiers (VGAs) 374 and 376, but other implementations of the phase shifter may be used. For example, a phase shifter with a polyphase filter and an active or passive VGA may be implemented. In an exemplary embodiment, the HQG 380 may be configured to generate in-phase (I) signals and quadrature (Q) signals separated by 90 degrees. For example, the VGA 374 may be configured to operate on the in-phase signal, and the VGA 376 may be configured to operate on the quadrature signal. In an exemplary embodiment, a vector modulator driver (VMDR) 366 may be coupled to EM element 361 and configured to operate on a transmit signal, such as providing a differential transmit signal to the opposite end of inductor element 362.

[0066] In an exemplary embodiment, the output of VGA 374 is provided to the opposite side of inductor 372, and the output of VGA 376 is provided to the opposite side of inductor 372 of EM element 368. In an exemplary embodiment, switch 377 may be connected between one end of inductor 371 and ground, and switch 378 may be connected between the other end of inductor 371 and ground. Switch 377 may be controlled by control signal Rx_en, and switch 378 may be controlled by control signal Rx_enb, such that when switch 377 is on, switch 378 is off, and when switch 378 is on, switch 377 is off. Complementary control signals Rx_en and Rx_enb may be controlled by data processor (210, Figure 2C (or provided by another controller.)

[0067] In an exemplary embodiment, a transmit (TX) signal can be provided to VMDR 326 and VMDR 366 via connections 341a and 341b. In the illustrated example, the TX signal is provided on a connection shared by elements 310 and 350, but in other examples, each of elements 310 and 350 can be coupled to the same or separate transmit signals via corresponding connections. In an exemplary embodiment, the TX signal can be a differential signal, but in other embodiments, it is a single-ended TX signal. Connection 341 can be coupled to up-inverter 240 or 275. In an exemplary embodiment, arrow 344 can be used to indicate the transmit path in element 310, wherein, in an exemplary embodiment, transmit path 344 includes VMDR 326, EM element 321, HQG 340, VGA 334 and 336, EM element 328, drive amplifier 319, PA 318, and EM element 312. In an exemplary embodiment, arrow 384 may be used to indicate the transmit path in element 350, wherein, in an exemplary embodiment, transmit path 384 includes VMDR 366, EM element 361, HQG 380, VGA 374 and 376, EM element 368, drive amplifier 359, PA 358 and EM element 352.

[0068] In an exemplary embodiment, the received signal may be provided to downstream processing elements, for example, via a phased array output through connection 342. In an exemplary embodiment, the RX signal may be a differential signal or a single-ended signal. In an exemplary embodiment, the received signal may be a single-ended signal. In the illustrated example, the RX signal is provided over a connection shared by elements 310 and 350, but in other examples, each of elements 310 and 350 may provide a transmit signal via a corresponding connection. Connection 342 may be coupled to downconverter 260 or 285. In an exemplary embodiment, arrow 345 may be used to indicate the receive path in element 310, wherein, in an exemplary embodiment, the receive path 345 includes EM element 312, LNA 316, second-stage LNA 317, EM element 321, HQG 340, VGA 334 and 336, EM element 328, and connection 342. In an exemplary embodiment, arrow 385 may be used to indicate the receiving path in element 350, wherein, in an exemplary embodiment, receiving path 385 includes EM element 352, LNA 356, second-stage LNA 357, EM element 361, HQG 380, VGA 374 and 376, EM element 368, and connection 342. In an exemplary embodiment, transmit path 344 and receive path 345 follow the same path (in the same direction) through phase shifter 320, and transmit path 384 and receive path 385 follow the same path (in the same direction) through phase shifter 370.

[0069] Figure 4A and Figure 4B yes Figure 3 A schematic diagram of an exemplary embodiment of the three-coil configuration. Figure 4A In the middle, three coils of 400 can be Figure 3 Examples of EM element 321 or EM element 361. In an exemplary embodiment, the three-coil 400 may include a first winding 402 coupled to a transmitting signal source (e.g., via VMDR 326 or 366), a second winding 403 coupled to an LNA (e.g., a second-stage LNA 317 or 357), and a third winding 404 coupled to a phase shifter input (e.g., a phase shifter 320 or 370). In an exemplary embodiment, the first winding 402 may correspond to the first inductor element 322 or 362 ( Figure 3 The second winding 403 can correspond to the second inductor element 323 or 363. Figure 3 ), and the third winding 404 can correspond to the third inductor element 324 or 364 ( Figure 3 ).

[0070] In an exemplary embodiment, the three-coil 400 further includes switches 412 and 414 located in the first winding 402. In an exemplary embodiment, switches 412 and 414 may correspond to... Figure 3 Switches 325 / 365 and 327 / 367 are included. Node 415 between switches 412 and 414 can be connected to the system voltage, VDD. In the exemplary embodiment, although the first winding 402, the second winding 403, and the third winding 404 are shown as single-turn coils with a generally rectangular shape, the first winding 402, the second winding 403, and the third winding 404 can be manufactured with different numbers of turns and can be different shapes, such as square, hexagonal, octagonal, or other shapes.

[0071] In an exemplary embodiment, switches 412 and 414 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, but in other embodiments, switches 412 and 414 may be N-type MOS (NMOS) switches or switches manufactured using other manufacturing techniques. In an exemplary embodiment, switches 412 and 414 may be controlled by control signals from data processor 210 or another controller. In an exemplary embodiment, switches 412 and 414 may be configured to selectively change the impedance of the first winding 402 when in transmit or receive mode. For example, in receive mode, switches 412 and 414 may be open, presenting a high impedance to the second stage LNA 317 (or 357) and HQG 340 (or 380). In transmit mode, switches 412 and 414 may be closed, allowing a transmit signal to be transmitted from the first winding 402 to the third winding 404.

[0072] In an exemplary embodiment, the location of switches 412 and 414 in the first winding 402 near node 415, which has a system voltage, VDD, can add little or no parasitic losses to the differential-mode signal. Positioning switches 412 and 414 near node 415 (e.g., closer to the center tap of the first winding 402 rather than the external terminals of the first winding 402 connected to VMDR 326 or 366) reduces or avoids any differential parasitic capacitance from switches 412 and 414 loading VMDR 326 in differential mode.

[0073] In an exemplary embodiment, VMDR 326 and VMDR 366 operate at sufficiently low currents to allow switches 412 and 414 to have moderate resistances, for example, one (1) ohm to two (2) ohms, without causing a drop in voltage margin that could negatively affect signal quality.

[0074] In an exemplary embodiment, when switches 412 and 414 are located near node 415, when in a non-conducting state, the switches parasitize through the inductive resonance of the first winding 402, which helps to maintain a relatively high turn-off impedance for switches 412 and 414.

[0075] In an exemplary embodiment, the second-stage LNA 317 has a very high turn-off impedance, which reduces or minimizes the load presented to the second-stage LNA 317 of the transmitter circuit in the first element 310.

[0076] In an exemplary embodiment, in RX mode, switches 412 and 414 are non-conductive, thus allowing the received signal to be easily transmitted from the second winding 403 to the third winding 404.

[0077] In an exemplary embodiment, in TX mode, LNA 316 and the second-stage LNA 317 are disconnected, and switches 412 and 414 are turned on to facilitate the transmission of the transmit signal from the first winding 402 to the third winding 404.

[0078] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of an exemplary embodiment of the three-coil configuration. Figure 5A In the middle, three coils of 500 can be Figure 3 Examples of EM element 328 or EM element 368. In an exemplary embodiment, the three-coil 500 may include a first winding 502 coupled to a phase shifter output (e.g., phase shifter 320 or 370), a second winding 503 coupled to a receiving network (e.g., connection 342 and other downstream circuitry), and a third winding 504 coupled to a PA (e.g., PA 318 or 358, e.g., via DA 319 or 359). In an exemplary embodiment, the first winding 502 may correspond to a first inductor element 332 or 372 ( Figure 3 The second winding 503 can correspond to the second inductor element 331 or 371. Figure 3 ), and the third winding 504 can correspond to the third inductor element 329 or 369 ( Figure 3 ).

[0079] In an exemplary embodiment, the three-coil 500 further includes switches 512 and 514 located in the third winding 504; and switches 522 and 524 located in the second winding 503. In an exemplary embodiment, switches 512 and 514 may correspond to... Figure 3Switches 333 / 373 and 335 / 375 are included, and switches 522 and 524 may correspond to switches 337 / 377 and 338 / 378. Node 515 between switches 512 and 514 may be connected to a bias voltage, Vbias. In the exemplary embodiment, although the first winding 502, the second winding 503, and the third winding 504 are shown as single-turn coils having a generally rectangular shape, the first winding 502, the second winding 503, and the third winding 504 may be manufactured with different numbers of turns and may be of different shapes, such as square, hexagonal, octagonal, or other shapes.

[0080] In an exemplary embodiment, switches 512 and 514 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, but in other embodiments, switches 512 and 514 may be N-type MOS (NMOS) switches or switches manufactured using other manufacturing techniques. Similarly, switches 522 and 524 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, but in other embodiments, switches 522 and 524 may be N-type MOS (NMOS) switches or switches manufactured using other manufacturing techniques. In an exemplary embodiment, switches 512, 514, 522, and 524 may be controlled by control signals from data processor 210 or another controller to selectively change the impedance of the second winding 503 and the third winding 504.

[0081] In an exemplary embodiment, as described above, the positions of switches 512 and 514 in the third winding 504 and switches 522 and 524 in the second winding 331 can add little or no parasitic losses or load to the differential-mode signal. In an exemplary embodiment, switch 522 is located near the lowest differential-mode voltage swing point and does not add capacitive parasitic losses to the second winding 503. Ideally, switch 524 can be much smaller than switch 522 (1 / 5 the size or less) to maintain the desired isolation between the first winding 502 and the second winding 503 in transmit mode while providing minimal load to the second winding 503.

[0082] In an exemplary embodiment, in the drive amplifier 319 ( Figure 3 There is no DC current on the gate of the NMOS switch 512, which causes the NMOS switches 512 and 514 to operate as level-shifting switches respectively. For example, in TX mode, switches 512 and 514 will have the same characteristics as the drive amplifier 319. Figure 3 The gate-source voltage of the amplifier is the same as the drain-source voltage. Therefore, the gate voltage VDD is applied to the drive amplifier 319 ( Figure 3 The gate-source voltage is used to turn on switches 512 and 514.

[0083] In an exemplary embodiment, in RX mode, switches 512 and 514 are de-conducting, switch 524 is de-conducting, and switch 522 is on, thereby allowing the received signal to be easily transmitted from the first winding 502 to the second winding 503. Switches 522 and 524 receive complementary control signals Rx_en and Rx_enb, such that they are controlled complementaryly.

[0084] In an exemplary embodiment, in TX mode, LNA 316 (or 356) and the second-stage LNA 317 (or 357) are disconnected, switches 512 and 514 are turned on, switch 524 is turned on, and switch 522 is turned off to facilitate the transmission of the transmit signal from the first winding 502 to the third winding 504. Switches 522 and 524 receive complementary control signals Rx_en and Rx_enb, such that they are controlled complementaryly.

[0085] Figure 6 This is a flowchart 600 illustrating an example of the operation of a method for processing signals. The blocks in method 600 may be executed in the order shown or not, and in some embodiments, they may be executed at least partially in parallel.

[0086] In block 602, a transmit signal (e.g., mmW) or a receive signal (e.g., mmW) is selectively applied to the phase shifter. For example, the EM element 321, which can be configured as a three-coil unit, can be configured to apply the transmit signal from VMDR 326 to HQG 340, or the EM element 321 can be configured to selectively apply the receive signal from the second-stage LNA 317 to HQG 340.

[0087] In block 604, the transmitted or received signal is phase-shifted by a shared phase shifter. For example, the transmitted or received signal may be phase-shifted by an HQG 340 and variable gain amplifiers (VGAs) 334 and 336.

[0088] In block 606, a phase-shifted transmit signal is selectively applied to a power amplifier, or a phase-shifted receive signal is selectively applied to the phased array output. For example, in transmit mode, the transmit signal may be applied to a drive amplifier 319 by an EM element 328 that can be configured as a three-coil, or the receive signal may be selectively applied to connection 342 by the EM element 328 for further processing.

[0089] Figure 7 This is a functional block diagram of a device 700 for processing signals. The device 1700 includes a unit 702 for selectively applying a transmitted signal or a received signal to a unit for phase shifting. In some embodiments, the unit 702 for selectively applying a transmitted signal or a received signal to a unit for phase shifting may be configured to perform method 600. Figure 6 The operation block 602 describes one or more functions. In an exemplary embodiment, unit 702 for selectively applying a transmit signal or a receive signal to the unit for phase shifting may include EM element 321, which may be configured as a three-coil unit.

[0090] The apparatus 700 may further include a shared unit 704 for phase shifting the transmitted or received signal. In some embodiments, the shared unit 704 for phase shifting the transmitted or received signal may be configured to perform in method 600. Figure 6 The shared unit 704 for phase shifting the transmitted or received signal may include one or more of the functions described in operation block 604. In an exemplary embodiment, the shared unit 704 for phase shifting the transmitted or received signal may include an HQG 340 and variable gain amplifiers (VGAs) 334 and 336.

[0091] The device 700 may further include a unit 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output. In some embodiments, the unit 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output may be configured to execute method 600 ( Figure 6 One or more of the functions described in operation block 606. In an exemplary embodiment, unit 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output may include EM element 312, which may be configured as a three-coil.

[0092] Examples of implementation methods are described in the following numbered clauses:

[0093] 1. A millimeter-wave (mmW) communication system located on a millimeter-wave integrated circuit (MMW-IC), comprising: a phase shifter selectively connected to a receiving path via a first electromagnetic (EM) element and selectively connected to a transmitting path via a second EM element; the first EM element being configured to receive a transmitting signal and to receive a receiving signal from a low-noise amplifier (LNA); the second EM element being configured to receive a phase-shifted transmitting signal or a phase-shifted receiving signal from the phase shifter; and wherein the second EM element is configured to selectively provide the phase-shifted transmitting signal to a power amplifier on the mmW-IC and to a receiving signal processing circuit located outside the mmW-IC.

[0094] 2. The communication system according to Clause 1, wherein the first EM element includes a first winding, a second winding and a third winding, and the first winding includes a switch configured to change the impedance of the first winding.

[0095] 3. The communication system according to Clause 1 or Clause 2, wherein the second EM element includes a first winding, a second winding and a third winding, the second winding including a switch configured to change the impedance of the second winding, and the third winding including a switch configured to change the impedance of the third winding.

[0096] 4. The communication system according to Clause 2, wherein, in the receiving mode, the switch in the first winding is configured to be non-conductive to present high impedance to the second winding and the third winding.

[0097] 5. The communication system according to Clause 2, wherein, in the transmission mode, the switch in the first winding is configured to be turned on, such that the transmission signal is transmitted from the first winding to the third winding.

[0098] 6. A communication system according to any one of clauses 2, 4 or 5, wherein the switch in the first winding is located near the center tap of the first winding to minimize parasitic losses to differential-mode signals.

[0099] 7. The communication system according to Clause 3, wherein, in the receiving mode, a first switch in the second winding is selectively turned on, a second switch in the second winding is selectively turned off, and the switch in the third winding is turned off, to allow a received signal to be transmitted from the first winding to the second winding.

[0100] 8. The communication system according to Clause 3, wherein, in the transmission mode, a first switch in the second winding is selectively turned on, a second switch in the second winding is selectively turned off, and the switch in the third winding is turned on to allow a transmission signal to be transmitted from the first winding to the third winding.

[0101] 9. A communication system according to any one of clauses 3, 7 or 8, wherein the switch in the third winding is located near the center tap of the third winding to minimize parasitic losses to differential-mode signals.

[0102] 10. A method for phase-shifting a signal, comprising: selectively applying a transmitted signal or a received signal to a shared phase shifter; phase-shifting the transmitted signal or the received signal; and selectively applying the phase-shifted transmitted signal to a power amplifier or selectively applying the phase-shifted received signal to a phased array output.

[0103] 11. The method according to Clause 10, wherein selectively applying the transmitted signal or the received signal to the shared phase shifter includes impedance matching.

[0104] 12. The method according to any one of clauses 10 to 11, wherein selectively applying the received signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to non-conducting, such that the received signal is transmitted from the second winding of the first EM element to the third winding of the first EM element.

[0105] 13. The method according to any one of clauses 10 to 12, wherein selectively applying the transmit signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to conduct, such that the transmit signal is transmitted from the first winding of the first EM element to the third winding of the first EM element.

[0106] 14. The method according to Clause 12, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

[0107] 15. The method according to Clause 10, wherein selectively applying the phase-shifted received signal to the phased array output comprises: selectively setting a complementary switch in the second winding of the second EM element to be on and off, and selectively setting a switch in the third winding of the second EM element to be off, such that the phase-shifted received signal is transmitted from the first winding of the second EM element to the second winding of the second EM element.

[0108] 16. The method according to Clause 15, wherein selectively applying the phase-shifted transmit signal to the power amplifier comprises selectively setting the complementary switch in the second winding of the second EM element to be on and off, and selectively setting the switch in the third winding of the second EM element to be on, such that the phase-shifted transmit signal is transmitted from the first winding of the second EM element to the third winding of the second EM element.

[0109] 17. The method according to any one of Clauses 15 to 16, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

[0110] 18. An apparatus for phase-shifting a signal, comprising: a unit for selectively applying a transmitted signal or a received signal to a shared phase shifter; a unit for phase-shifting the transmitted signal or the received signal; and a unit for selectively applying the phase-shifted transmitted signal to a power amplifier or selectively applying the phase-shifted received signal to a phased array output.

[0111] 19. The device according to Clause 18, wherein the unit for selectively applying the transmitted signal or the received signal to the shared phase shifter includes a unit for impedance matching.

[0112] 20. The device according to any one of clauses 18 to 19, wherein the unit for selectively applying the received signal to the shared phase shifter includes a unit for selectively setting a switch in the first winding of the first EM element to non-conducting, such that the received signal is transmitted from the second winding of the first EM element to the third winding of the first EM element.

[0113] 21. The device according to any one of clauses 18 to 20, wherein the unit for selectively applying the transmit signal to the shared phase shifter comprises: a unit for selectively setting a switch in a first winding of a first EM element to be turned on, such that the transmit signal is transmitted from the first winding of the first EM element to a third winding of the first EM element.

[0114] 22. The device according to Clause 20, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

[0115] 23. The device according to Clause 18, wherein the unit for selectively applying the phase-shifted received signal to the phased array output includes a unit for selectively setting a complementary switch in the second winding of the second EM element to be on and off and selectively setting a switch in the third winding of the second EM element to be off, such that the phase-shifted received signal is transmitted from the first winding of the second EM element to the second winding of the second EM element.

[0116] 24. The apparatus according to Clause 18, wherein the unit for selectively applying the phase-shifted transmit signal to the power amplifier comprises: a unit for selectively setting a complementary switch in a second winding of a second EM element to be on and off and selectively setting a switch in a third winding of the second EM element to be on, such that the phase-shifted transmit signal is transmitted from a first winding of the second EM element to the third winding of the second EM element.

[0117] 25. The device according to any one of clauses 23 to 24, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

[0118] 26. A phased array element, comprising: a receiving circuit; a transmitting circuit; a first electromagnetic (EM) element coupled to the receiving circuit; a second EM element coupled to the transmitting circuit; and a phase shifter coupled between the first EM element and the second EM element, wherein the phased array element is configured such that the phase shifter is shared by the receiving circuit and the transmitting circuit.

[0119] 27. The phased array element according to Clause 26, wherein the phased array element is configured such that the transmitted signal and the received signal follow the same path through the phase shifter.

[0120] 28. The phased array element according to any one of clauses 26 to 27, wherein the first EM element includes a first three-coil, and the second EM element includes a second three-coil.

[0121] 29. The phased array element according to Clause 28, wherein the first EM element is differentially coupled to a hybrid quadrature generator or a polyphase filter configured to provide quadrature signals to respective variable gain amplifiers, and each of the variable gain amplifiers is differentially coupled to the second EM element.

[0122] 30. The phased array element according to Clause 29, wherein the second EM element is configured to provide a single-ended received signal.

[0123] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0124] The means of implementing the circuit described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RFIC such as an RF receiver (RFR) or RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handheld device, or a mobile unit, (vii) and so on.

[0125] Although selected aspects have been shown and described in detail, it will be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A millimeter-wave (mmW) communication system located on a millimeter-wave integrated circuit (MMW-IC), comprising: A phase shifter, which is selectively connected to the receiving path via a first electromagnetic (EM) element and selectively connected to the transmitting path via a second EM element; The first EM element is configured to receive a transmitted signal and is configured to receive a received signal from a low-noise amplifier (LNA); The second EM element is configured to receive a phase-shifted transmitted signal or a phase-shifted received signal from the phase shifter; as well as The second EM element is configured to selectively provide a phase-shifted transmit signal to a power amplifier on the mmW-IC and a phase-shifted receive signal to a receive signal processing circuit located outside the mmW-IC.

2. The communication system according to claim 1, wherein, The first EM element includes a first winding, a second winding, and a third winding, and the first winding includes a switch configured to change the impedance of the first winding.

3. The communication system according to claim 1, wherein, The second EM element includes a first winding, a second winding, and a third winding, the second winding including a switch configured to change the impedance of the second winding, and the third winding including a switch configured to change the impedance of the third winding.

4. The communication system according to claim 2, wherein, In the receiving mode, the switch in the first winding is configured to be non-conductive to present high impedance to the second and third windings.

5. The communication system according to claim 2, wherein, In the transmission mode, the switch in the first winding is configured to be on, so that the transmission signal is transmitted from the first winding to the third winding.

6. The communication system according to claim 2, wherein, The switch in the first winding is located near the center tap of the first winding to minimize parasitic losses to differential signals.

7. The communication system according to claim 3, wherein, In the receiving mode, a first switch in the second winding is selectively turned on, a second switch in the second winding is selectively turned off, and the switch in the third winding is turned off, to allow the received signal to be transmitted from the first winding to the second winding.

8. The communication system according to claim 3, wherein, In the transmit mode, a first switch in the second winding is selectively turned on, a second switch in the second winding is selectively turned off, and the switch in the third winding is turned on to allow the transmit signal to be transmitted from the first winding to the third winding.

9. The communication system according to claim 3, wherein, The switch in the third winding is located near the center tap of the third winding to minimize parasitic losses on differential signals.

10. A method for phase-shifting a signal, comprising: Selectively apply the transmitted or received signal to the shared phase shifter; Phase shifting is applied to the transmitted signal or the received signal; as well as The phase-shifted transmit signal can be selectively applied to the power amplifier or the phase-shifted receive signal can be selectively applied to the phased array output.

11. The method according to claim 10, wherein, Selectively applying the transmitted signal or the received signal to the shared phase shifter includes impedance matching.

12. The method according to claim 10, wherein, Selectively applying the received signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to non-conducting, such that the received signal is transmitted from the second winding of the first EM element to the third winding of the first EM element.

13. The method according to claim 12, wherein, Selectively applying the transmit signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to be on, such that the transmit signal is transmitted from the first winding of the first EM element to the third winding of the first EM element.

14. The method according to claim 12, wherein, The switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

15. The method according to claim 10, wherein, Selectively applying the phase-shifted received signal to the phased array output includes: selectively setting a complementary switch in the second winding of the second EM element to be on and off, and selectively setting a switch in the third winding of the second EM element to be off, such that the phase-shifted received signal is transmitted from the first winding of the second EM element to the second winding of the second EM element.

16. The method according to claim 15, wherein, Selectively applying the phase-shifted transmit signal to the power amplifier includes: selectively setting the complementary switch in the second winding of the second EM element to be on and off, and selectively setting the switch in the third winding of the second EM element to be on, such that the phase-shifted transmit signal is transmitted from the first winding of the second EM element to the third winding of the second EM element.

17. The method according to claim 15, wherein, The switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

18. An apparatus for phase-shifting a signal, comprising: A unit used to selectively apply transmitted or received signals to a shared phase shifter; A unit for phase shifting the transmitted signal or the received signal; as well as A unit for selectively applying a phase-shifted transmit signal to a power amplifier or selectively applying a phase-shifted receive signal to the output of a phased array.

19. The device according to claim 18, wherein, The unit for selectively applying the transmitted signal or the received signal to the shared phase shifter includes a unit for impedance matching.

20. The device according to claim 18, wherein, The unit for selectively applying the received signal to the shared phase shifter includes a unit for selectively setting a switch in the first winding of the first EM element to be non-conductive, such that the received signal is transmitted from the second winding of the first EM element to the third winding of the first EM element.

21. The device according to claim 18, wherein, The unit for selectively applying the transmit signal to the shared phase shifter includes a unit for selectively setting a switch in the first winding of the first EM element to be turned on, such that the transmit signal is transmitted from the first winding of the first EM element to the third winding of the first EM element.

22. The device according to claim 20, wherein, The switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

23. The device according to claim 18, wherein, The unit for selectively applying the phase-shifted received signal to the phased array output includes a unit for selectively setting a complementary switch in the second winding of the second EM element to be on and off, and selectively setting a switch in the third winding of the second EM element to be off, such that the phase-shifted received signal is transmitted from the first winding of the second EM element to the second winding of the second EM element.

24. The device according to claim 18, wherein, The unit for selectively applying the phase-shifted transmit signal to the power amplifier includes a unit for selectively setting a complementary switch in the second winding of the second EM element to be on and off, and selectively setting a switch in the third winding of the second EM element to be on, such that the phase-shifted transmit signal is transmitted from the first winding of the second EM element to the third winding of the second EM element.

25. The device according to claim 23, wherein, The switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

26. A phased array element, comprising: Receiver circuit; Transmitting circuit; A first electromagnetic (EM) element coupled to the receiving circuit; A second EM element coupled to the transmitting circuit; as well as A phase shifter, coupled between the first EM element and the second EM element, The phased array element is configured such that the phase shifter is shared by the receiving circuit and the transmitting circuit.

27. The phased array element according to claim 26, wherein, The phased array elements are configured such that the transmitted signal and the received signal follow the same path through the phase shifter.

28. The phased array element according to claim 26, wherein, The first EM element includes a first three-coil, and the second EM element includes a second three-coil.

29. The phased array element according to claim 28, wherein, The first EM element is differentially coupled to a hybrid quadrature generator or a polyphase filter, which is configured to provide quadrature signals to respective variable gain amplifiers, and each of the variable gain amplifiers is differentially coupled to the second EM element.

30. The phased array element according to claim 29, wherein, The second EM element is configured to provide a single-ended receive signal.

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