On-chip clock generation circuit with adjustable frequency

Abstract

The invention discloses a frequency-adjustable on-chip clock generation circuit, and belongs to the technical field of integrated circuits. The clock generation circuit comprises a reference current generation module, a frequency auxiliary calibration module and a clock generation module. The reference current generation module is connected with the frequency auxiliary calibration module and the clock generation module. The reference current generation module generates reference current with low temperature drift, the frequency auxiliary calibration module is used for assisting off-chip equipment to carry out frequency calibration during middle measurement, and in the clock generation circuit, a clock signal is generated by utilizing charging and discharging of a capacitor. The on-chip clock generation circuit is simple in structure, small in temperature excursion, high in integration level, adjustable in frequency, low in power consumption and low in cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and relates to a frequency-calibratable on-chip clock generation circuit. BACKGROUND

[0002] Clock generation circuits are widely used in the field of integrated circuits, and with the rapid development of communication interfaces, sensor interface circuits and microcontrollers, people's demand for on-chip high-stability clock sources is increasing. Different application scenarios have different requirements for clock signals, and the main performance indicators of clock generation circuits include clock signal accuracy, temperature drift, jitter, power consumption and area, and there is a mutual influence and compromise relationship between each performance indicator. Therefore, designing a high-performance clock generation circuit has always been the goal of circuit designers.

[0003] Traditional clocks are generated by off-chip crystal oscillators, which cannot be integrated on-chip and have high costs. The present application provides an on-chip clock generation circuit, which generates a low-temperature-drift reference current and reference voltage through a bandgap reference, so that the temperature drift of the clock frequency is small. The frequency is calibrated through a frequency calibration circuit to realize accurate control of the frequency. The circuit is implemented on-chip, and the circuit structure is simple, so it occupies a small area and is easy to integrate. SUMMARY

[0004] In order to be suitable for high-precision, small-size and low-cost application scenarios, the present application provides a frequency-calibratable on-chip clock generation circuit, which comprises:

[0005] a reference current generation module, a frequency auxiliary calibration module and a clock generation module;

[0006] The reference current generation module is connected to the frequency auxiliary calibration module and the clock generation module. The reference current generation module is used to generate a low-temperature-drift reference current.

[0007] The frequency auxiliary calibration module is used to calibrate the frequency with the aid of an off-chip device. The calibration process includes current coarse adjustment and current fine adjustment. The current is adjusted successively to make it approach the calibration frequency, and a clock signal is generated through the charging and discharging of a capacitor in the clock generation module and outputted to the outside.

[0008] Preferably, the reference current generation module comprises:

[0009] The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are numbered as MP1, MP2, MP3, MP4, MP5 and MP6, respectively.

[0010] The first NMOS transistor, the second NMOS transistor and the third NMOS transistor are numbered as MN1, MN2 and MN3 respectively;

[0011] The first operational amplifier is numbered as OPA;

[0012] The first resistor, the second resistor and the third resistor are numbered as R1, R2 and R3 respectively;

[0013] The first PNP transistor and the second PNP transistor are numbered as Q1 and Q2 respectively;

[0014] The gate of the MP1 is connected to the gate of the MN1, and the connection node is numbered as N21;

[0015] The source of the MP1 is connected to the gate of the MP2 and the drain of the MP2, and the connection node is numbered as N2;

[0016] The drain of the MP1 is connected to the drain of the MN1 and the gate of the MN2, and the connection node is numbered as N1;

[0017] The source of the MP2 is connected to the power voltage, and the power voltage is numbered as VDD;

[0018] The source of the MN1 is connected to the ground voltage, and the ground voltage is numbered as GND;

[0019] The source of the MN2 is connected to the ground voltage GND;

[0020] The drain of the MN2 is connected to the source of the MN3, and the connection node is numbered as N3;

[0021] The gate of the MN3 is connected to the gate of the MP3, and the connection node is numbered as EN;

[0022] The drain of the MN3 is connected to the drain of the MP3, the gate of the MP4, the gate of the MP5 and the output of the OPA, and the connection node is numbered as N4;

[0023] The source of the MP3 is connected to the voltage VDD;

[0024] The source of the MP4 is connected to the voltage VDD;

[0025] The drain of the MP4 is connected to the first end of the resistor R1, the negative input of the OPA and the emitter of the Q1, and the connection node is numbered as N5;

[0026] The source of the MP5 is connected to the voltage VDD;

[0027] The drain of the MP5 is connected to the first end of the resistor R2, the positive input of the OPA and the first end of the resistor R3, and the connection node is numbered as N6.

[0028] 10. The frequency-calibratable on-chip clock generation circuit according to claim 2, wherein,

[0029] Q1 base connects voltage GND;

[0030] Q1 collector connects voltage GND;

[0031] Q2 base connects voltage GND;

[0032] Q2 collector connects voltage GND;

[0033] Q2 emitter connects R2 second end;

[0034] R1 second end connects voltage GND;

[0035] R3 second end connects voltage GND.

[0036] Preferably, the frequency auxiliary calibration module comprises:

[0037] The sixth PMOS tube, the seventh PMOS tube and the eighth PMOS tube are numbered as MP6, MP7 and MP8 respectively;

[0038] The fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the twenty-sixth NMOS tube, the twenty-seventh NMOS tube, the twenty-eighth NMOS tube, the twenty-ninth NMOS tube, the thirtieth NMOS tube, the thirty-first NMOS tube, the thirty-second NMOS tube and the thirty-third NMOS tube are numbered as MN4-MN33 respectively;

[0039] The first SAR LOGIC module is numbered as SR1;

[0040] The second SAR LOGIC module is numbered as SR2.

[0041] Preferably, the MP6 gate connects the node N4;

[0042] The MP6 source connects the voltage VDD;

[0043] The MP6 drain connects the MN4 drain, the MN4 gate, the MN5 gate, the MN6 gate, the MN7 gate, the MN8 gate, the MN9 gate, the MN10 gate and the MN11 gate, and the connection node is numbered as N8;

[0044] The MN4 source connects the voltage GND;

[0045] MN5 source connects voltage GND;

[0046] MN5 drain connects MN12 source;

[0047] MN6 source connects voltage GND;

[0048] MN6 drain connects MN13 source;

[0049] MN7 source connects voltage GND;

[0050] MN7 drain connects MN14 source;

[0051] MN8 source connects voltage GND;

[0052] MN8 drain connects MN15 source;

[0053] MN9 source connects voltage GND;

[0054] MN9 drain connects MN16 source;

[0055] MN10 source connects voltage GND;

[0056] MN10 drain connects MN17 source;

[0057] MN11 source connects voltage GND;

[0058] MN11 drain connects MN18 source.

[0059] Preferably, MN12 gate connects SR1 first output, the connection node is numbered: SC<0>;

[0060] MN13 gate connects SR1 second output, the connection node is numbered: SC<1>;

[0061] MN14 gate connects SR1 third output, the connection node is numbered: SC<2>;

[0062] MN15 gate connects SR1 fourth output, the connection node is numbered: SC<3>;

[0063] MN16 gate connects SR1 fifth output, the connection node is numbered: SC<4>;

[0064] MN17 gate connects SR1 sixth output, the connection node is numbered: SC<5>;

[0065] MN18 gate connects SR1 seventh output, the connection node is numbered: SC<6>;

[0066] The MN12 drain connects the MN13 drain, the MN14 drain, the MN15 drain, the MN16 drain, the MN17 drain, the MN18 drain, the MN27 drain, the MN28 drain, the MN29 drain, the MN30 drain, the MN31 drain, the MN32 drain, the MN33 drain, the MP8 gate and the MP8 drain, and the connection node is numbered as N10;

[0067] The MP7 drain connects the MN19 drain, the MN19 gate, the MN20 gate, the MN21 gate, the MN22 gate, the MN23 gate, the MN24 gate, the MN25 gate and the MN26 gate, and the connection node is numbered as N9;

[0068] The MN19 source connects the voltage GND;

[0069] The MN20 source connects the voltage GND;

[0070] The MN20 drain connects the MN27 source;

[0071] The MN21 source connects the voltage GND;

[0072] The MN21 drain connects the MN28 source;

[0073] The MN22 source connects the voltage GND;

[0074] The MN22 drain connects the MN29 source;

[0075] The MN23 source connects the voltage GND;

[0076] The MN23 drain connects the MN30 source;

[0077] The MN24 source connects the voltage GND;

[0078] The MN24 drain connects the MN31 source;

[0079] The MN25 source connects the voltage GND;

[0080] The MN25 drain connects the MN32 source;

[0081] The MN26 source connects the voltage GND;

[0082] The MN26 drain connects the MN33 source;

[0083] The MN27 gate connects the SR2 first output, and the connection node is numbered as SF<0>;

[0084] The MN28 gate connects the SR2 second output, and the connection node is numbered as SF<1>;

[0085] MN29 is connected with the third output terminal of SR2, and the connection node is numbered as SF<2>;

[0086] MN30 is connected with the fourth output terminal of SR2, and the connection node is numbered as SF<3>;

[0087] MN31 is connected with the fifth output terminal of SR2, and the connection node is numbered as SF<4>;

[0088] MN32 is connected with the sixth output terminal of SR2, and the connection node is numbered as SF<5>;

[0089] MN33 is connected with the seventh output terminal of SR2, and the connection node is numbered as SF<6>;

[0090] The first input terminal of SR1 is connected with control voltage CTL1;

[0091] The second input terminal of SR1 is connected with control voltage CK1;

[0092] The second input terminal of SR1 is connected with control voltage RST1;

[0093] The first input terminal of SR2 is connected with control voltage CTL2;

[0094] The second input terminal of SR2 is connected with control voltage CK2;

[0095] The second input terminal of SR2 is connected with control voltage RST2.

[0096] Preferably, the clock generation module comprises:

[0097] The ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube and the nineteenth PMOS tube are numbered as MP9-MP19 respectively;

[0098] The thirty-fourth NMOS tube, the thirty-fifth NMOS tube, the thirty-sixth NMOS tube, the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, the thirty-ninth NMOS tube, the fortieth NMOS tube, the forty-first NMOS tube and the forty-second NMOS tube are numbered as MP34-42 respectively;

[0099] The first capacitor is numbered as C1;

[0100] The fourth resistor and the fifth resistor are numbered as R4 and R5 respectively;

[0101] The first inverter, the second inverter, the third inverter, the fourth inverter, and the fifth inverter are numbered INV1, INV2, INV3, INV4, and INV5, respectively.

[0102] Preferably, the MP9 gate is connected to node N10;

[0103] MP9 source connection voltage VDD;

[0104] The drain of MP9 is connected to the source of MP10, the source of MP11, the drain of MN36, and the drain of MN37. This connection node is numbered N11.

[0105] The gate of MN36 is connected to the gate of MP11 and the output terminal of INV3. The connection node is numbered N12.

[0106] The source of MN36 is connected to the drain of MP10, the drain of MN34, the gate of MN34, and the gate of MN35. This connection node is numbered N14.

[0107] The MP10 gate connects to the MN37 gate and the INV2 output terminal. This connection node is numbered N13.

[0108] The drain of MP11 is connected to the source of MN37, the drain of MN35, the gate of MP13, and the first terminal of capacitor C1. This connection node is numbered N15.

[0109] MN34 source connection voltage GND;

[0110] MN35 source connection voltage GND;

[0111] MP12 source connection voltage VDD;

[0112] MP12 gate connection node N4;

[0113] The drain of MP12 is connected to the source of MP13, the source of MP14, and the source of MP15. This connection node is numbered N18.

[0114] MP13 drain is connected to MN38 drain, MN38 gate and MN40 gate, and the connection node is numbered N16;

[0115] The gate of MP14 is connected to the drain of MP16 and the first terminal of resistor R4;

[0116] The drain of MP14 is connected to the drain of MP15, the drain of MN39, the gate of MN39, and the gate of MN41. This connection node is numbered...

[0117] The serial number is: N17;

[0118] The gate of MP15 is connected to the source of MN42 and the drain of MP17. This connection node is numbered N21.

[0119] MP16 source terminal is connected with voltage VDD;

[0120] MP16 gate terminal is connected with node N4;

[0121] MP17 source terminal is connected with voltage VDD;

[0122] MP17 gate terminal is connected with node N4;

[0123] MN42 gate terminal is connected with INV1 output terminal, and the connection node is numbered as N24;

[0124] MN42 source terminal is connected with resistor R5 first terminal, and the connection node is numbered as N20;

[0125] Resistor R4 second terminal is connected with voltage GND;

[0126] Resistor R5 second terminal is connected with voltage GND;

[0127] MN40 source terminal is connected with voltage GND;

[0128] MN40 drain terminal is connected with MP18 drain terminal, MP18 gate terminal and MP19 gate terminal, and the connection node is numbered as N22;

[0129] MP18 source terminal is connected with voltage VDD;

[0130] MP19 source terminal is connected with voltage VDD;

[0131] MP19 drain terminal is connected with MN41 drain terminal and INV1 input terminal, and the connection node is numbered as N23;

[0132] MN41 source terminal is connected with voltage GND;

[0133] INV4 input terminal is connected with INV3 output terminal;

[0134] INV5 input terminal is connected with INV4 output terminal;

[0135] INV5 output terminal is clock signal output terminal.

[0136] Technical effects

[0137] The application provides a frequency-calibratable on-chip clock generation circuit, which comprises a reference current generation module, a frequency auxiliary calibration module and a clock generation module.

[0138] The clock signal generated by the chip is detected in frequency by the off-chip frequency detection module, and the detection result is sent into the successive approximation logic circuit, and the current is adjusted by the switch tubes MN12-MN18 and MN27-MN33 controlled by the successive approximation logic circuit, so that the clock frequency is changed. MN12-MN18 is a current coarse adjustment control switch, and MN27-MN33 is a current fine adjustment control switch. First, the current is coarsely adjusted by the successive approximation logic circuit 1, and then the current is finely adjusted by the successive approximation logic circuit 2, so that the effect of successive approximation calibration frequency is achieved. The on-chip clock generation circuit in the application has the advantages of simple structure, small temperature drift, high integration, frequency calibratable, low power consumption and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0139] Figure 1 The specific implementation circuit of the frequency calibratable on-chip clock generation circuit of the application;

[0140] Figure 2 The working principle diagram of the reference current generation module in the frequency calibratable on-chip clock generation circuit of the application;

[0141] Figure 3 The current simulation result of the reference current generation module in the frequency calibratable on-chip clock generation circuit of the application;

[0142] Figure 4 The voltage simulation result of the reference current generation module in the frequency calibratable on-chip clock generation circuit of the application;

[0143] Figure 5 The working principle diagram of the frequency auxiliary calibration module in the frequency calibratable on-chip clock generation circuit of the application;

[0144] Figure 6 The working principle diagram of the successive approximation logic circuit in the frequency calibratable on-chip clock generation circuit of the application;

[0145] Figure 7 The working principle diagram of the clock generation module in the frequency calibratable on-chip clock generation circuit of the application;

[0146] Figure 8 The simulation result diagram of the frequency calibratable on-chip clock generation circuit of the application. DETAILED DESCRIPTION

[0147] In order for the professional technical personnel to more comprehensively understand the application, the application provides an implementable example, which will be further described in combination with the drawings.

[0148] As Figure 1As shown, the frequency-calibratable on-chip clock generation circuit comprises a reference current generation module, a frequency auxiliary calibration module and a clock generation module.

[0149] The reference current generation module is connected to the frequency auxiliary calibration module and the clock generation module, and is configured to generate a low-temperature-drift reference current.

[0150] The frequency auxiliary calibration module is configured to perform frequency calibration with the aid of an auxiliary off-chip device; the calibration process comprises current coarse adjustment and current fine adjustment; the current is adjusted successively to approach the calibration frequency, and a clock signal is generated through charging and discharging of a capacitor in the clock generation module and outputted to the outside.

[0151] In this embodiment, as shown in the figure, Figure 1 The reference current generation module comprises:

[0152] The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are numbered as MP1, MP2, MP3, MP4, MP5 and MP6 respectively.

[0153] The first NMOS transistor, the second NMOS transistor and the third NMOS transistor are numbered as MN1, MN2 and MN3 respectively.

[0154] The first operational amplifier is numbered as OPA.

[0155] The first resistor, the second resistor and the third resistor are numbered as R1, R2 and R3 respectively.

[0156] The first PNP transistor and the second PNP transistor are numbered as Q1 and Q2 respectively.

[0157] The gate of the MP1 is connected to the gate of the MN1, and the connection node is numbered as N21.

[0158] The source of the MP1 is connected to the gate and the drain of the MP2, and the connection node is numbered as N2.

[0159] The drain of the MP1 is connected to the drain of the MN1 and the gate of the MN2, and the connection node is numbered as N1.

[0160] The source of the MP2 is connected to a power supply voltage, which is numbered as VDD.

[0161] The source of the MN1 is connected to a ground voltage, which is numbered as GND.

[0162] The source of the MN2 is connected to the voltage GND.

[0163] The drain of the MN2 is connected to the source of the MN3, and the connection node is numbered as N3.

[0164] MN3 connects with the gate of MP3, and the connection node is numbered as EN;

[0165] MN3 connects with the drain of MP3, the gate of MP4, the gate of MP5 and the output of OPA, and the connection node is numbered as N4;

[0166] The source of MP3 connects with the voltage VDD;

[0167] The source of MP4 connects with the voltage VDD;

[0168] The drain of MP4 connects with the first end of resistor R1, the negative input of OPA and the emitter of Q1, and the connection node is numbered as N5;

[0169] The source of MP5 connects with the voltage VDD;

[0170] The drain of MP5 connects with the first end of resistor R2, the positive input of OPA and the first end of R3, and the connection node is numbered as N6;

[0171] The base of Q1 connects with the voltage GND;

[0172] The collector of Q1 connects with the voltage GND;

[0173] The base of Q2 connects with the voltage GND;

[0174] The collector of Q2 connects with the voltage GND;

[0175] The emitter of Q2 connects with the second end of R2;

[0176] The second end of R1 connects with the voltage GND;

[0177] The second end of R3 connects with the voltage GND.

[0178] As shown in Figure 1 , the frequency auxiliary calibration module comprises:

[0179] a sixth PMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor, numbered as MP6, MP7 and MP8 respectively;

[0180] Fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh NMOS transistor, eighth NMOS transistor, ninth NMOS transistor, tenth NMOS transistor, eleventh NMOS transistor, twelfth NMOS transistor, thirteenth NMOS transistor, fourteenth NMOS transistor, fifteenth NMOS transistor, sixteenth NMOS transistor, seventeenth NMOS transistor, eighteenth NMOS transistor, nineteenth NMOS transistor, twentieth NMOS transistor, twenty-first NMOS transistor, twenty-second NMOS transistor, twenty-third NMOS transistor, twenty-fourth NMOS transistor, twenty-fifth NMOS transistor, twenty-sixth NMOS transistor, twenty-seventh NMOS transistor, twenty-eighth NMOS transistor, twenty-ninth NMOS transistor, thirtieth NMOS transistor, thirty-first NMOS transistor, thirty-second NMOS transistor and thirty-third NMOS transistor, numbered MN4-MN33 respectively;

[0181] First SAR LOGIC module, numbered SR1;

[0182] Second SAR LOGIC module, numbered SR2.

[0183] MP6 gate connection node N4;

[0184] MP6 source connection voltage VDD;

[0185] MP6 drain connection MN4 drain, MN4 gate, MN5 gate, MN6 gate, MN7 gate, MN8 gate, MN9 gate, MN10 gate and MN11 gate, the connection node is numbered N8;

[0186] MN4 source connection voltage GND;

[0187] MN5 source connection voltage GND;

[0188] MN5 drain connection MN12 source;

[0189] MN6 source connection voltage GND;

[0190] MN6 drain connection MN13 source;

[0191] MN7 source connection voltage GND;

[0192] MN7 drain connection MN14 source;

[0193] MN8 source connection voltage GND;

[0194] MN8 drain connection MN15 source;

[0195] MN9 source connection voltage GND;

[0196] MN9 drain connection MN16 source;

[0197] MN10 source connected to voltage GND;

[0198] MN10 drain connected to MN17 source;

[0199] MN11 source connected to voltage GND;

[0200] MN11 drain connected to MN18 source;

[0201] MN12 gate connected to SR1 first output, the connection node is numbered as: SC<0>;

[0202] MN13 gate connected to SR1 second output, the connection node is numbered as: SC<1>;

[0203] MN14 gate connected to SR1 third output, the connection node is numbered as: SC<2>;

[0204] MN15 gate connected to SR1 fourth output, the connection node is numbered as: SC<3>;

[0205] MN16 gate connected to SR1 fifth output, the connection node is numbered as: SC<4>;

[0206] MN17 gate connected to SR1 sixth output, the connection node is numbered as: SC<5>;

[0207] MN18 gate connected to SR1 seventh output, the connection node is numbered as: SC<6>;

[0208] MN12 drain connected to MN13 drain, MN14 drain, MN15 drain, MN16 drain, MN17 drain, MN18 drain, MN27 drain, MN28 drain, MN29 drain, MN30 drain, MN31 drain, MN32 drain, MN33 drain, MP8 gate and MP8 drain, the connection node is numbered as: N10;

[0209] MP7 drain connected to MN19 drain, MN19 gate, MN20 gate, MN21 gate, MN22 gate, MN23 gate, MN24 gate, MN25 gate and MN26 gate, the connection node is numbered as: N9;

[0210] MN19 source connected to voltage GND;

[0211] MN20 source connected to voltage GND;

[0212] MN20 drain connected to MN27 source;

[0213] MN21 source connected to voltage GND;

[0214] MN21 drain connected to MN28 source;

[0215] MN22 source connected to voltage GND;

[0216] MN22 drain connected to MN29 source;

[0217] MN23 source connected to voltage GND;

[0218] MN23 drain connected to MN30 source;

[0219] MN24 source connected to voltage GND;

[0220] MN24 drain connected to MN31 source;

[0221] MN25 source connected to voltage GND;

[0222] MN25 drain connected to MN32 source;

[0223] MN26 source connected to voltage GND;

[0224] MN26 drain connected to MN33 source;

[0225] MN27 gate connected to SR2 first output, the connection node is numbered: SF<0>;

[0226] MN28 gate connected to SR2 second output, the connection node is numbered: SF<1>;

[0227] MN29 gate connected to SR2 third output, the connection node is numbered: SF<2>;

[0228] MN30 gate connected to SR2 fourth output, the connection node is numbered: SF<3>;

[0229] MN31 gate connected to SR2 fifth output, the connection node is numbered: SF<4>;

[0230] MN32 gate connected to SR2 sixth output, the connection node is numbered: SF<5>;

[0231] MN33 gate connected to SR2 seventh output, the connection node is numbered: SF<6>;

[0232] SR1 first input connected to control voltage CTL1;

[0233] SR1 second input connected to control voltage CK1;

[0234] SR1 second input connected to control voltage RST1;

[0235] The first input end of the SR2 is connected with a control voltage CTL2.

[0236] The second input end of the SR2 is connected with a control voltage CK2.

[0237] The second input end of the SR2 is connected with a control voltage RST2.

[0238] As shown in Figure 1 The clock generation module comprises:

[0239] The ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube and the nineteenth PMOS tube are numbered as MP9-MP19 respectively.

[0240] The thirty-fourth NMOS tube, the thirty-fifth NMOS tube, the thirty-sixth NMOS tube, the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, the thirty-ninth NMOS tube, the fortieth NMOS tube, the forty-first NMOS tube and the forty-second NMOS tube are numbered as MP34-42 respectively.

[0241] The first capacitor is numbered as C1.

[0242] The fourth resistor and the fifth resistor are numbered as R4 and R5 respectively.

[0243] The first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are numbered as INV1, INV2, INV3, INV4 and INV5 respectively.

[0244] The gate of the MP9 is connected with a node N10.

[0245] The source of the MP9 is connected with a voltage VDD.

[0246] The drain of the MP9 is connected with the source of the MP10, the source of the MP11, the drain of the MN36 and the drain of the MN37, and the connection node is numbered as N11.

[0247] The gate of the MN36 is connected with the gate of the MP11 and the output end of the INV3, and the connection node is numbered as N12.

[0248] The source of the MN36 is connected with the drain of the MP10, the drain of the MN34, the gate of the MN34 and the gate of the MN35, and the connection node is numbered as N14.

[0249] The gate of the MP10 is connected with the gate of the MN37 and the output end of the INV2, and the connection node is numbered as N13.

[0250] MP11 drain connects MN37 source, MN35 drain, MP13 gate and capacitor C1 first end, the connection node number is: N15;

[0251] MN34 source connects voltage GND;

[0252] MN35 source connects voltage GND;

[0253] MP12 source connects voltage VDD;

[0254] MP12 gate connects node N4;

[0255] MP12 drain connects MP13 source, MP14 source and MP15 source, the connection node number is: N18;

[0256] MP13 drain connects MN38 drain, MN38 gate and MN40 gate, the connection node number is: N16;

[0257] MP14 gate connects MP16 drain, resistance R4 first end;

[0258] MP14 drain connects MP15 drain, MN39 drain, MN39 gate and MN41 gate, the connection node number is: N17;

[0259] MP15 gate connects MN42 source and MP17 drain, the connection node number is: N21;

[0260] MP16 source connects voltage VDD;

[0261] MP16 gate connects node N4;

[0262] MP17 source connects voltage VDD;

[0263] MP17 gate connects node N4;

[0264] MN42 gate connects INV1 output, the connection node number is: N24;

[0265] MN42 source connects resistance R5 first end, the connection node number is: N20;

[0266] Resistance R4 second end connects voltage GND;

[0267] Resistance R5 second end connects voltage GND;

[0268] MN40 source connects voltage GND;

[0269] MN40 drain connects MP18 drain, MP18 gate and MP19 gate, the connection node number is: N22;

[0270] MP18 source connects voltage VDD;

[0271] MP19 source connects voltage VDD;

[0272] MP19 drain connects MN41 drain and INV1 input, the connection node is numbered as: N23;

[0273] MN41 source connects voltage GND;

[0274] INV4 input connects INV3 output;

[0275] INV5 input connects INV4 output;

[0276] INV5 output is clock signal output end.

[0277] As shown in Figure 2 , the working principle of the reference current generating module in the frequency-calibratable on-chip clock generating circuit is:

[0278] Due to the action of the operational amplifier OPA, V N5 = VN6 = V BE1 , the current flowing through R2 is (V BE1 -V BE2 ) / R2, and the current flowing through the resistor R3 is V BE1 / R3, so the current flowing through MP5 is (V BE1 -V BE2 ) / R2 + V BE1 / R3 = VT*lnn / R2 + V BE1 / R3, and the current IBG is B*(VT*lnn / R2 + V BE1 / R3), which is a low-temperature-drift reference current, wherein B is the current ratio of the current mirror MP5 and MP6, and the current flowing through the resistor can generate a low-temperature-drift reference voltage. The left part is a starting circuit, when the circuit is not started, EN is low, the voltage at N4 node is high, the voltage at N19 node is low, the voltage at N1 node is high, and MN2 is turned on; when EN changes from low to high, MN3 is turned on, the voltage at N4 node is low, and the PMOS connected with N4 is turned on, the current flows into the circuit, the circuit is started, after the circuit is started, the voltage at N19 node becomes high, the voltage at N1 node becomes low, and MN2 is turned off.

[0279] As shown in Figure 3 and Figure 4 , the simulation results of the reference current and the reference voltage of the reference current generating module in the frequency-calibratable on-chip clock generating circuit are shown, and it can be seen from the simulation results that the reference current changes very little with temperature, and the temperature coefficient of the reference voltage is only 3.4ppm / ℃.

[0280] As Figure 5 shown, the frequency auxiliary calibration principle diagram of the on-chip clock generation circuit with calibratable frequency of the application, the working principle is:

[0281] The clock signal generated by the chip is detected by the off-chip frequency detection module, and the detection result is sent into the successive approximation logic circuit, which controls the switch tubes MN12-MN18 and MN27-MN33 to adjust the current, so as to change the clock frequency. Among them, MN12-MN18 is a current coarse control switch, and MN27-MN33 is a current fine control switch. First, the current is coarsely adjusted by using the successive approximation logic circuit 1, and then the current is finely adjusted by using the successive approximation logic circuit 2, so as to achieve the effect of successive approximation calibration frequency.

[0282] As Figure 6 shown, the frequency auxiliary calibration principle diagram of the on-chip clock generation circuit with calibratable frequency of the application, the working principle is:

[0283] At initialization, all D flip-flops are set to 0, and when the RST pulse arrives, Q7 and SC<6> are set to 1. In the shift logic module, with the arrival of the CK rising edge, Q7 changes from 1 to 0, and Q6 changes from 0 to 1, and so on, realizing the shift operation of high level. In the data register module, the output of the next D flip-flop is used as the clock input of the previous D flip-flop, and when the CK rising edge arrives, since Q7 is 0 and Q6 is 1, SC<5> changes from 0 to 1, forming a rising edge, and at this time SC<6> changes from 1 to the value of the off-chip control signal CTL, that is, when the next D flip-flop changes from 0 to 1, the previous D flip-flop is triggered, and the output changes from 1 to the value of the off-chip control signal CTL.

[0284] As Figure 7 shown, the working principle diagram of the clock generation module in the on-chip clock generation circuit with calibratable frequency of the application, the working principle is:

[0285] Suppose V N15 =GND, after comparison by the comparator, V N23 =VDD, V N24 =GND, V N13 =VDD, V N12 =GND, then MN42 is closed, MN36 and MP10 are closed, MN37 and MP11 are opened, and the capacitor C1 is in charging mode, V N15 gradually rises, when V N15 >V N19 , V N23 =GND, V N24 =VDD, V N13 =GND, V N12=VDD, MN42 opens, MN36 and MP10 open, MN37 and MP11 close, capacitor C1 is in discharging mode, V N15 decreases gradually, wherein MP13, MP14 and MP15 are completely same in size, MN40 and MN41 are completely same, MP18 and MP19 are completely same, when V N15 <V N19 +V N21 -V N18 , V N23 =VDD, V N24 =GND, V N13 =VDD, V N12 =GND, MN42 closes, MN36 and MP10 close, MN37 and MP11 open, capacitor C1 is in charging mode, so V N15 upper threshold value is V N19 , V N15 lower threshold value is V N19 +V N21 -V N18 , charging current value and discharging current value are both I C =k*IBG, the capacitance value of capacitor C1 is C c , charging time and discharging time are both:

[0286]

[0287] clock period is:

[0288]

[0289] clock frequency is:

[0290]

[0291] current I C is a low-temperature coefficient reference current, V N21 is a low-temperature coefficient reference voltage, so the clock signal changes very little with temperature, and the charging and discharging current of the capacitor is controlled through the frequency auxiliary calibration module, that is, the variable clock frequency is accurately controlled.

[0292] As Figure 8 described above, the simulation result graph of the frequency-calibratable on-chip clock generation circuit is as follows:

[0293] The frequency-calibratable on-chip clock generation circuit is realized by using 180nm CMOS process, and the power supply voltage is 3V, and the simulation result is completely consistent with the principle description.

Claims

1. A frequency-calibratable on-chip clock generation circuit, characterized by comprising: include: Reference current generation module, frequency auxiliary calibration module, and clock generation module; The reference current generation module is connected to the frequency auxiliary calibration module and the clock generation module; the reference current generation module is used to generate a reference current with low temperature drift. The frequency auxiliary calibration module is used to perform frequency calibration on an auxiliary external device; the calibration process includes coarse current adjustment and fine current adjustment; the current is adjusted successively to approach the calibration frequency, and a clock signal is generated by charging and discharging the capacitor in the clock generation module and output to the outside.

2. The frequency calibratable on-chip clock generation circuit according to claim 1, wherein, The reference current generation module includes: The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are numbered MP1, MP2, MP3, MP4, MP5, and MP6, respectively. The first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are numbered MN1, MN2, and MN3, respectively. The first operational amplifier is designated OPA; The first resistor, the second resistor, and the third resistor are numbered R1, R2, and R3, respectively. The first PNP transistor and the second PNP transistor are numbered Q1 and Q2, respectively.

3. The frequency-calibrable on-chip clock generation circuit according to claim 2, characterized in that, The MP1 gate is connected to the MN1 gate, and the connection node is numbered N21. The source of MP1 is connected to the gate and drain of MP2. This connection node is numbered N2. The drain of MP1 is connected to the drain of MN1 and the gate of MN2. This connection node is numbered N1. MP2 source is connected to a power supply voltage, which is designated as VDD. The source of MN1 is connected to ground voltage, which is designated as GND. MN2 source connection voltage GND; The drain of MN2 is connected to the source of MN3, and the connection node is numbered N3. The gate of MN3 is connected to the gate of MP3, and the connection node is numbered EN. The drain of MN3 is connected to the drain of MP3, the gate of MP4, the gate of MP5, and the output terminal of OPA. The connection node number is: N4； MP3 source connection voltage VDD; MP4 source connection voltage VDD; The drain of MP4 is connected to the first terminal of resistor R1, the negative input terminal of OPA, and the emitter of Q1. This connection node is numbered N5. MP5 source connection voltage VDD; The drain of MP5 is connected to the first terminal of resistor R2, the positive input terminal of OPA, and the first terminal of R3. This connection node is numbered as follows: N6。 4. The frequency-calibrable on-chip clock generation circuit according to claim 2, characterized in that, Q1 base connection voltage GND; Q1 collector connection voltage GND; Q2 base connection voltage GND; Q2 collector connection voltage GND; The emitter of Q2 is connected to the second terminal of R2; The second terminal of R1 is connected to voltage GND; The second terminal of R3 is connected to the voltage GND.

5. The frequency-calibrable on-chip clock generation circuit according to claim 1, characterized in that, The frequency-assisted calibration module includes: The sixth, seventh, and eighth PMOS transistors are numbered MP6, MP7, and MP8, respectively. The fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, twenty-ninth, thirtieth, thirty-first, thirty-second, and thirty-third NMOS transistors are numbered MN4-MN33 respectively. The first SAR LOGIC module is numbered SR1; The second SAR LOGIC module is numbered SR2.

6. The frequency-calibrable on-chip clock generation circuit according to claim 5, characterized in that, MP6 gate connection node N4; MP6 source connection voltage VDD; MP6 drain is connected to MN4 drain, MN4 gate, MN5 gate, MN6 gate, MN7 gate, MN8 gate. Gates MN9, MN10, and MN11, the connection node is numbered N8; MN4 source connection voltage GND; MN5 source connection voltage GND; The drain of MN5 is connected to the source of MN12; MN6 source connection voltage GND; The drain of MN6 is connected to the source of MN13; MN7 source connection voltage GND; The drain of MN7 is connected to the source of MN14; MN8 source connection voltage GND; The drain of MN8 is connected to the source of MN15; MN9 source connection voltage GND; The drain of MN9 is connected to the source of MN16; MN10 source connection voltage GND; The drain of MN10 is connected to the source of MN17; MN11 source connection voltage GND; The drain of MN11 is connected to the source of MN18.

7. The frequency-calibrable on-chip clock generation circuit according to claim 6, characterized in that, The gate of MN12 is connected to the first output terminal of SR1. The connection node is numbered SC. <0> ; The gate of MN13 is connected to the second output terminal of SR1. The connection node is numbered SC. <1> ; The gate of MN14 is connected to the third output terminal of SR1. The connection node is numbered SC. <2> ; The gate of MN15 is connected to the fourth output terminal of SR1. The connection node is numbered SC. <3> ; The gate of MN16 is connected to the fifth output terminal of SR1. The connection node is numbered SC. <4> ; The gate of MN17 is connected to the sixth output terminal of SR1. The connection node number is: SC. <5> ; The gate of MN18 is connected to the seventh output terminal of SR1. The connection node number is: SC. <6> ; The drain of MN12 is connected to the drains of MN13, MN14, MN15, MN16, MN17, MN18, MN27, MN28, MN29, MN30, MN31, MN32, MN33, the gate of MP8, and the drain of MP8. This connection node is numbered N10. MP7 drain is connected to MN19 drain, MN19 gate, MN20 gate, MN21 gate, MN22 gate, MN23 gate, MN24 gate, MN25 gate and MN26 gate. This connection node is numbered N9. MN19 source connection voltage GND; MN20 source connection voltage GND; The drain of MN20 is connected to the source of MN27; MN21 source connection voltage GND; The drain of MN21 is connected to the source of MN28; MN22 source connection voltage GND; The drain of MN22 is connected to the source of MN29; MN23 source connection voltage GND; The drain of MN23 is connected to the source of MN30; MN24 source connection voltage GND; The drain of MN24 is connected to the source of MN31; MN25 source connection voltage GND; The drain of MN25 is connected to the source of MN32; MN26 source connection voltage GND; The drain of MN26 is connected to the source of MN33; The gate of MN27 is connected to the first output terminal of SR2. The connection node number is: SF. <0> ; The gate of MN28 is connected to the second output terminal of SR2. The connection node number is: SF. <1> ; The gate of MN29 is connected to the third output terminal of SR2. The connection node number is: SF. <2> ; The gate of MN30 is connected to the fourth output terminal of SR2. The connection node number is: SF. <3> ; The gate of MN31 is connected to the fifth output terminal of SR2. The connection node number is: SF. <4> ; The gate of MN32 is connected to the sixth output terminal of SR2. The connection node number is: SF. <5> ; The gate of MN33 is connected to the seventh output terminal of SR2. The connection node number is: SF. <6> ; The first input terminal of SR1 is connected to the control voltage CTL1; The second input terminal of SR1 is connected to the control voltage CK1; The second input terminal of SR1 is connected to the control voltage RST1; The first input terminal of SR2 is connected to the control voltage CTL2; The second input terminal of SR2 is connected to the control voltage CK2; The second input terminal of SR2 is connected to the control voltage RST2.

8. The frequency-calibrable on-chip clock generation circuit according to claim 1, characterized in that, The clock generation module includes: The ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, and nineteenth PMOS transistors are numbered MP9-MP19 respectively. The 34th, 35th, 36th, 37th, 38th, 39th, 40th, 41st and 42nd NMOS transistors are numbered MP34-42 respectively. The first capacitor is labeled C1. The fourth and fifth resistors are numbered R4 and R5 respectively; The first inverter, the second inverter, the third inverter, the fourth inverter, and the fifth inverter are numbered INV1, INV2, INV3, INV4, and INV5, respectively.

9. The frequency-calibrable on-chip clock generation circuit according to claim 8, characterized in that, MP9 gate connection node N10; MP9 source connection voltage VDD; The drain of MP9 is connected to the source of MP10, the source of MP11, the drain of MN36, and the drain of MN37. This connection node is numbered N11. The gate of MN36 is connected to the gate of MP11 and the output terminal of INV3. The connection node is numbered N12. The source of MN36 is connected to the drain of MP10, the drain of MN34, the gate of MN34, and the gate of MN35. This connection node is numbered N14. The MP10 gate connects to the MN37 gate and the INV2 output terminal. This connection node is numbered N13. The drain of MP11 is connected to the source of MN37, the drain of MN35, the gate of MP13, and the first terminal of capacitor C1. This connection node is numbered N15. MN34 source connection voltage GND; MN35 source connection voltage GND; MP12 source connection voltage VDD; MP12 gate connection node N4; The drain of MP12 is connected to the source of MP13, the source of MP14, and the source of MP15. This connection node is numbered N18. MP13 drain is connected to MN38 drain, MN38 gate and MN40 gate, and the connection node is numbered N16; The gate of MP14 is connected to the drain of MP16 and the first terminal of resistor R4; The drain of MP14 is connected to the drain of MP15, the drain of MN39, the gate of MN39 and the gate of MN41. This connection node is numbered N17. The gate of MP15 is connected to the source of MN42 and the drain of MP17. This connection node is numbered N21. MP16 source connection voltage VDD; MP16 gate connection node N4; MP17 source connection voltage VDD; MP17 gate connection node N4; The gate of MN42 is connected to the output terminal of INV1, and the connection node is numbered N24. The source of MN42 is connected to the first terminal of resistor R5, and the connection node is numbered N20. The second terminal of resistor R4 is connected to voltage GND; The second terminal of resistor R5 is connected to voltage GND; MN40 source connection voltage GND; The drain of MN40 is connected to the drain of MP18, the gate of MP18, and the gate of MP19. This connection node is numbered N22. The source of MP18 is connected to the voltage VDD. MP19 source connection voltage VDD; The drain of MP19 is connected to the drain of MN41 and the input terminal of INV1. The connection node is numbered N23. MN41 source connection voltage GND; The input terminal of INV4 is connected to the output terminal of INV3; The input terminal of INV5 is connected to the output terminal of INV4. The INV5 output terminal is the clock signal output terminal.

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