Based on heterojunction-ferroelectric dual-mode reconfigurable transistor

Abstract

This invention proposes a heterojunction-ferroelectric dual-mode reconfigurable transistor, comprising the following layers stacked from top to bottom: a top gate, an electrolytic layer, a porous contact layer, a heterojunction layer, a ferroelectric layer, a nanowire channel, a coupling capacitor, an isolation layer, a P-type substrate, and a back gate. The nanowire channel connects the source and drain at both ends, forming a current path, and a ring gate surrounds the nanowire channel. The heterojunction layer adsorbs environmental ions and outputs a signal indicating changes in surface charge density. The ferroelectric layer amplifies the output signal of the heterojunction layer through negative capacitance and generates a ferroelectric output voltage. The porous contact layer allows ion penetration but blocks electron conduction. This invention features dual-mode operation and can integrate sensing and logic functions, alleviating the trade-off between system efficiency and power consumption in traditional discrete solutions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a heterojunction-ferroelectric dual-mode reconfigurable transistor. Background Technology

[0002] The traditional discrete approach of sensors and logic chips suffers from bottlenecks such as low system efficiency, high power consumption, and poor real-time performance. Bioinformatics security also faces challenges due to the lack of key management and hardware encryption. Furthermore, the Nernst limit and insufficient environmental adaptability of traditional ISFETs restrict sensing performance. Although two-dimensional material heterojunction sensors have improved sensitivity, ferroelectric materials have shown computational potential, and reconfigurable transistors have driven innovation in logic functions, none of these three have achieved functional integration.

[0003] Against this backdrop, this study focuses on the vertical integration of two-dimensional heterojunctions and ferroelectric layers, aiming to overcome the limitations of the separation of "sensing-computing" and construct a dual-modal reconfigurable transistor with high sensitivity, fast response (<50ms) and hardware encryption capabilities, providing an integrated solution for fields such as biomedical point-of-care diagnostics, industrial intelligent control and IoT security. Summary of the Invention

[0004] In view of the above situation, the main objective of the present invention is to propose a heterojunction-ferroelectric dual-mode reconfigurable transistor to solve the above-mentioned technical problems.

[0005] This invention proposes a heterojunction-ferroelectric dual-mode reconfigurable transistor, comprising the following layer structure stacked from top to bottom:

[0006] Top gate, electrolytic layer, porous contact layer, heterojunction layer, ferroelectric layer, nanowire channel, coupling capacitor, isolation layer, P-type substrate and back gate;

[0007] The two ends of the nanowire channel are connected to the source and drain, forming a current path. A ring gate surrounds the nanowire channel.

[0008] The heterojunction layer is used to adsorb environmental ions and output a signal of surface charge density change;

[0009] The ferroelectric layer is used to amplify the output signal of the heterojunction layer through the negative capacitance effect with the coupling capacitor, and to generate a ferroelectric output voltage.

[0010] The porous contact layer is used to allow ion penetration but block electron conduction;

[0011] Transistors have dual-mode operation capability:

[0012] Sensing mode: When the ambient pH value is between 5 and 9, the output voltage signal is linearly related to pH.

[0013] Logic mode: When the ambient pH value is <5 or >9, switch to logic operation mode and output an alarm signal through the drain.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] This invention provides a new solution to overcome the technical bottlenecks of low system efficiency and high power consumption in traditional discrete sensor and logic chip designs through a closed-loop design of "sensing signal - ferroelectric amplification - multi-gate modulation". Compared with the problems of large signal transmission loss and limited cooperative response speed caused by the independent operation of sensors and logic chips in traditional discrete designs, this design improves the electric field coupling efficiency between functional modules to a certain extent by vertically integrating a two-dimensional heterojunction and a ferroelectric layer, and reduces the power consumption caused by the interconnection of discrete devices, providing a better physical architecture choice for realizing integrated sensing and logic functions. In scenarios such as biomedical point-of-care diagnostics and industrial intelligent control, this integration method is expected to alleviate the contradiction between system efficiency and power consumption in traditional discrete solutions, providing a valuable implementation path for technological upgrades in related fields.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by means of embodiments of the invention. Attached Figure Description

[0017] Figure 1 This is an exploded view of the heterojunction-ferroelectric dual-mode reconfigurable transistor proposed in this invention.

[0018] Figure 2 This is a cross-sectional view of the heterojunction-ferroelectric dual-mode reconfigurable transistor proposed in this invention;

[0019] Figure 3 This is the complete signal flow diagram of the heterojunction-ferroelectric dual-mode reconfigurable transistor proposed in this invention;

[0020] Figure 4 This is a flowchart illustrating the specific implementation process of the logic circuit in the logic mode of this invention;

[0021] Among them, 1. top gate, 2. electrolytic layer, 3. porous contact layer, 4. heterojunction layer, 5. ferroelectric layer, 6. ring gate, 7. nanowire channel, 8. source, 9. drain, 10. coupling capacitor, 11. isolation layer, 12. P-type substrate, 13. back gate, 14. ion transport path, 15. coupling path. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] These and other aspects of the embodiments of the present invention will become clear from the following description and accompanying drawings. In these descriptions and drawings, some specific embodiments of the present invention are specifically disclosed to illustrate some ways of implementing the principles of the embodiments of the present invention; however, it should be understood that the scope of the embodiments of the present invention is not limited thereto.

[0024] Please see Figure 1 and Figure 2 This embodiment provides a heterojunction-ferroelectric dual-mode reconfigurable transistor, comprising the following layer structure stacked from top to bottom:

[0025] Top gate 1, electrolytic layer 2, porous contact layer 3, heterojunction layer 4, ferroelectric layer 5, nanowire channel 7, coupling capacitor 10, isolation layer 11, P-type substrate 12, and back gate 13;

[0026] The two ends of the nanowire channel are connected to the source 8 and the drain 9 to form a current path, and a ring gate 6 surrounds the nanowire channel.

[0027] The top gate, in this embodiment, is made of TiN and is in direct physical contact with the upper surface of the ferroelectric layer; it serves as an external voltage input port, where a top gate voltage V is applied. G By controlling the polarization direction and intensity of the ferroelectric layer, the surface charge distribution of the heterojunction can be indirectly affected, thereby controlling the electrical behavior of the entire device.

[0028] In this embodiment, the electrolytic layer, made of KCl solution, has its lower surface in direct contact with the porous SiO2 contact layer. The porous contact layer below indirectly couples with the heterojunction layer (ion-permeable contact), providing an ionic environment. When the solution pH is measured, H... + Changes in concentration drive subsequent sensing and logic responses, essentially acting as a medium to "transmit environmental information" to devices.

[0029] The porous contact layer, in this embodiment, is made of porous SiO2 with a thickness of 100 nm. The upper surface contacts the electrolytic layer, and the lower surface contacts the heterojunction layer. Its porous structure allows ions in the KCl electrolytic layer to penetrate to the surface of the heterojunction while blocking direct electron conduction, ensuring that "ion signals can be transmitted and electronic signals are not short-circuited", thus creating conditions for the heterojunction to capture ion signals.

[0030] The heterojunction layer serves as the core "sensing unit." In this embodiment, it is composed of stacked 3nm thick WSe2 and 3nm thick MoS2 two-dimensional materials. The heterojunction surface charge adsorption effect parameters are: sensitivity 4.38V / pH, detection range pH 3-11. The lower surface of the heterojunction layer contacts the ferroelectric layer, and the upper side is indirectly coupled to the electrolytic layer through a porous SiO2 contact layer. Utilizing the high surface energy and type II band alignment characteristics of two-dimensional materials, H... + Adsorption alters the dipole layer at the heterojunction interface, causing a change in surface charge density. This transforms the "ionic environment stimulus" into a "measurable electrical signal," providing the raw input for subsequent signal amplification and logic operations.

[0031] Ferroelectric layer; the material used in this embodiment is Al-doped HfO2 (Al-HfO2), with a thickness of 41 nm. The upper surface contacts the heterojunction layer, and the lower surface is close to the SiO2 isolation layer. It serves as a signal amplification and coupling bridge. Based on the Landau-Khalatnikov equation, and utilizing the polarization characteristics of the ferroelectric material, the weak charge signal transmitted from the heterojunction is amplified using the negative capacitance effect, resulting in an output voltage V. FE =4.38×(7-pH)V, and at the same time, through the coupling of polarization charge with the electric field of heterojunction and nanowire channel, the transmission of "sensing signal to logic signal" is realized.

[0032] Nanowire channel; the material used in this embodiment is Si (with a diameter of 10 nm, n / p gradient doping, and an n-type surface). + The nanowire channel, with a p-type core, utilizes n / p gradient doping to provide the foundation for carrier transport and threshold voltage regulation, serving as the physical carrier for logic operations. Located at the center of the gate ring, the nanowire channel connects to the source and drain at its two ends, forming a current path. Below, near the SiO2 isolation layer, lies the "logic operation core." Current on / off control is achieved by regulating the distribution and transport of carriers within the channel through multiple gates (top gate, back gate, and gate ring). When the ferroelectric layer outputs a sensing signal (ferroelectric output voltage V), the current is controlled. FE After being coupled into the channel, its threshold voltage will change accordingly (0.4V / 0.8V / 1.2V), thereby performing AND, OR, NOT and other logical operations to convert "environmental sensing information" into "digital logic results".

[0033] The isolation layer, in this embodiment, is made of dense SiO2 with a thickness of 10 nm. Its upper surface is close to the ferroelectric layer and nanowire channel, while its lower surface contacts the P-type Si substrate, serving as an "electrical isolation and electric field transfer layer." On one hand, it isolates the Si nanowire channel from the P-type Si substrate, preventing direct short circuits and ensuring a stable electrical environment for logic operations. On the other hand, it allows the electric field of the ferroelectric layer and back gate to penetrate, providing a physical basis for regulating the threshold voltage of the nanowire channel and achieving "non-contact electric field control."

[0034] P-type substrate; the material used in this embodiment is Si, with a doping concentration of 1×10⁻⁶. 15 cm -3 The upper surface contacts the SiO2 isolation layer, and the lower surface contacts the back gate, serving as a "physical support and potential reference." As the substrate of the entire device, it provides mechanical stability; at the same time, through its connection with the back gate, it provides a stable potential reference for the device, ensuring a unified benchmark for the measurement and control of electrical signals across all layers.

[0035] Back gate; in this embodiment, the material used is Al, which is in direct contact with the lower surface of the P-type Si substrate, serving as an "auxiliary threshold control terminal". Applied voltage V BG， By coupling the electric field between the substrate and the SiO2 isolation layer, the threshold voltage of the Si nanowire channel is finely adjusted, mainly for temperature compensation and mode switching, thereby improving the stability and adaptability of the device operation.

[0036] Source and drain; in this embodiment, Al is used as the material, which is connected to both ends of the Si nanowire channel to form a current loop of "source → nanowire channel → drain", serving as the "input and output interface for logic signals". The source inputs the electrical signal to be processed (such as high or low level), and the drain outputs the result after logic operation through the nanowire channel (such as outputting a high-level alarm when pH is abnormal), realizing the "in" and "out" of electrical signals and giving logic operations practical application value.

[0037] The ring gate, made of TiN in this embodiment, is a closed ring structure that completely surrounds the Si nanowire channel, serving as a "uniform electric field controller." By applying voltage through the ring electrode, a uniform electric field is formed in three-dimensional space for the nanowire channel, compensating for the non-uniformity of the electric field between the top and back gates. This ensures a more uniform distribution and transport of charge carriers within the channel, improving the accuracy and stability of logic operations and avoiding logic errors caused by uneven electric fields.

[0038] The coupling capacitor, made of TiN with a unit of 10fF in this embodiment, efficiently couples the electric field. Through induction, it helps transmit the electric field, reducing signal attenuation during modulation and allowing the ferroelectric layer output voltage V to be increased. FE The logic operation instructions are accurately converted into nanowire channels.

[0039] The transistor disclosed in this embodiment has dual-mode operation capability, including sensing mode and logic mode, as detailed below:

[0040] Sensing Mode: The device senses the environmental ion concentration (pH 5-9) and outputs an electrical signal linearly related to pH. Its core function is "environmental monitoring." In sensing mode, the pH range is 5 ≤ ​​pH ≤ 9, and the ferroelectric output voltage V... FE The nanowire channel threshold V is between -9.4V and 9.4V. THIt is 0.8V (default value), and the typical response time is less than 10ms during the signal amplification phase.

[0041] Logic mode: When the pH is abnormal (<5 or >9), the device switches to the logic operation state and outputs an alarm signal. The core function is "abnormal response".

[0042] When in logic mode (acidic pH < 5), the pH range is pH < 5, and the ferroelectric output voltage V FE Greater than 9.4V, nanowire channel threshold V TH It operates at 1.2V, with a typical response time of less than 50ms throughout the entire process.

[0043] In the logic mode (alkaline pH > 9), the pH range is pH > 9, and the ferroelectric output voltage V FE Less than -9.4V, nanowire channel threshold V TH The voltage is 0.4V, and the typical response time for the entire process is also less than 50ms.

[0044] To more clearly illustrate the principles and implementation process of this invention, the various components are divided into a sensing module, an electric field coupling interface, and a logic module.

[0045] The sensing-amplification module consists of an electrolytic layer, a WSe2 / MoS2 heterojunction layer (3nm / 3nm), an Al:HfO2 ferroelectric layer (41nm), and a porous SiO2 contact layer (100nm). Its function is to sense ion concentration and amplify the signal through the negative capacitance effect, outputting a ferroelectric output voltage V. FE =4.38×(7-pH)V. The ion transport pathway 14, observed through the electrolytic layer, porous contact layer, and heterojunction layer, shows that the electrolytic layer, located at the top, serves as the input source for the environmental pH signal, transferring H+ through ion permeation. + The porous SiO2 contact layer below is the starting point for "ionic environment information" to enter the device.

[0046] The porous contact layer connects the electrolytic layer and the heterojunction layer, allowing H... + It penetrates to the surface of the heterojunction while simultaneously blocking electron conduction, ensuring unidirectional transmission of ion signals to the sensing core. The heterojunction layer, acting as the sensing core, adsorbs H... + Then, by changing the surface charge density, the "ion signal" is converted into a "charge signal," which is directly transmitted to the underlying ferroelectric layer. After receiving the charge signal from the heterojunction, the ferroelectric layer amplifies it through the negative capacitance effect, outputting a ferroelectric output voltage V. FE =4.38×(7-pH)V, and simultaneously in physical contact with the top gate, providing the original amplified signal for the logic module.

[0047] As can be seen from the coupling path 15 of the heterojunction layer, ferroelectric layer, and nanowire channel, the electric field coupling interface serves as a "signal bridge" between the sensing module and the logic module, receiving the ferroelectric output voltage V from the ferroelectric layer on one hand. FE On the other hand, the signal is received by the top grid pressed V. G =0.1×V FE The coupled control voltage transmits these signals to the underlying Si nanowire channel through the electric field penetration effect, realizing "contactless transmission of electrical signals from the sensing module to the logic module".

[0048] The logic module consists of a top gate, a ring gate, a back gate, a nanowire channel, an isolation layer, a source, and a drain. The top gate is in direct contact with the ferroelectric layer, transmitting the ferroelectric output voltage V. FE Proportional conversion to a top gate voltage V suitable for logic control G The input electric field coupling region participates in the threshold voltage regulation of the nanowire channel. A ring gate surrounds the nanowire channel, providing a uniform electric field to ensure uniform carrier distribution within the channel and improve logic operation accuracy. The back gate directly contacts the lower surface of the p-type Si substrate, fine-tuning the threshold voltage of the Si nanowire channel, compensating for temperature drift and mode switching, and working with the top gate to achieve multi-gate coordinated regulation. The nanowire channel is the core carrier for logic operations; after receiving the electric field signal transmitted from the coupling region, it adjusts the threshold voltage according to the top gate voltage V. G By varying the threshold voltage (0.4V / 0.8V / 1.2V), NAND / XOR logic operations are performed, and the result is output through a current loop formed by the source and drain. An isolation layer is located beneath the nanowire, providing electrical isolation while allowing electric field penetration, ensuring signal isolation and stable operation between the logic module and the underlying substrate. The source and drain are connected to the two ends of the nanowire, forming a current path. The source inputs the signal to be processed, and the drain outputs the logic operation result (such as an alarm signal in case of pH abnormality), completing the logical closed loop of "signal input-operation-output".

[0049] The transistor disclosed in this embodiment is in a sensing mode under normal conditions. During pH environment monitoring, the pH threshold trigger logic is triggered when the H+ in the electrolyte... + When the concentration exceeds the critical value:

[0050] Acid trigger: pH < 5 → H + Concentration >10 -5 mol / L → Heterojunction surface charge density > 3 × 10 12 cm -2 →V FE >9.4V; At this point, it automatically switches to logic mode, triggering multi-gate collaborative modulation to regulate the threshold voltage steps of the Si nanowire channel;

[0051] Alkaline trigger: pH>9→H + Concentration <10-9 mol / L → Heterojunction surface charge density < -3×10 12 cm -2 →V FE When the voltage drops below -9.4V, the system automatically switches to logic mode, triggering multi-gate collaborative regulation to control the threshold voltage gradient of the Si nanowire channel.

[0052] The multi-gate coordinated modulation in mode switching is as follows:

[0053] 1) Top gate: Signal mapping to the threshold voltage V of the Si nanowire channel TH Regulation of the control benchmark

[0054] Voltage relationship: V G =0.1×V FE The high voltage amplified from the ferroelectric layer is mapped to a voltage suitable for nanowire modulation.

[0055] Function: Directly enhances the threshold reference component of nanowires, laying the foundation for threshold grading.

[0056] 2) Back gate: Threshold step-by-step fine-tuning and temperature compensation

[0057] Voltage formula: V BG =c×(7-pH), where c is from 0.05V to 0.2V; when c is 0.05V and pH=4, V BG =0.15V;

[0058] Dual function: fine-tuning the threshold step point; achieving temperature compensation coefficient through substrate electric field feedback.

[0059] In the above description, the example back gate voltage given in this embodiment is 0.05V. Under this voltage condition, the back gate is mainly used for threshold step fine-tuning and temperature compensation. To ensure better results, after increasing the back gate voltage amplitude within the range of 0.05V to 0.2V, the electric field of the back gate can penetrate the substrate and SiO2 isolation layer more strongly and act on the bottom of the Si nanowire channel, which enhances the control effect in synergy with the ring gate, while retaining its temperature compensation and auxiliary mode switching functions. Moreover, the electric field is applied from the back gate longitudinally and from the ring gate radially, and the two complement each other, further ensuring the uniformity of carrier distribution and threshold step accuracy.

[0060] 3) Ring grid: Ensures uniformity of carriers in the channel

[0061] Structural function: The closed-loop electrode surrounding the nanowire suppresses carrier distribution distortion during mode transitions through a uniform electric field. Performance impact: Improves threshold precision and increases noise tolerance in logic operations.

[0062] 4) Dynamic coupling mechanism of multi-gate cooperation

[0063] The top gate, back gate, and ring gate do not operate independently, but rather form a closed loop through "voltage linkage - electric field superposition - carrier coordinated control" to ensure the accuracy and stability of threshold gradation during mode transitions.

[0064] Voltage linkage logic: Top gate voltage V G =0.1×V FE With ferroelectric output voltage V FE Direct bonding (originating from the physical contact between the top gate and the ferroelectric layer), back gate voltage V BG =0.05×(7-pH) then through V FE =4.38×(7-pH) indirectly forms a proportional relationship with the top gate, realizing voltage coordination of "main control + fine adjustment".

[0065] The electric field superposition effect: the top gate electric field penetrates vertically through the ferroelectric layer and the SiO2 isolation layer, directly acting on the surface of the nanowire channel; the back gate electric field applies a longitudinal electric field from the bottom of the channel through the dielectric coupling between the substrate and the SiO2 isolation layer; and the ring gate electric field uniformly wraps around the nanowire radially, forming a three-dimensional electric field superposition. The combined effect of these three factors significantly reduces the standard deviation of the electric field intensity distribution within the channel, ensuring a uniform change in carrier concentration along the channel.

[0066] This multi-gate collaborative design achieves precise mapping between ferroelectric signals and logic thresholds through voltage linkage, and ensures the stability of mode conversion through the superposition of three-dimensional electric fields. It is the core support for this structure to realize dual-mode reconfigurable function.

[0067] like Figure 3 As shown, Figure 3 Presenting the complete signal flow of transistor dual-mode (sensing / logic) switching: First, after the ambient pH value is input, the WSe2 / MoS2 heterojunction layer adsorbs H2... + Ions alter the surface charge density, converting the chemical ion signal into an electrical charge signal; then, the Al:HfO2 ferroelectric layer amplifies the signal through the negative capacitance effect, outputting V. FE =4.38×(7-pH)V, top gate according to VG=0.1×V FE The coupling voltage modulates the threshold reference component of the nanowire; the ring gate provides a radially uniform electric field to ensure stable carrier distribution; the back gate applies a voltage V through the p-type Si substrate and the SiO2 isolation layer. BG =0.05×(7-pH)V Adjusting the voltage, fine-tuning the threshold, and compensating for temperature drift, multi-gate synergy allows the nanowire channel threshold to be stepped into three levels: 0.8V (pH 5-9), 1.2V (pH < 5), and 0.4V (pH > 9). Finally, the operating mode is determined based on whether the pH is within the 5-9 range. When the pH is normal, it enters the sensing mode and outputs the ferroelectric output voltage V. FEWhen the pH value is abnormal, the system enters a logic mode to perform NAND / XOR operations and outputs an alarm signal through the drain electrode, forming a sensing-logic closed loop of "ion input - charge change - voltage amplification - threshold regulation - mode switching" to achieve dual-modal intelligent response.

[0068] like Figure 4 As shown, Figure 4 The specific implementation process of the logic circuit in the logic mode of the present invention is shown below:

[0069] Core component: It adopts a dual-mode reconfigurable transistor, which integrates top gate, back gate, ring gate, nanowire channel, source and drain, and is the basic hardware unit for realizing logic operations.

[0070] Input Port: Two logic input signals are provided, each mapped to the back gate voltage V. BG and the ring gate voltage V RG It is used to input logic control information to the transistor.

[0071] Output port: with drain current I DS As output, the logic state is determined by judging the current magnitude. When I DS When I > 1μA, it is determined as logic "1"; when I DS A value less than 0.1μA is considered as logic "0".

[0072] Triggering condition: When the solution pH < 5, the transistor threshold voltage V TH =1.2V; when pH>9, V TH =0.4V. When this condition is met, the transistor enters the logic mode and can perform logic operations.

[0073] Logic input A and back gate voltage: Logic input A is used to control the back gate voltage offset. When A=1 (representing a high-level logic), V BG Increase by 0.5V; when A=0 (representing low logic), V BG Reduce by 0.5V.

[0074] Logic input B and the ring gate voltage: Logic input B controls the ring gate voltage. When B=1, V RG =1.0V; when B=0, V RG =0V. The function of the ring gate is to provide a uniform electric field for the nanowire channel, ensuring the stability of logic operations.

[0075] Top gate voltage: Top gate voltage V G With ferroelectric layer output voltage V FE Related, satisfying V G =0.1×V FE , and V FEIt is obtained by amplifying the pH signal through the ferroelectric layer, specifically V. FE =4.38×(7-pH), which reflects the amplification effect of the ferroelectric layer on the pH signal.

[0076] NAND gate logic implementation (taking pH=3 as an example, V) TH =1.2V), when the solution pH=3, first calculate the ferroelectric layer output voltage V. FE According to formula V FE =4.38×(7-3)=17.52V; thus, the top grid voltage V is obtained. G =0.1×17.52=1.752V; Back grid base voltage V BG（基础） =0.1×(7-3)=0.4V. Effective gate voltage V eff By V G Back gate voltage V after offset BG（偏移后） and the ring gate voltage V RG Joint decision, i.e., V eff =V G +V BG（偏移后） +V RG By V eff With threshold voltage V TH =1.2V comparison to determine the conduction state of the nanowire channel. The following is a table of logic results obtained from different logic input signals A and B.

[0077]

[0078] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A heterojunction-ferroelectric dual-mode reconfigurable transistor, comprising: The layer structure includes the following layers stacked from top to bottom in turn: Top gate, electrolyte layer, porous contact layer, heterojunction layer, ferroelectric layer, nanowire channel, coupling capacitor, isolation layer, P-type Si substrate and back gate; the material of the electrolyte layer is KCL solution, and the lower surface directly contacts the porous contact layer; the ion environment is provided through the indirect coupling between the porous contact layer and the heterojunction layer arranged below; the material of the top gate is TiN, which directly physically contacts the upper surface of the ferroelectric layer; as an external voltage input port, the top gate voltage V G The polarization direction and intensity of the ferroelectric layer are regulated, the polarization direction and intensity of the ferroelectric layer are changed, the surface charge distribution of the heterojunction is indirectly affected, and the electrical behavior of the entire device is regulated. The two ends of the nanowire channel are connected to the source and the drain to form a current path, and the nanowire channel is surrounded by a ring gate, the material of the nanowire channel is Si, and the nanowire channel adopts n / p gradient doping; The heterojunction layer is used for adsorbing environmental ions and outputting surface charge density change signals; The ferroelectric layer is used for amplifying the output signals of the heterojunction layer through a negative capacitance effect and generating a ferroelectric output voltage; The porous contact layer is used for allowing ion penetration but blocking electron conduction; The transistor has a dual-mode working capability: Sensing mode: when the environmental pH value is between 5 and 9, a voltage signal linearly related to the pH value is outputted; Logic mode: when the environmental pH value is <5 or >9, the logic operation state is switched to, and an alarm signal is outputted through the drain; The bimodal of transistor is cooperatively regulated by back gate, top gate and ring gate according to external environment pH value to regulate threshold voltage V of Si nanowire channel TH Implementation in stages.

2. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 1, wherein: The nanowire channel surface is n + Type, core p type.

3. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 2, wherein: The corresponding relationship between the threshold voltage of the Si nanowire channel and the pH value is: pH 5-9, V TH = 0.8 V; pH < 5, V TH = 1.2 V; pH > 9, V TH = 0.4 V.

4. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 3, wherein: The back gate and the top gate and the ring gate are cooperatively regulated, which specifically includes: Top gate voltage V G for providing a threshold voltage V TH Regulation reference; Back gate voltage V BG for fine tuning the threshold voltage V of Si nanowire channels TH of the stepwise points; The ring gate is used for suppressing carrier distribution distortion through a radial uniform electric field and locking the hierarchical value accuracy.

5. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 4, wherein: The voltage generated by the back gate satisfies V BG = c x (7 - pH), where c is 0.05 V to 0.2 V; When pH < 5 or pH > 9, the back gate cooperates with the top gate and the ring gate to regulate and drive the threshold voltage V of the Si nanowire channel TH Step to 1.2V or 0.4V, realize the switching of sensing mode to logic mode.

6. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 5, wherein: Top gate voltage V G Output voltage V of the ferroelectric layer FE Satisfies V G = 0.1 x V FE Output voltage of the ferroelectric layer satisfies V FE = k x (7 - pH), where k is 4.38 V / pH.

7. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 6, wherein: The ring gate is a closed ring-shaped TiN electrode surrounding the Si nanowire channel and is used for applying a uniform electric field in three-dimensional space to suppress carrier distribution distortion.

8. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 7, wherein: The surface charge density of the heterojunction layer and H + The mapping relationship of the concentration is: pH<5, H + Concentration>10 -5 mol / L, heterojunction layer surface charge density>3×10 12 cm -2 , ferroelectric layer output voltage V FE >9.4V; pH>9, H + Concentration <10 -9 mol / L, heterojunction layer surface charge density <-3×10 12 cm -2 , ferroelectric layer output voltage V FE <-9.4V; The surface charge density change triggers the ferroelectric layer to output a voltage VFE exceeding ±9.4V, thereby activating the logic mode.

9. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 8, wherein: The logic mode supports NAND, XOR and inverter operations, and outputs a high-level alarm signal through the drain when the pH value is abnormal; The response time of the sensing mode is <10ms, and the full-process response time of the logic mode is <50ms.

10. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to any one of claims 1-9, wherein: The material of the porous contact layer is porous SiO2, the thickness of the porous contact layer is 100nm, the thickness of the ferroelectric layer is 41nm, and the heterojunction layer is composed of vertically stacked WSe2 and MoS2, wherein the thickness of WSe2 and MoS2 is 3nm.

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