TSN redundant message elimination method and device
By constructing a combined structure of triple hash table and CAM table, the resource and clock frequency limitations of redundant message elimination on FPGA are solved, enabling efficient processing of redundant messages in TSN network at low clock frequencies, thus improving data processing capability and accuracy.
Patent Information
- Application Number
- CN202511091867.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-07
AI Technical Summary
The existing IEEE 802.1CB standard's redundant message elimination function is difficult to deploy on FPGAs, and is limited by resources and clock frequency, making it unable to efficiently handle the real-time data transmission requirements of TSN networks.
By employing a combination structure of triple HASH table and CAM table, and constructing a HASH+CAM flow table, the block RAM and register array of the FPGA are utilized to optimize the table entry storage and access strategy, thereby achieving efficient judgment and elimination of redundant messages.
It improves the performance and accuracy of TSN packet processing under low clock frequency and limited resources, reduces the network resource occupation of redundant packets, and adapts to the management needs of TSN packet flows of different sizes.
Smart Images
Figure CN120915727A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of message processing technology, and in particular to a method and apparatus for eliminating redundant TSN messages. Background Technology
[0002] The IEEE 802.1CB protocol is a standard in Time-Sensitive Networking (TSN) specifically designed to provide redundant paths, ensuring reliable data transmission even in the event of network failures. Currently, the redundancy elimination function of the IEEE 802.1CB standard primarily relies on ASICs (Application-Specific Integrated Circuits) for implementation. While ASICs offer advantages such as high efficiency and low latency, their fixed design and limited flexibility can restrict their application in scenarios requiring efficient processing of large volumes of real-time data.
[0003] Compared to ASICs, FPGAs (Field-Programmable Gate Arrays) offer greater flexibility, allowing users to customize circuits through programming. However, they are relatively limited in resources (such as logic cells and memory), and FPGAs typically operate at lower clock frequencies, which may be insufficient to support high-speed data processing demands, especially for applications requiring strict real-time performance like TSN networks. Therefore, due to these resource and clock frequency limitations, the redundancy message elimination function of the existing IEEE 802.1CB standard is difficult to deploy on FPGAs. Summary of the Invention
[0004] In view of this, this application proposes a method and apparatus for eliminating redundant TSN packets. Through efficient HASH table and CAM table design, as well as optimized table entry storage and access strategies, redundancy elimination of high-volume TSN packets is achieved at low clock frequencies.
[0005] Firstly, this application provides a method for eliminating redundant TSN packets, including:
[0006] Construct a HASH+CAM flow table structure with a triple HASH table as the main component and a CAM table as the auxiliary component. The HASH+CAM flow table structure pre-stores the key value of the TSN packet flow and its corresponding flow ID number.
[0007] Obtain the TSN packet to be judged, extract the key information of the TSN packet, and generate the key type and key value based on the key information;
[0008] The query is performed in the triple HASH table according to the Key type and Key value, and the stream ID number corresponding to the Key value is output when a match is found.
[0009] If the query of the triple HASH table does not hit, the Key value is queried in the CAM table, and the flow ID number corresponding to the Key value is output when hitting;
[0010] It is confirmed whether the TSN packet is a redundant packet according to the flow ID number, and the redundant packet is discarded after confirmation.
[0011] According to the above, in the TSN redundant packet elimination method provided by the application, by constructing a HASH+CAM flow table structure taking a triple HASH table as the main and a CAM table as the auxiliary, the Key value of the TSN packet flow and the corresponding flow ID number can be efficiently stored and managed. When judging the redundant packet, the key information of the TSN packet is extracted, the Key type and Key value are generated based on the key information, then the triple HASH table is queried first, and the CAM table is queried again when it does not hit. In this way, it can be quickly confirmed whether the TSN packet is a redundant packet and discarded. The application can realize high-performance data processing capability under low clock frequency and less resource occupation, and effectively reduce the occupation of network resources by redundant packets.
[0012] Optionally, the key information of the TSN packet includes at least one of a source MAC address, a destination MAC address, an IP type or other specified identifier;
[0013] The S / DMAC type or S+DMAC type Key value is generated based on the source MAC address and the destination MAC address, and / or the IP type Key value is generated based on the IP type or other specified identifier.
[0014] According to the above, by specifying the composition of the key information of the TSN packet and generating different types of Key values based on different key information, the generation of Key values is more flexible and targeted, which can more accurately identify different TSN packet flows and provide a basis for accurate query of flow ID number in the HASH+CAM flow table structure, which helps to improve the accuracy of redundant packet judgment.
[0015] Optionally, the triple HASH table takes a block RAM inside the FPGA as a basic storage entity, each block RAM can be configured as different combinations of bit width and depth, and supports the use of multiple block RAMs in parallel to expand the bit width and depth.
[0016] The triple HASH table includes an S / DMAC HASH table, an S+DMAC HASH table and an IP type HASH table, and the triple HASH table queries the Key type and Key value according to the HASH algorithm and writes the query result to the first FIFO buffer.
[0017] From the above, the triple HASH table takes the block RAM inside the FPGA as the basic storage entity, can flexibly configure the bit width and depth combination of each block RAM, supports the parallel splicing and expansion of multiple block RAMs, can reasonably use the FPGA resources according to actual needs, and meets the management needs of different sizes of TSN packet streams. Meanwhile, when the HASH algorithm query hits, the flow ID number can be written into the first FIFO cache, and if the query does not hit, a 0 value can be written into the first FIFO cache, so that whether the triple HASH table query hits can be determined according to the content written in the first FIFO cache.
[0018] Optionally, the CAM table takes the register array of the FPGA as the basic storage entity, each register group in the register array stores a Key table item, the CAM table performs the Key value query in the manner of reading all Key table items in parallel, and writes the query result into the second FIFO cache.
[0019] From the above, the CAM table takes the register array of the FPGA as the basic storage entity, adopts the manner of reading all Key table items in parallel to perform the query, and writes the result into the second FIFO cache. This query manner is fast, can quickly determine whether the Key value hits, cooperates with the triple HASH table, further improves the overall query efficiency, and ensures that whether the TSN packet is a redundant packet can be confirmed in time. Meanwhile, when the query hits, the flow ID number can be written into the second FIFO cache, and if the query does not hit, a 0 value can be written into the second FIFO cache, so that whether the CAM table query hits can be determined according to the content written in the second FIFO cache, and whether the search process is completed can also be determined according to the data valid flags of the two FIFO caches.
[0020] Optionally, the query in the triple HASH table according to the Key type and the Key value comprises:
[0021] determining the HASH function corresponding to each level of HASH table according to the Key type, and calculating the HASH value of each level of HASH table through the HASH function, the HASH value is used to determine the row and column address of the HASH table;
[0022] querying the Key value in the triple HASH table level by level according to the determined row and column address, and outputting the flow ID number corresponding to the Key value when hitting.
[0023] According to the Key type, the HASH function corresponding to each level of the HASH table is determined, and the HASH value of each level of the HASH table is calculated in sequence through the HASH function. The HASH value is used to determine the row and column address of the HASH table. Then, the Key value is sequentially queried in the triple HASH table, and the flow ID number corresponding to the Key value is output when a hit is found. This ordered query method improves the accuracy and efficiency of the query, and quickly finds the flow ID number corresponding to the Key value, which provides a basis for subsequent judgment of redundant messages.
[0024] Optionally, the method further comprises:
[0025] If the query of the CAM table does not hit, a new flow ID number is allocated for the Key type and the Key value. When the triple HASH table is not full, the HASH table to be added in the triple HASH table is determined according to the Key type, and the Key value and the corresponding flow ID number are added to the row and column address of the HASH table. The row and column address are determined according to the HASH calculation result of the Key type.
[0026] If the triple HASH table is full and the CAM table is not full, the Key value and the corresponding flow ID number are added to the CAM table.
[0027] If the CAM table is full, the current addition is terminated.
[0028] According to the above, when the query of the CAM table does not hit, the flow ID number is allocated for the new Key type and the Key value according to the storage condition of the triple HASH table and the CAM table, and is added to the corresponding table. If the table is full, the addition is terminated. This processing mechanism ensures that the HASH+CAM flow table structure can be dynamically updated, adapts to the changing TSN message flow, and at the same time avoids data loss or processing errors caused by full tables.
[0029] Optionally, the method further comprises:
[0030] Obtaining state information corresponding to the flow ID number, the state information including a window value, a counter and a flag bit.
[0031] Comparing whether the timestamp or sequence number of the TSN message has been recorded within the window value range, or whether the TSN message has been marked for processing in the flag bit.
[0032] If yes, the TSN message is confirmed as a redundant message and is discarded. If no, the TSN message is normally processed, and the state information is updated after being discarded or normally processed.
[0033] From the above, by acquiring the state information corresponding to the flow ID number, comparing whether the timestamp or sequence number of the TSN message is recorded in the window value range, or searching whether it has been marked in the flag bit, the TSN message is accurately judged whether it is a redundant message. And the state information is updated after discarding or normal processing, so that the state information can reflect the message processing in real time, provide accurate reference for subsequent message processing, and improve the stability and reliability of the whole system.
[0034] Optionally, the triple HASH table takes a block RAM in the FPGA as a basic storage entity, and the read operation of the block RAM is set to two clock cycles to data valid;
[0035] When the state information of the flow ID number is acquired in the block RAM for two times in succession, whether the current flow ID number is consistent with the previous flow ID number is compared through a data feedback selection mechanism, if not, the state information of the current flow ID number stored in the block RAM is acquired, and if yes, the state information updated previously is acquired.
[0036] From the above, for the case that the triple HASH table takes a block RAM in the FPGA as a storage entity, since there is a certain delay in the read and write operations of the block RAM, the read operation of the block RAM to data valid is set to two clock cycles, so as to ensure that there is enough time to meet the timing requirement when the block RAM completes the read operation and outputs valid data. When the state information of the flow ID number is acquired for two times in succession, the current and previous flow ID numbers are compared through the data feedback selection mechanism, and according to the comparison result, it is decided to acquire what kind of state information. When the comparison is inconsistent, the state information corresponding to the current flow ID number can be normally acquired, and when the comparison is consistent, due to the delay of the write operation of the block RAM, the state information updated previously is still in the cache and has not been written into the block RAM, at this time, the state information updated previously in the cache should be acquired, so as to ensure the accuracy and consistency of the data.
[0037] Optionally, it further comprises:
[0038] When the TSN message flow is added in the HASH+CAM flow table structure, the Key type and Key value of the TSN message flow are sequentially queried in the triple HASH table and the CAM table, and when hit, the Key value of the TSN message flow and the flow ID number corresponding thereto are overlaid on the hit triple HASH table or CAM table;
[0039] If not hit, it is preferentially added to the triple HASH table which is not full, if the triple HASH table is full, it is added to the CAM table, and if the CAM table is full, the current addition is terminated.
[0040] From the above, when adding a TSN message stream to the HASH+CAM flow table structure, first, query in the triple HASH table and the CAM table in turn, if hit, overwrite the original information, ensure the timely update of the information in the table. If not hit, add to the triple HASH table which is not full first, then consider the CAM table, if the table is full, terminate the addition. This adding mechanism reasonably utilizes the storage resources, ensures that the newly added TSN message stream can be effectively managed, and at the same time maintains the stability and high efficiency of the HASH+CAM flow table structure.
[0041] In a second aspect, the present application provides a TSN redundant message elimination device, comprising:
[0042] A construction module is configured to construct a HASH+CAM flow table structure taking a triple HASH table as the main and a CAM table as the auxiliary, and the HASH+CAM flow table structure pre-stores Key values of TSN message streams and corresponding flow ID numbers thereof;
[0043] An acquisition module is configured to acquire a TSN message to be judged, extract key information of the TSN message, and generate a Key type and a Key value based on the key information;
[0044] A query module is configured to query in the triple HASH table according to the Key type and the Key value, and output a flow ID number corresponding to the Key value when hit; if the query in the triple HASH table is not hit, query in the CAM table according to the Key value, and output a flow ID number corresponding to the Key value when hit;
[0045] A processing module is configured to confirm whether the TSN message is a redundant message according to the flow ID number, and discard the redundant message after confirmation.
[0046] In a third aspect, the present application provides a computing device, comprising:
[0047] A processor;
[0048] A memory configured to store one or more programs;
[0049] When the one or more programs are executed by the processor, the processor implements the above-mentioned TSN redundant message elimination method.
[0050] In a fourth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, and the computer program is executed by a computer to implement the above-mentioned TSN redundant message elimination method.
[0051] These and other aspects of the present application will become more fully understood from the following description of (multiple) embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0052] Figure 1 A flowchart illustrating a TSN redundant message elimination method provided in this application embodiment;
[0053] Figure 2 A schematic diagram illustrating the data feedback selection process for two stream ID numbers provided in an embodiment of this application;
[0054] Figure 3 A schematic diagram of adding TSN packet flows to the HASH+CAM flow table structure provided in the embodiments of this application;
[0055] Figure 4 A structural diagram of a TSN redundant message elimination device provided in an embodiment of this application;
[0056] Figure 5 This is a structural diagram of a computing device provided in an embodiment of this application.
[0057] It should be understood that the dimensions and shapes of the block diagrams in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the block diagrams presented in the structural diagrams are only schematic representations of the structural relationships between the block diagrams, and are not intended to limit the physical connection methods of the embodiments of this application. Detailed Implementation
[0058] The technical solutions provided in this application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the system architecture and business scenarios provided in the embodiments of this application are mainly for illustrating possible implementations of the technical solutions of this application and should not be construed as the sole limitation on the technical solutions of this application. Those skilled in the art will recognize that the technical solutions provided in this application are equally applicable to similar technical problems as system architectures evolve and new business scenarios emerge.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.
[0060] This application proposes a method and apparatus for eliminating redundant TSN packets. Through efficient HASH and CAM table design, combined with the unique block RAM and pipeline structure of FPGA, redundancy elimination of high-volume TSN packets is achieved at low clock frequencies. This allows the application to fully utilize the flexibility and high-speed lookup capabilities of FPGAs, achieving high-performance data processing capabilities at lower clock frequencies and with less resource consumption, thereby implementing ASIC-like redundant packet elimination functionality through FPGA.
[0061] As shown in Figure 1 , the embodiment of the application provides a TSN redundant message elimination method, which realizes deployment of a TSN redundant elimination mechanism on an FPGA. Referring to Figure 1 , the method comprises the following steps.
[0062] S110: Construct a HASH+CAM flow table structure taking a triple HASH table as a main memory and a CAM table as a supplementary memory.
[0063] Based on the elimination characteristics of redundant messages, the embodiment constructs a HASH+CAM flow table structure taking a triple HASH table as a main memory and a CAM table as a supplementary memory, processes most TSN messages through the triple HASH table, and carries overflown TSN messages through the CAM (Content Addressable Memory) table to be compatible with the resource characteristics of the FPGA. The HASH+CAM flow table structure pre-stores Key values and corresponding flow ID numbers of TSN message flows, and constantly updates table entries with the processing of TSN messages, so as to be used for querying and matching the flow ID numbers of subsequently received TSN messages. Meanwhile, the HASH+CAM flow table structure also supports initialization, writing, reading, adding and querying operations, and ensures efficient management of the HASH table and the CAM table.
[0064] In some embodiments, the triple HASH table comprises an S / DMAC HASH table, an S+DMAC HASH table and an IP type HASH table, which are used to match the flow to which a TSN message belongs and determine the flow ID number thereof.
[0065] S120: Obtain a TSN message to be judged, extract key information of the TSN message and generate a Key type and a Key value based on the key information.
[0066] Based on the above-constructed HASH+CAM flow table structure, when the system receives a TSN message, the TSN message can be parsed and its key information can be extracted for subsequent matching operations. The key information of the TSN message includes but is not limited to a source MAC address (SMAC), a destination MAC address (DMAC), an IP type or other specified identifiers, etc. These key information can be used to generate one or more types of keys (Key values), which are data composed of information extracted from the message and used to identify specific data flows or message characteristics. Different Key types are used to identify and classify different categories of Key values.
[0067] In some embodiments, a S / D MAC type Key value can be generated by combining the source MAC address and the destination MAC address, or a S+D MAC type Key value can be generated by combining the source MAC address and the destination MAC address after performing some operation (such as a HASH function) on the source MAC address and the destination MAC address, so as to increase the uniqueness of the Key value, or an IP type Key value can be generated based on an IP type or other specified identifier. By generating different types of Key values based on different key information, the generation of the Key value is more flexible and targeted, and different TSN message flows can be more accurately identified, which provides a basis for subsequent accurate query of the flow ID number in the HASH+CAM flow table structure, and helps to improve the accuracy of redundant message judgment.
[0068] S130: Query in the triple HASH table according to the Key type and the Key value, and output the flow ID number corresponding to the Key value when a hit is obtained.
[0069] In this step, the triple HASH table includes a S / D MAC HASH table, a S+D MAC HASH table and an IP type HASH table, and different HASH tables correspond to different HASH functions.
[0070] Based on the Key type and the Key value generated in step S120, the HASH function corresponding to each level of HASH table is determined by analyzing the Key type, and the HASH value of each level of HASH table is calculated in sequence by using the HASH function, and the HASH value is used to determine the row and column address of the HASH table. According to the row and column address of each level of HASH table, the Key value is queried in the triple HASH table in sequence, and the flow ID number corresponding to the Key value is output when a hit is obtained. This ordered query method improves the accuracy and efficiency of the query, and can quickly find the flow ID number corresponding to the Key value, which provides a basis for subsequent judgment of redundant messages.
[0071] For example, a HASH function corresponding to the S / DMAC HASH table is selected to perform HASH calculation on the Key type, and the row and column address (bucket) of the S / DMAC HASH table is determined according to the calculated HASH value. Then it is checked whether a table entry matching the Key value is stored in the row and column address. If so, the flow ID number corresponding to the Key value is output. If not, a HASH function corresponding to the S+DMAC HASH table is selected to perform HASH calculation on the Key type, and the row and column address (bucket) of the S+DMAC HASH table is determined according to the calculated HASH value. Then it is checked whether a table entry matching the Key value is stored in the row and column address. If so, the flow ID number corresponding to the Key value is output. If not, a HASH function corresponding to the IP type HASH table is selected to perform HASH calculation on the Key type, and the row and column address (bucket) of the IP type HASH table is determined according to the calculated HASH value. Then it is checked whether a table entry matching the Key value is stored in the row and column address. If so, the flow ID number corresponding to the Key value is output. If not, further query in the CAM table is needed.
[0072] In some embodiments, the triple HASH table takes block RAM inside the FPGA as the basic storage entity, each block RAM can be configured into different bit width and depth combinations, and supports the expansion of bit width and depth in the way of using multiple block RAMs in parallel splicing. For example, the block RAM can organize the table entry bit width and depth in the unit of 72 bits x 512, and a single block RAM supports a maximum bit width of 72 bits. If the table entry bit width exceeds 72, 2, 3, 4... block RAMs are used in order of 144, 216, 288... to splice the bit width. A single block RAM supports a maximum depth of 512. If the table entry depth exceeds 512, 2, 4, 8... block RAMs are used in order of 1024, 2048, 4096... to expand the depth.
[0073] S140: If the query of the triple HASH table does not hit, the Key value is queried in the CAM table, and the flow ID number corresponding to the Key value is output when it hits.
[0074] In this step, after three-layer HASH calculation and lookup, no entry completely matching the Key value is found in each level of the triple HASH table. The system can determine that the triple HASH table query is not hit. At this time, the system can pass the not-hit Key value from the triple HASH table query process to the CAM table query module. The CAM table uses parallel comparison internally. Each storage unit compares with the input Key value in the same clock cycle. If an entry completely matching the input Key value is found in the CAM table, the entry is immediately marked as hit, and the flow ID number corresponding to the Key value in the entry is output.
[0075] If the CAM table query is not hit, the system determines that the entire query process is not hit. At this time, the system can trigger a new entry addition process by assigning a new flow ID number to the Key type and Key value to form a new entry. Then, the state of the triple HASH table is checked level by level. If the triple HASH table is in an unfull state, the HASH function corresponding to the HASH table to be added can be selected according to the Key type, and the Key type is calculated by the HASH function to determine the row and column address of the new entry in the HASH table. Then, the Key value and the corresponding flow ID number are added to the row and column address of the HASH table. If the triple HASH table is in a full state, the state of the CAM table can be checked. If the CAM table is in an unfull state, the Key value and the corresponding flow ID number can be added to the CAM table, thereby completing the dynamic update of the HASH+CAM flow table structure. If the triple HASH table and the CAM table are both in a full state, the addition is terminated.
[0076] In some embodiments, the CAM table is a content lookup storage structure. The CAM table uses a register array of an FPGA as a basic storage entity. The register array includes a plurality of register groups. Each register group stores a Key entry (Key value and corresponding flow ID number). The CAM table queries the Key value in a parallel manner by reading all Key entries. When the query is hit, the flow ID number in the hit Key entry is extracted and output.
[0077] In some embodiments, for the query of the triple HASH table, due to the read delay of the block RAM in the FPGA, which is usually 2 clock cycles (i.e. after the read request is sent, the data is valid after 2 taps), the lookup result of the HASH table with a depth less than 1024 is output every 2 taps. The CAM table is a register group + comparator structure, and the lookup process is combinational logic + pipeline, so the lookup result can be output every tap. The HASH table lookup result and the CAM table lookup result are written into two independent FIFOs (First In First Out queue) respectively. When the triple HASH table is queried, the flow ID number can be written into the first FIFO cache corresponding to the triple HASH table when it hits, and a 0 value (indicating a miss) can be written into the first FIFO cache when it misses. If the query of the triple HASH table misses, the CAM table can be further queried, and the flow ID number can be written into the second FIFO cache corresponding to the CAM table when it hits, and a 0 value (indicating a miss) can be written into the second FIFO cache when it misses. Only when both FIFO caches are completed, a complete query operation is completed, which ensures the synchronization of the lookup result and facilitates subsequent logic processing.
[0078] S150: Confirming whether the TSN packet is a redundant packet according to the flow ID number, and discarding the redundant packet after the confirmation.
[0079] In this step, after obtaining the flow ID number output by the triple HASH table or the CAM table, it can be judged whether the current TSN packet is a redundant packet by checking the state information of the flow ID number. The state information includes window value, counters and flags, etc. The window value defines a time window, and the repeated packets in this window are considered redundant. The counters record the number of received packets or other related information. The flags can be used to mark that a packet has been processed or indicate a certain specific state. By comparing whether the timestamp or sequence number of the TSN packet has been recorded in the window value range, or whether the TSN packet has been marked for processing in the flags, it can be judged whether the TSN packet is a redundant packet. If it is judged that the TSN packet is a redundant packet, the TSN packet can be discarded directly, and some statistical information (such as redundant packet count) can be updated. If it is judged that the TSN packet is not a redundant packet, the packet can be processed normally and the state information of the flow ID number can be updated correspondingly, such as increasing the counters, updating the window value or the flags, etc. By updating the state information of the flow ID number in real time, the processing of the TSN packet can be reflected in real time, providing accurate reference for subsequent TSN packet processing.
[0080] In some embodiments, since the triple HASH table takes the block RAM inside the FPGA as the basic storage entity, based on the read-write delay of the block RAM, the read operation of the block RAM can be set to two taps to the clock cycle of valid data, ensuring that there is enough time to meet the timing requirements when the block RAM completes the read operation and outputs valid data. And since the state information acquisition of the flow ID number needs to rely on the read operation of the block RAM or the register group, and these read operations themselves have pipeline delay, therefore, when searching for state information in the block RAM or the register group according to the flow ID number, the search request cannot be continuously sent out, and at least one clock cycle needs to be separated (the register group + comparator structure outputs the search result once every tap).
[0081] In some embodiments, when the state information acquisition of the flow ID number is performed in the block RAM for two consecutive times, the state information corresponding to the same flow ID number may be accessed, and the state information of the second search may be the old state information stored in the block RAM due to the fact that the state information returned by the first search has not been processed (the state information updated by the first search needs two clock cycles to be written back to the block RAM). In order to ensure the correct processing and transmission of data, as shown in Figure 2 the embodiment can set a data feedback selection (Feedback Select Logic) mechanism, which can feed back the data read out last time to the current processing flow according to certain selection logic, so as to perform further processing or comparison. For example, the data feedback selection mechanism can be used to compare whether the current flow ID number is consistent with the previous flow ID number (historical flow ID cache), if not, the state information of the current flow ID number stored in the block RAM is acquired, and if yes, the state information updated last time is acquired, which may still be located in the cache of the write operation and has not been formally written back to the block RAM. Through the data feedback selection mechanism, the problem that the data read out before and after may be related can be solved, and it is ensured that the update of the table item (such as window value, counter, flag bit, etc.) after processing each packet is accurate and consistent.
[0082] In some embodiments, the HASH+CAM flow table structure described above can be dynamically updated according to the processing requirements of the packet, as shown in Figure 3 when it is necessary to add a TSN packet flow in the HASH+CAM flow table structure, the Key type and Key value of the TSN packet flow are sequentially queried in the triple HASH table and the CAM table, and the Key value of the TSN packet flow and the corresponding flow ID number are overwritten in the hit triple HASH table or CAM table; if not hit, it is added to the triple HASH table that is not full, if the triple HASH table is full, it is added to the CAM table, and if the CAM table is full, the addition is terminated.
[0083] In some embodiments, the pre-insert lookup and packet lookup involve different query actions and their subsequent operations. The purpose of the pre-insert lookup is to confirm whether a Key value has been stored in the table. If a hit (the Key value exists), it is updated, and a new table entry is not inserted. If a miss (the Key does not exist), a new table entry is inserted, and it is determined which table (e.g., HASH table or CAM table) to insert into. The operation frequency of the pre-insert lookup is low, and it needs to determine whether to write a table entry and which table to write to according to the lookup result. It is usually initiated by the control level (e.g., CPU or register interface) and allows back pressure to the initiator (e.g., register interface). The purpose of the packet lookup is to identify which flow the current packet belongs to. If a hit, the corresponding flow ID number is returned. If a miss, the process of adding a new table entry is triggered. The operation frequency of the packet lookup is high, and only the lookup result is needed, without the need for a write operation. It is usually initiated by the data plane (e.g., high-speed interface). Since the subsequent processing logic of the two queries is different, their query results cannot be mixed. The present embodiment can use different cache mechanisms to isolate the query results. For example, a FIFO structure (with a large depth) can be used to cache the packet lookup results, to improve throughput and avoid packet loss or back pressure. A single register (with a depth of 1) can be used to cache the pre-insert lookup results. If the cache is full (i.e., the previous request is being processed), the control signal can be back-pressured to make the initiator wait, achieving the effect of saving resources.
[0084] In summary, the present embodiment achieves the elimination of redundant TSN packets with large flow under low clock frequency through efficient HSAH table and CAM table design, combined with the block RAM and pipeline structure specific to FPGA. Specifically, by optimizing the storage and access strategy of table entries and using appropriate cache mechanisms to reduce delay and improve throughput, the entire system can adapt to the resource limitations of FPGA without sacrificing performance. In addition, the feedback selection circuit introduced further ensures the accuracy and reliability of data processing. This FPGA-based solution not only improves the scalability and flexibility of the system, but also provides a solid foundation for future applications, especially in scenarios that require efficient processing of large amounts of real-time data transmission.
[0085] As shown in Figure 4 , the present embodiment also provides a TSN redundant packet elimination device. The device can be used to implement any step of the TSN redundant packet elimination method and its optional embodiments, as shown in Figure 4 . The device includes a construction module 210, an acquisition module 220, a query module 230, and a processing module 240.
[0086] The construction module 210 is configured to construct a HASH+CAM flow table structure mainly in a triple HASH table and secondarily in a CAM table, the HASH+CAM flow table structure pre-storing a Key value of a TSN packet flow and a corresponding flow ID number; the acquisition module 220 is configured to acquire a TSN packet to be judged, extract key information of the TSN packet and generate a Key type and a Key value based on the key information; the query module 230 is configured to query the triple HASH table according to the Key type and the Key value, and output the flow ID number corresponding to the Key value when a hit is made; if the triple HASH table query does not hit, the CAM table is queried according to the Key value, and the flow ID number corresponding to the Key value is output when a hit is made; and the processing module 240 is configured to confirm whether the TSN packet is a redundant packet according to the flow ID number, and discard the redundant packet after the confirmation.
[0087] It should be understood that the apparatus or module in the embodiments of the present application can be implemented by software, for example, can be implemented by a computer program or instruction with the above functions, and the corresponding computer program or instruction can be stored in a memory inside a terminal, and the above functions can be implemented by a processor reading the corresponding computer program or instruction inside the memory. Alternatively, the apparatus or module of the embodiments of the present application can also be implemented by hardware. Alternatively, the apparatus or module in the embodiments of the present application can also be implemented by a combination of a processor and a software module.
[0088] It should be understood that the processing details of the apparatus or module in the embodiments of the present application can refer to the related descriptions of the embodiments shown in the above Figures 1-3 and related extended embodiments, and the embodiments of the present application will not be repeated.
[0089] Figure 5 is a structural diagram of a computing device 1000 provided by the embodiments of the present application. The computing device 1000 includes a processor 1010, a memory 1020, a communication interface 1030 and a bus 1040.
[0090] It should be understood that the communication interface 1030 in the computing device 1000 shown in the above Figure 5 can be used for communication between other devices.
[0091] The processor 1010 can be connected with the memory 1020. The memory 1020 can be used for storing program codes and data. Therefore, the memory 1020 can be a storage unit inside the processor 1010, can be an external storage unit independent of the processor 1010, or can be a component including the storage unit inside the processor 1010 and the external storage unit independent of the processor 1010.
[0092] Optionally, the computing device 1000 can further include a bus 1040. The bus 1040 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 1040 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one line is used to represent the bus, but this does not mean there is only one bus or only one type of bus.
[0093] It should be understood that the processor 1010 can be a central processing unit (CPU) in the embodiments of the present application. The processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. Alternatively, the processor 1010 can be one or more integrated circuits for performing related programs to implement the technical solutions provided by the embodiments of the present application.
[0094] The memory 1020 can include read-only memory and random access memory, and provide instructions and data to the processor 1010. A part of the processor 1010 can also include a non-volatile random access memory. For example, the processor 1010 can also store device type information.
[0095] When the computing device 1000 is running, the processor 1010 executes computer execution instructions in the memory 1020 to perform the operation steps of the above method.
[0096] It should be understood that the computing device 1000 according to the embodiments of the present application can correspond to the execution of the corresponding subject in the method according to the embodiments of the present application, and the above-mentioned other operations and / or functions of each module in the computing device 1000 are respectively for realizing the corresponding flow of each method of the embodiments, and for the sake of brevity, will not be repeated here.
[0097] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0098] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.
[0099] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.
[0100] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
[0101] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.
[0102] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.
[0103] The computer readable storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.
[0104] The computer readable storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.
[0105] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is carried. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus.
[0106] The program code embodied on the computer readable media can be transmitted using any appropriate medium, including, but not limited to, wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
[0107] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).
[0108] It is to be understood that the embodiments described herein are merely exemplary of the application and that a myriad of modifications, both as to the types of embodiments and implementations employed in the application and as to the particulars of the application itself, can be made within the scope of the application, without departing from the scope thereof.
[0109] The words "first", "second", "third", etc. or the words "module A", "module B", "module C" and the like in the description and in the claims, merely denote like objects, do not necessarily indicate a specific order or sequence, and can be interchanged, where appropriate, to facilitate the description of the embodiments of the present application.
[0110] In the above description, the steps involved in the description are not necessarily performed in the order described, and can include intermediate steps or be replaced by other steps, and the order of the steps can be interchanged, or the steps can be performed simultaneously, where appropriate.
[0111] The term "comprising" as used in the specification and in claims includes everything within its meaning. It should be interpreted as specifying the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof. Thus, the term "comprising" as used in the specification and in claims should not be interpreted as a limitation on what can be claimed but rather as an indication that the disclosure contemplates several embodiments.
[0112] The terms "one embodiment" or "an embodiment" as may appear in the specification are to be interpreted to mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. Furthermore, the terms "one embodiment" or "an embodiment" as used in the specification are not necessarily to be interpreted as having a cumulative effect with regard to the different embodiments of the application.
[0113] It is noted that the foregoing are merely preferred embodiments of, and the technical principles of, the present application. It is understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, and various obvious changes, modifications and substitutions can be made thereto without departing from the protection scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments only, and more other equivalent embodiments can be included without departing from the concept of the present application, and all of them belong to the protection scope of the present application.
Claims
1. A method for eliminating TSN redundant messages, characterized in that, The application comprises: a HASH+CAM flow table structure mainly composed of a triple HASH table and a CAM table, in which the Key value of a TSN message stream and the corresponding flow ID number are pre-stored; acquiring a TSN message to be judged, extracting the key information of the TSN message and generating a Key type and a Key value based on the key information; querying the Key type and the Key value in the triple HASH table, and outputting the flow ID number corresponding to the Key value when a hit is obtained; if the triple HASH table query does not hit, querying the Key value in the CAM table, and outputting the flow ID number corresponding to the Key value when a hit is obtained; confirming whether the TSN message is a redundant message according to the flow ID number, and discarding the redundant message after confirmation.
2. The method of claim 1, wherein, The key information of the TSN message comprises at least one of a source MAC address, a destination MAC address, an IP type or other specified identifiers; generating a S / DMAC type or a S+DMAC type Key value based on the source MAC address and the destination MAC address, and / or generating an IP type Key value based on the IP type or other specified identifiers.
3. The method of claim 1, wherein, The triple HASH table takes a block RAM in the FPGA as a basic storage entity, each block RAM can be configured as different combinations of bit width and depth, and supports the extension of bit width and depth in the form of parallel splicing of multiple block RAMs; The triple HASH table comprises a S / DMAC HASH table, a S+DMAC HASH table and an IP type HASH table, which queries the Key type and the Key value according to the HASH algorithm and writes the query result into a first FIFO buffer.
4. The method of claim 1, wherein, The CAM table takes a register array of the FPGA as a basic storage entity, each register group in the register array stores a Key table item, the CAM table queries the Key value in the form of reading all Key table items in parallel, and writes the query result into a second FIFO buffer.
5. The method of claim 1, wherein, The query of the Key type and the Key value in the triple HASH table comprises: determining the HASH function corresponding to each level of HASH table according to the Key type, and calculating the HASH value of each level of HASH table by the HASH function, which is used to determine the row and column address of the HASH table; determining the row and column address in the triple HASH table according to the Key value, and outputting the flow ID number corresponding to the Key value when a hit is obtained.
6. The method of claim 1, wherein, Further comprising: if the CAM table query does not hit, assigning a new flow ID number for the Key type and the Key value, and when the triple HASH table is not full, determining the HASH table to be added in the triple HASH table according to the Key type, and adding the Key value and the corresponding flow ID number to the row and column address of the HASH table; The row and column address is determined according to the HASH calculation result of the Key type. If the triple HASH table is full and the CAM table is not full, the Key value and the corresponding flow ID number are added to the CAM table; If the CAM table is full, the current addition is terminated.
7. The method of claim 1, wherein, The confirmation of whether the TSN packet is a redundant packet according to the flow ID number comprises: Obtaining state information corresponding to the flow ID number, the state information comprising a window value, a counter and a flag bit; Comparing whether the timestamp or sequence number of the TSN packet has a record within the window value range, or searching whether the TSN packet has been marked for processing in the flag bit; If yes, the TSN packet is confirmed as a redundant packet and discarded, and if no, the TSN packet is normally processed, and the state information is updated after being discarded or normally processed.
8. The method of claim 7, wherein, The triple HASH table takes a block RAM in the FPGA as a basic storage entity, and the read operation of the block RAM is set to two clock cycles when the data is valid; When the state information of the flow ID number is obtained in the block RAM for two times in succession, whether the current flow ID number is consistent with the previous flow ID number is compared through a data feedback selection mechanism, if not, the state information of the current flow ID number stored in the block RAM is obtained, and if yes, the state information updated previously is obtained.
9. The method of claim 1, wherein, Further comprising: When adding a TSN packet flow in the HASH+CAM flow table structure, the Key type and Key value of the TSN packet flow are sequentially queried in the triple HASH table and the CAM table according to the Key type and Key value, and the Key value of the TSN packet flow and the corresponding flow ID number are overlaid on the hit triple HASH table or CAM table when hit; If not hit, the triple HASH table is preferentially added to the full triple HASH table, if the triple HASH table is full, the CAM table is added, and if the CAM table is full, the current addition is terminated.
10. A TSN redundancy message elimination apparatus, comprising: Comprise: A construction module for constructing a HASH+CAM flow table structure taking a triple HASH table as the main and a CAM table as the auxiliary, the HASH+CAM flow table structure pre-storing Key values of TSN packet flows and corresponding flow ID numbers; An acquisition module for acquiring a TSN packet to be judged, extracting key information of the TSN packet and generating a Key type and a Key value based on the key information; A query module for querying in the triple HASH table according to the Key type and the Key value, and outputting a flow ID number corresponding to the Key value when hit; If the query of the triple HASH table is not hit, the Key value is queried in the CAM table, and a flow ID number corresponding to the Key value is outputted when hit; A processing module for confirming whether the TSN packet is a redundant packet according to the flow ID number, and discarding the redundant packet after confirmation.